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KGDB_SERIAL_CONSOLE check for module
[linux-2.6.git] / drivers / serial / 8250_pci.c
blob7ddff3f55087c0a1581783c882858cb09e4f1074
1 /*
2 * linux/drivers/char/8250_pci.c
3 *
4 * Probe module for 8250/16550-type PCI serial ports.
5 *
6 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
7 *
8 * Copyright (C) 2001 Russell King, All Rights Reserved.
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License.
13 */
14 #include <linux/module.h>
15 #include <linux/init.h>
16 #include <linux/pci.h>
17 #include <linux/string.h>
18 #include <linux/kernel.h>
19 #include <linux/slab.h>
20 #include <linux/delay.h>
21 #include <linux/tty.h>
22 #include <linux/serial_core.h>
23 #include <linux/8250_pci.h>
24 #include <linux/bitops.h>
25
26 #include <asm/byteorder.h>
27 #include <asm/io.h>
28
29 #include "8250.h"
30
31 #undef SERIAL_DEBUG_PCI
32
33 /*
34 * init function returns:
35 * > 0 - number of ports
36 * = 0 - use board->num_ports
37 * < 0 - error
38 */
39 struct pci_serial_quirk {
40 u32 vendor;
41 u32 device;
42 u32 subvendor;
43 u32 subdevice;
44 int (*init)(struct pci_dev *dev);
45 int (*setup)(struct serial_private *,
46 const struct pciserial_board *,
47 struct uart_port *, int);
48 void (*exit)(struct pci_dev *dev);
49 };
50
51 #define PCI_NUM_BAR_RESOURCES 6
52
53 struct serial_private {
54 struct pci_dev *dev;
55 unsigned int nr;
56 void __iomem *remapped_bar[PCI_NUM_BAR_RESOURCES];
57 struct pci_serial_quirk *quirk;
58 int line[0];
59 };
60
61 static void moan_device(const char *str, struct pci_dev *dev)
62 {
63 printk(KERN_WARNING "%s: %s\n"
64 KERN_WARNING "Please send the output of lspci -vv, this\n"
65 KERN_WARNING "message (0x%04x,0x%04x,0x%04x,0x%04x), the\n"
66 KERN_WARNING "manufacturer and name of serial board or\n"
67 KERN_WARNING "modem board to rmk+serial@arm.linux.org.uk.\n",
68 pci_name(dev), str, dev->vendor, dev->device,
69 dev->subsystem_vendor, dev->subsystem_device);
70 }
71
72 static int
73 setup_port(struct serial_private *priv, struct uart_port *port,
74 int bar, int offset, int regshift)
75 {
76 struct pci_dev *dev = priv->dev;
77 unsigned long base, len;
78
79 if (bar >= PCI_NUM_BAR_RESOURCES)
80 return -EINVAL;
81
82 base = pci_resource_start(dev, bar);
83
84 if (pci_resource_flags(dev, bar) & IORESOURCE_MEM) {
85 len = pci_resource_len(dev, bar);
86
87 if (!priv->remapped_bar[bar])
88 priv->remapped_bar[bar] = ioremap_nocache(base, len);
89 if (!priv->remapped_bar[bar])
90 return -ENOMEM;
91
92 port->iotype = UPIO_MEM;
93 port->iobase = 0;
94 port->mapbase = base + offset;
95 port->membase = priv->remapped_bar[bar] + offset;
96 port->regshift = regshift;
97 } else {
98 port->iotype = UPIO_PORT;
99 port->iobase = base + offset;
100 port->mapbase = 0;
101 port->membase = NULL;
102 port->regshift = 0;
103 }
104 return 0;
105 }
106
107 /*
108 * ADDI-DATA GmbH communication cards <info@addi-data.com>
109 */
110 static int addidata_apci7800_setup(struct serial_private *priv,
111 const struct pciserial_board *board,
112 struct uart_port *port, int idx)
113 {
114 unsigned int bar = 0, offset = board->first_offset;
115 bar = FL_GET_BASE(board->flags);
116
117 if (idx < 2) {
118 offset += idx * board->uart_offset;
119 } else if ((idx >= 2) && (idx < 4)) {
120 bar += 1;
121 offset += ((idx - 2) * board->uart_offset);
122 } else if ((idx >= 4) && (idx < 6)) {
123 bar += 2;
124 offset += ((idx - 4) * board->uart_offset);
125 } else if (idx >= 6) {
126 bar += 3;
127 offset += ((idx - 6) * board->uart_offset);
128 }
129
130 return setup_port(priv, port, bar, offset, board->reg_shift);
131 }
132
133 /*
134 * AFAVLAB uses a different mixture of BARs and offsets
135 * Not that ugly ;) -- HW
136 */
137 static int
138 afavlab_setup(struct serial_private *priv, const struct pciserial_board *board,
139 struct uart_port *port, int idx)
140 {
141 unsigned int bar, offset = board->first_offset;
142
143 bar = FL_GET_BASE(board->flags);
144 if (idx < 4)
145 bar += idx;
146 else {
147 bar = 4;
148 offset += (idx - 4) * board->uart_offset;
149 }
150
151 return setup_port(priv, port, bar, offset, board->reg_shift);
152 }
153
154 /*
155 * HP's Remote Management Console. The Diva chip came in several
156 * different versions. N-class, L2000 and A500 have two Diva chips, each
157 * with 3 UARTs (the third UART on the second chip is unused). Superdome
158 * and Keystone have one Diva chip with 3 UARTs. Some later machines have
159 * one Diva chip, but it has been expanded to 5 UARTs.
160 */
161 static int pci_hp_diva_init(struct pci_dev *dev)
162 {
163 int rc = 0;
164
165 switch (dev->subsystem_device) {
166 case PCI_DEVICE_ID_HP_DIVA_TOSCA1:
167 case PCI_DEVICE_ID_HP_DIVA_HALFDOME:
168 case PCI_DEVICE_ID_HP_DIVA_KEYSTONE:
169 case PCI_DEVICE_ID_HP_DIVA_EVEREST:
170 rc = 3;
171 break;
172 case PCI_DEVICE_ID_HP_DIVA_TOSCA2:
173 rc = 2;
174 break;
175 case PCI_DEVICE_ID_HP_DIVA_MAESTRO:
176 rc = 4;
177 break;
178 case PCI_DEVICE_ID_HP_DIVA_POWERBAR:
179 case PCI_DEVICE_ID_HP_DIVA_HURRICANE:
180 rc = 1;
181 break;
182 }
183
184 return rc;
185 }
186
187 /*
188 * HP's Diva chip puts the 4th/5th serial port further out, and
189 * some serial ports are supposed to be hidden on certain models.
190 */
191 static int
192 pci_hp_diva_setup(struct serial_private *priv,
193 const struct pciserial_board *board,
194 struct uart_port *port, int idx)
195 {
196 unsigned int offset = board->first_offset;
197 unsigned int bar = FL_GET_BASE(board->flags);
198
199 switch (priv->dev->subsystem_device) {
200 case PCI_DEVICE_ID_HP_DIVA_MAESTRO:
201 if (idx == 3)
202 idx++;
203 break;
204 case PCI_DEVICE_ID_HP_DIVA_EVEREST:
205 if (idx > 0)
206 idx++;
207 if (idx > 2)
208 idx++;
209 break;
210 }
211 if (idx > 2)
212 offset = 0x18;
213
214 offset += idx * board->uart_offset;
215
216 return setup_port(priv, port, bar, offset, board->reg_shift);
217 }
218
219 /*
220 * Added for EKF Intel i960 serial boards
221 */
222 static int pci_inteli960ni_init(struct pci_dev *dev)
223 {
224 unsigned long oldval;
225
226 if (!(dev->subsystem_device & 0x1000))
227 return -ENODEV;
228
229 /* is firmware started? */
230 pci_read_config_dword(dev, 0x44, (void *)&oldval);
231 if (oldval == 0x00001000L) { /* RESET value */
232 printk(KERN_DEBUG "Local i960 firmware missing");
233 return -ENODEV;
234 }
235 return 0;
236 }
237
238 /*
239 * Some PCI serial cards using the PLX 9050 PCI interface chip require
240 * that the card interrupt be explicitly enabled or disabled. This
241 * seems to be mainly needed on card using the PLX which also use I/O
242 * mapped memory.
243 */
244 static int pci_plx9050_init(struct pci_dev *dev)
245 {
246 u8 irq_config;
247 void __iomem *p;
248
249 if ((pci_resource_flags(dev, 0) & IORESOURCE_MEM) == 0) {
250 moan_device("no memory in bar 0", dev);
251 return 0;
252 }
253
254 irq_config = 0x41;
255 if (dev->vendor == PCI_VENDOR_ID_PANACOM ||
256 dev->subsystem_vendor == PCI_SUBVENDOR_ID_EXSYS)
257 irq_config = 0x43;
258
259 if ((dev->vendor == PCI_VENDOR_ID_PLX) &&
260 (dev->device == PCI_DEVICE_ID_PLX_ROMULUS))
261 /*
262 * As the megawolf cards have the int pins active
263 * high, and have 2 UART chips, both ints must be
264 * enabled on the 9050. Also, the UARTS are set in
265 * 16450 mode by default, so we have to enable the
266 * 16C950 'enhanced' mode so that we can use the
267 * deep FIFOs
268 */
269 irq_config = 0x5b;
270 /*
271 * enable/disable interrupts
272 */
273 p = ioremap_nocache(pci_resource_start(dev, 0), 0x80);
274 if (p == NULL)
275 return -ENOMEM;
276 writel(irq_config, p + 0x4c);
277
278 /*
279 * Read the register back to ensure that it took effect.
280 */
281 readl(p + 0x4c);
282 iounmap(p);
283
284 return 0;
285 }
286
287 static void __devexit pci_plx9050_exit(struct pci_dev *dev)
288 {
289 u8 __iomem *p;
290
291 if ((pci_resource_flags(dev, 0) & IORESOURCE_MEM) == 0)
292 return;
293
294 /*
295 * disable interrupts
296 */
297 p = ioremap_nocache(pci_resource_start(dev, 0), 0x80);
298 if (p != NULL) {
299 writel(0, p + 0x4c);
300
301 /*
302 * Read the register back to ensure that it took effect.
303 */
304 readl(p + 0x4c);
305 iounmap(p);
306 }
307 }
308
309 #define NI8420_INT_ENABLE_REG 0x38
310 #define NI8420_INT_ENABLE_BIT 0x2000
311
312 static void __devexit pci_ni8420_exit(struct pci_dev *dev)
313 {
314 void __iomem *p;
315 unsigned long base, len;
316 unsigned int bar = 0;
317
318 if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) {
319 moan_device("no memory in bar", dev);
320 return;
321 }
322
323 base = pci_resource_start(dev, bar);
324 len = pci_resource_len(dev, bar);
325 p = ioremap_nocache(base, len);
326 if (p == NULL)
327 return;
328
329 /* Disable the CPU Interrupt */
330 writel(readl(p + NI8420_INT_ENABLE_REG) & ~(NI8420_INT_ENABLE_BIT),
331 p + NI8420_INT_ENABLE_REG);
332 iounmap(p);
333 }
334
335
336 /* MITE registers */
337 #define MITE_IOWBSR1 0xc4
338 #define MITE_IOWCR1 0xf4
339 #define MITE_LCIMR1 0x08
340 #define MITE_LCIMR2 0x10
341
342 #define MITE_LCIMR2_CLR_CPU_IE (1 << 30)
343
344 static void __devexit pci_ni8430_exit(struct pci_dev *dev)
345 {
346 void __iomem *p;
347 unsigned long base, len;
348 unsigned int bar = 0;
349
350 if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) {
351 moan_device("no memory in bar", dev);
352 return;
353 }
354
355 base = pci_resource_start(dev, bar);
356 len = pci_resource_len(dev, bar);
357 p = ioremap_nocache(base, len);
358 if (p == NULL)
359 return;
360
361 /* Disable the CPU Interrupt */
362 writel(MITE_LCIMR2_CLR_CPU_IE, p + MITE_LCIMR2);
363 iounmap(p);
364 }
365
366 /* SBS Technologies Inc. PMC-OCTPRO and P-OCTAL cards */
367 static int
368 sbs_setup(struct serial_private *priv, const struct pciserial_board *board,
369 struct uart_port *port, int idx)
370 {
371 unsigned int bar, offset = board->first_offset;
372
373 bar = 0;
374
375 if (idx < 4) {
376 /* first four channels map to 0, 0x100, 0x200, 0x300 */
377 offset += idx * board->uart_offset;
378 } else if (idx < 8) {
379 /* last four channels map to 0x1000, 0x1100, 0x1200, 0x1300 */
380 offset += idx * board->uart_offset + 0xC00;
381 } else /* we have only 8 ports on PMC-OCTALPRO */
382 return 1;
383
384 return setup_port(priv, port, bar, offset, board->reg_shift);
385 }
386
387 /*
388 * This does initialization for PMC OCTALPRO cards:
389 * maps the device memory, resets the UARTs (needed, bc
390 * if the module is removed and inserted again, the card
391 * is in the sleep mode) and enables global interrupt.
392 */
393
394 /* global control register offset for SBS PMC-OctalPro */
395 #define OCT_REG_CR_OFF 0x500
396
397 static int sbs_init(struct pci_dev *dev)
398 {
399 u8 __iomem *p;
400
401 p = ioremap_nocache(pci_resource_start(dev, 0),
402 pci_resource_len(dev, 0));
403
404 if (p == NULL)
405 return -ENOMEM;
406 /* Set bit-4 Control Register (UART RESET) in to reset the uarts */
407 writeb(0x10, p + OCT_REG_CR_OFF);
408 udelay(50);
409 writeb(0x0, p + OCT_REG_CR_OFF);
410
411 /* Set bit-2 (INTENABLE) of Control Register */
412 writeb(0x4, p + OCT_REG_CR_OFF);
413 iounmap(p);
414
415 return 0;
416 }
417
418 /*
419 * Disables the global interrupt of PMC-OctalPro
420 */
421
422 static void __devexit sbs_exit(struct pci_dev *dev)
423 {
424 u8 __iomem *p;
425
426 p = ioremap_nocache(pci_resource_start(dev, 0),
427 pci_resource_len(dev, 0));
428 /* FIXME: What if resource_len < OCT_REG_CR_OFF */
429 if (p != NULL)
430 writeb(0, p + OCT_REG_CR_OFF);
431 iounmap(p);
432 }
433
434 /*
435 * SIIG serial cards have an PCI interface chip which also controls
436 * the UART clocking frequency. Each UART can be clocked independently
437 * (except cards equiped with 4 UARTs) and initial clocking settings
438 * are stored in the EEPROM chip. It can cause problems because this
439 * version of serial driver doesn't support differently clocked UART's
440 * on single PCI card. To prevent this, initialization functions set
441 * high frequency clocking for all UART's on given card. It is safe (I
442 * hope) because it doesn't touch EEPROM settings to prevent conflicts
443 * with other OSes (like M$ DOS).
444 *
445 * SIIG support added by Andrey Panin <pazke@donpac.ru>, 10/1999
446 *
447 * There is two family of SIIG serial cards with different PCI
448 * interface chip and different configuration methods:
449 * - 10x cards have control registers in IO and/or memory space;
450 * - 20x cards have control registers in standard PCI configuration space.
451 *
452 * Note: all 10x cards have PCI device ids 0x10..
453 * all 20x cards have PCI device ids 0x20..
454 *
455 * There are also Quartet Serial cards which use Oxford Semiconductor
456 * 16954 quad UART PCI chip clocked by 18.432 MHz quartz.
457 *
458 * Note: some SIIG cards are probed by the parport_serial object.
459 */
460
461 #define PCI_DEVICE_ID_SIIG_1S_10x (PCI_DEVICE_ID_SIIG_1S_10x_550 & 0xfffc)
462 #define PCI_DEVICE_ID_SIIG_2S_10x (PCI_DEVICE_ID_SIIG_2S_10x_550 & 0xfff8)
463
464 static int pci_siig10x_init(struct pci_dev *dev)
465 {
466 u16 data;
467 void __iomem *p;
468
469 switch (dev->device & 0xfff8) {
470 case PCI_DEVICE_ID_SIIG_1S_10x: /* 1S */
471 data = 0xffdf;
472 break;
473 case PCI_DEVICE_ID_SIIG_2S_10x: /* 2S, 2S1P */
474 data = 0xf7ff;
475 break;
476 default: /* 1S1P, 4S */
477 data = 0xfffb;
478 break;
479 }
480
481 p = ioremap_nocache(pci_resource_start(dev, 0), 0x80);
482 if (p == NULL)
483 return -ENOMEM;
484
485 writew(readw(p + 0x28) & data, p + 0x28);
486 readw(p + 0x28);
487 iounmap(p);
488 return 0;
489 }
490
491 #define PCI_DEVICE_ID_SIIG_2S_20x (PCI_DEVICE_ID_SIIG_2S_20x_550 & 0xfffc)
492 #define PCI_DEVICE_ID_SIIG_2S1P_20x (PCI_DEVICE_ID_SIIG_2S1P_20x_550 & 0xfffc)
493
494 static int pci_siig20x_init(struct pci_dev *dev)
495 {
496 u8 data;
497
498 /* Change clock frequency for the first UART. */
499 pci_read_config_byte(dev, 0x6f, &data);
500 pci_write_config_byte(dev, 0x6f, data & 0xef);
501
502 /* If this card has 2 UART, we have to do the same with second UART. */
503 if (((dev->device & 0xfffc) == PCI_DEVICE_ID_SIIG_2S_20x) ||
504 ((dev->device & 0xfffc) == PCI_DEVICE_ID_SIIG_2S1P_20x)) {
505 pci_read_config_byte(dev, 0x73, &data);
506 pci_write_config_byte(dev, 0x73, data & 0xef);
507 }
508 return 0;
509 }
510
511 static int pci_siig_init(struct pci_dev *dev)
512 {
513 unsigned int type = dev->device & 0xff00;
514
515 if (type == 0x1000)
516 return pci_siig10x_init(dev);
517 else if (type == 0x2000)
518 return pci_siig20x_init(dev);
519
520 moan_device("Unknown SIIG card", dev);
521 return -ENODEV;
522 }
523
524 static int pci_siig_setup(struct serial_private *priv,
525 const struct pciserial_board *board,
526 struct uart_port *port, int idx)
527 {
528 unsigned int bar = FL_GET_BASE(board->flags) + idx, offset = 0;
529
530 if (idx > 3) {
531 bar = 4;
532 offset = (idx - 4) * 8;
533 }
534
535 return setup_port(priv, port, bar, offset, 0);
536 }
537
538 /*
539 * Timedia has an explosion of boards, and to avoid the PCI table from
540 * growing *huge*, we use this function to collapse some 70 entries
541 * in the PCI table into one, for sanity's and compactness's sake.
542 */
543 static const unsigned short timedia_single_port[] = {
544 0x4025, 0x4027, 0x4028, 0x5025, 0x5027, 0
545 };
546
547 static const unsigned short timedia_dual_port[] = {
548 0x0002, 0x4036, 0x4037, 0x4038, 0x4078, 0x4079, 0x4085,
549 0x4088, 0x4089, 0x5037, 0x5078, 0x5079, 0x5085, 0x6079,
550 0x7079, 0x8079, 0x8137, 0x8138, 0x8237, 0x8238, 0x9079,
551 0x9137, 0x9138, 0x9237, 0x9238, 0xA079, 0xB079, 0xC079,
552 0xD079, 0
553 };
554
555 static const unsigned short timedia_quad_port[] = {
556 0x4055, 0x4056, 0x4095, 0x4096, 0x5056, 0x8156, 0x8157,
557 0x8256, 0x8257, 0x9056, 0x9156, 0x9157, 0x9158, 0x9159,
558 0x9256, 0x9257, 0xA056, 0xA157, 0xA158, 0xA159, 0xB056,
559 0xB157, 0
560 };
561
562 static const unsigned short timedia_eight_port[] = {
563 0x4065, 0x4066, 0x5065, 0x5066, 0x8166, 0x9066, 0x9166,
564 0x9167, 0x9168, 0xA066, 0xA167, 0xA168, 0
565 };
566
567 static const struct timedia_struct {
568 int num;
569 const unsigned short *ids;
570 } timedia_data[] = {
571 { 1, timedia_single_port },
572 { 2, timedia_dual_port },
573 { 4, timedia_quad_port },
574 { 8, timedia_eight_port }
575 };
576
577 static int pci_timedia_init(struct pci_dev *dev)
578 {
579 const unsigned short *ids;
580 int i, j;
581
582 for (i = 0; i < ARRAY_SIZE(timedia_data); i++) {
583 ids = timedia_data[i].ids;
584 for (j = 0; ids[j]; j++)
585 if (dev->subsystem_device == ids[j])
586 return timedia_data[i].num;
587 }
588 return 0;
589 }
590
591 /*
592 * Timedia/SUNIX uses a mixture of BARs and offsets
593 * Ugh, this is ugly as all hell --- TYT
594 */
595 static int
596 pci_timedia_setup(struct serial_private *priv,
597 const struct pciserial_board *board,
598 struct uart_port *port, int idx)
599 {
600 unsigned int bar = 0, offset = board->first_offset;
601
602 switch (idx) {
603 case 0:
604 bar = 0;
605 break;
606 case 1:
607 offset = board->uart_offset;
608 bar = 0;
609 break;
610 case 2:
611 bar = 1;
612 break;
613 case 3:
614 offset = board->uart_offset;
615 /* FALLTHROUGH */
616 case 4: /* BAR 2 */
617 case 5: /* BAR 3 */
618 case 6: /* BAR 4 */
619 case 7: /* BAR 5 */
620 bar = idx - 2;
621 }
622
623 return setup_port(priv, port, bar, offset, board->reg_shift);
624 }
625
626 /*
627 * Some Titan cards are also a little weird
628 */
629 static int
630 titan_400l_800l_setup(struct serial_private *priv,
631 const struct pciserial_board *board,
632 struct uart_port *port, int idx)
633 {
634 unsigned int bar, offset = board->first_offset;
635
636 switch (idx) {
637 case 0:
638 bar = 1;
639 break;
640 case 1:
641 bar = 2;
642 break;
643 default:
644 bar = 4;
645 offset = (idx - 2) * board->uart_offset;
646 }
647
648 return setup_port(priv, port, bar, offset, board->reg_shift);
649 }
650
651 static int pci_xircom_init(struct pci_dev *dev)
652 {
653 msleep(100);
654 return 0;
655 }
656
657 static int pci_ni8420_init(struct pci_dev *dev)
658 {
659 void __iomem *p;
660 unsigned long base, len;
661 unsigned int bar = 0;
662
663 if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) {
664 moan_device("no memory in bar", dev);
665 return 0;
666 }
667
668 base = pci_resource_start(dev, bar);
669 len = pci_resource_len(dev, bar);
670 p = ioremap_nocache(base, len);
671 if (p == NULL)
672 return -ENOMEM;
673
674 /* Enable CPU Interrupt */
675 writel(readl(p + NI8420_INT_ENABLE_REG) | NI8420_INT_ENABLE_BIT,
676 p + NI8420_INT_ENABLE_REG);
677
678 iounmap(p);
679 return 0;
680 }
681
682 #define MITE_IOWBSR1_WSIZE 0xa
683 #define MITE_IOWBSR1_WIN_OFFSET 0x800
684 #define MITE_IOWBSR1_WENAB (1 << 7)
685 #define MITE_LCIMR1_IO_IE_0 (1 << 24)
686 #define MITE_LCIMR2_SET_CPU_IE (1 << 31)
687 #define MITE_IOWCR1_RAMSEL_MASK 0xfffffffe
688
689 static int pci_ni8430_init(struct pci_dev *dev)
690 {
691 void __iomem *p;
692 unsigned long base, len;
693 u32 device_window;
694 unsigned int bar = 0;
695
696 if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) {
697 moan_device("no memory in bar", dev);
698 return 0;
699 }
700
701 base = pci_resource_start(dev, bar);
702 len = pci_resource_len(dev, bar);
703 p = ioremap_nocache(base, len);
704 if (p == NULL)
705 return -ENOMEM;
706
707 /* Set device window address and size in BAR0 */
708 device_window = ((base + MITE_IOWBSR1_WIN_OFFSET) & 0xffffff00)
709 | MITE_IOWBSR1_WENAB | MITE_IOWBSR1_WSIZE;
710 writel(device_window, p + MITE_IOWBSR1);
711
712 /* Set window access to go to RAMSEL IO address space */
713 writel((readl(p + MITE_IOWCR1) & MITE_IOWCR1_RAMSEL_MASK),
714 p + MITE_IOWCR1);
715
716 /* Enable IO Bus Interrupt 0 */
717 writel(MITE_LCIMR1_IO_IE_0, p + MITE_LCIMR1);
718
719 /* Enable CPU Interrupt */
720 writel(MITE_LCIMR2_SET_CPU_IE, p + MITE_LCIMR2);
721
722 iounmap(p);
723 return 0;
724 }
725
726 /* UART Port Control Register */
727 #define NI8430_PORTCON 0x0f
728 #define NI8430_PORTCON_TXVR_ENABLE (1 << 3)
729
730 static int
731 pci_ni8430_setup(struct serial_private *priv,
732 const struct pciserial_board *board,
733 struct uart_port *port, int idx)
734 {
735 void __iomem *p;
736 unsigned long base, len;
737 unsigned int bar, offset = board->first_offset;
738
739 if (idx >= board->num_ports)
740 return 1;
741
742 bar = FL_GET_BASE(board->flags);
743 offset += idx * board->uart_offset;
744
745 base = pci_resource_start(priv->dev, bar);
746 len = pci_resource_len(priv->dev, bar);
747 p = ioremap_nocache(base, len);
748
749 /* enable the transciever */
750 writeb(readb(p + offset + NI8430_PORTCON) | NI8430_PORTCON_TXVR_ENABLE,
751 p + offset + NI8430_PORTCON);
752
753 iounmap(p);
754
755 return setup_port(priv, port, bar, offset, board->reg_shift);
756 }
757
758
759 static int pci_netmos_init(struct pci_dev *dev)
760 {
761 /* subdevice 0x00PS means <P> parallel, <S> serial */
762 unsigned int num_serial = dev->subsystem_device & 0xf;
763
764 if (dev->subsystem_vendor == PCI_VENDOR_ID_IBM &&
765 dev->subsystem_device == 0x0299)
766 return 0;
767
768 if (num_serial == 0)
769 return -ENODEV;
770 return num_serial;
771 }
772
773 /*
774 * ITE support by Niels de Vos <niels.devos@wincor-nixdorf.com>
775 *
776 * These chips are available with optionally one parallel port and up to
777 * two serial ports. Unfortunately they all have the same product id.
778 *
779 * Basic configuration is done over a region of 32 I/O ports. The base
780 * ioport is called INTA or INTC, depending on docs/other drivers.
781 *
782 * The region of the 32 I/O ports is configured in POSIO0R...
783 */
784
785 /* registers */
786 #define ITE_887x_MISCR 0x9c
787 #define ITE_887x_INTCBAR 0x78
788 #define ITE_887x_UARTBAR 0x7c
789 #define ITE_887x_PS0BAR 0x10
790 #define ITE_887x_POSIO0 0x60
791
792 /* I/O space size */
793 #define ITE_887x_IOSIZE 32
794 /* I/O space size (bits 26-24; 8 bytes = 011b) */
795 #define ITE_887x_POSIO_IOSIZE_8 (3 << 24)
796 /* I/O space size (bits 26-24; 32 bytes = 101b) */
797 #define ITE_887x_POSIO_IOSIZE_32 (5 << 24)
798 /* Decoding speed (1 = slow, 2 = medium, 3 = fast) */
799 #define ITE_887x_POSIO_SPEED (3 << 29)
800 /* enable IO_Space bit */
801 #define ITE_887x_POSIO_ENABLE (1 << 31)
802
803 static int pci_ite887x_init(struct pci_dev *dev)
804 {
805 /* inta_addr are the configuration addresses of the ITE */
806 static const short inta_addr[] = { 0x2a0, 0x2c0, 0x220, 0x240, 0x1e0,
807 0x200, 0x280, 0 };
808 int ret, i, type;
809 struct resource *iobase = NULL;
810 u32 miscr, uartbar, ioport;
811
812 /* search for the base-ioport */
813 i = 0;
814 while (inta_addr[i] && iobase == NULL) {
815 iobase = request_region(inta_addr[i], ITE_887x_IOSIZE,
816 "ite887x");
817 if (iobase != NULL) {
818 /* write POSIO0R - speed | size | ioport */
819 pci_write_config_dword(dev, ITE_887x_POSIO0,
820 ITE_887x_POSIO_ENABLE | ITE_887x_POSIO_SPEED |
821 ITE_887x_POSIO_IOSIZE_32 | inta_addr[i]);
822 /* write INTCBAR - ioport */
823 pci_write_config_dword(dev, ITE_887x_INTCBAR,
824 inta_addr[i]);
825 ret = inb(inta_addr[i]);
826 if (ret != 0xff) {
827 /* ioport connected */
828 break;
829 }
830 release_region(iobase->start, ITE_887x_IOSIZE);
831 iobase = NULL;
832 }
833 i++;
834 }
835
836 if (!inta_addr[i]) {
837 printk(KERN_ERR "ite887x: could not find iobase\n");
838 return -ENODEV;
839 }
840
841 /* start of undocumented type checking (see parport_pc.c) */
842 type = inb(iobase->start + 0x18) & 0x0f;
843
844 switch (type) {
845 case 0x2: /* ITE8871 (1P) */
846 case 0xa: /* ITE8875 (1P) */
847 ret = 0;
848 break;
849 case 0xe: /* ITE8872 (2S1P) */
850 ret = 2;
851 break;
852 case 0x6: /* ITE8873 (1S) */
853 ret = 1;
854 break;
855 case 0x8: /* ITE8874 (2S) */
856 ret = 2;
857 break;
858 default:
859 moan_device("Unknown ITE887x", dev);
860 ret = -ENODEV;
861 }
862
863 /* configure all serial ports */
864 for (i = 0; i < ret; i++) {
865 /* read the I/O port from the device */
866 pci_read_config_dword(dev, ITE_887x_PS0BAR + (0x4 * (i + 1)),
867 &ioport);
868 ioport &= 0x0000FF00; /* the actual base address */
869 pci_write_config_dword(dev, ITE_887x_POSIO0 + (0x4 * (i + 1)),
870 ITE_887x_POSIO_ENABLE | ITE_887x_POSIO_SPEED |
871 ITE_887x_POSIO_IOSIZE_8 | ioport);
872
873 /* write the ioport to the UARTBAR */
874 pci_read_config_dword(dev, ITE_887x_UARTBAR, &uartbar);
875 uartbar &= ~(0xffff << (16 * i)); /* clear half the reg */
876 uartbar |= (ioport << (16 * i)); /* set the ioport */
877 pci_write_config_dword(dev, ITE_887x_UARTBAR, uartbar);
878
879 /* get current config */
880 pci_read_config_dword(dev, ITE_887x_MISCR, &miscr);
881 /* disable interrupts (UARTx_Routing[3:0]) */
882 miscr &= ~(0xf << (12 - 4 * i));
883 /* activate the UART (UARTx_En) */
884 miscr |= 1 << (23 - i);
885 /* write new config with activated UART */
886 pci_write_config_dword(dev, ITE_887x_MISCR, miscr);
887 }
888
889 if (ret <= 0) {
890 /* the device has no UARTs if we get here */
891 release_region(iobase->start, ITE_887x_IOSIZE);
892 }
893
894 return ret;
895 }
896
897 static void __devexit pci_ite887x_exit(struct pci_dev *dev)
898 {
899 u32 ioport;
900 /* the ioport is bit 0-15 in POSIO0R */
901 pci_read_config_dword(dev, ITE_887x_POSIO0, &ioport);
902 ioport &= 0xffff;
903 release_region(ioport, ITE_887x_IOSIZE);
904 }
905
906 /*
907 * Oxford Semiconductor Inc.
908 * Check that device is part of the Tornado range of devices, then determine
909 * the number of ports available on the device.
910 */
911 static int pci_oxsemi_tornado_init(struct pci_dev *dev)
912 {
913 u8 __iomem *p;
914 unsigned long deviceID;
915 unsigned int number_uarts = 0;
916
917 /* OxSemi Tornado devices are all 0xCxxx */
918 if (dev->vendor == PCI_VENDOR_ID_OXSEMI &&
919 (dev->device & 0xF000) != 0xC000)
920 return 0;
921
922 p = pci_iomap(dev, 0, 5);
923 if (p == NULL)
924 return -ENOMEM;
925
926 deviceID = ioread32(p);
927 /* Tornado device */
928 if (deviceID == 0x07000200) {
929 number_uarts = ioread8(p + 4);
930 printk(KERN_DEBUG
931 "%d ports detected on Oxford PCI Express device\n",
932 number_uarts);
933 }
934 pci_iounmap(dev, p);
935 return number_uarts;
936 }
937
938 static int
939 pci_default_setup(struct serial_private *priv,
940 const struct pciserial_board *board,
941 struct uart_port *port, int idx)
942 {
943 unsigned int bar, offset = board->first_offset, maxnr;
944
945 bar = FL_GET_BASE(board->flags);
946 if (board->flags & FL_BASE_BARS)
947 bar += idx;
948 else
949 offset += idx * board->uart_offset;
950
951 maxnr = (pci_resource_len(priv->dev, bar) - board->first_offset) >>
952 (board->reg_shift + 3);
953
954 if (board->flags & FL_REGION_SZ_CAP && idx >= maxnr)
955 return 1;
956
957 return setup_port(priv, port, bar, offset, board->reg_shift);
958 }
959
960 static int skip_tx_en_setup(struct serial_private *priv,
961 const struct pciserial_board *board,
962 struct uart_port *port, int idx)
963 {
964 port->flags |= UPF_NO_TXEN_TEST;
965 printk(KERN_DEBUG "serial8250: skipping TxEn test for device "
966 "[%04x:%04x] subsystem [%04x:%04x]\n",
967 priv->dev->vendor,
968 priv->dev->device,
969 priv->dev->subsystem_vendor,
970 priv->dev->subsystem_device);
971
972 return pci_default_setup(priv, board, port, idx);
973 }
974
975 /* This should be in linux/pci_ids.h */
976 #define PCI_VENDOR_ID_SBSMODULARIO 0x124B
977 #define PCI_SUBVENDOR_ID_SBSMODULARIO 0x124B
978 #define PCI_DEVICE_ID_OCTPRO 0x0001
979 #define PCI_SUBDEVICE_ID_OCTPRO232 0x0108
980 #define PCI_SUBDEVICE_ID_OCTPRO422 0x0208
981 #define PCI_SUBDEVICE_ID_POCTAL232 0x0308
982 #define PCI_SUBDEVICE_ID_POCTAL422 0x0408
983 #define PCI_VENDOR_ID_ADVANTECH 0x13fe
984 #define PCI_DEVICE_ID_ADVANTECH_PCI3620 0x3620
985
986 /* Unknown vendors/cards - this should not be in linux/pci_ids.h */
987 #define PCI_SUBDEVICE_ID_UNKNOWN_0x1584 0x1584
988
989 /*
990 * Master list of serial port init/setup/exit quirks.
991 * This does not describe the general nature of the port.
992 * (ie, baud base, number and location of ports, etc)
993 *
994 * This list is ordered alphabetically by vendor then device.
995 * Specific entries must come before more generic entries.
996 */
997 static struct pci_serial_quirk pci_serial_quirks[] __refdata = {
998 /*
999 * ADDI-DATA GmbH communication cards <info@addi-data.com>
1000 */
1001 {
1002 .vendor = PCI_VENDOR_ID_ADDIDATA_OLD,
1003 .device = PCI_DEVICE_ID_ADDIDATA_APCI7800,
1004 .subvendor = PCI_ANY_ID,
1005 .subdevice = PCI_ANY_ID,
1006 .setup = addidata_apci7800_setup,
1007 },
1008 /*
1009 * AFAVLAB cards - these may be called via parport_serial
1010 * It is not clear whether this applies to all products.
1011 */
1012 {
1013 .vendor = PCI_VENDOR_ID_AFAVLAB,
1014 .device = PCI_ANY_ID,
1015 .subvendor = PCI_ANY_ID,
1016 .subdevice = PCI_ANY_ID,
1017 .setup = afavlab_setup,
1018 },
1019 /*
1020 * HP Diva
1021 */
1022 {
1023 .vendor = PCI_VENDOR_ID_HP,
1024 .device = PCI_DEVICE_ID_HP_DIVA,
1025 .subvendor = PCI_ANY_ID,
1026 .subdevice = PCI_ANY_ID,
1027 .init = pci_hp_diva_init,
1028 .setup = pci_hp_diva_setup,
1029 },
1030 /*
1031 * Intel
1032 */
1033 {
1034 .vendor = PCI_VENDOR_ID_INTEL,
1035 .device = PCI_DEVICE_ID_INTEL_80960_RP,
1036 .subvendor = 0xe4bf,
1037 .subdevice = PCI_ANY_ID,
1038 .init = pci_inteli960ni_init,
1039 .setup = pci_default_setup,
1040 },
1041 {
1042 .vendor = PCI_VENDOR_ID_INTEL,
1043 .device = PCI_DEVICE_ID_INTEL_8257X_SOL,
1044 .subvendor = PCI_ANY_ID,
1045 .subdevice = PCI_ANY_ID,
1046 .setup = skip_tx_en_setup,
1047 },
1048 {
1049 .vendor = PCI_VENDOR_ID_INTEL,
1050 .device = PCI_DEVICE_ID_INTEL_82573L_SOL,
1051 .subvendor = PCI_ANY_ID,
1052 .subdevice = PCI_ANY_ID,
1053 .setup = skip_tx_en_setup,
1054 },
1055 {
1056 .vendor = PCI_VENDOR_ID_INTEL,
1057 .device = PCI_DEVICE_ID_INTEL_82573E_SOL,
1058 .subvendor = PCI_ANY_ID,
1059 .subdevice = PCI_ANY_ID,
1060 .setup = skip_tx_en_setup,
1061 },
1062 /*
1063 * ITE
1064 */
1065 {
1066 .vendor = PCI_VENDOR_ID_ITE,
1067 .device = PCI_DEVICE_ID_ITE_8872,
1068 .subvendor = PCI_ANY_ID,
1069 .subdevice = PCI_ANY_ID,
1070 .init = pci_ite887x_init,
1071 .setup = pci_default_setup,
1072 .exit = __devexit_p(pci_ite887x_exit),
1073 },
1074 /*
1075 * National Instruments
1076 */
1077 {
1078 .vendor = PCI_VENDOR_ID_NI,
1079 .device = PCI_DEVICE_ID_NI_PCI23216,
1080 .subvendor = PCI_ANY_ID,
1081 .subdevice = PCI_ANY_ID,
1082 .init = pci_ni8420_init,
1083 .setup = pci_default_setup,
1084 .exit = __devexit_p(pci_ni8420_exit),
1085 },
1086 {
1087 .vendor = PCI_VENDOR_ID_NI,
1088 .device = PCI_DEVICE_ID_NI_PCI2328,
1089 .subvendor = PCI_ANY_ID,
1090 .subdevice = PCI_ANY_ID,
1091 .init = pci_ni8420_init,
1092 .setup = pci_default_setup,
1093 .exit = __devexit_p(pci_ni8420_exit),
1094 },
1095 {
1096 .vendor = PCI_VENDOR_ID_NI,
1097 .device = PCI_DEVICE_ID_NI_PCI2324,
1098 .subvendor = PCI_ANY_ID,
1099 .subdevice = PCI_ANY_ID,
1100 .init = pci_ni8420_init,
1101 .setup = pci_default_setup,
1102 .exit = __devexit_p(pci_ni8420_exit),
1103 },
1104 {
1105 .vendor = PCI_VENDOR_ID_NI,
1106 .device = PCI_DEVICE_ID_NI_PCI2322,
1107 .subvendor = PCI_ANY_ID,
1108 .subdevice = PCI_ANY_ID,
1109 .init = pci_ni8420_init,
1110 .setup = pci_default_setup,
1111 .exit = __devexit_p(pci_ni8420_exit),
1112 },
1113 {
1114 .vendor = PCI_VENDOR_ID_NI,
1115 .device = PCI_DEVICE_ID_NI_PCI2324I,
1116 .subvendor = PCI_ANY_ID,
1117 .subdevice = PCI_ANY_ID,
1118 .init = pci_ni8420_init,
1119 .setup = pci_default_setup,
1120 .exit = __devexit_p(pci_ni8420_exit),
1121 },
1122 {
1123 .vendor = PCI_VENDOR_ID_NI,
1124 .device = PCI_DEVICE_ID_NI_PCI2322I,
1125 .subvendor = PCI_ANY_ID,
1126 .subdevice = PCI_ANY_ID,
1127 .init = pci_ni8420_init,
1128 .setup = pci_default_setup,
1129 .exit = __devexit_p(pci_ni8420_exit),
1130 },
1131 {
1132 .vendor = PCI_VENDOR_ID_NI,
1133 .device = PCI_DEVICE_ID_NI_PXI8420_23216,
1134 .subvendor = PCI_ANY_ID,
1135 .subdevice = PCI_ANY_ID,
1136 .init = pci_ni8420_init,
1137 .setup = pci_default_setup,
1138 .exit = __devexit_p(pci_ni8420_exit),
1139 },
1140 {
1141 .vendor = PCI_VENDOR_ID_NI,
1142 .device = PCI_DEVICE_ID_NI_PXI8420_2328,
1143 .subvendor = PCI_ANY_ID,
1144 .subdevice = PCI_ANY_ID,
1145 .init = pci_ni8420_init,
1146 .setup = pci_default_setup,
1147 .exit = __devexit_p(pci_ni8420_exit),
1148 },
1149 {
1150 .vendor = PCI_VENDOR_ID_NI,
1151 .device = PCI_DEVICE_ID_NI_PXI8420_2324,
1152 .subvendor = PCI_ANY_ID,
1153 .subdevice = PCI_ANY_ID,
1154 .init = pci_ni8420_init,
1155 .setup = pci_default_setup,
1156 .exit = __devexit_p(pci_ni8420_exit),
1157 },
1158 {
1159 .vendor = PCI_VENDOR_ID_NI,
1160 .device = PCI_DEVICE_ID_NI_PXI8420_2322,
1161 .subvendor = PCI_ANY_ID,
1162 .subdevice = PCI_ANY_ID,
1163 .init = pci_ni8420_init,
1164 .setup = pci_default_setup,
1165 .exit = __devexit_p(pci_ni8420_exit),
1166 },
1167 {
1168 .vendor = PCI_VENDOR_ID_NI,
1169 .device = PCI_DEVICE_ID_NI_PXI8422_2324,
1170 .subvendor = PCI_ANY_ID,
1171 .subdevice = PCI_ANY_ID,
1172 .init = pci_ni8420_init,
1173 .setup = pci_default_setup,
1174 .exit = __devexit_p(pci_ni8420_exit),
1175 },
1176 {
1177 .vendor = PCI_VENDOR_ID_NI,
1178 .device = PCI_DEVICE_ID_NI_PXI8422_2322,
1179 .subvendor = PCI_ANY_ID,
1180 .subdevice = PCI_ANY_ID,
1181 .init = pci_ni8420_init,
1182 .setup = pci_default_setup,
1183 .exit = __devexit_p(pci_ni8420_exit),
1184 },
1185 {
1186 .vendor = PCI_VENDOR_ID_NI,
1187 .device = PCI_ANY_ID,
1188 .subvendor = PCI_ANY_ID,
1189 .subdevice = PCI_ANY_ID,
1190 .init = pci_ni8430_init,
1191 .setup = pci_ni8430_setup,
1192 .exit = __devexit_p(pci_ni8430_exit),
1193 },
1194 /*
1195 * Panacom
1196 */
1197 {
1198 .vendor = PCI_VENDOR_ID_PANACOM,
1199 .device = PCI_DEVICE_ID_PANACOM_QUADMODEM,
1200 .subvendor = PCI_ANY_ID,
1201 .subdevice = PCI_ANY_ID,
1202 .init = pci_plx9050_init,
1203 .setup = pci_default_setup,
1204 .exit = __devexit_p(pci_plx9050_exit),
1205 },
1206 {
1207 .vendor = PCI_VENDOR_ID_PANACOM,
1208 .device = PCI_DEVICE_ID_PANACOM_DUALMODEM,
1209 .subvendor = PCI_ANY_ID,
1210 .subdevice = PCI_ANY_ID,
1211 .init = pci_plx9050_init,
1212 .setup = pci_default_setup,
1213 .exit = __devexit_p(pci_plx9050_exit),
1214 },
1215 /*
1216 * PLX
1217 */
1218 {
1219 .vendor = PCI_VENDOR_ID_PLX,
1220 .device = PCI_DEVICE_ID_PLX_9030,
1221 .subvendor = PCI_SUBVENDOR_ID_PERLE,
1222 .subdevice = PCI_ANY_ID,
1223 .setup = pci_default_setup,
1224 },
1225 {
1226 .vendor = PCI_VENDOR_ID_PLX,
1227 .device = PCI_DEVICE_ID_PLX_9050,
1228 .subvendor = PCI_SUBVENDOR_ID_EXSYS,
1229 .subdevice = PCI_SUBDEVICE_ID_EXSYS_4055,
1230 .init = pci_plx9050_init,
1231 .setup = pci_default_setup,
1232 .exit = __devexit_p(pci_plx9050_exit),
1233 },
1234 {
1235 .vendor = PCI_VENDOR_ID_PLX,
1236 .device = PCI_DEVICE_ID_PLX_9050,
1237 .subvendor = PCI_SUBVENDOR_ID_KEYSPAN,
1238 .subdevice = PCI_SUBDEVICE_ID_KEYSPAN_SX2,
1239 .init = pci_plx9050_init,
1240 .setup = pci_default_setup,
1241 .exit = __devexit_p(pci_plx9050_exit),
1242 },
1243 {
1244 .vendor = PCI_VENDOR_ID_PLX,
1245 .device = PCI_DEVICE_ID_PLX_9050,
1246 .subvendor = PCI_VENDOR_ID_PLX,
1247 .subdevice = PCI_SUBDEVICE_ID_UNKNOWN_0x1584,
1248 .init = pci_plx9050_init,
1249 .setup = pci_default_setup,
1250 .exit = __devexit_p(pci_plx9050_exit),
1251 },
1252 {
1253 .vendor = PCI_VENDOR_ID_PLX,
1254 .device = PCI_DEVICE_ID_PLX_ROMULUS,
1255 .subvendor = PCI_VENDOR_ID_PLX,
1256 .subdevice = PCI_DEVICE_ID_PLX_ROMULUS,
1257 .init = pci_plx9050_init,
1258 .setup = pci_default_setup,
1259 .exit = __devexit_p(pci_plx9050_exit),
1260 },
1261 /*
1262 * SBS Technologies, Inc., PMC-OCTALPRO 232
1263 */
1264 {
1265 .vendor = PCI_VENDOR_ID_SBSMODULARIO,
1266 .device = PCI_DEVICE_ID_OCTPRO,
1267 .subvendor = PCI_SUBVENDOR_ID_SBSMODULARIO,
1268 .subdevice = PCI_SUBDEVICE_ID_OCTPRO232,
1269 .init = sbs_init,
1270 .setup = sbs_setup,
1271 .exit = __devexit_p(sbs_exit),
1272 },
1273 /*
1274 * SBS Technologies, Inc., PMC-OCTALPRO 422
1275 */
1276 {
1277 .vendor = PCI_VENDOR_ID_SBSMODULARIO,
1278 .device = PCI_DEVICE_ID_OCTPRO,
1279 .subvendor = PCI_SUBVENDOR_ID_SBSMODULARIO,
1280 .subdevice = PCI_SUBDEVICE_ID_OCTPRO422,
1281 .init = sbs_init,
1282 .setup = sbs_setup,
1283 .exit = __devexit_p(sbs_exit),
1284 },
1285 /*
1286 * SBS Technologies, Inc., P-Octal 232
1287 */
1288 {
1289 .vendor = PCI_VENDOR_ID_SBSMODULARIO,
1290 .device = PCI_DEVICE_ID_OCTPRO,
1291 .subvendor = PCI_SUBVENDOR_ID_SBSMODULARIO,
1292 .subdevice = PCI_SUBDEVICE_ID_POCTAL232,
1293 .init = sbs_init,
1294 .setup = sbs_setup,
1295 .exit = __devexit_p(sbs_exit),
1296 },
1297 /*
1298 * SBS Technologies, Inc., P-Octal 422
1299 */
1300 {
1301 .vendor = PCI_VENDOR_ID_SBSMODULARIO,
1302 .device = PCI_DEVICE_ID_OCTPRO,
1303 .subvendor = PCI_SUBVENDOR_ID_SBSMODULARIO,
1304 .subdevice = PCI_SUBDEVICE_ID_POCTAL422,
1305 .init = sbs_init,
1306 .setup = sbs_setup,
1307 .exit = __devexit_p(sbs_exit),
1308 },
1309 /*
1310 * SIIG cards - these may be called via parport_serial
1311 */
1312 {
1313 .vendor = PCI_VENDOR_ID_SIIG,
1314 .device = PCI_ANY_ID,
1315 .subvendor = PCI_ANY_ID,
1316 .subdevice = PCI_ANY_ID,
1317 .init = pci_siig_init,
1318 .setup = pci_siig_setup,
1319 },
1320 /*
1321 * Titan cards
1322 */
1323 {
1324 .vendor = PCI_VENDOR_ID_TITAN,
1325 .device = PCI_DEVICE_ID_TITAN_400L,
1326 .subvendor = PCI_ANY_ID,
1327 .subdevice = PCI_ANY_ID,
1328 .setup = titan_400l_800l_setup,
1329 },
1330 {
1331 .vendor = PCI_VENDOR_ID_TITAN,
1332 .device = PCI_DEVICE_ID_TITAN_800L,
1333 .subvendor = PCI_ANY_ID,
1334 .subdevice = PCI_ANY_ID,
1335 .setup = titan_400l_800l_setup,
1336 },
1337 /*
1338 * Timedia cards
1339 */
1340 {
1341 .vendor = PCI_VENDOR_ID_TIMEDIA,
1342 .device = PCI_DEVICE_ID_TIMEDIA_1889,
1343 .subvendor = PCI_VENDOR_ID_TIMEDIA,
1344 .subdevice = PCI_ANY_ID,
1345 .init = pci_timedia_init,
1346 .setup = pci_timedia_setup,
1347 },
1348 {
1349 .vendor = PCI_VENDOR_ID_TIMEDIA,
1350 .device = PCI_ANY_ID,
1351 .subvendor = PCI_ANY_ID,
1352 .subdevice = PCI_ANY_ID,
1353 .setup = pci_timedia_setup,
1354 },
1355 /*
1356 * Xircom cards
1357 */
1358 {
1359 .vendor = PCI_VENDOR_ID_XIRCOM,
1360 .device = PCI_DEVICE_ID_XIRCOM_X3201_MDM,
1361 .subvendor = PCI_ANY_ID,
1362 .subdevice = PCI_ANY_ID,
1363 .init = pci_xircom_init,
1364 .setup = pci_default_setup,
1365 },
1366 /*
1367 * Netmos cards - these may be called via parport_serial
1368 */
1369 {
1370 .vendor = PCI_VENDOR_ID_NETMOS,
1371 .device = PCI_ANY_ID,
1372 .subvendor = PCI_ANY_ID,
1373 .subdevice = PCI_ANY_ID,
1374 .init = pci_netmos_init,
1375 .setup = pci_default_setup,
1376 },
1377 /*
1378 * For Oxford Semiconductor and Mainpine
1379 */
1380 {
1381 .vendor = PCI_VENDOR_ID_OXSEMI,
1382 .device = PCI_ANY_ID,
1383 .subvendor = PCI_ANY_ID,
1384 .subdevice = PCI_ANY_ID,
1385 .init = pci_oxsemi_tornado_init,
1386 .setup = pci_default_setup,
1387 },
1388 {
1389 .vendor = PCI_VENDOR_ID_MAINPINE,
1390 .device = PCI_ANY_ID,
1391 .subvendor = PCI_ANY_ID,
1392 .subdevice = PCI_ANY_ID,
1393 .init = pci_oxsemi_tornado_init,
1394 .setup = pci_default_setup,
1395 },
1396 /*
1397 * Default "match everything" terminator entry
1398 */
1399 {
1400 .vendor = PCI_ANY_ID,
1401 .device = PCI_ANY_ID,
1402 .subvendor = PCI_ANY_ID,
1403 .subdevice = PCI_ANY_ID,
1404 .setup = pci_default_setup,
1405 }
1406 };
1407
1408 static inline int quirk_id_matches(u32 quirk_id, u32 dev_id)
1409 {
1410 return quirk_id == PCI_ANY_ID || quirk_id == dev_id;
1411 }
1412
1413 static struct pci_serial_quirk *find_quirk(struct pci_dev *dev)
1414 {
1415 struct pci_serial_quirk *quirk;
1416
1417 for (quirk = pci_serial_quirks; ; quirk++)
1418 if (quirk_id_matches(quirk->vendor, dev->vendor) &&
1419 quirk_id_matches(quirk->device, dev->device) &&
1420 quirk_id_matches(quirk->subvendor, dev->subsystem_vendor) &&
1421 quirk_id_matches(quirk->subdevice, dev->subsystem_device))
1422 break;
1423 return quirk;
1424 }
1425
1426 static inline int get_pci_irq(struct pci_dev *dev,
1427 const struct pciserial_board *board)
1428 {
1429 if (board->flags & FL_NOIRQ)
1430 return 0;
1431 else
1432 return dev->irq;
1433 }
1434
1435 /*
1436 * This is the configuration table for all of the PCI serial boards
1437 * which we support. It is directly indexed by the pci_board_num_t enum
1438 * value, which is encoded in the pci_device_id PCI probe table's
1439 * driver_data member.
1440 *
1441 * The makeup of these names are:
1442 * pbn_bn{_bt}_n_baud{_offsetinhex}
1443 *
1444 * bn = PCI BAR number
1445 * bt = Index using PCI BARs
1446 * n = number of serial ports
1447 * baud = baud rate
1448 * offsetinhex = offset for each sequential port (in hex)
1449 *
1450 * This table is sorted by (in order): bn, bt, baud, offsetindex, n.
1451 *
1452 * Please note: in theory if n = 1, _bt infix should make no difference.
1453 * ie, pbn_b0_1_115200 is the same as pbn_b0_bt_1_115200
1454 */
1455 enum pci_board_num_t {
1456 pbn_default = 0,
1457
1458 pbn_b0_1_115200,
1459 pbn_b0_2_115200,
1460 pbn_b0_4_115200,
1461 pbn_b0_5_115200,
1462 pbn_b0_8_115200,
1463
1464 pbn_b0_1_921600,
1465 pbn_b0_2_921600,
1466 pbn_b0_4_921600,
1467
1468 pbn_b0_2_1130000,
1469
1470 pbn_b0_4_1152000,
1471
1472 pbn_b0_2_1843200,
1473 pbn_b0_4_1843200,
1474
1475 pbn_b0_2_1843200_200,
1476 pbn_b0_4_1843200_200,
1477 pbn_b0_8_1843200_200,
1478
1479 pbn_b0_1_4000000,
1480
1481 pbn_b0_bt_1_115200,
1482 pbn_b0_bt_2_115200,
1483 pbn_b0_bt_8_115200,
1484
1485 pbn_b0_bt_1_460800,
1486 pbn_b0_bt_2_460800,
1487 pbn_b0_bt_4_460800,
1488
1489 pbn_b0_bt_1_921600,
1490 pbn_b0_bt_2_921600,
1491 pbn_b0_bt_4_921600,
1492 pbn_b0_bt_8_921600,
1493
1494 pbn_b1_1_115200,
1495 pbn_b1_2_115200,
1496 pbn_b1_4_115200,
1497 pbn_b1_8_115200,
1498 pbn_b1_16_115200,
1499
1500 pbn_b1_1_921600,
1501 pbn_b1_2_921600,
1502 pbn_b1_4_921600,
1503 pbn_b1_8_921600,
1504
1505 pbn_b1_2_1250000,
1506
1507 pbn_b1_bt_1_115200,
1508 pbn_b1_bt_2_115200,
1509 pbn_b1_bt_4_115200,
1510
1511 pbn_b1_bt_2_921600,
1512
1513 pbn_b1_1_1382400,
1514 pbn_b1_2_1382400,
1515 pbn_b1_4_1382400,
1516 pbn_b1_8_1382400,
1517
1518 pbn_b2_1_115200,
1519 pbn_b2_2_115200,
1520 pbn_b2_4_115200,
1521 pbn_b2_8_115200,
1522
1523 pbn_b2_1_460800,
1524 pbn_b2_4_460800,
1525 pbn_b2_8_460800,
1526 pbn_b2_16_460800,
1527
1528 pbn_b2_1_921600,
1529 pbn_b2_4_921600,
1530 pbn_b2_8_921600,
1531
1532 pbn_b2_bt_1_115200,
1533 pbn_b2_bt_2_115200,
1534 pbn_b2_bt_4_115200,
1535
1536 pbn_b2_bt_2_921600,
1537 pbn_b2_bt_4_921600,
1538
1539 pbn_b3_2_115200,
1540 pbn_b3_4_115200,
1541 pbn_b3_8_115200,
1542
1543 /*
1544 * Board-specific versions.
1545 */
1546 pbn_panacom,
1547 pbn_panacom2,
1548 pbn_panacom4,
1549 pbn_exsys_4055,
1550 pbn_plx_romulus,
1551 pbn_oxsemi,
1552 pbn_oxsemi_1_4000000,
1553 pbn_oxsemi_2_4000000,
1554 pbn_oxsemi_4_4000000,
1555 pbn_oxsemi_8_4000000,
1556 pbn_intel_i960,
1557 pbn_sgi_ioc3,
1558 pbn_computone_4,
1559 pbn_computone_6,
1560 pbn_computone_8,
1561 pbn_sbsxrsio,
1562 pbn_exar_XR17C152,
1563 pbn_exar_XR17C154,
1564 pbn_exar_XR17C158,
1565 pbn_pasemi_1682M,
1566 pbn_ni8430_2,
1567 pbn_ni8430_4,
1568 pbn_ni8430_8,
1569 pbn_ni8430_16,
1570 };
1571
1572 /*
1573 * uart_offset - the space between channels
1574 * reg_shift - describes how the UART registers are mapped
1575 * to PCI memory by the card.
1576 * For example IER register on SBS, Inc. PMC-OctPro is located at
1577 * offset 0x10 from the UART base, while UART_IER is defined as 1
1578 * in include/linux/serial_reg.h,
1579 * see first lines of serial_in() and serial_out() in 8250.c
1580 */
1581
1582 static struct pciserial_board pci_boards[] __devinitdata = {
1583 [pbn_default] = {
1584 .flags = FL_BASE0,
1585 .num_ports = 1,
1586 .base_baud = 115200,
1587 .uart_offset = 8,
1588 },
1589 [pbn_b0_1_115200] = {
1590 .flags = FL_BASE0,
1591 .num_ports = 1,
1592 .base_baud = 115200,
1593 .uart_offset = 8,
1594 },
1595 [pbn_b0_2_115200] = {
1596 .flags = FL_BASE0,
1597 .num_ports = 2,
1598 .base_baud = 115200,
1599 .uart_offset = 8,
1600 },
1601 [pbn_b0_4_115200] = {
1602 .flags = FL_BASE0,
1603 .num_ports = 4,
1604 .base_baud = 115200,
1605 .uart_offset = 8,
1606 },
1607 [pbn_b0_5_115200] = {
1608 .flags = FL_BASE0,
1609 .num_ports = 5,
1610 .base_baud = 115200,
1611 .uart_offset = 8,
1612 },
1613 [pbn_b0_8_115200] = {
1614 .flags = FL_BASE0,
1615 .num_ports = 8,
1616 .base_baud = 115200,
1617 .uart_offset = 8,
1618 },
1619 [pbn_b0_1_921600] = {
1620 .flags = FL_BASE0,
1621 .num_ports = 1,
1622 .base_baud = 921600,
1623 .uart_offset = 8,
1624 },
1625 [pbn_b0_2_921600] = {
1626 .flags = FL_BASE0,
1627 .num_ports = 2,
1628 .base_baud = 921600,
1629 .uart_offset = 8,
1630 },
1631 [pbn_b0_4_921600] = {
1632 .flags = FL_BASE0,
1633 .num_ports = 4,
1634 .base_baud = 921600,
1635 .uart_offset = 8,
1636 },
1637
1638 [pbn_b0_2_1130000] = {
1639 .flags = FL_BASE0,
1640 .num_ports = 2,
1641 .base_baud = 1130000,
1642 .uart_offset = 8,
1643 },
1644
1645 [pbn_b0_4_1152000] = {
1646 .flags = FL_BASE0,
1647 .num_ports = 4,
1648 .base_baud = 1152000,
1649 .uart_offset = 8,
1650 },
1651
1652 [pbn_b0_2_1843200] = {
1653 .flags = FL_BASE0,
1654 .num_ports = 2,
1655 .base_baud = 1843200,
1656 .uart_offset = 8,
1657 },
1658 [pbn_b0_4_1843200] = {
1659 .flags = FL_BASE0,
1660 .num_ports = 4,
1661 .base_baud = 1843200,
1662 .uart_offset = 8,
1663 },
1664
1665 [pbn_b0_2_1843200_200] = {
1666 .flags = FL_BASE0,
1667 .num_ports = 2,
1668 .base_baud = 1843200,
1669 .uart_offset = 0x200,
1670 },
1671 [pbn_b0_4_1843200_200] = {
1672 .flags = FL_BASE0,
1673 .num_ports = 4,
1674 .base_baud = 1843200,
1675 .uart_offset = 0x200,
1676 },
1677 [pbn_b0_8_1843200_200] = {
1678 .flags = FL_BASE0,
1679 .num_ports = 8,
1680 .base_baud = 1843200,
1681 .uart_offset = 0x200,
1682 },
1683 [pbn_b0_1_4000000] = {
1684 .flags = FL_BASE0,
1685 .num_ports = 1,
1686 .base_baud = 4000000,
1687 .uart_offset = 8,
1688 },
1689
1690 [pbn_b0_bt_1_115200] = {
1691 .flags = FL_BASE0|FL_BASE_BARS,
1692 .num_ports = 1,
1693 .base_baud = 115200,
1694 .uart_offset = 8,
1695 },
1696 [pbn_b0_bt_2_115200] = {
1697 .flags = FL_BASE0|FL_BASE_BARS,
1698 .num_ports = 2,
1699 .base_baud = 115200,
1700 .uart_offset = 8,
1701 },
1702 [pbn_b0_bt_8_115200] = {
1703 .flags = FL_BASE0|FL_BASE_BARS,
1704 .num_ports = 8,
1705 .base_baud = 115200,
1706 .uart_offset = 8,
1707 },
1708
1709 [pbn_b0_bt_1_460800] = {
1710 .flags = FL_BASE0|FL_BASE_BARS,
1711 .num_ports = 1,
1712 .base_baud = 460800,
1713 .uart_offset = 8,
1714 },
1715 [pbn_b0_bt_2_460800] = {
1716 .flags = FL_BASE0|FL_BASE_BARS,
1717 .num_ports = 2,
1718 .base_baud = 460800,
1719 .uart_offset = 8,
1720 },
1721 [pbn_b0_bt_4_460800] = {
1722 .flags = FL_BASE0|FL_BASE_BARS,
1723 .num_ports = 4,
1724 .base_baud = 460800,
1725 .uart_offset = 8,
1726 },
1727
1728 [pbn_b0_bt_1_921600] = {
1729 .flags = FL_BASE0|FL_BASE_BARS,
1730 .num_ports = 1,
1731 .base_baud = 921600,
1732 .uart_offset = 8,
1733 },
1734 [pbn_b0_bt_2_921600] = {
1735 .flags = FL_BASE0|FL_BASE_BARS,
1736 .num_ports = 2,
1737 .base_baud = 921600,
1738 .uart_offset = 8,
1739 },
1740 [pbn_b0_bt_4_921600] = {
1741 .flags = FL_BASE0|FL_BASE_BARS,
1742 .num_ports = 4,
1743 .base_baud = 921600,
1744 .uart_offset = 8,
1745 },
1746 [pbn_b0_bt_8_921600] = {
1747 .flags = FL_BASE0|FL_BASE_BARS,
1748 .num_ports = 8,
1749 .base_baud = 921600,
1750 .uart_offset = 8,
1751 },
1752
1753 [pbn_b1_1_115200] = {
1754 .flags = FL_BASE1,
1755 .num_ports = 1,
1756 .base_baud = 115200,
1757 .uart_offset = 8,
1758 },
1759 [pbn_b1_2_115200] = {
1760 .flags = FL_BASE1,
1761 .num_ports = 2,
1762 .base_baud = 115200,
1763 .uart_offset = 8,
1764 },
1765 [pbn_b1_4_115200] = {
1766 .flags = FL_BASE1,
1767 .num_ports = 4,
1768 .base_baud = 115200,
1769 .uart_offset = 8,
1770 },
1771 [pbn_b1_8_115200] = {
1772 .flags = FL_BASE1,
1773 .num_ports = 8,
1774 .base_baud = 115200,
1775 .uart_offset = 8,
1776 },
1777 [pbn_b1_16_115200] = {
1778 .flags = FL_BASE1,
1779 .num_ports = 16,
1780 .base_baud = 115200,
1781 .uart_offset = 8,
1782 },
1783
1784 [pbn_b1_1_921600] = {
1785 .flags = FL_BASE1,
1786 .num_ports = 1,
1787 .base_baud = 921600,
1788 .uart_offset = 8,
1789 },
1790 [pbn_b1_2_921600] = {
1791 .flags = FL_BASE1,
1792 .num_ports = 2,
1793 .base_baud = 921600,
1794 .uart_offset = 8,
1795 },
1796 [pbn_b1_4_921600] = {
1797 .flags = FL_BASE1,
1798 .num_ports = 4,
1799 .base_baud = 921600,
1800 .uart_offset = 8,
1801 },
1802 [pbn_b1_8_921600] = {
1803 .flags = FL_BASE1,
1804 .num_ports = 8,
1805 .base_baud = 921600,
1806 .uart_offset = 8,
1807 },
1808 [pbn_b1_2_1250000] = {
1809 .flags = FL_BASE1,
1810 .num_ports = 2,
1811 .base_baud = 1250000,
1812 .uart_offset = 8,
1813 },
1814
1815 [pbn_b1_bt_1_115200] = {
1816 .flags = FL_BASE1|FL_BASE_BARS,
1817 .num_ports = 1,
1818 .base_baud = 115200,
1819 .uart_offset = 8,
1820 },
1821 [pbn_b1_bt_2_115200] = {
1822 .flags = FL_BASE1|FL_BASE_BARS,
1823 .num_ports = 2,
1824 .base_baud = 115200,
1825 .uart_offset = 8,
1826 },
1827 [pbn_b1_bt_4_115200] = {
1828 .flags = FL_BASE1|FL_BASE_BARS,
1829 .num_ports = 4,
1830 .base_baud = 115200,
1831 .uart_offset = 8,
1832 },
1833
1834 [pbn_b1_bt_2_921600] = {
1835 .flags = FL_BASE1|FL_BASE_BARS,
1836 .num_ports = 2,
1837 .base_baud = 921600,
1838 .uart_offset = 8,
1839 },
1840
1841 [pbn_b1_1_1382400] = {
1842 .flags = FL_BASE1,
1843 .num_ports = 1,
1844 .base_baud = 1382400,
1845 .uart_offset = 8,
1846 },
1847 [pbn_b1_2_1382400] = {
1848 .flags = FL_BASE1,
1849 .num_ports = 2,
1850 .base_baud = 1382400,
1851 .uart_offset = 8,
1852 },
1853 [pbn_b1_4_1382400] = {
1854 .flags = FL_BASE1,
1855 .num_ports = 4,
1856 .base_baud = 1382400,
1857 .uart_offset = 8,
1858 },
1859 [pbn_b1_8_1382400] = {
1860 .flags = FL_BASE1,
1861 .num_ports = 8,
1862 .base_baud = 1382400,
1863 .uart_offset = 8,
1864 },
1865
1866 [pbn_b2_1_115200] = {
1867 .flags = FL_BASE2,
1868 .num_ports = 1,
1869 .base_baud = 115200,
1870 .uart_offset = 8,
1871 },
1872 [pbn_b2_2_115200] = {
1873 .flags = FL_BASE2,
1874 .num_ports = 2,
1875 .base_baud = 115200,
1876 .uart_offset = 8,
1877 },
1878 [pbn_b2_4_115200] = {
1879 .flags = FL_BASE2,
1880 .num_ports = 4,
1881 .base_baud = 115200,
1882 .uart_offset = 8,
1883 },
1884 [pbn_b2_8_115200] = {
1885 .flags = FL_BASE2,
1886 .num_ports = 8,
1887 .base_baud = 115200,
1888 .uart_offset = 8,
1889 },
1890
1891 [pbn_b2_1_460800] = {
1892 .flags = FL_BASE2,
1893 .num_ports = 1,
1894 .base_baud = 460800,
1895 .uart_offset = 8,
1896 },
1897 [pbn_b2_4_460800] = {
1898 .flags = FL_BASE2,
1899 .num_ports = 4,
1900 .base_baud = 460800,
1901 .uart_offset = 8,
1902 },
1903 [pbn_b2_8_460800] = {
1904 .flags = FL_BASE2,
1905 .num_ports = 8,
1906 .base_baud = 460800,
1907 .uart_offset = 8,
1908 },
1909 [pbn_b2_16_460800] = {
1910 .flags = FL_BASE2,
1911 .num_ports = 16,
1912 .base_baud = 460800,
1913 .uart_offset = 8,
1914 },
1915
1916 [pbn_b2_1_921600] = {
1917 .flags = FL_BASE2,
1918 .num_ports = 1,
1919 .base_baud = 921600,
1920 .uart_offset = 8,
1921 },
1922 [pbn_b2_4_921600] = {
1923 .flags = FL_BASE2,
1924 .num_ports = 4,
1925 .base_baud = 921600,
1926 .uart_offset = 8,
1927 },
1928 [pbn_b2_8_921600] = {
1929 .flags = FL_BASE2,
1930 .num_ports = 8,
1931 .base_baud = 921600,
1932 .uart_offset = 8,
1933 },
1934
1935 [pbn_b2_bt_1_115200] = {
1936 .flags = FL_BASE2|FL_BASE_BARS,
1937 .num_ports = 1,
1938 .base_baud = 115200,
1939 .uart_offset = 8,
1940 },
1941 [pbn_b2_bt_2_115200] = {
1942 .flags = FL_BASE2|FL_BASE_BARS,
1943 .num_ports = 2,
1944 .base_baud = 115200,
1945 .uart_offset = 8,
1946 },
1947 [pbn_b2_bt_4_115200] = {
1948 .flags = FL_BASE2|FL_BASE_BARS,
1949 .num_ports = 4,
1950 .base_baud = 115200,
1951 .uart_offset = 8,
1952 },
1953
1954 [pbn_b2_bt_2_921600] = {
1955 .flags = FL_BASE2|FL_BASE_BARS,
1956 .num_ports = 2,
1957 .base_baud = 921600,
1958 .uart_offset = 8,
1959 },
1960 [pbn_b2_bt_4_921600] = {
1961 .flags = FL_BASE2|FL_BASE_BARS,
1962 .num_ports = 4,
1963 .base_baud = 921600,
1964 .uart_offset = 8,
1965 },
1966
1967 [pbn_b3_2_115200] = {
1968 .flags = FL_BASE3,
1969 .num_ports = 2,
1970 .base_baud = 115200,
1971 .uart_offset = 8,
1972 },
1973 [pbn_b3_4_115200] = {
1974 .flags = FL_BASE3,
1975 .num_ports = 4,
1976 .base_baud = 115200,
1977 .uart_offset = 8,
1978 },
1979 [pbn_b3_8_115200] = {
1980 .flags = FL_BASE3,
1981 .num_ports = 8,
1982 .base_baud = 115200,
1983 .uart_offset = 8,
1984 },
1985
1986 /*
1987 * Entries following this are board-specific.
1988 */
1989
1990 /*
1991 * Panacom - IOMEM
1992 */
1993 [pbn_panacom] = {
1994 .flags = FL_BASE2,
1995 .num_ports = 2,
1996 .base_baud = 921600,
1997 .uart_offset = 0x400,
1998 .reg_shift = 7,
1999 },
2000 [pbn_panacom2] = {
2001 .flags = FL_BASE2|FL_BASE_BARS,
2002 .num_ports = 2,
2003 .base_baud = 921600,
2004 .uart_offset = 0x400,
2005 .reg_shift = 7,
2006 },
2007 [pbn_panacom4] = {
2008 .flags = FL_BASE2|FL_BASE_BARS,
2009 .num_ports = 4,
2010 .base_baud = 921600,
2011 .uart_offset = 0x400,
2012 .reg_shift = 7,
2013 },
2014
2015 [pbn_exsys_4055] = {
2016 .flags = FL_BASE2,
2017 .num_ports = 4,
2018 .base_baud = 115200,
2019 .uart_offset = 8,
2020 },
2021
2022 /* I think this entry is broken - the first_offset looks wrong --rmk */
2023 [pbn_plx_romulus] = {
2024 .flags = FL_BASE2,
2025 .num_ports = 4,
2026 .base_baud = 921600,
2027 .uart_offset = 8 << 2,
2028 .reg_shift = 2,
2029 .first_offset = 0x03,
2030 },
2031
2032 /*
2033 * This board uses the size of PCI Base region 0 to
2034 * signal now many ports are available
2035 */
2036 [pbn_oxsemi] = {
2037 .flags = FL_BASE0|FL_REGION_SZ_CAP,
2038 .num_ports = 32,
2039 .base_baud = 115200,
2040 .uart_offset = 8,
2041 },
2042 [pbn_oxsemi_1_4000000] = {
2043 .flags = FL_BASE0,
2044 .num_ports = 1,
2045 .base_baud = 4000000,
2046 .uart_offset = 0x200,
2047 .first_offset = 0x1000,
2048 },
2049 [pbn_oxsemi_2_4000000] = {
2050 .flags = FL_BASE0,
2051 .num_ports = 2,
2052 .base_baud = 4000000,
2053 .uart_offset = 0x200,
2054 .first_offset = 0x1000,
2055 },
2056 [pbn_oxsemi_4_4000000] = {
2057 .flags = FL_BASE0,
2058 .num_ports = 4,
2059 .base_baud = 4000000,
2060 .uart_offset = 0x200,
2061 .first_offset = 0x1000,
2062 },
2063 [pbn_oxsemi_8_4000000] = {
2064 .flags = FL_BASE0,
2065 .num_ports = 8,
2066 .base_baud = 4000000,
2067 .uart_offset = 0x200,
2068 .first_offset = 0x1000,
2069 },
2070
2071
2072 /*
2073 * EKF addition for i960 Boards form EKF with serial port.
2074 * Max 256 ports.
2075 */
2076 [pbn_intel_i960] = {
2077 .flags = FL_BASE0,
2078 .num_ports = 32,
2079 .base_baud = 921600,
2080 .uart_offset = 8 << 2,
2081 .reg_shift = 2,
2082 .first_offset = 0x10000,
2083 },
2084 [pbn_sgi_ioc3] = {
2085 .flags = FL_BASE0|FL_NOIRQ,
2086 .num_ports = 1,
2087 .base_baud = 458333,
2088 .uart_offset = 8,
2089 .reg_shift = 0,
2090 .first_offset = 0x20178,
2091 },
2092
2093 /*
2094 * Computone - uses IOMEM.
2095 */
2096 [pbn_computone_4] = {
2097 .flags = FL_BASE0,
2098 .num_ports = 4,
2099 .base_baud = 921600,
2100 .uart_offset = 0x40,
2101 .reg_shift = 2,
2102 .first_offset = 0x200,
2103 },
2104 [pbn_computone_6] = {
2105 .flags = FL_BASE0,
2106 .num_ports = 6,
2107 .base_baud = 921600,
2108 .uart_offset = 0x40,
2109 .reg_shift = 2,
2110 .first_offset = 0x200,
2111 },
2112 [pbn_computone_8] = {
2113 .flags = FL_BASE0,
2114 .num_ports = 8,
2115 .base_baud = 921600,
2116 .uart_offset = 0x40,
2117 .reg_shift = 2,
2118 .first_offset = 0x200,
2119 },
2120 [pbn_sbsxrsio] = {
2121 .flags = FL_BASE0,
2122 .num_ports = 8,
2123 .base_baud = 460800,
2124 .uart_offset = 256,
2125 .reg_shift = 4,
2126 },
2127 /*
2128 * Exar Corp. XR17C15[248] Dual/Quad/Octal UART
2129 * Only basic 16550A support.
2130 * XR17C15[24] are not tested, but they should work.
2131 */
2132 [pbn_exar_XR17C152] = {
2133 .flags = FL_BASE0,
2134 .num_ports = 2,
2135 .base_baud = 921600,
2136 .uart_offset = 0x200,
2137 },
2138 [pbn_exar_XR17C154] = {
2139 .flags = FL_BASE0,
2140 .num_ports = 4,
2141 .base_baud = 921600,
2142 .uart_offset = 0x200,
2143 },
2144 [pbn_exar_XR17C158] = {
2145 .flags = FL_BASE0,
2146 .num_ports = 8,
2147 .base_baud = 921600,
2148 .uart_offset = 0x200,
2149 },
2150 /*
2151 * PA Semi PWRficient PA6T-1682M on-chip UART
2152 */
2153 [pbn_pasemi_1682M] = {
2154 .flags = FL_BASE0,
2155 .num_ports = 1,
2156 .base_baud = 8333333,
2157 },
2158 /*
2159 * National Instruments 843x
2160 */
2161 [pbn_ni8430_16] = {
2162 .flags = FL_BASE0,
2163 .num_ports = 16,
2164 .base_baud = 3686400,
2165 .uart_offset = 0x10,
2166 .first_offset = 0x800,
2167 },
2168 [pbn_ni8430_8] = {
2169 .flags = FL_BASE0,
2170 .num_ports = 8,
2171 .base_baud = 3686400,
2172 .uart_offset = 0x10,
2173 .first_offset = 0x800,
2174 },
2175 [pbn_ni8430_4] = {
2176 .flags = FL_BASE0,
2177 .num_ports = 4,
2178 .base_baud = 3686400,
2179 .uart_offset = 0x10,
2180 .first_offset = 0x800,
2181 },
2182 [pbn_ni8430_2] = {
2183 .flags = FL_BASE0,
2184 .num_ports = 2,
2185 .base_baud = 3686400,
2186 .uart_offset = 0x10,
2187 .first_offset = 0x800,
2188 },
2189 };
2190
2191 static const struct pci_device_id softmodem_blacklist[] = {
2192 { PCI_VDEVICE(AL, 0x5457), }, /* ALi Corporation M5457 AC'97 Modem */
2193 };
2194
2195 /*
2196 * Given a complete unknown PCI device, try to use some heuristics to
2197 * guess what the configuration might be, based on the pitiful PCI
2198 * serial specs. Returns 0 on success, 1 on failure.
2199 */
2200 static int __devinit
2201 serial_pci_guess_board(struct pci_dev *dev, struct pciserial_board *board)
2202 {
2203 const struct pci_device_id *blacklist;
2204 int num_iomem, num_port, first_port = -1, i;
2205
2206 /*
2207 * If it is not a communications device or the programming
2208 * interface is greater than 6, give up.
2209 *
2210 * (Should we try to make guesses for multiport serial devices
2211 * later?)
2212 */
2213 if ((((dev->class >> 8) != PCI_CLASS_COMMUNICATION_SERIAL) &&
2214 ((dev->class >> 8) != PCI_CLASS_COMMUNICATION_MODEM)) ||
2215 (dev->class & 0xff) > 6)
2216 return -ENODEV;
2217
2218 /*
2219 * Do not access blacklisted devices that are known not to
2220 * feature serial ports.
2221 */
2222 for (blacklist = softmodem_blacklist;
2223 blacklist < softmodem_blacklist + ARRAY_SIZE(softmodem_blacklist);
2224 blacklist++) {
2225 if (dev->vendor == blacklist->vendor &&
2226 dev->device == blacklist->device)
2227 return -ENODEV;
2228 }
2229
2230 num_iomem = num_port = 0;
2231 for (i = 0; i < PCI_NUM_BAR_RESOURCES; i++) {
2232 if (pci_resource_flags(dev, i) & IORESOURCE_IO) {
2233 num_port++;
2234 if (first_port == -1)
2235 first_port = i;
2236 }
2237 if (pci_resource_flags(dev, i) & IORESOURCE_MEM)
2238 num_iomem++;
2239 }
2240
2241 /*
2242 * If there is 1 or 0 iomem regions, and exactly one port,
2243 * use it. We guess the number of ports based on the IO
2244 * region size.
2245 */
2246 if (num_iomem <= 1 && num_port == 1) {
2247 board->flags = first_port;
2248 board->num_ports = pci_resource_len(dev, first_port) / 8;
2249 return 0;
2250 }
2251
2252 /*
2253 * Now guess if we've got a board which indexes by BARs.
2254 * Each IO BAR should be 8 bytes, and they should follow
2255 * consecutively.
2256 */
2257 first_port = -1;
2258 num_port = 0;
2259 for (i = 0; i < PCI_NUM_BAR_RESOURCES; i++) {
2260 if (pci_resource_flags(dev, i) & IORESOURCE_IO &&
2261 pci_resource_len(dev, i) == 8 &&
2262 (first_port == -1 || (first_port + num_port) == i)) {
2263 num_port++;
2264 if (first_port == -1)
2265 first_port = i;
2266 }
2267 }
2268
2269 if (num_port > 1) {
2270 board->flags = first_port | FL_BASE_BARS;
2271 board->num_ports = num_port;
2272 return 0;
2273 }
2274
2275 return -ENODEV;
2276 }
2277
2278 static inline int
2279 serial_pci_matches(const struct pciserial_board *board,
2280 const struct pciserial_board *guessed)
2281 {
2282 return
2283 board->num_ports == guessed->num_ports &&
2284 board->base_baud == guessed->base_baud &&
2285 board->uart_offset == guessed->uart_offset &&
2286 board->reg_shift == guessed->reg_shift &&
2287 board->first_offset == guessed->first_offset;
2288 }
2289
2290 struct serial_private *
2291 pciserial_init_ports(struct pci_dev *dev, const struct pciserial_board *board)
2292 {
2293 struct uart_port serial_port;
2294 struct serial_private *priv;
2295 struct pci_serial_quirk *quirk;
2296 int rc, nr_ports, i;
2297
2298 nr_ports = board->num_ports;
2299
2300 /*
2301 * Find an init and setup quirks.
2302 */
2303 quirk = find_quirk(dev);
2304
2305 /*
2306 * Run the new-style initialization function.
2307 * The initialization function returns:
2308 * <0 - error
2309 * 0 - use board->num_ports
2310 * >0 - number of ports
2311 */
2312 if (quirk->init) {
2313 rc = quirk->init(dev);
2314 if (rc < 0) {
2315 priv = ERR_PTR(rc);
2316 goto err_out;
2317 }
2318 if (rc)
2319 nr_ports = rc;
2320 }
2321
2322 priv = kzalloc(sizeof(struct serial_private) +
2323 sizeof(unsigned int) * nr_ports,
2324 GFP_KERNEL);
2325 if (!priv) {
2326 priv = ERR_PTR(-ENOMEM);
2327 goto err_deinit;
2328 }
2329
2330 priv->dev = dev;
2331 priv->quirk = quirk;
2332
2333 memset(&serial_port, 0, sizeof(struct uart_port));
2334 serial_port.flags = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF | UPF_SHARE_IRQ;
2335 serial_port.uartclk = board->base_baud * 16;
2336 serial_port.irq = get_pci_irq(dev, board);
2337 serial_port.dev = &dev->dev;
2338
2339 for (i = 0; i < nr_ports; i++) {
2340 if (quirk->setup(priv, board, &serial_port, i))
2341 break;
2342
2343 #ifdef SERIAL_DEBUG_PCI
2344 printk(KERN_DEBUG "Setup PCI port: port %x, irq %d, type %d\n",
2345 serial_port.iobase, serial_port.irq, serial_port.iotype);
2346 #endif
2347
2348 priv->line[i] = serial8250_register_port(&serial_port);
2349 if (priv->line[i] < 0) {
2350 printk(KERN_WARNING "Couldn't register serial port %s: %d\n", pci_name(dev), priv->line[i]);
2351 break;
2352 }
2353 }
2354 priv->nr = i;
2355 return priv;
2356
2357 err_deinit:
2358 if (quirk->exit)
2359 quirk->exit(dev);
2360 err_out:
2361 return priv;
2362 }
2363 EXPORT_SYMBOL_GPL(pciserial_init_ports);
2364
2365 void pciserial_remove_ports(struct serial_private *priv)
2366 {
2367 struct pci_serial_quirk *quirk;
2368 int i;
2369
2370 for (i = 0; i < priv->nr; i++)
2371 serial8250_unregister_port(priv->line[i]);
2372
2373 for (i = 0; i < PCI_NUM_BAR_RESOURCES; i++) {
2374 if (priv->remapped_bar[i])
2375 iounmap(priv->remapped_bar[i]);
2376 priv->remapped_bar[i] = NULL;
2377 }
2378
2379 /*
2380 * Find the exit quirks.
2381 */
2382 quirk = find_quirk(priv->dev);
2383 if (quirk->exit)
2384 quirk->exit(priv->dev);
2385
2386 kfree(priv);
2387 }
2388 EXPORT_SYMBOL_GPL(pciserial_remove_ports);
2389
2390 void pciserial_suspend_ports(struct serial_private *priv)
2391 {
2392 int i;
2393
2394 for (i = 0; i < priv->nr; i++)
2395 if (priv->line[i] >= 0)
2396 serial8250_suspend_port(priv->line[i]);
2397 }
2398 EXPORT_SYMBOL_GPL(pciserial_suspend_ports);
2399
2400 void pciserial_resume_ports(struct serial_private *priv)
2401 {
2402 int i;
2403
2404 /*
2405 * Ensure that the board is correctly configured.
2406 */
2407 if (priv->quirk->init)
2408 priv->quirk->init(priv->dev);
2409
2410 for (i = 0; i < priv->nr; i++)
2411 if (priv->line[i] >= 0)
2412 serial8250_resume_port(priv->line[i]);
2413 }
2414 EXPORT_SYMBOL_GPL(pciserial_resume_ports);
2415
2416 /*
2417 * Probe one serial board. Unfortunately, there is no rhyme nor reason
2418 * to the arrangement of serial ports on a PCI card.
2419 */
2420 static int __devinit
2421 pciserial_init_one(struct pci_dev *dev, const struct pci_device_id *ent)
2422 {
2423 struct serial_private *priv;
2424 const struct pciserial_board *board;
2425 struct pciserial_board tmp;
2426 int rc;
2427
2428 if (ent->driver_data >= ARRAY_SIZE(pci_boards)) {
2429 printk(KERN_ERR "pci_init_one: invalid driver_data: %ld\n",
2430 ent->driver_data);
2431 return -EINVAL;
2432 }
2433
2434 board = &pci_boards[ent->driver_data];
2435
2436 rc = pci_enable_device(dev);
2437 if (rc)
2438 return rc;
2439
2440 if (ent->driver_data == pbn_default) {
2441 /*
2442 * Use a copy of the pci_board entry for this;
2443 * avoid changing entries in the table.
2444 */
2445 memcpy(&tmp, board, sizeof(struct pciserial_board));
2446 board = &tmp;
2447
2448 /*
2449 * We matched one of our class entries. Try to
2450 * determine the parameters of this board.
2451 */
2452 rc = serial_pci_guess_board(dev, &tmp);
2453 if (rc)
2454 goto disable;
2455 } else {
2456 /*
2457 * We matched an explicit entry. If we are able to
2458 * detect this boards settings with our heuristic,
2459 * then we no longer need this entry.
2460 */
2461 memcpy(&tmp, &pci_boards[pbn_default],
2462 sizeof(struct pciserial_board));
2463 rc = serial_pci_guess_board(dev, &tmp);
2464 if (rc == 0 && serial_pci_matches(board, &tmp))
2465 moan_device("Redundant entry in serial pci_table.",
2466 dev);
2467 }
2468
2469 priv = pciserial_init_ports(dev, board);
2470 if (!IS_ERR(priv)) {
2471 pci_set_drvdata(dev, priv);
2472 return 0;
2473 }
2474
2475 rc = PTR_ERR(priv);
2476
2477 disable:
2478 pci_disable_device(dev);
2479 return rc;
2480 }
2481
2482 static void __devexit pciserial_remove_one(struct pci_dev *dev)
2483 {
2484 struct serial_private *priv = pci_get_drvdata(dev);
2485
2486 pci_set_drvdata(dev, NULL);
2487
2488 pciserial_remove_ports(priv);
2489
2490 pci_disable_device(dev);
2491 }
2492
2493 #ifdef CONFIG_PM
2494 static int pciserial_suspend_one(struct pci_dev *dev, pm_message_t state)
2495 {
2496 struct serial_private *priv = pci_get_drvdata(dev);
2497
2498 if (priv)
2499 pciserial_suspend_ports(priv);
2500
2501 pci_save_state(dev);
2502 pci_set_power_state(dev, pci_choose_state(dev, state));
2503 return 0;
2504 }
2505
2506 static int pciserial_resume_one(struct pci_dev *dev)
2507 {
2508 int err;
2509 struct serial_private *priv = pci_get_drvdata(dev);
2510
2511 pci_set_power_state(dev, PCI_D0);
2512 pci_restore_state(dev);
2513
2514 if (priv) {
2515 /*
2516 * The device may have been disabled. Re-enable it.
2517 */
2518 err = pci_enable_device(dev);
2519 /* FIXME: We cannot simply error out here */
2520 if (err)
2521 printk(KERN_ERR "pciserial: Unable to re-enable ports, trying to continue.\n");
2522 pciserial_resume_ports(priv);
2523 }
2524 return 0;
2525 }
2526 #endif
2527
2528 static struct pci_device_id serial_pci_tbl[] = {
2529 /* Advantech use PCI_DEVICE_ID_ADVANTECH_PCI3620 (0x3620) as 'PCI_SUBVENDOR_ID' */
2530 { PCI_VENDOR_ID_ADVANTECH, PCI_DEVICE_ID_ADVANTECH_PCI3620,
2531 PCI_DEVICE_ID_ADVANTECH_PCI3620, 0x0001, 0, 0,
2532 pbn_b2_8_921600 },
2533 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960,
2534 PCI_SUBVENDOR_ID_CONNECT_TECH,
2535 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_232, 0, 0,
2536 pbn_b1_8_1382400 },
2537 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960,
2538 PCI_SUBVENDOR_ID_CONNECT_TECH,
2539 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_232, 0, 0,
2540 pbn_b1_4_1382400 },
2541 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960,
2542 PCI_SUBVENDOR_ID_CONNECT_TECH,
2543 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_232, 0, 0,
2544 pbn_b1_2_1382400 },
2545 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
2546 PCI_SUBVENDOR_ID_CONNECT_TECH,
2547 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_232, 0, 0,
2548 pbn_b1_8_1382400 },
2549 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
2550 PCI_SUBVENDOR_ID_CONNECT_TECH,
2551 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_232, 0, 0,
2552 pbn_b1_4_1382400 },
2553 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
2554 PCI_SUBVENDOR_ID_CONNECT_TECH,
2555 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_232, 0, 0,
2556 pbn_b1_2_1382400 },
2557 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
2558 PCI_SUBVENDOR_ID_CONNECT_TECH,
2559 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485, 0, 0,
2560 pbn_b1_8_921600 },
2561 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
2562 PCI_SUBVENDOR_ID_CONNECT_TECH,
2563 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485_4_4, 0, 0,
2564 pbn_b1_8_921600 },
2565 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
2566 PCI_SUBVENDOR_ID_CONNECT_TECH,
2567 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_485, 0, 0,
2568 pbn_b1_4_921600 },
2569 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
2570 PCI_SUBVENDOR_ID_CONNECT_TECH,
2571 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_485_2_2, 0, 0,
2572 pbn_b1_4_921600 },
2573 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
2574 PCI_SUBVENDOR_ID_CONNECT_TECH,
2575 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_485, 0, 0,
2576 pbn_b1_2_921600 },
2577 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
2578 PCI_SUBVENDOR_ID_CONNECT_TECH,
2579 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485_2_6, 0, 0,
2580 pbn_b1_8_921600 },
2581 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
2582 PCI_SUBVENDOR_ID_CONNECT_TECH,
2583 PCI_SUBDEVICE_ID_CONNECT_TECH_BH081101V1, 0, 0,
2584 pbn_b1_8_921600 },
2585 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
2586 PCI_SUBVENDOR_ID_CONNECT_TECH,
2587 PCI_SUBDEVICE_ID_CONNECT_TECH_BH041101V1, 0, 0,
2588 pbn_b1_4_921600 },
2589 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
2590 PCI_SUBVENDOR_ID_CONNECT_TECH,
2591 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_20MHZ, 0, 0,
2592 pbn_b1_2_1250000 },
2593 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
2594 PCI_SUBVENDOR_ID_CONNECT_TECH,
2595 PCI_SUBDEVICE_ID_CONNECT_TECH_TITAN_2, 0, 0,
2596 pbn_b0_2_1843200 },
2597 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
2598 PCI_SUBVENDOR_ID_CONNECT_TECH,
2599 PCI_SUBDEVICE_ID_CONNECT_TECH_TITAN_4, 0, 0,
2600 pbn_b0_4_1843200 },
2601 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
2602 PCI_VENDOR_ID_AFAVLAB,
2603 PCI_SUBDEVICE_ID_AFAVLAB_P061, 0, 0,
2604 pbn_b0_4_1152000 },
2605 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
2606 PCI_SUBVENDOR_ID_CONNECT_TECH,
2607 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_232, 0, 0,
2608 pbn_b0_2_1843200_200 },
2609 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
2610 PCI_SUBVENDOR_ID_CONNECT_TECH,
2611 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_232, 0, 0,
2612 pbn_b0_4_1843200_200 },
2613 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
2614 PCI_SUBVENDOR_ID_CONNECT_TECH,
2615 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8_232, 0, 0,
2616 pbn_b0_8_1843200_200 },
2617 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
2618 PCI_SUBVENDOR_ID_CONNECT_TECH,
2619 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_1_1, 0, 0,
2620 pbn_b0_2_1843200_200 },
2621 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
2622 PCI_SUBVENDOR_ID_CONNECT_TECH,
2623 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_2, 0, 0,
2624 pbn_b0_4_1843200_200 },
2625 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
2626 PCI_SUBVENDOR_ID_CONNECT_TECH,
2627 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_4, 0, 0,
2628 pbn_b0_8_1843200_200 },
2629 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
2630 PCI_SUBVENDOR_ID_CONNECT_TECH,
2631 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2, 0, 0,
2632 pbn_b0_2_1843200_200 },
2633 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
2634 PCI_SUBVENDOR_ID_CONNECT_TECH,
2635 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4, 0, 0,
2636 pbn_b0_4_1843200_200 },
2637 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
2638 PCI_SUBVENDOR_ID_CONNECT_TECH,
2639 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8, 0, 0,
2640 pbn_b0_8_1843200_200 },
2641 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
2642 PCI_SUBVENDOR_ID_CONNECT_TECH,
2643 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_485, 0, 0,
2644 pbn_b0_2_1843200_200 },
2645 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
2646 PCI_SUBVENDOR_ID_CONNECT_TECH,
2647 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_485, 0, 0,
2648 pbn_b0_4_1843200_200 },
2649 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
2650 PCI_SUBVENDOR_ID_CONNECT_TECH,
2651 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8_485, 0, 0,
2652 pbn_b0_8_1843200_200 },
2653
2654 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_U530,
2655 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2656 pbn_b2_bt_1_115200 },
2657 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM2,
2658 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2659 pbn_b2_bt_2_115200 },
2660 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM422,
2661 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2662 pbn_b2_bt_4_115200 },
2663 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM232,
2664 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2665 pbn_b2_bt_2_115200 },
2666 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_COMM4,
2667 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2668 pbn_b2_bt_4_115200 },
2669 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_COMM8,
2670 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2671 pbn_b2_8_115200 },
2672 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_7803,
2673 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2674 pbn_b2_8_460800 },
2675 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM8,
2676 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2677 pbn_b2_8_115200 },
2678
2679 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_GTEK_SERIAL2,
2680 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2681 pbn_b2_bt_2_115200 },
2682 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_SPCOM200,
2683 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2684 pbn_b2_bt_2_921600 },
2685 /*
2686 * VScom SPCOM800, from sl@s.pl
2687 */
2688 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_SPCOM800,
2689 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2690 pbn_b2_8_921600 },
2691 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_1077,
2692 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2693 pbn_b2_4_921600 },
2694 /* Unknown card - subdevice 0x1584 */
2695 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
2696 PCI_VENDOR_ID_PLX,
2697 PCI_SUBDEVICE_ID_UNKNOWN_0x1584, 0, 0,
2698 pbn_b0_4_115200 },
2699 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
2700 PCI_SUBVENDOR_ID_KEYSPAN,
2701 PCI_SUBDEVICE_ID_KEYSPAN_SX2, 0, 0,
2702 pbn_panacom },
2703 { PCI_VENDOR_ID_PANACOM, PCI_DEVICE_ID_PANACOM_QUADMODEM,
2704 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2705 pbn_panacom4 },
2706 { PCI_VENDOR_ID_PANACOM, PCI_DEVICE_ID_PANACOM_DUALMODEM,
2707 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2708 pbn_panacom2 },
2709 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030,
2710 PCI_VENDOR_ID_ESDGMBH,
2711 PCI_DEVICE_ID_ESDGMBH_CPCIASIO4, 0, 0,
2712 pbn_b2_4_115200 },
2713 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
2714 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
2715 PCI_SUBDEVICE_ID_CHASE_PCIFAST4, 0, 0,
2716 pbn_b2_4_460800 },
2717 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
2718 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
2719 PCI_SUBDEVICE_ID_CHASE_PCIFAST8, 0, 0,
2720 pbn_b2_8_460800 },
2721 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
2722 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
2723 PCI_SUBDEVICE_ID_CHASE_PCIFAST16, 0, 0,
2724 pbn_b2_16_460800 },
2725 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
2726 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
2727 PCI_SUBDEVICE_ID_CHASE_PCIFAST16FMC, 0, 0,
2728 pbn_b2_16_460800 },
2729 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
2730 PCI_SUBVENDOR_ID_CHASE_PCIRAS,
2731 PCI_SUBDEVICE_ID_CHASE_PCIRAS4, 0, 0,
2732 pbn_b2_4_460800 },
2733 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
2734 PCI_SUBVENDOR_ID_CHASE_PCIRAS,
2735 PCI_SUBDEVICE_ID_CHASE_PCIRAS8, 0, 0,
2736 pbn_b2_8_460800 },
2737 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
2738 PCI_SUBVENDOR_ID_EXSYS,
2739 PCI_SUBDEVICE_ID_EXSYS_4055, 0, 0,
2740 pbn_exsys_4055 },
2741 /*
2742 * Megawolf Romulus PCI Serial Card, from Mike Hudson
2743 * (Exoray@isys.ca)
2744 */
2745 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_ROMULUS,
2746 0x10b5, 0x106a, 0, 0,
2747 pbn_plx_romulus },
2748 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSC100,
2749 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2750 pbn_b1_4_115200 },
2751 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSC100,
2752 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2753 pbn_b1_2_115200 },
2754 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_ESC100D,
2755 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2756 pbn_b1_8_115200 },
2757 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_ESC100M,
2758 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2759 pbn_b1_8_115200 },
2760 { PCI_VENDOR_ID_SPECIALIX, PCI_DEVICE_ID_OXSEMI_16PCI954,
2761 PCI_VENDOR_ID_SPECIALIX, PCI_SUBDEVICE_ID_SPECIALIX_SPEED4,
2762 0, 0,
2763 pbn_b0_4_921600 },
2764 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
2765 PCI_SUBVENDOR_ID_SIIG, PCI_SUBDEVICE_ID_SIIG_QUARTET_SERIAL,
2766 0, 0,
2767 pbn_b0_4_1152000 },
2768
2769 /*
2770 * The below card is a little controversial since it is the
2771 * subject of a PCI vendor/device ID clash. (See
2772 * www.ussg.iu.edu/hypermail/linux/kernel/0303.1/0516.html).
2773 * For now just used the hex ID 0x950a.
2774 */
2775 { PCI_VENDOR_ID_OXSEMI, 0x950a,
2776 PCI_SUBVENDOR_ID_SIIG, PCI_SUBDEVICE_ID_SIIG_DUAL_SERIAL, 0, 0,
2777 pbn_b0_2_115200 },
2778 { PCI_VENDOR_ID_OXSEMI, 0x950a,
2779 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2780 pbn_b0_2_1130000 },
2781 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
2782 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2783 pbn_b0_4_115200 },
2784 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI952,
2785 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2786 pbn_b0_bt_2_921600 },
2787
2788 /*
2789 * Oxford Semiconductor Inc. Tornado PCI express device range.
2790 */
2791 { PCI_VENDOR_ID_OXSEMI, 0xc101, /* OXPCIe952 1 Legacy UART */
2792 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2793 pbn_b0_1_4000000 },
2794 { PCI_VENDOR_ID_OXSEMI, 0xc105, /* OXPCIe952 1 Legacy UART */
2795 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2796 pbn_b0_1_4000000 },
2797 { PCI_VENDOR_ID_OXSEMI, 0xc11b, /* OXPCIe952 1 Native UART */
2798 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2799 pbn_oxsemi_1_4000000 },
2800 { PCI_VENDOR_ID_OXSEMI, 0xc11f, /* OXPCIe952 1 Native UART */
2801 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2802 pbn_oxsemi_1_4000000 },
2803 { PCI_VENDOR_ID_OXSEMI, 0xc120, /* OXPCIe952 1 Legacy UART */
2804 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2805 pbn_b0_1_4000000 },
2806 { PCI_VENDOR_ID_OXSEMI, 0xc124, /* OXPCIe952 1 Legacy UART */
2807 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2808 pbn_b0_1_4000000 },
2809 { PCI_VENDOR_ID_OXSEMI, 0xc138, /* OXPCIe952 1 Native UART */
2810 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2811 pbn_oxsemi_1_4000000 },
2812 { PCI_VENDOR_ID_OXSEMI, 0xc13d, /* OXPCIe952 1 Native UART */
2813 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2814 pbn_oxsemi_1_4000000 },
2815 { PCI_VENDOR_ID_OXSEMI, 0xc140, /* OXPCIe952 1 Legacy UART */
2816 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2817 pbn_b0_1_4000000 },
2818 { PCI_VENDOR_ID_OXSEMI, 0xc141, /* OXPCIe952 1 Legacy UART */
2819 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2820 pbn_b0_1_4000000 },
2821 { PCI_VENDOR_ID_OXSEMI, 0xc144, /* OXPCIe952 1 Legacy UART */
2822 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2823 pbn_b0_1_4000000 },
2824 { PCI_VENDOR_ID_OXSEMI, 0xc145, /* OXPCIe952 1 Legacy UART */
2825 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2826 pbn_b0_1_4000000 },
2827 { PCI_VENDOR_ID_OXSEMI, 0xc158, /* OXPCIe952 2 Native UART */
2828 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2829 pbn_oxsemi_2_4000000 },
2830 { PCI_VENDOR_ID_OXSEMI, 0xc15d, /* OXPCIe952 2 Native UART */
2831 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2832 pbn_oxsemi_2_4000000 },
2833 { PCI_VENDOR_ID_OXSEMI, 0xc208, /* OXPCIe954 4 Native UART */
2834 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2835 pbn_oxsemi_4_4000000 },
2836 { PCI_VENDOR_ID_OXSEMI, 0xc20d, /* OXPCIe954 4 Native UART */
2837 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2838 pbn_oxsemi_4_4000000 },
2839 { PCI_VENDOR_ID_OXSEMI, 0xc308, /* OXPCIe958 8 Native UART */
2840 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2841 pbn_oxsemi_8_4000000 },
2842 { PCI_VENDOR_ID_OXSEMI, 0xc30d, /* OXPCIe958 8 Native UART */
2843 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2844 pbn_oxsemi_8_4000000 },
2845 { PCI_VENDOR_ID_OXSEMI, 0xc40b, /* OXPCIe200 1 Native UART */
2846 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2847 pbn_oxsemi_1_4000000 },
2848 { PCI_VENDOR_ID_OXSEMI, 0xc40f, /* OXPCIe200 1 Native UART */
2849 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2850 pbn_oxsemi_1_4000000 },
2851 { PCI_VENDOR_ID_OXSEMI, 0xc41b, /* OXPCIe200 1 Native UART */
2852 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2853 pbn_oxsemi_1_4000000 },
2854 { PCI_VENDOR_ID_OXSEMI, 0xc41f, /* OXPCIe200 1 Native UART */
2855 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2856 pbn_oxsemi_1_4000000 },
2857 { PCI_VENDOR_ID_OXSEMI, 0xc42b, /* OXPCIe200 1 Native UART */
2858 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2859 pbn_oxsemi_1_4000000 },
2860 { PCI_VENDOR_ID_OXSEMI, 0xc42f, /* OXPCIe200 1 Native UART */
2861 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2862 pbn_oxsemi_1_4000000 },
2863 { PCI_VENDOR_ID_OXSEMI, 0xc43b, /* OXPCIe200 1 Native UART */
2864 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2865 pbn_oxsemi_1_4000000 },
2866 { PCI_VENDOR_ID_OXSEMI, 0xc43f, /* OXPCIe200 1 Native UART */
2867 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2868 pbn_oxsemi_1_4000000 },
2869 { PCI_VENDOR_ID_OXSEMI, 0xc44b, /* OXPCIe200 1 Native UART */
2870 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2871 pbn_oxsemi_1_4000000 },
2872 { PCI_VENDOR_ID_OXSEMI, 0xc44f, /* OXPCIe200 1 Native UART */
2873 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2874 pbn_oxsemi_1_4000000 },
2875 { PCI_VENDOR_ID_OXSEMI, 0xc45b, /* OXPCIe200 1 Native UART */
2876 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2877 pbn_oxsemi_1_4000000 },
2878 { PCI_VENDOR_ID_OXSEMI, 0xc45f, /* OXPCIe200 1 Native UART */
2879 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2880 pbn_oxsemi_1_4000000 },
2881 { PCI_VENDOR_ID_OXSEMI, 0xc46b, /* OXPCIe200 1 Native UART */
2882 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2883 pbn_oxsemi_1_4000000 },
2884 { PCI_VENDOR_ID_OXSEMI, 0xc46f, /* OXPCIe200 1 Native UART */
2885 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2886 pbn_oxsemi_1_4000000 },
2887 { PCI_VENDOR_ID_OXSEMI, 0xc47b, /* OXPCIe200 1 Native UART */
2888 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2889 pbn_oxsemi_1_4000000 },
2890 { PCI_VENDOR_ID_OXSEMI, 0xc47f, /* OXPCIe200 1 Native UART */
2891 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2892 pbn_oxsemi_1_4000000 },
2893 { PCI_VENDOR_ID_OXSEMI, 0xc48b, /* OXPCIe200 1 Native UART */
2894 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2895 pbn_oxsemi_1_4000000 },
2896 { PCI_VENDOR_ID_OXSEMI, 0xc48f, /* OXPCIe200 1 Native UART */
2897 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2898 pbn_oxsemi_1_4000000 },
2899 { PCI_VENDOR_ID_OXSEMI, 0xc49b, /* OXPCIe200 1 Native UART */
2900 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2901 pbn_oxsemi_1_4000000 },
2902 { PCI_VENDOR_ID_OXSEMI, 0xc49f, /* OXPCIe200 1 Native UART */
2903 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2904 pbn_oxsemi_1_4000000 },
2905 { PCI_VENDOR_ID_OXSEMI, 0xc4ab, /* OXPCIe200 1 Native UART */
2906 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2907 pbn_oxsemi_1_4000000 },
2908 { PCI_VENDOR_ID_OXSEMI, 0xc4af, /* OXPCIe200 1 Native UART */
2909 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2910 pbn_oxsemi_1_4000000 },
2911 { PCI_VENDOR_ID_OXSEMI, 0xc4bb, /* OXPCIe200 1 Native UART */
2912 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2913 pbn_oxsemi_1_4000000 },
2914 { PCI_VENDOR_ID_OXSEMI, 0xc4bf, /* OXPCIe200 1 Native UART */
2915 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2916 pbn_oxsemi_1_4000000 },
2917 { PCI_VENDOR_ID_OXSEMI, 0xc4cb, /* OXPCIe200 1 Native UART */
2918 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2919 pbn_oxsemi_1_4000000 },
2920 { PCI_VENDOR_ID_OXSEMI, 0xc4cf, /* OXPCIe200 1 Native UART */
2921 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2922 pbn_oxsemi_1_4000000 },
2923 /*
2924 * Mainpine Inc. IQ Express "Rev3" utilizing OxSemi Tornado
2925 */
2926 { PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 1 Port V.34 Super-G3 Fax */
2927 PCI_VENDOR_ID_MAINPINE, 0x4001, 0, 0,
2928 pbn_oxsemi_1_4000000 },
2929 { PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 2 Port V.34 Super-G3 Fax */
2930 PCI_VENDOR_ID_MAINPINE, 0x4002, 0, 0,
2931 pbn_oxsemi_2_4000000 },
2932 { PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 4 Port V.34 Super-G3 Fax */
2933 PCI_VENDOR_ID_MAINPINE, 0x4004, 0, 0,
2934 pbn_oxsemi_4_4000000 },
2935 { PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 8 Port V.34 Super-G3 Fax */
2936 PCI_VENDOR_ID_MAINPINE, 0x4008, 0, 0,
2937 pbn_oxsemi_8_4000000 },
2938 /*
2939 * SBS Technologies, Inc. P-Octal and PMC-OCTPRO cards,
2940 * from skokodyn@yahoo.com
2941 */
2942 { PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
2943 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_OCTPRO232, 0, 0,
2944 pbn_sbsxrsio },
2945 { PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
2946 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_OCTPRO422, 0, 0,
2947 pbn_sbsxrsio },
2948 { PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
2949 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_POCTAL232, 0, 0,
2950 pbn_sbsxrsio },
2951 { PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
2952 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_POCTAL422, 0, 0,
2953 pbn_sbsxrsio },
2954
2955 /*
2956 * Digitan DS560-558, from jimd@esoft.com
2957 */
2958 { PCI_VENDOR_ID_ATT, PCI_DEVICE_ID_ATT_VENUS_MODEM,
2959 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2960 pbn_b1_1_115200 },
2961
2962 /*
2963 * Titan Electronic cards
2964 * The 400L and 800L have a custom setup quirk.
2965 */
2966 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_100,
2967 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2968 pbn_b0_1_921600 },
2969 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200,
2970 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2971 pbn_b0_2_921600 },
2972 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400,
2973 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2974 pbn_b0_4_921600 },
2975 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800B,
2976 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2977 pbn_b0_4_921600 },
2978 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_100L,
2979 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2980 pbn_b1_1_921600 },
2981 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200L,
2982 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2983 pbn_b1_bt_2_921600 },
2984 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400L,
2985 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2986 pbn_b0_bt_4_921600 },
2987 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800L,
2988 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2989 pbn_b0_bt_8_921600 },
2990
2991 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_550,
2992 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2993 pbn_b2_1_460800 },
2994 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_650,
2995 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2996 pbn_b2_1_460800 },
2997 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_850,
2998 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2999 pbn_b2_1_460800 },
3000 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_550,
3001 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3002 pbn_b2_bt_2_921600 },
3003 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_650,
3004 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3005 pbn_b2_bt_2_921600 },
3006 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_850,
3007 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3008 pbn_b2_bt_2_921600 },
3009 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_550,
3010 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3011 pbn_b2_bt_4_921600 },
3012 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_650,
3013 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3014 pbn_b2_bt_4_921600 },
3015 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_850,
3016 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3017 pbn_b2_bt_4_921600 },
3018 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_550,
3019 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3020 pbn_b0_1_921600 },
3021 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_650,
3022 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3023 pbn_b0_1_921600 },
3024 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_850,
3025 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3026 pbn_b0_1_921600 },
3027 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_550,
3028 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3029 pbn_b0_bt_2_921600 },
3030 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_650,
3031 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3032 pbn_b0_bt_2_921600 },
3033 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_850,
3034 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3035 pbn_b0_bt_2_921600 },
3036 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_550,
3037 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3038 pbn_b0_bt_4_921600 },
3039 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_650,
3040 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3041 pbn_b0_bt_4_921600 },
3042 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_850,
3043 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3044 pbn_b0_bt_4_921600 },
3045 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_8S_20x_550,
3046 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3047 pbn_b0_bt_8_921600 },
3048 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_8S_20x_650,
3049 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3050 pbn_b0_bt_8_921600 },
3051 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_8S_20x_850,
3052 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3053 pbn_b0_bt_8_921600 },
3054
3055 /*
3056 * Computone devices submitted by Doug McNash dmcnash@computone.com
3057 */
3058 { PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG,
3059 PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG4,
3060 0, 0, pbn_computone_4 },
3061 { PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG,
3062 PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG8,
3063 0, 0, pbn_computone_8 },
3064 { PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG,
3065 PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG6,
3066 0, 0, pbn_computone_6 },
3067
3068 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI95N,
3069 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3070 pbn_oxsemi },
3071 { PCI_VENDOR_ID_TIMEDIA, PCI_DEVICE_ID_TIMEDIA_1889,
3072 PCI_VENDOR_ID_TIMEDIA, PCI_ANY_ID, 0, 0,
3073 pbn_b0_bt_1_921600 },
3074
3075 /*
3076 * AFAVLAB serial card, from Harald Welte <laforge@gnumonks.org>
3077 */
3078 { PCI_VENDOR_ID_AFAVLAB, PCI_DEVICE_ID_AFAVLAB_P028,
3079 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3080 pbn_b0_bt_8_115200 },
3081 { PCI_VENDOR_ID_AFAVLAB, PCI_DEVICE_ID_AFAVLAB_P030,
3082 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3083 pbn_b0_bt_8_115200 },
3084
3085 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_DSERIAL,
3086 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3087 pbn_b0_bt_2_115200 },
3088 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATRO_A,
3089 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3090 pbn_b0_bt_2_115200 },
3091 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATRO_B,
3092 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3093 pbn_b0_bt_2_115200 },
3094 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_OCTO_A,
3095 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3096 pbn_b0_bt_4_460800 },
3097 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_OCTO_B,
3098 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3099 pbn_b0_bt_4_460800 },
3100 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_PORT_PLUS,
3101 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3102 pbn_b0_bt_2_460800 },
3103 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUAD_A,
3104 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3105 pbn_b0_bt_2_460800 },
3106 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUAD_B,
3107 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3108 pbn_b0_bt_2_460800 },
3109 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_SSERIAL,
3110 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3111 pbn_b0_bt_1_115200 },
3112 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_PORT_650,
3113 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3114 pbn_b0_bt_1_460800 },
3115
3116 /*
3117 * Korenix Jetcard F0/F1 cards (JC1204, JC1208, JC1404, JC1408).
3118 * Cards are identified by their subsystem vendor IDs, which
3119 * (in hex) match the model number.
3120 *
3121 * Note that JC140x are RS422/485 cards which require ox950
3122 * ACR = 0x10, and as such are not currently fully supported.
3123 */
3124 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0,
3125 0x1204, 0x0004, 0, 0,
3126 pbn_b0_4_921600 },
3127 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0,
3128 0x1208, 0x0004, 0, 0,
3129 pbn_b0_4_921600 },
3130 /* { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0,
3131 0x1402, 0x0002, 0, 0,
3132 pbn_b0_2_921600 }, */
3133 /* { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0,
3134 0x1404, 0x0004, 0, 0,
3135 pbn_b0_4_921600 }, */
3136 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF1,
3137 0x1208, 0x0004, 0, 0,
3138 pbn_b0_4_921600 },
3139
3140 /*
3141 * Dell Remote Access Card 4 - Tim_T_Murphy@Dell.com
3142 */
3143 { PCI_VENDOR_ID_DELL, PCI_DEVICE_ID_DELL_RAC4,
3144 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3145 pbn_b1_1_1382400 },
3146
3147 /*
3148 * Dell Remote Access Card III - Tim_T_Murphy@Dell.com
3149 */
3150 { PCI_VENDOR_ID_DELL, PCI_DEVICE_ID_DELL_RACIII,
3151 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3152 pbn_b1_1_1382400 },
3153
3154 /*
3155 * RAStel 2 port modem, gerg@moreton.com.au
3156 */
3157 { PCI_VENDOR_ID_MORETON, PCI_DEVICE_ID_RASTEL_2PORT,
3158 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3159 pbn_b2_bt_2_115200 },
3160
3161 /*
3162 * EKF addition for i960 Boards form EKF with serial port
3163 */
3164 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80960_RP,
3165 0xE4BF, PCI_ANY_ID, 0, 0,
3166 pbn_intel_i960 },
3167
3168 /*
3169 * Xircom Cardbus/Ethernet combos
3170 */
3171 { PCI_VENDOR_ID_XIRCOM, PCI_DEVICE_ID_XIRCOM_X3201_MDM,
3172 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3173 pbn_b0_1_115200 },
3174 /*
3175 * Xircom RBM56G cardbus modem - Dirk Arnold (temp entry)
3176 */
3177 { PCI_VENDOR_ID_XIRCOM, PCI_DEVICE_ID_XIRCOM_RBM56G,
3178 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3179 pbn_b0_1_115200 },
3180
3181 /*
3182 * Untested PCI modems, sent in from various folks...
3183 */
3184
3185 /*
3186 * Elsa Model 56K PCI Modem, from Andreas Rath <arh@01019freenet.de>
3187 */
3188 { PCI_VENDOR_ID_ROCKWELL, 0x1004,
3189 0x1048, 0x1500, 0, 0,
3190 pbn_b1_1_115200 },
3191
3192 { PCI_VENDOR_ID_SGI, PCI_DEVICE_ID_SGI_IOC3,
3193 0xFF00, 0, 0, 0,
3194 pbn_sgi_ioc3 },
3195
3196 /*
3197 * HP Diva card
3198 */
3199 { PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA,
3200 PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA_RMP3, 0, 0,
3201 pbn_b1_1_115200 },
3202 { PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA,
3203 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3204 pbn_b0_5_115200 },
3205 { PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA_AUX,
3206 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3207 pbn_b2_1_115200 },
3208
3209 { PCI_VENDOR_ID_DCI, PCI_DEVICE_ID_DCI_PCCOM2,
3210 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3211 pbn_b3_2_115200 },
3212 { PCI_VENDOR_ID_DCI, PCI_DEVICE_ID_DCI_PCCOM4,
3213 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3214 pbn_b3_4_115200 },
3215 { PCI_VENDOR_ID_DCI, PCI_DEVICE_ID_DCI_PCCOM8,
3216 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3217 pbn_b3_8_115200 },
3218
3219 /*
3220 * Exar Corp. XR17C15[248] Dual/Quad/Octal UART
3221 */
3222 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
3223 PCI_ANY_ID, PCI_ANY_ID,
3224 0,
3225 0, pbn_exar_XR17C152 },
3226 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
3227 PCI_ANY_ID, PCI_ANY_ID,
3228 0,
3229 0, pbn_exar_XR17C154 },
3230 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
3231 PCI_ANY_ID, PCI_ANY_ID,
3232 0,
3233 0, pbn_exar_XR17C158 },
3234
3235 /*
3236 * Topic TP560 Data/Fax/Voice 56k modem (reported by Evan Clarke)
3237 */
3238 { PCI_VENDOR_ID_TOPIC, PCI_DEVICE_ID_TOPIC_TP560,
3239 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3240 pbn_b0_1_115200 },
3241 /*
3242 * ITE
3243 */
3244 { PCI_VENDOR_ID_ITE, PCI_DEVICE_ID_ITE_8872,
3245 PCI_ANY_ID, PCI_ANY_ID,
3246 0, 0,
3247 pbn_b1_bt_1_115200 },
3248
3249 /*
3250 * IntaShield IS-200
3251 */
3252 { PCI_VENDOR_ID_INTASHIELD, PCI_DEVICE_ID_INTASHIELD_IS200,
3253 PCI_ANY_ID, PCI_ANY_ID, 0, 0, /* 135a.0811 */
3254 pbn_b2_2_115200 },
3255 /*
3256 * IntaShield IS-400
3257 */
3258 { PCI_VENDOR_ID_INTASHIELD, PCI_DEVICE_ID_INTASHIELD_IS400,
3259 PCI_ANY_ID, PCI_ANY_ID, 0, 0, /* 135a.0dc0 */
3260 pbn_b2_4_115200 },
3261 /*
3262 * Perle PCI-RAS cards
3263 */
3264 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030,
3265 PCI_SUBVENDOR_ID_PERLE, PCI_SUBDEVICE_ID_PCI_RAS4,
3266 0, 0, pbn_b2_4_921600 },
3267 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030,
3268 PCI_SUBVENDOR_ID_PERLE, PCI_SUBDEVICE_ID_PCI_RAS8,
3269 0, 0, pbn_b2_8_921600 },
3270
3271 /*
3272 * Mainpine series cards: Fairly standard layout but fools
3273 * parts of the autodetect in some cases and uses otherwise
3274 * unmatched communications subclasses in the PCI Express case
3275 */
3276
3277 { /* RockForceDUO */
3278 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3279 PCI_VENDOR_ID_MAINPINE, 0x0200,
3280 0, 0, pbn_b0_2_115200 },
3281 { /* RockForceQUATRO */
3282 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3283 PCI_VENDOR_ID_MAINPINE, 0x0300,
3284 0, 0, pbn_b0_4_115200 },
3285 { /* RockForceDUO+ */
3286 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3287 PCI_VENDOR_ID_MAINPINE, 0x0400,
3288 0, 0, pbn_b0_2_115200 },
3289 { /* RockForceQUATRO+ */
3290 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3291 PCI_VENDOR_ID_MAINPINE, 0x0500,
3292 0, 0, pbn_b0_4_115200 },
3293 { /* RockForce+ */
3294 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3295 PCI_VENDOR_ID_MAINPINE, 0x0600,
3296 0, 0, pbn_b0_2_115200 },
3297 { /* RockForce+ */
3298 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3299 PCI_VENDOR_ID_MAINPINE, 0x0700,
3300 0, 0, pbn_b0_4_115200 },
3301 { /* RockForceOCTO+ */
3302 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3303 PCI_VENDOR_ID_MAINPINE, 0x0800,
3304 0, 0, pbn_b0_8_115200 },
3305 { /* RockForceDUO+ */
3306 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3307 PCI_VENDOR_ID_MAINPINE, 0x0C00,
3308 0, 0, pbn_b0_2_115200 },
3309 { /* RockForceQUARTRO+ */
3310 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3311 PCI_VENDOR_ID_MAINPINE, 0x0D00,
3312 0, 0, pbn_b0_4_115200 },
3313 { /* RockForceOCTO+ */
3314 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3315 PCI_VENDOR_ID_MAINPINE, 0x1D00,
3316 0, 0, pbn_b0_8_115200 },
3317 { /* RockForceD1 */
3318 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3319 PCI_VENDOR_ID_MAINPINE, 0x2000,
3320 0, 0, pbn_b0_1_115200 },
3321 { /* RockForceF1 */
3322 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3323 PCI_VENDOR_ID_MAINPINE, 0x2100,
3324 0, 0, pbn_b0_1_115200 },
3325 { /* RockForceD2 */
3326 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3327 PCI_VENDOR_ID_MAINPINE, 0x2200,
3328 0, 0, pbn_b0_2_115200 },
3329 { /* RockForceF2 */
3330 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3331 PCI_VENDOR_ID_MAINPINE, 0x2300,
3332 0, 0, pbn_b0_2_115200 },
3333 { /* RockForceD4 */
3334 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3335 PCI_VENDOR_ID_MAINPINE, 0x2400,
3336 0, 0, pbn_b0_4_115200 },
3337 { /* RockForceF4 */
3338 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3339 PCI_VENDOR_ID_MAINPINE, 0x2500,
3340 0, 0, pbn_b0_4_115200 },
3341 { /* RockForceD8 */
3342 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3343 PCI_VENDOR_ID_MAINPINE, 0x2600,
3344 0, 0, pbn_b0_8_115200 },
3345 { /* RockForceF8 */
3346 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3347 PCI_VENDOR_ID_MAINPINE, 0x2700,
3348 0, 0, pbn_b0_8_115200 },
3349 { /* IQ Express D1 */
3350 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3351 PCI_VENDOR_ID_MAINPINE, 0x3000,
3352 0, 0, pbn_b0_1_115200 },
3353 { /* IQ Express F1 */
3354 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3355 PCI_VENDOR_ID_MAINPINE, 0x3100,
3356 0, 0, pbn_b0_1_115200 },
3357 { /* IQ Express D2 */
3358 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3359 PCI_VENDOR_ID_MAINPINE, 0x3200,
3360 0, 0, pbn_b0_2_115200 },
3361 { /* IQ Express F2 */
3362 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3363 PCI_VENDOR_ID_MAINPINE, 0x3300,
3364 0, 0, pbn_b0_2_115200 },
3365 { /* IQ Express D4 */
3366 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3367 PCI_VENDOR_ID_MAINPINE, 0x3400,
3368 0, 0, pbn_b0_4_115200 },
3369 { /* IQ Express F4 */
3370 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3371 PCI_VENDOR_ID_MAINPINE, 0x3500,
3372 0, 0, pbn_b0_4_115200 },
3373 { /* IQ Express D8 */
3374 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3375 PCI_VENDOR_ID_MAINPINE, 0x3C00,
3376 0, 0, pbn_b0_8_115200 },
3377 { /* IQ Express F8 */
3378 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3379 PCI_VENDOR_ID_MAINPINE, 0x3D00,
3380 0, 0, pbn_b0_8_115200 },
3381
3382
3383 /*
3384 * PA Semi PA6T-1682M on-chip UART
3385 */
3386 { PCI_VENDOR_ID_PASEMI, 0xa004,
3387 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3388 pbn_pasemi_1682M },
3389
3390 /*
3391 * National Instruments
3392 */
3393 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI23216,
3394 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3395 pbn_b1_16_115200 },
3396 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2328,
3397 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3398 pbn_b1_8_115200 },
3399 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2324,
3400 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3401 pbn_b1_bt_4_115200 },
3402 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2322,
3403 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3404 pbn_b1_bt_2_115200 },
3405 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2324I,
3406 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3407 pbn_b1_bt_4_115200 },
3408 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2322I,
3409 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3410 pbn_b1_bt_2_115200 },
3411 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_23216,
3412 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3413 pbn_b1_16_115200 },
3414 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_2328,
3415 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3416 pbn_b1_8_115200 },
3417 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_2324,
3418 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3419 pbn_b1_bt_4_115200 },
3420 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_2322,
3421 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3422 pbn_b1_bt_2_115200 },
3423 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8422_2324,
3424 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3425 pbn_b1_bt_4_115200 },
3426 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8422_2322,
3427 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3428 pbn_b1_bt_2_115200 },
3429 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_2322,
3430 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3431 pbn_ni8430_2 },
3432 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_2322,
3433 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3434 pbn_ni8430_2 },
3435 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_2324,
3436 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3437 pbn_ni8430_4 },
3438 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_2324,
3439 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3440 pbn_ni8430_4 },
3441 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_2328,
3442 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3443 pbn_ni8430_8 },
3444 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_2328,
3445 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3446 pbn_ni8430_8 },
3447 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_23216,
3448 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3449 pbn_ni8430_16 },
3450 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_23216,
3451 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3452 pbn_ni8430_16 },
3453 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8432_2322,
3454 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3455 pbn_ni8430_2 },
3456 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8432_2322,
3457 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3458 pbn_ni8430_2 },
3459 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8432_2324,
3460 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3461 pbn_ni8430_4 },
3462 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8432_2324,
3463 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3464 pbn_ni8430_4 },
3465
3466 /*
3467 * ADDI-DATA GmbH communication cards <info@addi-data.com>
3468 */
3469 { PCI_VENDOR_ID_ADDIDATA,
3470 PCI_DEVICE_ID_ADDIDATA_APCI7500,
3471 PCI_ANY_ID,
3472 PCI_ANY_ID,
3473 0,
3474 0,
3475 pbn_b0_4_115200 },
3476
3477 { PCI_VENDOR_ID_ADDIDATA,
3478 PCI_DEVICE_ID_ADDIDATA_APCI7420,
3479 PCI_ANY_ID,
3480 PCI_ANY_ID,
3481 0,
3482 0,
3483 pbn_b0_2_115200 },
3484
3485 { PCI_VENDOR_ID_ADDIDATA,
3486 PCI_DEVICE_ID_ADDIDATA_APCI7300,
3487 PCI_ANY_ID,
3488 PCI_ANY_ID,
3489 0,
3490 0,
3491 pbn_b0_1_115200 },
3492
3493 { PCI_VENDOR_ID_ADDIDATA_OLD,
3494 PCI_DEVICE_ID_ADDIDATA_APCI7800,
3495 PCI_ANY_ID,
3496 PCI_ANY_ID,
3497 0,
3498 0,
3499 pbn_b1_8_115200 },
3500
3501 { PCI_VENDOR_ID_ADDIDATA,
3502 PCI_DEVICE_ID_ADDIDATA_APCI7500_2,
3503 PCI_ANY_ID,
3504 PCI_ANY_ID,
3505 0,
3506 0,
3507 pbn_b0_4_115200 },
3508
3509 { PCI_VENDOR_ID_ADDIDATA,
3510 PCI_DEVICE_ID_ADDIDATA_APCI7420_2,
3511 PCI_ANY_ID,
3512 PCI_ANY_ID,
3513 0,
3514 0,
3515 pbn_b0_2_115200 },
3516
3517 { PCI_VENDOR_ID_ADDIDATA,
3518 PCI_DEVICE_ID_ADDIDATA_APCI7300_2,
3519 PCI_ANY_ID,
3520 PCI_ANY_ID,
3521 0,
3522 0,
3523 pbn_b0_1_115200 },
3524
3525 { PCI_VENDOR_ID_ADDIDATA,
3526 PCI_DEVICE_ID_ADDIDATA_APCI7500_3,
3527 PCI_ANY_ID,
3528 PCI_ANY_ID,
3529 0,
3530 0,
3531 pbn_b0_4_115200 },
3532
3533 { PCI_VENDOR_ID_ADDIDATA,
3534 PCI_DEVICE_ID_ADDIDATA_APCI7420_3,
3535 PCI_ANY_ID,
3536 PCI_ANY_ID,
3537 0,
3538 0,
3539 pbn_b0_2_115200 },
3540
3541 { PCI_VENDOR_ID_ADDIDATA,
3542 PCI_DEVICE_ID_ADDIDATA_APCI7300_3,
3543 PCI_ANY_ID,
3544 PCI_ANY_ID,
3545 0,
3546 0,
3547 pbn_b0_1_115200 },
3548
3549 { PCI_VENDOR_ID_ADDIDATA,
3550 PCI_DEVICE_ID_ADDIDATA_APCI7800_3,
3551 PCI_ANY_ID,
3552 PCI_ANY_ID,
3553 0,
3554 0,
3555 pbn_b0_8_115200 },
3556
3557 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9835,
3558 PCI_VENDOR_ID_IBM, 0x0299,
3559 0, 0, pbn_b0_bt_2_115200 },
3560
3561 /*
3562 * These entries match devices with class COMMUNICATION_SERIAL,
3563 * COMMUNICATION_MODEM or COMMUNICATION_MULTISERIAL
3564 */
3565 { PCI_ANY_ID, PCI_ANY_ID,
3566 PCI_ANY_ID, PCI_ANY_ID,
3567 PCI_CLASS_COMMUNICATION_SERIAL << 8,
3568 0xffff00, pbn_default },
3569 { PCI_ANY_ID, PCI_ANY_ID,
3570 PCI_ANY_ID, PCI_ANY_ID,
3571 PCI_CLASS_COMMUNICATION_MODEM << 8,
3572 0xffff00, pbn_default },
3573 { PCI_ANY_ID, PCI_ANY_ID,
3574 PCI_ANY_ID, PCI_ANY_ID,
3575 PCI_CLASS_COMMUNICATION_MULTISERIAL << 8,
3576 0xffff00, pbn_default },
3577 { 0, }
3578 };
3579
3580 static struct pci_driver serial_pci_driver = {
3581 .name = "serial",
3582 .probe = pciserial_init_one,
3583 .remove = __devexit_p(pciserial_remove_one),
3584 #ifdef CONFIG_PM
3585 .suspend = pciserial_suspend_one,
3586 .resume = pciserial_resume_one,
3587 #endif
3588 .id_table = serial_pci_tbl,
3589 };
3590
3591 static int __init serial8250_pci_init(void)
3592 {
3593 return pci_register_driver(&serial_pci_driver);
3594 }
3595
3596 static void __exit serial8250_pci_exit(void)
3597 {
3598 pci_unregister_driver(&serial_pci_driver);
3599 }
3600
3601 module_init(serial8250_pci_init);
3602 module_exit(serial8250_pci_exit);
3603
3604 MODULE_LICENSE("GPL");
3605 MODULE_DESCRIPTION("Generic 8250/16x50 PCI serial probe module");
3606 MODULE_DEVICE_TABLE(pci, serial_pci_tbl);
Linus' kernel tree