drivers/gpu/drm/nouveau/nv50_instmem.c

   1 /*
   2  * Copyright (C) 2007 Ben Skeggs.
   3  *
   4  * All Rights Reserved.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining
   7  * a copy of this software and associated documentation files (the
   8  * "Software"), to deal in the Software without restriction, including
   9  * without limitation the rights to use, copy, modify, merge, publish,
  10  * distribute, sublicense, and/or sell copies of the Software, and to
  11  * permit persons to whom the Software is furnished to do so, subject to
  12  * the following conditions:
  13  *
  14  * The above copyright notice and this permission notice (including the
  15  * next paragraph) shall be included in all copies or substantial
  16  * portions of the Software.
  17  *
  18  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  19  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  20  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
  21  * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
  22  * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
  23  * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
  24  * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  25  *
  26  */
  27
  28 #include "drmP.h"
  29 #include "drm.h"
  30 #include "nouveau_drv.h"
  31
  32 struct nv50_instmem_priv {
  33         uint32_t save1700[5]; /* 0x1700->0x1710 */
  34
  35         struct nouveau_gpuobj *pramin_pt;
  36         struct nouveau_gpuobj *pramin_bar;
  37         struct nouveau_gpuobj *fb_bar;
  38 };
  39
  40 #define NV50_INSTMEM_PAGE_SHIFT 12
  41 #define NV50_INSTMEM_PAGE_SIZE  (1 << NV50_INSTMEM_PAGE_SHIFT)
  42 #define NV50_INSTMEM_PT_SIZE(a) (((a) >> 12) << 3)
  43
  44 /*NOTE: - Assumes 0x1700 already covers the correct MiB of PRAMIN
  45  */
  46 #define BAR0_WI32(g, o, v) do {                                   \
  47         u32 offset = (g)->vinst + (o);                            \
  48         nv_wr32(dev, NV_RAMIN + (offset & 0xfffff), (v));         \
  49 } while (0)
  50
  51 int
  52 nv50_instmem_init(struct drm_device *dev)
  53 {
  54         struct drm_nouveau_private *dev_priv = dev->dev_private;
  55         struct nouveau_channel *chan;
  56         uint32_t c_offset, c_size, c_ramfc, c_vmpd, c_base, pt_size;
  57         uint32_t save_nv001700;
  58         uint64_t v;
  59         struct nv50_instmem_priv *priv;
  60         int ret, i;
  61
  62         priv = kzalloc(sizeof(*priv), GFP_KERNEL);
  63         if (!priv)
  64                 return -ENOMEM;
  65         dev_priv->engine.instmem.priv = priv;
  66
  67         /* Save state, will restore at takedown. */
  68         for (i = 0x1700; i <= 0x1710; i += 4)
  69                 priv->save1700[(i-0x1700)/4] = nv_rd32(dev, i);
  70
  71         /* Reserve the last MiB of VRAM, we should probably try to avoid
  72          * setting up the below tables over the top of the VBIOS image at
  73          * some point.
  74          */
  75         dev_priv->ramin_rsvd_vram = 1 << 20;
  76         c_offset = dev_priv->vram_size - dev_priv->ramin_rsvd_vram;
  77         c_size   = 128 << 10;
  78         c_vmpd   = ((dev_priv->chipset & 0xf0) == 0x50) ? 0x1400 : 0x200;
  79         c_ramfc  = ((dev_priv->chipset & 0xf0) == 0x50) ? 0x0 : 0x20;
  80         c_base   = c_vmpd + 0x4000;
  81         pt_size  = NV50_INSTMEM_PT_SIZE(dev_priv->ramin_size);
  82
  83         NV_DEBUG(dev, " Rsvd VRAM base: 0x%08x\n", c_offset);
  84         NV_DEBUG(dev, "    VBIOS image: 0x%08x\n",
  85                                 (nv_rd32(dev, 0x619f04) & ~0xff) << 8);
  86         NV_DEBUG(dev, "  Aperture size: %d MiB\n", dev_priv->ramin_size >> 20);
  87         NV_DEBUG(dev, "        PT size: %d KiB\n", pt_size >> 10);
  88
  89         /* Determine VM layout, we need to do this first to make sure
  90          * we allocate enough memory for all the page tables.
  91          */
  92         dev_priv->vm_gart_base = roundup(NV50_VM_BLOCK, NV50_VM_BLOCK);
  93         dev_priv->vm_gart_size = NV50_VM_BLOCK;
  94
  95         dev_priv->vm_vram_base = dev_priv->vm_gart_base + dev_priv->vm_gart_size;
  96         dev_priv->vm_vram_size = dev_priv->vram_size;
  97         if (dev_priv->vm_vram_size > NV50_VM_MAX_VRAM)
  98                 dev_priv->vm_vram_size = NV50_VM_MAX_VRAM;
  99         dev_priv->vm_vram_size = roundup(dev_priv->vm_vram_size, NV50_VM_BLOCK);
 100         dev_priv->vm_vram_pt_nr = dev_priv->vm_vram_size / NV50_VM_BLOCK;
 101
 102         dev_priv->vm_end = dev_priv->vm_vram_base + dev_priv->vm_vram_size;
 103
 104         NV_DEBUG(dev, "NV50VM: GART 0x%016llx-0x%016llx\n",
 105                  dev_priv->vm_gart_base,
 106                  dev_priv->vm_gart_base + dev_priv->vm_gart_size - 1);
 107         NV_DEBUG(dev, "NV50VM: VRAM 0x%016llx-0x%016llx\n",
 108                  dev_priv->vm_vram_base,
 109                  dev_priv->vm_vram_base + dev_priv->vm_vram_size - 1);
 110
 111         c_size += dev_priv->vm_vram_pt_nr * (NV50_VM_BLOCK / 65536 * 8);
 112
 113         /* Map BAR0 PRAMIN aperture over the memory we want to use */
 114         save_nv001700 = nv_rd32(dev, NV50_PUNK_BAR0_PRAMIN);
 115         nv_wr32(dev, NV50_PUNK_BAR0_PRAMIN, (c_offset >> 16));
 116
 117         /* Create a fake channel, and use it as our "dummy" channels 0/127.
 118          * The main reason for creating a channel is so we can use the gpuobj
 119          * code.  However, it's probably worth noting that NVIDIA also setup
 120          * their channels 0/127 with the same values they configure here.
 121          * So, there may be some other reason for doing this.
 122          *
 123          * Have to create the entire channel manually, as the real channel
 124          * creation code assumes we have PRAMIN access, and we don't until
 125          * we're done here.
 126          */
 127         chan = kzalloc(sizeof(*chan), GFP_KERNEL);
 128         if (!chan)
 129                 return -ENOMEM;
 130         chan->id = 0;
 131         chan->dev = dev;
 132         chan->file_priv = (struct drm_file *)-2;
 133         dev_priv->fifos[0] = dev_priv->fifos[127] = chan;
 134
 135         INIT_LIST_HEAD(&chan->ramht_refs);
 136
 137         /* Channel's PRAMIN object + heap */
 138         ret = nouveau_gpuobj_new_fake(dev, 0, c_offset, c_size, 0, &chan->ramin);
 139         if (ret)
 140                 return ret;
 141
 142         if (drm_mm_init(&chan->ramin_heap, c_base, c_size - c_base))
 143                 return -ENOMEM;
 144
 145         /* RAMFC + zero channel's PRAMIN up to start of VM pagedir */
 146         ret = nouveau_gpuobj_new_fake(dev, c_ramfc, c_offset + c_ramfc,
 147                                       0x4000, 0, &chan->ramfc);
 148         if (ret)
 149                 return ret;
 150
 151         for (i = 0; i < c_vmpd; i += 4)
 152                 BAR0_WI32(chan->ramin, i, 0);
 153
 154         /* VM page directory */
 155         ret = nouveau_gpuobj_new_fake(dev, c_vmpd, c_offset + c_vmpd,
 156                                       0x4000, 0, &chan->vm_pd);
 157         if (ret)
 158                 return ret;
 159         for (i = 0; i < 0x4000; i += 8) {
 160                 BAR0_WI32(chan->vm_pd, i + 0x00, 0x00000000);
 161                 BAR0_WI32(chan->vm_pd, i + 0x04, 0x00000000);
 162         }
 163
 164         /* PRAMIN page table, cheat and map into VM at 0x0000000000.
 165          * We map the entire fake channel into the start of the PRAMIN BAR
 166          */
 167         ret = nouveau_gpuobj_new(dev, chan, pt_size, 0x1000, 0,
 168                                  &priv->pramin_pt);
 169         if (ret)
 170                 return ret;
 171
 172         v = c_offset | 1;
 173         if (dev_priv->vram_sys_base) {
 174                 v += dev_priv->vram_sys_base;
 175                 v |= 0x30;
 176         }
 177
 178         i = 0;
 179         while (v < dev_priv->vram_sys_base + c_offset + c_size) {
 180                 BAR0_WI32(priv->pramin_pt, i + 0, lower_32_bits(v));
 181                 BAR0_WI32(priv->pramin_pt, i + 4, upper_32_bits(v));
 182                 v += 0x1000;
 183                 i += 8;
 184         }
 185
 186         while (i < pt_size) {
 187                 BAR0_WI32(priv->pramin_pt, i + 0, 0x00000000);
 188                 BAR0_WI32(priv->pramin_pt, i + 4, 0x00000000);
 189                 i += 8;
 190         }
 191
 192         BAR0_WI32(chan->vm_pd, 0x00, priv->pramin_pt->vinst | 0x63);
 193         BAR0_WI32(chan->vm_pd, 0x04, 0x00000000);
 194
 195         /* VRAM page table(s), mapped into VM at +1GiB  */
 196         for (i = 0; i < dev_priv->vm_vram_pt_nr; i++) {
 197                 ret = nouveau_gpuobj_new(dev, chan, NV50_VM_BLOCK / 0x10000 * 8,
 198                                          0, 0, &chan->vm_vram_pt[i]);
 199                 if (ret) {
 200                         NV_ERROR(dev, "Error creating VRAM page tables: %d\n",
 201                                                                         ret);
 202                         dev_priv->vm_vram_pt_nr = i;
 203                         return ret;
 204                 }
 205                 /*XXX: double-check this is ok */
 206                 dev_priv->vm_vram_pt[i] = chan->vm_vram_pt[i];
 207
 208                 for (v = 0; v < dev_priv->vm_vram_pt[i]->size; v += 4)
 209                         BAR0_WI32(dev_priv->vm_vram_pt[i], v, 0);
 210
 211                 BAR0_WI32(chan->vm_pd, 0x10 + (i*8),
 212                           chan->vm_vram_pt[i]->vinst | 0x61);
 213                 BAR0_WI32(chan->vm_pd, 0x14 + (i*8), 0);
 214         }
 215
 216         /* DMA object for PRAMIN BAR */
 217         ret = nouveau_gpuobj_new(dev, chan, 6*4, 16, 0, &priv->pramin_bar);
 218         if (ret)
 219                 return ret;
 220         BAR0_WI32(priv->pramin_bar, 0x00, 0x7fc00000);
 221         BAR0_WI32(priv->pramin_bar, 0x04, dev_priv->ramin_size - 1);
 222         BAR0_WI32(priv->pramin_bar, 0x08, 0x00000000);
 223         BAR0_WI32(priv->pramin_bar, 0x0c, 0x00000000);
 224         BAR0_WI32(priv->pramin_bar, 0x10, 0x00000000);
 225         BAR0_WI32(priv->pramin_bar, 0x14, 0x00000000);
 226
 227         /* DMA object for FB BAR */
 228         ret = nouveau_gpuobj_new(dev, chan, 6*4, 16, 0, &priv->fb_bar);
 229         if (ret)
 230                 return ret;
 231         BAR0_WI32(priv->fb_bar, 0x00, 0x7fc00000);
 232         BAR0_WI32(priv->fb_bar, 0x04, 0x40000000 +
 233                                       pci_resource_len(dev->pdev, 1) - 1);
 234         BAR0_WI32(priv->fb_bar, 0x08, 0x40000000);
 235         BAR0_WI32(priv->fb_bar, 0x0c, 0x00000000);
 236         BAR0_WI32(priv->fb_bar, 0x10, 0x00000000);
 237         BAR0_WI32(priv->fb_bar, 0x14, 0x00000000);
 238
 239         /* Poke the relevant regs, and pray it works :) */
 240         nv_wr32(dev, NV50_PUNK_BAR_CFG_BASE, (chan->ramin->vinst >> 12));
 241         nv_wr32(dev, NV50_PUNK_UNK1710, 0);
 242         nv_wr32(dev, NV50_PUNK_BAR_CFG_BASE, (chan->ramin->vinst >> 12) |
 243                                          NV50_PUNK_BAR_CFG_BASE_VALID);
 244         nv_wr32(dev, NV50_PUNK_BAR1_CTXDMA, (priv->fb_bar->cinst >> 4) |
 245                                         NV50_PUNK_BAR1_CTXDMA_VALID);
 246         nv_wr32(dev, NV50_PUNK_BAR3_CTXDMA, (priv->pramin_bar->cinst >> 4) |
 247                                         NV50_PUNK_BAR3_CTXDMA_VALID);
 248
 249         for (i = 0; i < 8; i++)
 250                 nv_wr32(dev, 0x1900 + (i*4), 0);
 251
 252         dev_priv->ramin_available = true;
 253
 254         /* Assume that praying isn't enough, check that we can re-read the
 255          * entire fake channel back from the PRAMIN BAR */
 256         for (i = 0; i < c_size; i += 4) {
 257                 if (nv_rd32(dev, NV_RAMIN + i) != nv_ri32(dev, i)) {
 258                         NV_ERROR(dev, "Error reading back PRAMIN at 0x%08x\n",
 259                                                                         i);
 260                         return -EINVAL;
 261                 }
 262         }
 263
 264         nv_wr32(dev, NV50_PUNK_BAR0_PRAMIN, save_nv001700);
 265
 266         /* Global PRAMIN heap */
 267         if (drm_mm_init(&dev_priv->ramin_heap, c_size, dev_priv->ramin_size - c_size)) {
 268                 NV_ERROR(dev, "Failed to init RAMIN heap\n");
 269         }
 270
 271         /*XXX: incorrect, but needed to make hash func "work" */
 272         dev_priv->ramht_offset = 0x10000;
 273         dev_priv->ramht_bits   = 9;
 274         dev_priv->ramht_size   = (1 << dev_priv->ramht_bits) * 8;
 275         return 0;
 276 }
 277
 278 void
 279 nv50_instmem_takedown(struct drm_device *dev)
 280 {
 281         struct drm_nouveau_private *dev_priv = dev->dev_private;
 282         struct nv50_instmem_priv *priv = dev_priv->engine.instmem.priv;
 283         struct nouveau_channel *chan = dev_priv->fifos[0];
 284         int i;
 285
 286         NV_DEBUG(dev, "\n");
 287
 288         if (!priv)
 289                 return;
 290
 291         /* Restore state from before init */
 292         for (i = 0x1700; i <= 0x1710; i += 4)
 293                 nv_wr32(dev, i, priv->save1700[(i - 0x1700) / 4]);
 294
 295         nouveau_gpuobj_ref(NULL, &priv->fb_bar);
 296         nouveau_gpuobj_ref(NULL, &priv->pramin_bar);
 297         nouveau_gpuobj_ref(NULL, &priv->pramin_pt);
 298
 299         /* Destroy dummy channel */
 300         if (chan) {
 301                 for (i = 0; i < dev_priv->vm_vram_pt_nr; i++)
 302                         nouveau_gpuobj_ref(NULL, &chan->vm_vram_pt[i]);
 303                 dev_priv->vm_vram_pt_nr = 0;
 304
 305                 nouveau_gpuobj_ref(NULL, &chan->vm_pd);
 306                 nouveau_gpuobj_ref(NULL, &chan->ramfc);
 307                 nouveau_gpuobj_ref(NULL, &chan->ramin);
 308                 drm_mm_takedown(&chan->ramin_heap);
 309
 310                 dev_priv->fifos[0] = dev_priv->fifos[127] = NULL;
 311                 kfree(chan);
 312         }
 313
 314         dev_priv->engine.instmem.priv = NULL;
 315         kfree(priv);
 316 }
 317
 318 int
 319 nv50_instmem_suspend(struct drm_device *dev)
 320 {
 321         struct drm_nouveau_private *dev_priv = dev->dev_private;
 322         struct nouveau_channel *chan = dev_priv->fifos[0];
 323         struct nouveau_gpuobj *ramin = chan->ramin;
 324         int i;
 325
 326         ramin->im_backing_suspend = vmalloc(ramin->size);
 327         if (!ramin->im_backing_suspend)
 328                 return -ENOMEM;
 329
 330         for (i = 0; i < ramin->size; i += 4)
 331                 ramin->im_backing_suspend[i/4] = nv_ri32(dev, i);
 332         return 0;
 333 }
 334
 335 void
 336 nv50_instmem_resume(struct drm_device *dev)
 337 {
 338         struct drm_nouveau_private *dev_priv = dev->dev_private;
 339         struct nv50_instmem_priv *priv = dev_priv->engine.instmem.priv;
 340         struct nouveau_channel *chan = dev_priv->fifos[0];
 341         struct nouveau_gpuobj *ramin = chan->ramin;
 342         int i;
 343
 344         nv_wr32(dev, NV50_PUNK_BAR0_PRAMIN, (ramin->vinst >> 16));
 345         for (i = 0; i < ramin->size; i += 4)
 346                 BAR0_WI32(ramin, i, ramin->im_backing_suspend[i/4]);
 347         vfree(ramin->im_backing_suspend);
 348         ramin->im_backing_suspend = NULL;
 349
 350         /* Poke the relevant regs, and pray it works :) */
 351         nv_wr32(dev, NV50_PUNK_BAR_CFG_BASE, (chan->ramin->vinst >> 12));
 352         nv_wr32(dev, NV50_PUNK_UNK1710, 0);
 353         nv_wr32(dev, NV50_PUNK_BAR_CFG_BASE, (chan->ramin->vinst >> 12) |
 354                                          NV50_PUNK_BAR_CFG_BASE_VALID);
 355         nv_wr32(dev, NV50_PUNK_BAR1_CTXDMA, (priv->fb_bar->cinst >> 4) |
 356                                         NV50_PUNK_BAR1_CTXDMA_VALID);
 357         nv_wr32(dev, NV50_PUNK_BAR3_CTXDMA, (priv->pramin_bar->cinst >> 4) |
 358                                         NV50_PUNK_BAR3_CTXDMA_VALID);
 359
 360         for (i = 0; i < 8; i++)
 361                 nv_wr32(dev, 0x1900 + (i*4), 0);
 362 }
 363
 364 int
 365 nv50_instmem_populate(struct drm_device *dev, struct nouveau_gpuobj *gpuobj,
 366                       uint32_t *sz)
 367 {
 368         int ret;
 369
 370         if (gpuobj->im_backing)
 371                 return -EINVAL;
 372
 373         *sz = ALIGN(*sz, NV50_INSTMEM_PAGE_SIZE);
 374         if (*sz == 0)
 375                 return -EINVAL;
 376
 377         ret = nouveau_bo_new(dev, NULL, *sz, 0, TTM_PL_FLAG_VRAM, 0, 0x0000,
 378                              true, false, &gpuobj->im_backing);
 379         if (ret) {
 380                 NV_ERROR(dev, "error getting PRAMIN backing pages: %d\n", ret);
 381                 return ret;
 382         }
 383
 384         ret = nouveau_bo_pin(gpuobj->im_backing, TTM_PL_FLAG_VRAM);
 385         if (ret) {
 386                 NV_ERROR(dev, "error pinning PRAMIN backing VRAM: %d\n", ret);
 387                 nouveau_bo_ref(NULL, &gpuobj->im_backing);
 388                 return ret;
 389         }
 390
 391         gpuobj->vinst = gpuobj->im_backing->bo.mem.mm_node->start << PAGE_SHIFT;
 392         return 0;
 393 }
 394
 395 void
 396 nv50_instmem_clear(struct drm_device *dev, struct nouveau_gpuobj *gpuobj)
 397 {
 398         struct drm_nouveau_private *dev_priv = dev->dev_private;
 399
 400         if (gpuobj && gpuobj->im_backing) {
 401                 if (gpuobj->im_bound)
 402                         dev_priv->engine.instmem.unbind(dev, gpuobj);
 403                 nouveau_bo_unpin(gpuobj->im_backing);
 404                 nouveau_bo_ref(NULL, &gpuobj->im_backing);
 405                 gpuobj->im_backing = NULL;
 406         }
 407 }
 408
 409 int
 410 nv50_instmem_bind(struct drm_device *dev, struct nouveau_gpuobj *gpuobj)
 411 {
 412         struct drm_nouveau_private *dev_priv = dev->dev_private;
 413         struct nv50_instmem_priv *priv = dev_priv->engine.instmem.priv;
 414         struct nouveau_gpuobj *pramin_pt = priv->pramin_pt;
 415         uint32_t pte, pte_end;
 416         uint64_t vram;
 417
 418         if (!gpuobj->im_backing || !gpuobj->im_pramin || gpuobj->im_bound)
 419                 return -EINVAL;
 420
 421         NV_DEBUG(dev, "st=0x%lx sz=0x%lx\n",
 422                  gpuobj->im_pramin->start, gpuobj->im_pramin->size);
 423
 424         pte     = (gpuobj->im_pramin->start >> 12) << 1;
 425         pte_end = ((gpuobj->im_pramin->size >> 12) << 1) + pte;
 426         vram    = gpuobj->vinst;
 427
 428         NV_DEBUG(dev, "pramin=0x%lx, pte=%d, pte_end=%d\n",
 429                  gpuobj->im_pramin->start, pte, pte_end);
 430         NV_DEBUG(dev, "first vram page: 0x%010llx\n", gpuobj->vinst);
 431
 432         vram |= 1;
 433         if (dev_priv->vram_sys_base) {
 434                 vram += dev_priv->vram_sys_base;
 435                 vram |= 0x30;
 436         }
 437
 438         while (pte < pte_end) {
 439                 nv_wo32(pramin_pt, (pte * 4) + 0, lower_32_bits(vram));
 440                 nv_wo32(pramin_pt, (pte * 4) + 4, upper_32_bits(vram));
 441                 vram += NV50_INSTMEM_PAGE_SIZE;
 442                 pte += 2;
 443         }
 444         dev_priv->engine.instmem.flush(dev);
 445
 446         nv50_vm_flush(dev, 4);
 447         nv50_vm_flush(dev, 6);
 448
 449         gpuobj->im_bound = 1;
 450         return 0;
 451 }
 452
 453 int
 454 nv50_instmem_unbind(struct drm_device *dev, struct nouveau_gpuobj *gpuobj)
 455 {
 456         struct drm_nouveau_private *dev_priv = dev->dev_private;
 457         struct nv50_instmem_priv *priv = dev_priv->engine.instmem.priv;
 458         uint32_t pte, pte_end;
 459
 460         if (gpuobj->im_bound == 0)
 461                 return -EINVAL;
 462
 463         pte     = (gpuobj->im_pramin->start >> 12) << 1;
 464         pte_end = ((gpuobj->im_pramin->size >> 12) << 1) + pte;
 465
 466         while (pte < pte_end) {
 467                 nv_wo32(priv->pramin_pt, (pte * 4) + 0, 0x00000000);
 468                 nv_wo32(priv->pramin_pt, (pte * 4) + 4, 0x00000000);
 469                 pte += 2;
 470         }
 471         dev_priv->engine.instmem.flush(dev);
 472
 473         gpuobj->im_bound = 0;
 474         return 0;
 475 }
 476
 477 void
 478 nv50_instmem_flush(struct drm_device *dev)
 479 {
 480         nv_wr32(dev, 0x00330c, 0x00000001);
 481         if (!nv_wait(0x00330c, 0x00000002, 0x00000000))
 482                 NV_ERROR(dev, "PRAMIN flush timeout\n");
 483 }
 484
 485 void
 486 nv84_instmem_flush(struct drm_device *dev)
 487 {
 488         nv_wr32(dev, 0x070000, 0x00000001);
 489         if (!nv_wait(0x070000, 0x00000002, 0x00000000))
 490                 NV_ERROR(dev, "PRAMIN flush timeout\n");
 491 }
 492
 493 void
 494 nv50_vm_flush(struct drm_device *dev, int engine)
 495 {
 496         nv_wr32(dev, 0x100c80, (engine << 16) | 1);
 497         if (!nv_wait(0x100c80, 0x00000001, 0x00000000))
 498                 NV_ERROR(dev, "vm flush timeout: engine %d\n", engine);
 499 }
 500