3 * arch/ppc/platforms/hdpu_setup.c
5 * Board setup routines for the Sky Computers HDPU Compute Blade.
7 * Written by Brian Waite <waite@skycomputers.com>
9 * Based on code done by - Mark A. Greer <mgreer@mvista.com>
10 * Rabeeh Khoury - rabeeh@galileo.co.il
12 * This program is free software; you can redistribute it and/or modify it
13 * under the terms of the GNU General Public License as published by the
14 * Free Software Foundation; either version 2 of the License, or (at your
15 * option) any later version.
18 #include <linux/config.h>
20 #include <linux/pci.h>
21 #include <linux/delay.h>
22 #include <linux/irq.h>
23 #include <linux/ide.h>
24 #include <linux/seq_file.h>
25 #include <linux/platform_device.h>
27 #include <linux/initrd.h>
28 #include <linux/root_dev.h>
29 #include <linux/smp.h>
32 #include <asm/machdep.h>
34 #include <asm/mv64x60.h>
35 #include <asm/ppcboot.h>
36 #include <platforms/hdpu.h>
37 #include <linux/mv643xx.h>
38 #include <linux/hdpu_features.h>
39 #include <linux/device.h>
40 #include <linux/mtd/physmap.h>
42 #define BOARD_VENDOR "Sky Computers"
43 #define BOARD_MACHINE "HDPU-CB-A"
46 int ppcboot_bd_valid
= 0;
48 static mv64x60_handle_t bh
;
50 extern char cmd_line
[];
52 unsigned long hdpu_find_end_of_memory(void);
53 void hdpu_mpsc_progress(char *s
, unsigned short hex
);
54 void hdpu_heartbeat(void);
56 static void parse_bootinfo(unsigned long r3
,
57 unsigned long r4
, unsigned long r5
,
58 unsigned long r6
, unsigned long r7
);
59 static void hdpu_set_l1pe(void);
60 static void hdpu_cpustate_set(unsigned char new_state
);
62 static DEFINE_SPINLOCK(timebase_lock
);
63 static unsigned int timebase_upper
= 0, timebase_lower
= 0;
64 extern int smp_tb_synchronized
;
66 void __devinit
hdpu_tben_give(void);
67 void __devinit
hdpu_tben_take(void);
71 hdpu_map_irq(struct pci_dev
*dev
, unsigned char idsel
, unsigned char pin
)
73 struct pci_controller
*hose
= pci_bus_to_hose(dev
->bus
->number
);
75 if (hose
->index
== 0) {
76 static char pci_irq_table
[][4] = {
77 {HDPU_PCI_0_IRQ
, 0, 0, 0},
78 {HDPU_PCI_0_IRQ
, 0, 0, 0},
81 const long min_idsel
= 1, max_idsel
= 2, irqs_per_slot
= 4;
82 return PCI_IRQ_TABLE_LOOKUP
;
84 static char pci_irq_table
[][4] = {
85 {HDPU_PCI_1_IRQ
, 0, 0, 0},
88 const long min_idsel
= 1, max_idsel
= 1, irqs_per_slot
= 4;
89 return PCI_IRQ_TABLE_LOOKUP
;
93 static void __init
hdpu_intr_setup(void)
95 mv64x60_write(&bh
, MV64x60_GPP_IO_CNTL
,
96 (1 | (1 << 2) | (1 << 3) | (1 << 4) | (1 << 5) |
97 (1 << 6) | (1 << 7) | (1 << 12) | (1 << 16) |
98 (1 << 18) | (1 << 19) | (1 << 20) | (1 << 21) |
99 (1 << 22) | (1 << 23) | (1 << 24) | (1 << 25) |
100 (1 << 26) | (1 << 27) | (1 << 28) | (1 << 29)));
102 /* XXXX Erranum FEr PCI-#8 */
103 mv64x60_clr_bits(&bh
, MV64x60_PCI0_CMD
, (1 << 5) | (1 << 9));
104 mv64x60_clr_bits(&bh
, MV64x60_PCI1_CMD
, (1 << 5) | (1 << 9));
107 * Dismiss and then enable interrupt on GPP interrupt cause
110 mv64x60_write(&bh
, MV64x60_GPP_INTR_CAUSE
, ~((1 << 8) | (1 << 13)));
111 mv64x60_set_bits(&bh
, MV64x60_GPP_INTR_MASK
, (1 << 8) | (1 << 13));
114 * Dismiss and then enable interrupt on CPU #0 high cause reg
115 * BIT25 summarizes GPP interrupts 8-15
117 mv64x60_set_bits(&bh
, MV64360_IC_CPU0_INTR_MASK_HI
, (1 << 25));
120 static void __init
hdpu_setup_peripherals(void)
124 mv64x60_set_32bit_window(&bh
, MV64x60_CPU2BOOT_WIN
,
125 HDPU_EMB_FLASH_BASE
, HDPU_EMB_FLASH_SIZE
, 0);
126 bh
.ci
->enable_window_32bit(&bh
, MV64x60_CPU2BOOT_WIN
);
128 mv64x60_set_32bit_window(&bh
, MV64x60_CPU2DEV_0_WIN
,
129 HDPU_TBEN_BASE
, HDPU_TBEN_SIZE
, 0);
130 bh
.ci
->enable_window_32bit(&bh
, MV64x60_CPU2DEV_0_WIN
);
132 mv64x60_set_32bit_window(&bh
, MV64x60_CPU2DEV_1_WIN
,
133 HDPU_NEXUS_ID_BASE
, HDPU_NEXUS_ID_SIZE
, 0);
134 bh
.ci
->enable_window_32bit(&bh
, MV64x60_CPU2DEV_1_WIN
);
136 mv64x60_set_32bit_window(&bh
, MV64x60_CPU2SRAM_WIN
,
137 HDPU_INTERNAL_SRAM_BASE
,
138 HDPU_INTERNAL_SRAM_SIZE
, 0);
139 bh
.ci
->enable_window_32bit(&bh
, MV64x60_CPU2SRAM_WIN
);
141 bh
.ci
->disable_window_32bit(&bh
, MV64x60_ENET2MEM_4_WIN
);
142 mv64x60_set_32bit_window(&bh
, MV64x60_ENET2MEM_4_WIN
, 0, 0, 0);
144 mv64x60_clr_bits(&bh
, MV64x60_PCI0_PCI_DECODE_CNTL
, (1 << 3));
145 mv64x60_clr_bits(&bh
, MV64x60_PCI1_PCI_DECODE_CNTL
, (1 << 3));
146 mv64x60_clr_bits(&bh
, MV64x60_TIMR_CNTR_0_3_CNTL
,
147 ((1 << 0) | (1 << 8) | (1 << 16) | (1 << 24)));
149 /* Enable pipelining */
150 mv64x60_set_bits(&bh
, MV64x60_CPU_CONFIG
, (1 << 13));
151 /* Enable Snoop Pipelineing */
152 mv64x60_set_bits(&bh
, MV64360_D_UNIT_CONTROL_HIGH
, (1 << 24));
155 * Change DRAM read buffer assignment.
156 * Assign read buffer 0 dedicated only for CPU,
157 * and the rest read buffer 1.
159 val
= mv64x60_read(&bh
, MV64360_SDRAM_CONFIG
);
160 val
= val
& 0x03ffffff;
161 val
= val
| 0xf8000000;
162 mv64x60_write(&bh
, MV64360_SDRAM_CONFIG
, val
);
165 * Configure internal SRAM -
166 * Cache coherent write back, if CONFIG_MV64360_SRAM_CACHE_COHERENT set
168 * Parity error propagation
169 * Arbitration not parked for CPU only
170 * Other bits are reserved.
172 #ifdef CONFIG_MV64360_SRAM_CACHE_COHERENT
173 mv64x60_write(&bh
, MV64360_SRAM_CONFIG
, 0x001600b2);
175 mv64x60_write(&bh
, MV64360_SRAM_CONFIG
, 0x001600b0);
181 static void __init
hdpu_setup_bridge(void)
183 struct mv64x60_setup_info si
;
186 memset(&si
, 0, sizeof(si
));
188 si
.phys_reg_base
= HDPU_BRIDGE_REG_BASE
;
189 si
.pci_0
.enable_bus
= 1;
190 si
.pci_0
.pci_io
.cpu_base
= HDPU_PCI0_IO_START_PROC_ADDR
;
191 si
.pci_0
.pci_io
.pci_base_hi
= 0;
192 si
.pci_0
.pci_io
.pci_base_lo
= HDPU_PCI0_IO_START_PCI_ADDR
;
193 si
.pci_0
.pci_io
.size
= HDPU_PCI0_IO_SIZE
;
194 si
.pci_0
.pci_io
.swap
= MV64x60_CPU2PCI_SWAP_NONE
;
195 si
.pci_0
.pci_mem
[0].cpu_base
= HDPU_PCI0_MEM_START_PROC_ADDR
;
196 si
.pci_0
.pci_mem
[0].pci_base_hi
= HDPU_PCI0_MEM_START_PCI_HI_ADDR
;
197 si
.pci_0
.pci_mem
[0].pci_base_lo
= HDPU_PCI0_MEM_START_PCI_LO_ADDR
;
198 si
.pci_0
.pci_mem
[0].size
= HDPU_PCI0_MEM_SIZE
;
199 si
.pci_0
.pci_mem
[0].swap
= MV64x60_CPU2PCI_SWAP_NONE
;
200 si
.pci_0
.pci_cmd_bits
= 0;
201 si
.pci_0
.latency_timer
= 0x80;
203 si
.pci_1
.enable_bus
= 1;
204 si
.pci_1
.pci_io
.cpu_base
= HDPU_PCI1_IO_START_PROC_ADDR
;
205 si
.pci_1
.pci_io
.pci_base_hi
= 0;
206 si
.pci_1
.pci_io
.pci_base_lo
= HDPU_PCI1_IO_START_PCI_ADDR
;
207 si
.pci_1
.pci_io
.size
= HDPU_PCI1_IO_SIZE
;
208 si
.pci_1
.pci_io
.swap
= MV64x60_CPU2PCI_SWAP_NONE
;
209 si
.pci_1
.pci_mem
[0].cpu_base
= HDPU_PCI1_MEM_START_PROC_ADDR
;
210 si
.pci_1
.pci_mem
[0].pci_base_hi
= HDPU_PCI1_MEM_START_PCI_HI_ADDR
;
211 si
.pci_1
.pci_mem
[0].pci_base_lo
= HDPU_PCI1_MEM_START_PCI_LO_ADDR
;
212 si
.pci_1
.pci_mem
[0].size
= HDPU_PCI1_MEM_SIZE
;
213 si
.pci_1
.pci_mem
[0].swap
= MV64x60_CPU2PCI_SWAP_NONE
;
214 si
.pci_1
.pci_cmd_bits
= 0;
215 si
.pci_1
.latency_timer
= 0x80;
217 for (i
= 0; i
< MV64x60_CPU2MEM_WINDOWS
; i
++) {
218 #if defined(CONFIG_NOT_COHERENT_CACHE)
219 si
.cpu_prot_options
[i
] = 0;
220 si
.enet_options
[i
] = MV64360_ENET2MEM_SNOOP_NONE
;
221 si
.mpsc_options
[i
] = MV64360_MPSC2MEM_SNOOP_NONE
;
222 si
.idma_options
[i
] = MV64360_IDMA2MEM_SNOOP_NONE
;
224 si
.pci_1
.acc_cntl_options
[i
] =
225 MV64360_PCI_ACC_CNTL_SNOOP_NONE
|
226 MV64360_PCI_ACC_CNTL_SWAP_NONE
|
227 MV64360_PCI_ACC_CNTL_MBURST_128_BYTES
|
228 MV64360_PCI_ACC_CNTL_RDSIZE_256_BYTES
;
230 si
.pci_0
.acc_cntl_options
[i
] =
231 MV64360_PCI_ACC_CNTL_SNOOP_NONE
|
232 MV64360_PCI_ACC_CNTL_SWAP_NONE
|
233 MV64360_PCI_ACC_CNTL_MBURST_128_BYTES
|
234 MV64360_PCI_ACC_CNTL_RDSIZE_256_BYTES
;
237 si
.cpu_prot_options
[i
] = 0;
238 si
.enet_options
[i
] = MV64360_ENET2MEM_SNOOP_WB
; /* errata */
239 si
.mpsc_options
[i
] = MV64360_MPSC2MEM_SNOOP_WB
; /* errata */
240 si
.idma_options
[i
] = MV64360_IDMA2MEM_SNOOP_WB
; /* errata */
242 si
.pci_0
.acc_cntl_options
[i
] =
243 MV64360_PCI_ACC_CNTL_SNOOP_WB
|
244 MV64360_PCI_ACC_CNTL_SWAP_NONE
|
245 MV64360_PCI_ACC_CNTL_MBURST_32_BYTES
|
246 MV64360_PCI_ACC_CNTL_RDSIZE_256_BYTES
;
248 si
.pci_1
.acc_cntl_options
[i
] =
249 MV64360_PCI_ACC_CNTL_SNOOP_WB
|
250 MV64360_PCI_ACC_CNTL_SWAP_NONE
|
251 MV64360_PCI_ACC_CNTL_MBURST_32_BYTES
|
252 MV64360_PCI_ACC_CNTL_RDSIZE_256_BYTES
;
256 hdpu_cpustate_set(CPUSTATE_KERNEL_MAJOR
| CPUSTATE_KERNEL_INIT_PCI
);
258 /* Lookup PCI host bridges */
259 mv64x60_init(&bh
, &si
);
260 pci_dram_offset
= 0; /* System mem at same addr on PCI & cpu bus */
261 ppc_md
.pci_swizzle
= common_swizzle
;
262 ppc_md
.pci_map_irq
= hdpu_map_irq
;
264 mv64x60_set_bus(&bh
, 0, 0);
265 bh
.hose_a
->first_busno
= 0;
266 bh
.hose_a
->last_busno
= 0xff;
267 bh
.hose_a
->last_busno
= pciauto_bus_scan(bh
.hose_a
, 0);
269 bh
.hose_b
->first_busno
= bh
.hose_a
->last_busno
+ 1;
270 mv64x60_set_bus(&bh
, 1, bh
.hose_b
->first_busno
);
271 bh
.hose_b
->last_busno
= 0xff;
272 bh
.hose_b
->last_busno
= pciauto_bus_scan(bh
.hose_b
,
273 bh
.hose_b
->first_busno
);
275 ppc_md
.pci_exclude_device
= mv64x60_pci_exclude_device
;
277 hdpu_cpustate_set(CPUSTATE_KERNEL_MAJOR
| CPUSTATE_KERNEL_INIT_REG
);
279 * Enabling of PCI internal-vs-external arbitration
280 * is a platform- and errata-dependent decision.
285 #if defined(CONFIG_SERIAL_MPSC_CONSOLE)
286 static void __init
hdpu_early_serial_map(void)
289 static char first_time
= 1;
291 #if defined(CONFIG_KGDB_TTYS0)
293 #elif defined(CONFIG_KGDB_TTYS1)
296 #error "Invalid kgdb_tty port"
300 gt_early_mpsc_init(KGDB_PORT
,
301 B9600
| CS8
| CREAD
| HUPCL
| CLOCAL
);
310 static void hdpu_init2(void)
315 #if defined(CONFIG_MV643XX_ETH)
316 static void __init
hdpu_fixup_eth_pdata(struct platform_device
*pd
)
319 struct mv643xx_eth_platform_data
*eth_pd
;
320 eth_pd
= pd
->dev
.platform_data
;
322 eth_pd
->port_serial_control
=
323 mv64x60_read(&bh
, MV643XX_ETH_PORT_SERIAL_CONTROL_REG(pd
->id
) & ~1);
325 eth_pd
->force_phy_addr
= 1;
326 eth_pd
->phy_addr
= pd
->id
;
327 eth_pd
->tx_queue_size
= 400;
328 eth_pd
->rx_queue_size
= 800;
332 static void __init
hdpu_fixup_mpsc_pdata(struct platform_device
*pd
)
335 struct mpsc_pdata
*pdata
;
337 pdata
= (struct mpsc_pdata
*)pd
->dev
.platform_data
;
339 pdata
->max_idle
= 40;
340 if (ppcboot_bd_valid
)
341 pdata
->default_baud
= ppcboot_bd
.bi_baudrate
;
343 pdata
->default_baud
= HDPU_DEFAULT_BAUD
;
344 pdata
->brg_clk_src
= HDPU_MPSC_CLK_SRC
;
345 pdata
->brg_clk_freq
= HDPU_MPSC_CLK_FREQ
;
348 #if defined(CONFIG_HDPU_FEATURES)
349 static void __init
hdpu_fixup_cpustate_pdata(struct platform_device
*pd
)
351 struct platform_device
*pds
[1];
353 mv64x60_pd_fixup(&bh
, pds
, 1);
357 static int __init
hdpu_platform_notify(struct device
*dev
)
361 void ((*rtn
) (struct platform_device
* pdev
));
364 MPSC_CTLR_NAME
".0", hdpu_fixup_mpsc_pdata
},
365 #if defined(CONFIG_MV643XX_ETH)
367 MV643XX_ETH_NAME
".0", hdpu_fixup_eth_pdata
},
369 #if defined(CONFIG_HDPU_FEATURES)
371 HDPU_CPUSTATE_NAME
".0", hdpu_fixup_cpustate_pdata
},
374 struct platform_device
*pdev
;
377 if (dev
&& dev
->bus_id
)
378 for (i
= 0; i
< ARRAY_SIZE(dev_map
); i
++)
379 if (!strncmp(dev
->bus_id
, dev_map
[i
].bus_id
,
382 pdev
= container_of(dev
,
383 struct platform_device
,
385 dev_map
[i
].rtn(pdev
);
391 static void __init
hdpu_setup_arch(void)
394 ppc_md
.progress("hdpu_setup_arch: enter", 0);
395 #ifdef CONFIG_BLK_DEV_INITRD
397 ROOT_DEV
= Root_RAM0
;
400 #ifdef CONFIG_ROOT_NFS
403 ROOT_DEV
= Root_SDA2
;
406 ppc_md
.heartbeat
= hdpu_heartbeat
;
408 ppc_md
.heartbeat_reset
= HZ
;
409 ppc_md
.heartbeat_count
= 1;
412 ppc_md
.progress("hdpu_setup_arch: Enabling L2 cache", 0);
414 /* Enable L1 Parity Bits */
417 /* Enable L2 and L3 caches (if 745x) */
418 _set_L2CR(0x80080000);
421 ppc_md
.progress("hdpu_setup_arch: enter", 0);
425 hdpu_setup_peripherals();
427 #ifdef CONFIG_SERIAL_MPSC_CONSOLE
428 hdpu_early_serial_map();
431 printk("SKY HDPU Compute Blade \n");
434 ppc_md
.progress("hdpu_setup_arch: exit", 0);
436 hdpu_cpustate_set(CPUSTATE_KERNEL_MAJOR
| CPUSTATE_KERNEL_OK
);
439 static void __init
hdpu_init_irq(void)
444 static void __init
hdpu_set_l1pe()
447 asm volatile ("mfspr %0, 1011":"=r" (ictrl
):);
448 ictrl
|= ICTRL_EICE
| ICTRL_EDC
| ICTRL_EICP
;
449 asm volatile ("mtspr 1011, %0"::"r" (ictrl
));
453 * Set BAT 1 to map 0xf1000000 to end of physical memory space.
455 static __inline__
void hdpu_set_bat(void)
458 mtspr(SPRN_DBAT1U
, 0xf10001fe);
459 mtspr(SPRN_DBAT1L
, 0xf100002a);
465 unsigned long __init
hdpu_find_end_of_memory(void)
467 return mv64x60_get_mem_size(CONFIG_MV64X60_NEW_BASE
,
468 MV64x60_TYPE_MV64360
);
471 static void hdpu_reset_board(void)
473 volatile int infinite
= 1;
475 hdpu_cpustate_set(CPUSTATE_KERNEL_MAJOR
| CPUSTATE_KERNEL_RESET
);
479 /* Clear all the LEDs */
480 mv64x60_write(&bh
, MV64x60_GPP_VALUE_CLR
, ((1 << 4) |
481 (1 << 5) | (1 << 6)));
483 /* disable and invalidate the L2 cache */
487 /* flush and disable L1 I/D cache */
496 "isync\n" "sync\n" "mtspr 1008,5\n" "isync\n" "sync\n");
498 /* Hit the reset bit */
499 mv64x60_write(&bh
, MV64x60_GPP_VALUE_CLR
, (1 << 3));
507 static void hdpu_restart(char *cmd
)
509 volatile ulong i
= 10000000;
514 panic("restart failed\n");
517 static void hdpu_halt(void)
521 hdpu_cpustate_set(CPUSTATE_KERNEL_MAJOR
| CPUSTATE_KERNEL_HALT
);
523 /* Clear all the LEDs */
524 mv64x60_write(&bh
, MV64x60_GPP_VALUE_CLR
, ((1 << 4) | (1 << 5) |
530 static void hdpu_power_off(void)
536 static int hdpu_show_cpuinfo(struct seq_file
*m
)
540 pvid
= mfspr(SPRN_PVR
);
541 seq_printf(m
, "vendor\t\t: Sky Computers\n");
542 seq_printf(m
, "machine\t\t: HDPU Compute Blade\n");
543 seq_printf(m
, "PVID\t\t: 0x%x, vendor: %s\n",
544 pvid
, (pvid
& (1 << 15) ? "IBM" : "Motorola"));
549 static void __init
hdpu_calibrate_decr(void)
553 if (ppcboot_bd_valid
)
554 freq
= ppcboot_bd
.bi_busfreq
/ 4;
558 printk("time_init: decrementer frequency = %lu.%.6lu MHz\n",
559 freq
/ 1000000, freq
% 1000000);
561 tb_ticks_per_jiffy
= freq
/ HZ
;
562 tb_to_us
= mulhwu_scale_factor(freq
, 1000000);
567 static void parse_bootinfo(unsigned long r3
,
568 unsigned long r4
, unsigned long r5
,
569 unsigned long r6
, unsigned long r7
)
572 char *cmdline_start
= NULL
;
576 if ((r3
& 0xf0000000) == 0)
578 if ((r3
& 0xf0000000) == KERNELBASE
) {
581 memcpy(&ppcboot_bd
, bd
, sizeof(ppcboot_bd
));
582 ppcboot_bd_valid
= 1;
585 #ifdef CONFIG_BLK_DEV_INITRD
586 if (r4
&& r5
&& r5
> r4
) {
587 if ((r4
& 0xf0000000) == 0)
589 if ((r5
& 0xf0000000) == 0)
591 if ((r4
& 0xf0000000) == KERNELBASE
) {
594 initrd_below_start_ok
= 1;
597 #endif /* CONFIG_BLK_DEV_INITRD */
599 if (r6
&& r7
&& r7
> r6
) {
600 if ((r6
& 0xf0000000) == 0)
602 if ((r7
& 0xf0000000) == 0)
604 if ((r6
& 0xf0000000) == KERNELBASE
) {
605 cmdline_start
= (void *)r6
;
606 cmdline_len
= (r7
- r6
);
607 strncpy(cmd_line
, cmdline_start
, cmdline_len
);
612 #if defined(CONFIG_BLK_DEV_IDE) || defined(CONFIG_BLK_DEV_IDE_MODULE)
614 hdpu_ide_request_region(ide_ioreg_t from
, unsigned int extent
, const char *name
)
616 request_region(from
, extent
, name
);
620 static void hdpu_ide_release_region(ide_ioreg_t from
, unsigned int extent
)
622 release_region(from
, extent
);
627 hdpu_ide_pci_init_hwif_ports(hw_regs_t
* hw
, ide_ioreg_t data_port
,
628 ide_ioreg_t ctrl_port
, int *irq
)
632 pci_for_each_dev(dev
) {
633 if (((dev
->class >> 8) == PCI_CLASS_STORAGE_IDE
) ||
634 ((dev
->class >> 8) == PCI_CLASS_STORAGE_RAID
)) {
647 void hdpu_heartbeat(void)
649 if (mv64x60_read(&bh
, MV64x60_GPP_VALUE
) & (1 << 5))
650 mv64x60_write(&bh
, MV64x60_GPP_VALUE_CLR
, (1 << 5));
652 mv64x60_write(&bh
, MV64x60_GPP_VALUE_SET
, (1 << 5));
654 ppc_md
.heartbeat_count
= ppc_md
.heartbeat_reset
;
658 static void __init
hdpu_map_io(void)
660 io_block_mapping(0xf1000000, 0xf1000000, 0x20000, _PAGE_IO
);
664 char hdpu_smp0
[] = "SMP Cpu #0";
665 char hdpu_smp1
[] = "SMP Cpu #1";
667 static irqreturn_t
hdpu_smp_cpu0_int_handler(int irq
, void *dev_id
,
668 struct pt_regs
*regs
)
670 volatile unsigned int doorbell
;
672 doorbell
= mv64x60_read(&bh
, MV64360_CPU0_DOORBELL
);
674 /* Ack the doorbell interrupts */
675 mv64x60_write(&bh
, MV64360_CPU0_DOORBELL_CLR
, doorbell
);
678 smp_message_recv(0, regs
);
681 smp_message_recv(1, regs
);
684 smp_message_recv(2, regs
);
687 smp_message_recv(3, regs
);
692 static irqreturn_t
hdpu_smp_cpu1_int_handler(int irq
, void *dev_id
,
693 struct pt_regs
*regs
)
695 volatile unsigned int doorbell
;
697 doorbell
= mv64x60_read(&bh
, MV64360_CPU1_DOORBELL
);
699 /* Ack the doorbell interrupts */
700 mv64x60_write(&bh
, MV64360_CPU1_DOORBELL_CLR
, doorbell
);
703 smp_message_recv(0, regs
);
706 smp_message_recv(1, regs
);
709 smp_message_recv(2, regs
);
712 smp_message_recv(3, regs
);
717 static void smp_hdpu_CPU_two(void)
723 "mtspr 26, 3\n" "li 4,0\n" "mtspr 27,4\n" "rfi");
727 static int smp_hdpu_probe(void)
732 cpu_count_reg
= ioremap(HDPU_NEXUS_ID_BASE
, HDPU_NEXUS_ID_SIZE
);
734 num_cpus
= (*cpu_count_reg
>> 20) & 0x3;
735 iounmap(cpu_count_reg
);
738 /* Validate the bits in the CPLD. If we could not map the reg, return 2.
739 * If the register reported 0 or 3, return 2.
740 * Older CPLD revisions set these bits to all ones (val = 3).
742 if ((num_cpus
< 1) || (num_cpus
> 2)) {
744 ("Unable to determine the number of processors %d . deafulting to 2.\n",
752 smp_hdpu_message_pass(int target
, int msg
)
755 printk("SMP %d: smp_message_pass: unknown msg %d\n",
756 smp_processor_id(), msg
);
761 mv64x60_write(&bh
, MV64360_CPU0_DOORBELL
, 1 << msg
);
762 mv64x60_write(&bh
, MV64360_CPU1_DOORBELL
, 1 << msg
);
764 case MSG_ALL_BUT_SELF
:
765 if (smp_processor_id())
766 mv64x60_write(&bh
, MV64360_CPU0_DOORBELL
, 1 << msg
);
768 mv64x60_write(&bh
, MV64360_CPU1_DOORBELL
, 1 << msg
);
772 mv64x60_write(&bh
, MV64360_CPU0_DOORBELL
, 1 << msg
);
774 mv64x60_write(&bh
, MV64360_CPU1_DOORBELL
, 1 << msg
);
779 static void smp_hdpu_kick_cpu(int nr
)
781 volatile unsigned int *bootaddr
;
784 ppc_md
.progress("smp_hdpu_kick_cpu", 0);
786 hdpu_cpustate_set(CPUSTATE_KERNEL_MAJOR
| CPUSTATE_KERNEL_CPU1_KICK
);
788 /* Disable BootCS. Must also reduce the windows size to zero. */
789 bh
.ci
->disable_window_32bit(&bh
, MV64x60_CPU2BOOT_WIN
);
790 mv64x60_set_32bit_window(&bh
, MV64x60_CPU2BOOT_WIN
, 0, 0, 0);
792 bootaddr
= ioremap(HDPU_INTERNAL_SRAM_BASE
, HDPU_INTERNAL_SRAM_SIZE
);
795 ppc_md
.progress("smp_hdpu_kick_cpu: ioremap failed", 0);
799 memcpy((void *)(bootaddr
+ 0x40), (void *)&smp_hdpu_CPU_two
, 0x20);
801 /* map SRAM to 0xfff00000 */
802 bh
.ci
->disable_window_32bit(&bh
, MV64x60_CPU2SRAM_WIN
);
804 mv64x60_set_32bit_window(&bh
, MV64x60_CPU2SRAM_WIN
,
805 0xfff00000, HDPU_INTERNAL_SRAM_SIZE
, 0);
806 bh
.ci
->enable_window_32bit(&bh
, MV64x60_CPU2SRAM_WIN
);
808 /* Enable CPU1 arbitration */
809 mv64x60_clr_bits(&bh
, MV64x60_CPU_MASTER_CNTL
, (1 << 9));
812 * Wait 100mSecond until other CPU has reached __secondary_start.
813 * When it reaches, it is permittable to rever the SRAM mapping etc...
816 *(unsigned long *)KERNELBASE
= nr
;
817 asm volatile ("dcbf 0,%0"::"r" (KERNELBASE
):"memory");
821 /* Set up window for internal sram (256KByte insize) */
822 bh
.ci
->disable_window_32bit(&bh
, MV64x60_CPU2SRAM_WIN
);
823 mv64x60_set_32bit_window(&bh
, MV64x60_CPU2SRAM_WIN
,
824 HDPU_INTERNAL_SRAM_BASE
,
825 HDPU_INTERNAL_SRAM_SIZE
, 0);
826 bh
.ci
->enable_window_32bit(&bh
, MV64x60_CPU2SRAM_WIN
);
828 * Set up windows for embedded FLASH (using boot CS window).
831 bh
.ci
->disable_window_32bit(&bh
, MV64x60_CPU2BOOT_WIN
);
832 mv64x60_set_32bit_window(&bh
, MV64x60_CPU2BOOT_WIN
,
833 HDPU_EMB_FLASH_BASE
, HDPU_EMB_FLASH_SIZE
, 0);
834 bh
.ci
->enable_window_32bit(&bh
, MV64x60_CPU2BOOT_WIN
);
837 static void smp_hdpu_setup_cpu(int cpu_nr
)
841 ppc_md
.progress("smp_hdpu_setup_cpu 0", 0);
842 mv64x60_write(&bh
, MV64360_CPU0_DOORBELL_CLR
, 0xff);
843 mv64x60_write(&bh
, MV64360_CPU0_DOORBELL_MASK
, 0xff);
844 request_irq(60, hdpu_smp_cpu0_int_handler
,
845 SA_INTERRUPT
, hdpu_smp0
, 0);
850 ppc_md
.progress("smp_hdpu_setup_cpu 1", 0);
852 hdpu_cpustate_set(CPUSTATE_KERNEL_MAJOR
|
853 CPUSTATE_KERNEL_CPU1_OK
);
855 /* Enable L1 Parity Bits */
858 /* Enable L2 cache */
860 _set_L2CR(0x80080000);
862 mv64x60_write(&bh
, MV64360_CPU1_DOORBELL_CLR
, 0x0);
863 mv64x60_write(&bh
, MV64360_CPU1_DOORBELL_MASK
, 0xff);
864 request_irq(28, hdpu_smp_cpu1_int_handler
,
865 SA_INTERRUPT
, hdpu_smp1
, 0);
870 void __devinit
hdpu_tben_give()
872 volatile unsigned long *val
= 0;
874 /* By writing 0 to the TBEN_BASE, the timebases is frozen */
875 val
= ioremap(HDPU_TBEN_BASE
, 4);
879 spin_lock(&timebase_lock
);
880 timebase_upper
= get_tbu();
881 timebase_lower
= get_tbl();
882 spin_unlock(&timebase_lock
);
884 while (timebase_upper
|| timebase_lower
)
887 /* By writing 1 to the TBEN_BASE, the timebases is thawed */
895 void __devinit
hdpu_tben_take()
897 while (!(timebase_upper
|| timebase_lower
))
900 spin_lock(&timebase_lock
);
901 set_tb(timebase_upper
, timebase_lower
);
904 spin_unlock(&timebase_lock
);
907 static struct smp_ops_t hdpu_smp_ops
= {
908 .message_pass
= smp_hdpu_message_pass
,
909 .probe
= smp_hdpu_probe
,
910 .kick_cpu
= smp_hdpu_kick_cpu
,
911 .setup_cpu
= smp_hdpu_setup_cpu
,
912 .give_timebase
= hdpu_tben_give
,
913 .take_timebase
= hdpu_tben_take
,
915 #endif /* CONFIG_SMP */
918 platform_init(unsigned long r3
, unsigned long r4
, unsigned long r5
,
919 unsigned long r6
, unsigned long r7
)
921 parse_bootinfo(r3
, r4
, r5
, r6
, r7
);
925 ppc_md
.setup_arch
= hdpu_setup_arch
;
926 ppc_md
.init
= hdpu_init2
;
927 ppc_md
.show_cpuinfo
= hdpu_show_cpuinfo
;
928 ppc_md
.init_IRQ
= hdpu_init_irq
;
929 ppc_md
.get_irq
= mv64360_get_irq
;
930 ppc_md
.restart
= hdpu_restart
;
931 ppc_md
.power_off
= hdpu_power_off
;
932 ppc_md
.halt
= hdpu_halt
;
933 ppc_md
.find_end_of_memory
= hdpu_find_end_of_memory
;
934 ppc_md
.calibrate_decr
= hdpu_calibrate_decr
;
935 ppc_md
.setup_io_mappings
= hdpu_map_io
;
937 bh
.p_base
= CONFIG_MV64X60_NEW_BASE
;
938 bh
.v_base
= (unsigned long *)bh
.p_base
;
942 #if defined(CONFIG_SERIAL_TEXT_DEBUG)
943 ppc_md
.progress
= hdpu_mpsc_progress
; /* embedded UART */
944 mv64x60_progress_init(bh
.p_base
);
945 #endif /* CONFIG_SERIAL_TEXT_DEBUG */
948 smp_ops
= &hdpu_smp_ops
;
949 #endif /* CONFIG_SMP */
951 #if defined(CONFIG_SERIAL_MPSC) || defined(CONFIG_MV643XX_ETH)
952 platform_notify
= hdpu_platform_notify
;
957 #if defined(CONFIG_SERIAL_TEXT_DEBUG) && defined(CONFIG_SERIAL_MPSC_CONSOLE)
958 /* SMP safe version of the serial text debug routine. Uses Semaphore 0 */
959 void hdpu_mpsc_progress(char *s
, unsigned short hex
)
961 while (mv64x60_read(&bh
, MV64360_WHO_AM_I
) !=
962 mv64x60_read(&bh
, MV64360_SEMAPHORE_0
)) {
964 mv64x60_mpsc_progress(s
, hex
);
965 mv64x60_write(&bh
, MV64360_SEMAPHORE_0
, 0xff);
969 static void hdpu_cpustate_set(unsigned char new_state
)
971 unsigned int state
= (new_state
<< 21);
972 mv64x60_write(&bh
, MV64x60_GPP_VALUE_CLR
, (0xff << 21));
973 mv64x60_write(&bh
, MV64x60_GPP_VALUE_CLR
, state
);
976 #ifdef CONFIG_MTD_PHYSMAP
977 static struct mtd_partition hdpu_partitions
[] = {
986 .offset
= 0x03400000,
989 .name
= "Kernel Image",
991 .offset
= 0x03C00000,
996 .offset
= 0x03EC0000,
1001 .offset
= 0x03F00000,
1006 static int __init
hdpu_setup_mtd(void)
1009 physmap_set_partitions(hdpu_partitions
, 5);
1013 arch_initcall(hdpu_setup_mtd
);
1016 #ifdef CONFIG_HDPU_FEATURES
1018 static struct resource hdpu_cpustate_resources
[] = {
1020 .name
= "addr base",
1021 .start
= MV64x60_GPP_VALUE_SET
,
1022 .end
= MV64x60_GPP_VALUE_CLR
+ 1,
1023 .flags
= IORESOURCE_MEM
,
1027 static struct resource hdpu_nexus_resources
[] = {
1029 .name
= "nexus register",
1030 .start
= HDPU_NEXUS_ID_BASE
,
1031 .end
= HDPU_NEXUS_ID_BASE
+ HDPU_NEXUS_ID_SIZE
,
1032 .flags
= IORESOURCE_MEM
,
1036 static struct platform_device hdpu_cpustate_device
= {
1037 .name
= HDPU_CPUSTATE_NAME
,
1039 .num_resources
= ARRAY_SIZE(hdpu_cpustate_resources
),
1040 .resource
= hdpu_cpustate_resources
,
1043 static struct platform_device hdpu_nexus_device
= {
1044 .name
= HDPU_NEXUS_NAME
,
1046 .num_resources
= ARRAY_SIZE(hdpu_nexus_resources
),
1047 .resource
= hdpu_nexus_resources
,
1050 static int __init
hdpu_add_pds(void)
1052 platform_device_register(&hdpu_cpustate_device
);
1053 platform_device_register(&hdpu_nexus_device
);
1057 arch_initcall(hdpu_add_pds
);