2 * arch/ppc/platforms/chrp_pegasos_eth.c
4 * Copyright (C) 2005 Sven Luther <sl@bplan-gmbh.de>
6 * Dale Farnsworth <dale@farnsworth.org>
7 * Mark A. Greer <mgreer@mvista.com>
8 * Nicolas DET <nd@bplan-gmbh.de>
9 * Benjamin Herrenschmidt <benh@kernel.crashing.org>
10 * And anyone else who helped me on this.
13 #include <linux/types.h>
14 #include <linux/init.h>
15 #include <linux/ioport.h>
16 #include <linux/platform_device.h>
17 #include <linux/mv643xx.h>
18 #include <linux/pci.h>
20 #define PEGASOS2_MARVELL_REGBASE (0xf1000000)
21 #define PEGASOS2_MARVELL_REGSIZE (0x00004000)
22 #define PEGASOS2_SRAM_BASE (0xf2000000)
23 #define PEGASOS2_SRAM_SIZE (256*1024)
25 #define PEGASOS2_SRAM_BASE_ETH0 (PEGASOS2_SRAM_BASE)
26 #define PEGASOS2_SRAM_BASE_ETH1 (PEGASOS2_SRAM_BASE_ETH0 + (PEGASOS2_SRAM_SIZE / 2) )
29 #define PEGASOS2_SRAM_RXRING_SIZE (PEGASOS2_SRAM_SIZE/4)
30 #define PEGASOS2_SRAM_TXRING_SIZE (PEGASOS2_SRAM_SIZE/4)
34 static struct resource mv643xx_eth_shared_resources
[] = {
36 .name
= "ethernet shared base",
37 .start
= 0xf1000000 + MV643XX_ETH_SHARED_REGS
,
38 .end
= 0xf1000000 + MV643XX_ETH_SHARED_REGS
+
39 MV643XX_ETH_SHARED_REGS_SIZE
- 1,
40 .flags
= IORESOURCE_MEM
,
44 static struct platform_device mv643xx_eth_shared_device
= {
45 .name
= MV643XX_ETH_SHARED_NAME
,
47 .num_resources
= ARRAY_SIZE(mv643xx_eth_shared_resources
),
48 .resource
= mv643xx_eth_shared_resources
,
51 static struct resource mv643xx_eth0_resources
[] = {
56 .flags
= IORESOURCE_IRQ
,
61 static struct mv643xx_eth_platform_data eth0_pd
= {
62 .tx_sram_addr
= PEGASOS2_SRAM_BASE_ETH0
,
63 .tx_sram_size
= PEGASOS2_SRAM_TXRING_SIZE
,
64 .tx_queue_size
= PEGASOS2_SRAM_TXRING_SIZE
/16,
66 .rx_sram_addr
= PEGASOS2_SRAM_BASE_ETH0
+ PEGASOS2_SRAM_TXRING_SIZE
,
67 .rx_sram_size
= PEGASOS2_SRAM_RXRING_SIZE
,
68 .rx_queue_size
= PEGASOS2_SRAM_RXRING_SIZE
/16,
71 static struct platform_device eth0_device
= {
72 .name
= MV643XX_ETH_NAME
,
74 .num_resources
= ARRAY_SIZE(mv643xx_eth0_resources
),
75 .resource
= mv643xx_eth0_resources
,
77 .platform_data
= ð0_pd
,
81 static struct resource mv643xx_eth1_resources
[] = {
86 .flags
= IORESOURCE_IRQ
,
90 static struct mv643xx_eth_platform_data eth1_pd
= {
91 .tx_sram_addr
= PEGASOS2_SRAM_BASE_ETH1
,
92 .tx_sram_size
= PEGASOS2_SRAM_TXRING_SIZE
,
93 .tx_queue_size
= PEGASOS2_SRAM_TXRING_SIZE
/16,
95 .rx_sram_addr
= PEGASOS2_SRAM_BASE_ETH1
+ PEGASOS2_SRAM_TXRING_SIZE
,
96 .rx_sram_size
= PEGASOS2_SRAM_RXRING_SIZE
,
97 .rx_queue_size
= PEGASOS2_SRAM_RXRING_SIZE
/16,
100 static struct platform_device eth1_device
= {
101 .name
= MV643XX_ETH_NAME
,
103 .num_resources
= ARRAY_SIZE(mv643xx_eth1_resources
),
104 .resource
= mv643xx_eth1_resources
,
106 .platform_data
= ð1_pd
,
110 static struct platform_device
*mv643xx_eth_pd_devs
[] __initdata
= {
111 &mv643xx_eth_shared_device
,
118 #define MV_READ(offset,val) { val = readl(mv643xx_reg_base + offset); }
119 #define MV_WRITE(offset,data) writel(data, mv643xx_reg_base + offset)
121 static void __iomem
*mv643xx_reg_base
;
123 static int Enable_SRAM(void)
127 if (mv643xx_reg_base
== NULL
)
128 mv643xx_reg_base
= ioremap(PEGASOS2_MARVELL_REGBASE
,
129 PEGASOS2_MARVELL_REGSIZE
);
131 if (mv643xx_reg_base
== NULL
)
135 printk("Pegasos II/Marvell MV64361: register remapped from %p to %p\n",
136 (void *)PEGASOS2_MARVELL_REGBASE
, (void *)mv643xx_reg_base
);
139 MV_WRITE(MV64340_SRAM_CONFIG
, 0);
141 MV_WRITE(MV64340_INTEGRATED_SRAM_BASE_ADDR
, PEGASOS2_SRAM_BASE
>> 16);
143 MV_READ(MV64340_BASE_ADDR_ENABLE
, ALong
);
145 MV_WRITE(MV64340_BASE_ADDR_ENABLE
, ALong
);
148 ALong
|= PEGASOS2_SRAM_BASE
& 0xffff0000;
149 MV_WRITE(MV643XX_ETH_BAR_4
, ALong
);
151 MV_WRITE(MV643XX_ETH_SIZE_REG_4
, (PEGASOS2_SRAM_SIZE
-1) & 0xffff0000);
153 MV_READ(MV643XX_ETH_BASE_ADDR_ENABLE_REG
, ALong
);
155 MV_WRITE(MV643XX_ETH_BASE_ADDR_ENABLE_REG
, ALong
);
158 printk("Pegasos II/Marvell MV64361: register unmapped\n");
159 printk("Pegasos II/Marvell MV64361: SRAM at %p, size=%x\n", (void*) PEGASOS2_SRAM_BASE
, PEGASOS2_SRAM_SIZE
);
162 iounmap(mv643xx_reg_base
);
163 mv643xx_reg_base
= NULL
;
171 int mv643xx_eth_add_pds(void)
174 static struct pci_device_id pci_marvell_mv64360
[] = {
175 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, PCI_DEVICE_ID_MARVELL_MV64360
) },
180 printk("Pegasos II/Marvell MV64361: init\n");
183 if (pci_dev_present(pci_marvell_mv64360
)) {
184 ret
= platform_add_devices(mv643xx_eth_pd_devs
,
185 ARRAY_SIZE(mv643xx_eth_pd_devs
));
187 if ( Enable_SRAM() < 0)
189 eth0_pd
.tx_sram_addr
= 0;
190 eth0_pd
.tx_sram_size
= 0;
191 eth0_pd
.rx_sram_addr
= 0;
192 eth0_pd
.rx_sram_size
= 0;
194 eth1_pd
.tx_sram_addr
= 0;
195 eth1_pd
.tx_sram_size
= 0;
196 eth1_pd
.rx_sram_addr
= 0;
197 eth1_pd
.rx_sram_size
= 0;
200 printk("Pegasos II/Marvell MV64361: Can't enable the "
207 printk("Pegasos II/Marvell MV64361: init is over\n");
213 device_initcall(mv643xx_eth_add_pds
);