?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
[PATCH] rt2x00: Small optimizations
[linux-2.6.git] / drivers / net / wireless / rt2x00 / rt61pci.c
blobcd22817cced5b5bc8cd04f56a4da48941b1f861e
1 /*
2 Copyright (C) 2004 - 2007 rt2x00 SourceForge Project
3 <http://rt2x00.serialmonkey.com>
4
5 This program is free software; you can redistribute it and/or modify
6 it under the terms of the GNU General Public License as published by
7 the Free Software Foundation; either version 2 of the License, or
8 (at your option) any later version.
9
10 This program is distributed in the hope that it will be useful,
11 but WITHOUT ANY WARRANTY; without even the implied warranty of
12 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 GNU General Public License for more details.
14
15 You should have received a copy of the GNU General Public License
16 along with this program; if not, write to the
17 Free Software Foundation, Inc.,
18 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
19 */
20
21 /*
22 Module: rt61pci
23 Abstract: rt61pci device specific routines.
24 Supported chipsets: RT2561, RT2561s, RT2661.
25 */
26
27 /*
28 * Set enviroment defines for rt2x00.h
29 */
30 #define DRV_NAME "rt61pci"
31
32 #include <linux/delay.h>
33 #include <linux/etherdevice.h>
34 #include <linux/init.h>
35 #include <linux/kernel.h>
36 #include <linux/module.h>
37 #include <linux/pci.h>
38 #include <linux/eeprom_93cx6.h>
39
40 #include "rt2x00.h"
41 #include "rt2x00pci.h"
42 #include "rt61pci.h"
43
44 /*
45 * Register access.
46 * BBP and RF register require indirect register access,
47 * and use the CSR registers PHY_CSR3 and PHY_CSR4 to achieve this.
48 * These indirect registers work with busy bits,
49 * and we will try maximal REGISTER_BUSY_COUNT times to access
50 * the register while taking a REGISTER_BUSY_DELAY us delay
51 * between each attampt. When the busy bit is still set at that time,
52 * the access attempt is considered to have failed,
53 * and we will print an error.
54 */
55 static u32 rt61pci_bbp_check(const struct rt2x00_dev *rt2x00dev)
56 {
57 u32 reg;
58 unsigned int i;
59
60 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
61 rt2x00pci_register_read(rt2x00dev, PHY_CSR3, &reg);
62 if (!rt2x00_get_field32(reg, PHY_CSR3_BUSY))
63 break;
64 udelay(REGISTER_BUSY_DELAY);
65 }
66
67 return reg;
68 }
69
70 static void rt61pci_bbp_write(const struct rt2x00_dev *rt2x00dev,
71 const unsigned int word, const u8 value)
72 {
73 u32 reg;
74
75 /*
76 * Wait until the BBP becomes ready.
77 */
78 reg = rt61pci_bbp_check(rt2x00dev);
79 if (rt2x00_get_field32(reg, PHY_CSR3_BUSY)) {
80 ERROR(rt2x00dev, "PHY_CSR3 register busy. Write failed.\n");
81 return;
82 }
83
84 /*
85 * Write the data into the BBP.
86 */
87 reg = 0;
88 rt2x00_set_field32(&reg, PHY_CSR3_VALUE, value);
89 rt2x00_set_field32(&reg, PHY_CSR3_REGNUM, word);
90 rt2x00_set_field32(&reg, PHY_CSR3_BUSY, 1);
91 rt2x00_set_field32(&reg, PHY_CSR3_READ_CONTROL, 0);
92
93 rt2x00pci_register_write(rt2x00dev, PHY_CSR3, reg);
94 }
95
96 static void rt61pci_bbp_read(const struct rt2x00_dev *rt2x00dev,
97 const unsigned int word, u8 *value)
98 {
99 u32 reg;
100
101 /*
102 * Wait until the BBP becomes ready.
103 */
104 reg = rt61pci_bbp_check(rt2x00dev);
105 if (rt2x00_get_field32(reg, PHY_CSR3_BUSY)) {
106 ERROR(rt2x00dev, "PHY_CSR3 register busy. Read failed.\n");
107 return;
108 }
109
110 /*
111 * Write the request into the BBP.
112 */
113 reg = 0;
114 rt2x00_set_field32(&reg, PHY_CSR3_REGNUM, word);
115 rt2x00_set_field32(&reg, PHY_CSR3_BUSY, 1);
116 rt2x00_set_field32(&reg, PHY_CSR3_READ_CONTROL, 1);
117
118 rt2x00pci_register_write(rt2x00dev, PHY_CSR3, reg);
119
120 /*
121 * Wait until the BBP becomes ready.
122 */
123 reg = rt61pci_bbp_check(rt2x00dev);
124 if (rt2x00_get_field32(reg, PHY_CSR3_BUSY)) {
125 ERROR(rt2x00dev, "PHY_CSR3 register busy. Read failed.\n");
126 *value = 0xff;
127 return;
128 }
129
130 *value = rt2x00_get_field32(reg, PHY_CSR3_VALUE);
131 }
132
133 static void rt61pci_rf_write(const struct rt2x00_dev *rt2x00dev,
134 const unsigned int word, const u32 value)
135 {
136 u32 reg;
137 unsigned int i;
138
139 if (!word)
140 return;
141
142 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
143 rt2x00pci_register_read(rt2x00dev, PHY_CSR4, &reg);
144 if (!rt2x00_get_field32(reg, PHY_CSR4_BUSY))
145 goto rf_write;
146 udelay(REGISTER_BUSY_DELAY);
147 }
148
149 ERROR(rt2x00dev, "PHY_CSR4 register busy. Write failed.\n");
150 return;
151
152 rf_write:
153 reg = 0;
154 rt2x00_set_field32(&reg, PHY_CSR4_VALUE, value);
155 rt2x00_set_field32(&reg, PHY_CSR4_NUMBER_OF_BITS, 21);
156 rt2x00_set_field32(&reg, PHY_CSR4_IF_SELECT, 0);
157 rt2x00_set_field32(&reg, PHY_CSR4_BUSY, 1);
158
159 rt2x00pci_register_write(rt2x00dev, PHY_CSR4, reg);
160 rt2x00_rf_write(rt2x00dev, word, value);
161 }
162
163 static void rt61pci_mcu_request(const struct rt2x00_dev *rt2x00dev,
164 const u8 command, const u8 token,
165 const u8 arg0, const u8 arg1)
166 {
167 u32 reg;
168
169 rt2x00pci_register_read(rt2x00dev, H2M_MAILBOX_CSR, &reg);
170
171 if (rt2x00_get_field32(reg, H2M_MAILBOX_CSR_OWNER)) {
172 ERROR(rt2x00dev, "mcu request error. "
173 "Request 0x%02x failed for token 0x%02x.\n",
174 command, token);
175 return;
176 }
177
178 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_OWNER, 1);
179 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_CMD_TOKEN, token);
180 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_ARG0, arg0);
181 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_ARG1, arg1);
182 rt2x00pci_register_write(rt2x00dev, H2M_MAILBOX_CSR, reg);
183
184 rt2x00pci_register_read(rt2x00dev, HOST_CMD_CSR, &reg);
185 rt2x00_set_field32(&reg, HOST_CMD_CSR_HOST_COMMAND, command);
186 rt2x00_set_field32(&reg, HOST_CMD_CSR_INTERRUPT_MCU, 1);
187 rt2x00pci_register_write(rt2x00dev, HOST_CMD_CSR, reg);
188 }
189
190 static void rt61pci_eepromregister_read(struct eeprom_93cx6 *eeprom)
191 {
192 struct rt2x00_dev *rt2x00dev = eeprom->data;
193 u32 reg;
194
195 rt2x00pci_register_read(rt2x00dev, E2PROM_CSR, &reg);
196
197 eeprom->reg_data_in = !!rt2x00_get_field32(reg, E2PROM_CSR_DATA_IN);
198 eeprom->reg_data_out = !!rt2x00_get_field32(reg, E2PROM_CSR_DATA_OUT);
199 eeprom->reg_data_clock =
200 !!rt2x00_get_field32(reg, E2PROM_CSR_DATA_CLOCK);
201 eeprom->reg_chip_select =
202 !!rt2x00_get_field32(reg, E2PROM_CSR_CHIP_SELECT);
203 }
204
205 static void rt61pci_eepromregister_write(struct eeprom_93cx6 *eeprom)
206 {
207 struct rt2x00_dev *rt2x00dev = eeprom->data;
208 u32 reg = 0;
209
210 rt2x00_set_field32(&reg, E2PROM_CSR_DATA_IN, !!eeprom->reg_data_in);
211 rt2x00_set_field32(&reg, E2PROM_CSR_DATA_OUT, !!eeprom->reg_data_out);
212 rt2x00_set_field32(&reg, E2PROM_CSR_DATA_CLOCK,
213 !!eeprom->reg_data_clock);
214 rt2x00_set_field32(&reg, E2PROM_CSR_CHIP_SELECT,
215 !!eeprom->reg_chip_select);
216
217 rt2x00pci_register_write(rt2x00dev, E2PROM_CSR, reg);
218 }
219
220 #ifdef CONFIG_RT2X00_LIB_DEBUGFS
221 #define CSR_OFFSET(__word) ( CSR_REG_BASE + ((__word) * sizeof(u32)) )
222
223 static void rt61pci_read_csr(const struct rt2x00_dev *rt2x00dev,
224 const unsigned int word, u32 *data)
225 {
226 rt2x00pci_register_read(rt2x00dev, CSR_OFFSET(word), data);
227 }
228
229 static void rt61pci_write_csr(const struct rt2x00_dev *rt2x00dev,
230 const unsigned int word, u32 data)
231 {
232 rt2x00pci_register_write(rt2x00dev, CSR_OFFSET(word), data);
233 }
234
235 static const struct rt2x00debug rt61pci_rt2x00debug = {
236 .owner = THIS_MODULE,
237 .csr = {
238 .read = rt61pci_read_csr,
239 .write = rt61pci_write_csr,
240 .word_size = sizeof(u32),
241 .word_count = CSR_REG_SIZE / sizeof(u32),
242 },
243 .eeprom = {
244 .read = rt2x00_eeprom_read,
245 .write = rt2x00_eeprom_write,
246 .word_size = sizeof(u16),
247 .word_count = EEPROM_SIZE / sizeof(u16),
248 },
249 .bbp = {
250 .read = rt61pci_bbp_read,
251 .write = rt61pci_bbp_write,
252 .word_size = sizeof(u8),
253 .word_count = BBP_SIZE / sizeof(u8),
254 },
255 .rf = {
256 .read = rt2x00_rf_read,
257 .write = rt61pci_rf_write,
258 .word_size = sizeof(u32),
259 .word_count = RF_SIZE / sizeof(u32),
260 },
261 };
262 #endif /* CONFIG_RT2X00_LIB_DEBUGFS */
263
264 #ifdef CONFIG_RT61PCI_RFKILL
265 static int rt61pci_rfkill_poll(struct rt2x00_dev *rt2x00dev)
266 {
267 u32 reg;
268
269 rt2x00pci_register_read(rt2x00dev, MAC_CSR13, &reg);
270 return rt2x00_get_field32(reg, MAC_CSR13_BIT5);;
271 }
272 #else
273 #define rt61pci_rfkill_poll NULL
274 #endif /* CONFIG_RT61PCI_RFKILL */
275
276 /*
277 * Configuration handlers.
278 */
279 static void rt61pci_config_mac_addr(struct rt2x00_dev *rt2x00dev, __le32 *mac)
280 {
281 u32 tmp;
282
283 tmp = le32_to_cpu(mac[1]);
284 rt2x00_set_field32(&tmp, MAC_CSR3_UNICAST_TO_ME_MASK, 0xff);
285 mac[1] = cpu_to_le32(tmp);
286
287 rt2x00pci_register_multiwrite(rt2x00dev, MAC_CSR2, mac,
288 (2 * sizeof(__le32)));
289 }
290
291 static void rt61pci_config_bssid(struct rt2x00_dev *rt2x00dev, __le32 *bssid)
292 {
293 u32 tmp;
294
295 tmp = le32_to_cpu(bssid[1]);
296 rt2x00_set_field32(&tmp, MAC_CSR5_BSS_ID_MASK, 3);
297 bssid[1] = cpu_to_le32(tmp);
298
299 rt2x00pci_register_multiwrite(rt2x00dev, MAC_CSR4, bssid,
300 (2 * sizeof(__le32)));
301 }
302
303 static void rt61pci_config_type(struct rt2x00_dev *rt2x00dev, const int type,
304 const int tsf_sync)
305 {
306 u32 reg;
307
308 /*
309 * Clear current synchronisation setup.
310 * For the Beacon base registers we only need to clear
311 * the first byte since that byte contains the VALID and OWNER
312 * bits which (when set to 0) will invalidate the entire beacon.
313 */
314 rt2x00pci_register_write(rt2x00dev, TXRX_CSR9, 0);
315 rt2x00pci_register_write(rt2x00dev, HW_BEACON_BASE0, 0);
316 rt2x00pci_register_write(rt2x00dev, HW_BEACON_BASE1, 0);
317 rt2x00pci_register_write(rt2x00dev, HW_BEACON_BASE2, 0);
318 rt2x00pci_register_write(rt2x00dev, HW_BEACON_BASE3, 0);
319
320 /*
321 * Enable synchronisation.
322 */
323 rt2x00pci_register_read(rt2x00dev, TXRX_CSR9, &reg);
324 rt2x00_set_field32(&reg, TXRX_CSR9_TSF_TICKING, 1);
325 rt2x00_set_field32(&reg, TXRX_CSR9_TBTT_ENABLE, 1);
326 rt2x00_set_field32(&reg, TXRX_CSR9_BEACON_GEN, 0);
327 rt2x00_set_field32(&reg, TXRX_CSR9_TSF_SYNC, tsf_sync);
328 rt2x00pci_register_write(rt2x00dev, TXRX_CSR9, reg);
329 }
330
331 static void rt61pci_config_rate(struct rt2x00_dev *rt2x00dev, const int rate)
332 {
333 struct ieee80211_conf *conf = &rt2x00dev->hw->conf;
334 u32 reg;
335 u32 value;
336 u32 preamble;
337
338 if (DEVICE_GET_RATE_FIELD(rate, PREAMBLE))
339 preamble = SHORT_PREAMBLE;
340 else
341 preamble = PREAMBLE;
342
343 /*
344 * Extract the allowed ratemask from the device specific rate value,
345 * We need to set TXRX_CSR5 to the basic rate mask so we need to mask
346 * off the non-basic rates.
347 */
348 reg = DEVICE_GET_RATE_FIELD(rate, RATEMASK) & DEV_BASIC_RATEMASK;
349
350 rt2x00pci_register_write(rt2x00dev, TXRX_CSR5, reg);
351
352 rt2x00pci_register_read(rt2x00dev, TXRX_CSR0, &reg);
353 value = ((conf->flags & IEEE80211_CONF_SHORT_SLOT_TIME) ?
354 SHORT_DIFS : DIFS) +
355 PLCP + preamble + get_duration(ACK_SIZE, 10);
356 rt2x00_set_field32(&reg, TXRX_CSR0_RX_ACK_TIMEOUT, value);
357 rt2x00pci_register_write(rt2x00dev, TXRX_CSR0, reg);
358
359 rt2x00pci_register_read(rt2x00dev, TXRX_CSR4, &reg);
360 rt2x00_set_field32(&reg, TXRX_CSR4_AUTORESPOND_PREAMBLE,
361 (preamble == SHORT_PREAMBLE));
362 rt2x00pci_register_write(rt2x00dev, TXRX_CSR4, reg);
363 }
364
365 static void rt61pci_config_phymode(struct rt2x00_dev *rt2x00dev,
366 const int phymode)
367 {
368 struct ieee80211_hw_mode *mode;
369 struct ieee80211_rate *rate;
370
371 if (phymode == MODE_IEEE80211A)
372 rt2x00dev->curr_hwmode = HWMODE_A;
373 else if (phymode == MODE_IEEE80211B)
374 rt2x00dev->curr_hwmode = HWMODE_B;
375 else
376 rt2x00dev->curr_hwmode = HWMODE_G;
377
378 mode = &rt2x00dev->hwmodes[rt2x00dev->curr_hwmode];
379 rate = &mode->rates[mode->num_rates - 1];
380
381 rt61pci_config_rate(rt2x00dev, rate->val2);
382 }
383
384 static void rt61pci_config_lock_channel(struct rt2x00_dev *rt2x00dev,
385 struct rf_channel *rf,
386 const int txpower)
387 {
388 u8 r3;
389 u8 r94;
390 u8 smart;
391
392 rt2x00_set_field32(&rf->rf3, RF3_TXPOWER, TXPOWER_TO_DEV(txpower));
393 rt2x00_set_field32(&rf->rf4, RF4_FREQ_OFFSET, rt2x00dev->freq_offset);
394
395 smart = !(rt2x00_rf(&rt2x00dev->chip, RF5225) ||
396 rt2x00_rf(&rt2x00dev->chip, RF2527));
397
398 rt61pci_bbp_read(rt2x00dev, 3, &r3);
399 rt2x00_set_field8(&r3, BBP_R3_SMART_MODE, smart);
400 rt61pci_bbp_write(rt2x00dev, 3, r3);
401
402 r94 = 6;
403 if (txpower > MAX_TXPOWER && txpower <= (MAX_TXPOWER + r94))
404 r94 += txpower - MAX_TXPOWER;
405 else if (txpower < MIN_TXPOWER && txpower >= (MIN_TXPOWER - r94))
406 r94 += txpower;
407 rt61pci_bbp_write(rt2x00dev, 94, r94);
408
409 rt61pci_rf_write(rt2x00dev, 1, rf->rf1);
410 rt61pci_rf_write(rt2x00dev, 2, rf->rf2);
411 rt61pci_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004);
412 rt61pci_rf_write(rt2x00dev, 4, rf->rf4);
413
414 udelay(200);
415
416 rt61pci_rf_write(rt2x00dev, 1, rf->rf1);
417 rt61pci_rf_write(rt2x00dev, 2, rf->rf2);
418 rt61pci_rf_write(rt2x00dev, 3, rf->rf3 | 0x00000004);
419 rt61pci_rf_write(rt2x00dev, 4, rf->rf4);
420
421 udelay(200);
422
423 rt61pci_rf_write(rt2x00dev, 1, rf->rf1);
424 rt61pci_rf_write(rt2x00dev, 2, rf->rf2);
425 rt61pci_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004);
426 rt61pci_rf_write(rt2x00dev, 4, rf->rf4);
427
428 msleep(1);
429 }
430
431 static void rt61pci_config_channel(struct rt2x00_dev *rt2x00dev,
432 const int index, const int channel,
433 const int txpower)
434 {
435 struct rf_channel rf;
436
437 /*
438 * Fill rf_reg structure.
439 */
440 memcpy(&rf, &rt2x00dev->spec.channels[index], sizeof(rf));
441
442 rt61pci_config_lock_channel(rt2x00dev, &rf, txpower);
443 }
444
445 static void rt61pci_config_txpower(struct rt2x00_dev *rt2x00dev,
446 const int txpower)
447 {
448 struct rf_channel rf;
449
450 rt2x00_rf_read(rt2x00dev, 1, &rf.rf1);
451 rt2x00_rf_read(rt2x00dev, 2, &rf.rf2);
452 rt2x00_rf_read(rt2x00dev, 3, &rf.rf3);
453 rt2x00_rf_read(rt2x00dev, 4, &rf.rf4);
454
455 rt61pci_config_lock_channel(rt2x00dev, &rf, txpower);
456 }
457
458 static void rt61pci_config_antenna_5x(struct rt2x00_dev *rt2x00dev,
459 const int antenna_tx,
460 const int antenna_rx)
461 {
462 u8 r3;
463 u8 r4;
464 u8 r77;
465
466 rt61pci_bbp_read(rt2x00dev, 3, &r3);
467 rt61pci_bbp_read(rt2x00dev, 4, &r4);
468 rt61pci_bbp_read(rt2x00dev, 77, &r77);
469
470 rt2x00_set_field8(&r3, BBP_R3_SMART_MODE,
471 !rt2x00_rf(&rt2x00dev->chip, RF5225));
472
473 switch (antenna_rx) {
474 case ANTENNA_SW_DIVERSITY:
475 case ANTENNA_HW_DIVERSITY:
476 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA, 2);
477 rt2x00_set_field8(&r4, BBP_R4_RX_FRAME_END,
478 !!(rt2x00dev->curr_hwmode != HWMODE_A));
479 break;
480 case ANTENNA_A:
481 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA, 1);
482 rt2x00_set_field8(&r4, BBP_R4_RX_FRAME_END, 0);
483
484 if (rt2x00dev->curr_hwmode == HWMODE_A)
485 rt2x00_set_field8(&r77, BBP_R77_PAIR, 0);
486 else
487 rt2x00_set_field8(&r77, BBP_R77_PAIR, 3);
488 break;
489 case ANTENNA_B:
490 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA, 1);
491 rt2x00_set_field8(&r4, BBP_R4_RX_FRAME_END, 0);
492
493 if (rt2x00dev->curr_hwmode == HWMODE_A)
494 rt2x00_set_field8(&r77, BBP_R77_PAIR, 3);
495 else
496 rt2x00_set_field8(&r77, BBP_R77_PAIR, 0);
497 break;
498 }
499
500 rt61pci_bbp_write(rt2x00dev, 77, r77);
501 rt61pci_bbp_write(rt2x00dev, 3, r3);
502 rt61pci_bbp_write(rt2x00dev, 4, r4);
503 }
504
505 static void rt61pci_config_antenna_2x(struct rt2x00_dev *rt2x00dev,
506 const int antenna_tx,
507 const int antenna_rx)
508 {
509 u8 r3;
510 u8 r4;
511 u8 r77;
512
513 rt61pci_bbp_read(rt2x00dev, 3, &r3);
514 rt61pci_bbp_read(rt2x00dev, 4, &r4);
515 rt61pci_bbp_read(rt2x00dev, 77, &r77);
516
517 rt2x00_set_field8(&r3, BBP_R3_SMART_MODE,
518 !rt2x00_rf(&rt2x00dev->chip, RF2527));
519 rt2x00_set_field8(&r4, BBP_R4_RX_FRAME_END,
520 !test_bit(CONFIG_FRAME_TYPE, &rt2x00dev->flags));
521
522 switch (antenna_rx) {
523 case ANTENNA_SW_DIVERSITY:
524 case ANTENNA_HW_DIVERSITY:
525 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA, 2);
526 break;
527 case ANTENNA_A:
528 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA, 1);
529 rt2x00_set_field8(&r77, BBP_R77_PAIR, 3);
530 break;
531 case ANTENNA_B:
532 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA, 1);
533 rt2x00_set_field8(&r77, BBP_R77_PAIR, 0);
534 break;
535 }
536
537 rt61pci_bbp_write(rt2x00dev, 77, r77);
538 rt61pci_bbp_write(rt2x00dev, 3, r3);
539 rt61pci_bbp_write(rt2x00dev, 4, r4);
540 }
541
542 static void rt61pci_config_antenna_2529_rx(struct rt2x00_dev *rt2x00dev,
543 const int p1, const int p2)
544 {
545 u32 reg;
546
547 rt2x00pci_register_read(rt2x00dev, MAC_CSR13, &reg);
548
549 if (p1 != 0xff) {
550 rt2x00_set_field32(&reg, MAC_CSR13_BIT4, !!p1);
551 rt2x00_set_field32(&reg, MAC_CSR13_BIT12, 0);
552 rt2x00pci_register_write(rt2x00dev, MAC_CSR13, reg);
553 }
554 if (p2 != 0xff) {
555 rt2x00_set_field32(&reg, MAC_CSR13_BIT3, !p2);
556 rt2x00_set_field32(&reg, MAC_CSR13_BIT11, 0);
557 rt2x00pci_register_write(rt2x00dev, MAC_CSR13, reg);
558 }
559 }
560
561 static void rt61pci_config_antenna_2529(struct rt2x00_dev *rt2x00dev,
562 const int antenna_tx,
563 const int antenna_rx)
564 {
565 u16 eeprom;
566 u8 r3;
567 u8 r4;
568 u8 r77;
569
570 rt61pci_bbp_read(rt2x00dev, 3, &r3);
571 rt61pci_bbp_read(rt2x00dev, 4, &r4);
572 rt61pci_bbp_read(rt2x00dev, 77, &r77);
573 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &eeprom);
574
575 rt2x00_set_field8(&r3, BBP_R3_SMART_MODE, 0);
576
577 if (rt2x00_get_field16(eeprom, EEPROM_NIC_ENABLE_DIVERSITY) &&
578 rt2x00_get_field16(eeprom, EEPROM_NIC_TX_DIVERSITY)) {
579 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA, 2);
580 rt2x00_set_field8(&r4, BBP_R4_RX_FRAME_END, 1);
581 rt61pci_config_antenna_2529_rx(rt2x00dev, 0, 1);
582 } else if (rt2x00_get_field16(eeprom, EEPROM_NIC_ENABLE_DIVERSITY)) {
583 if (rt2x00_get_field16(eeprom, EEPROM_NIC_TX_RX_FIXED) >= 2) {
584 rt2x00_set_field8(&r77, BBP_R77_PAIR, 3);
585 rt61pci_bbp_write(rt2x00dev, 77, r77);
586 }
587 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA, 1);
588 rt61pci_config_antenna_2529_rx(rt2x00dev, 1, 1);
589 } else if (!rt2x00_get_field16(eeprom, EEPROM_NIC_ENABLE_DIVERSITY) &&
590 rt2x00_get_field16(eeprom, EEPROM_NIC_TX_DIVERSITY)) {
591 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA, 2);
592 rt2x00_set_field8(&r4, BBP_R4_RX_FRAME_END, 0);
593
594 switch (rt2x00_get_field16(eeprom, EEPROM_NIC_TX_RX_FIXED)) {
595 case 0:
596 rt61pci_config_antenna_2529_rx(rt2x00dev, 0, 1);
597 break;
598 case 1:
599 rt61pci_config_antenna_2529_rx(rt2x00dev, 1, 0);
600 break;
601 case 2:
602 rt61pci_config_antenna_2529_rx(rt2x00dev, 0, 0);
603 break;
604 case 3:
605 rt61pci_config_antenna_2529_rx(rt2x00dev, 1, 1);
606 break;
607 }
608 } else if (!rt2x00_get_field16(eeprom, EEPROM_NIC_ENABLE_DIVERSITY) &&
609 !rt2x00_get_field16(eeprom, EEPROM_NIC_TX_DIVERSITY)) {
610 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA, 1);
611 rt2x00_set_field8(&r4, BBP_R4_RX_FRAME_END, 0);
612
613 switch (rt2x00_get_field16(eeprom, EEPROM_NIC_TX_RX_FIXED)) {
614 case 0:
615 rt2x00_set_field8(&r77, BBP_R77_PAIR, 0);
616 rt61pci_bbp_write(rt2x00dev, 77, r77);
617 rt61pci_config_antenna_2529_rx(rt2x00dev, 0, 1);
618 break;
619 case 1:
620 rt2x00_set_field8(&r77, BBP_R77_PAIR, 0);
621 rt61pci_bbp_write(rt2x00dev, 77, r77);
622 rt61pci_config_antenna_2529_rx(rt2x00dev, 1, 0);
623 break;
624 case 2:
625 rt2x00_set_field8(&r77, BBP_R77_PAIR, 3);
626 rt61pci_bbp_write(rt2x00dev, 77, r77);
627 rt61pci_config_antenna_2529_rx(rt2x00dev, 0, 0);
628 break;
629 case 3:
630 rt2x00_set_field8(&r77, BBP_R77_PAIR, 3);
631 rt61pci_bbp_write(rt2x00dev, 77, r77);
632 rt61pci_config_antenna_2529_rx(rt2x00dev, 1, 1);
633 break;
634 }
635 }
636
637 rt61pci_bbp_write(rt2x00dev, 3, r3);
638 rt61pci_bbp_write(rt2x00dev, 4, r4);
639 }
640
641 struct antenna_sel {
642 u8 word;
643 /*
644 * value[0] -> non-LNA
645 * value[1] -> LNA
646 */
647 u8 value[2];
648 };
649
650 static const struct antenna_sel antenna_sel_a[] = {
651 { 96, { 0x58, 0x78 } },
652 { 104, { 0x38, 0x48 } },
653 { 75, { 0xfe, 0x80 } },
654 { 86, { 0xfe, 0x80 } },
655 { 88, { 0xfe, 0x80 } },
656 { 35, { 0x60, 0x60 } },
657 { 97, { 0x58, 0x58 } },
658 { 98, { 0x58, 0x58 } },
659 };
660
661 static const struct antenna_sel antenna_sel_bg[] = {
662 { 96, { 0x48, 0x68 } },
663 { 104, { 0x2c, 0x3c } },
664 { 75, { 0xfe, 0x80 } },
665 { 86, { 0xfe, 0x80 } },
666 { 88, { 0xfe, 0x80 } },
667 { 35, { 0x50, 0x50 } },
668 { 97, { 0x48, 0x48 } },
669 { 98, { 0x48, 0x48 } },
670 };
671
672 static void rt61pci_config_antenna(struct rt2x00_dev *rt2x00dev,
673 const int antenna_tx, const int antenna_rx)
674 {
675 const struct antenna_sel *sel;
676 unsigned int lna;
677 unsigned int i;
678 u32 reg;
679
680 rt2x00pci_register_read(rt2x00dev, PHY_CSR0, &reg);
681
682 if (rt2x00dev->curr_hwmode == HWMODE_A) {
683 sel = antenna_sel_a;
684 lna = test_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags);
685
686 rt2x00_set_field32(&reg, PHY_CSR0_PA_PE_BG, 0);
687 rt2x00_set_field32(&reg, PHY_CSR0_PA_PE_A, 1);
688 } else {
689 sel = antenna_sel_bg;
690 lna = test_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags);
691
692 rt2x00_set_field32(&reg, PHY_CSR0_PA_PE_BG, 1);
693 rt2x00_set_field32(&reg, PHY_CSR0_PA_PE_A, 0);
694 }
695
696 for (i = 0; i < ARRAY_SIZE(antenna_sel_a); i++)
697 rt61pci_bbp_write(rt2x00dev, sel[i].word, sel[i].value[lna]);
698
699 rt2x00pci_register_write(rt2x00dev, PHY_CSR0, reg);
700
701 if (rt2x00_rf(&rt2x00dev->chip, RF5225) ||
702 rt2x00_rf(&rt2x00dev->chip, RF5325))
703 rt61pci_config_antenna_5x(rt2x00dev, antenna_tx, antenna_rx);
704 else if (rt2x00_rf(&rt2x00dev->chip, RF2527))
705 rt61pci_config_antenna_2x(rt2x00dev, antenna_tx, antenna_rx);
706 else if (rt2x00_rf(&rt2x00dev->chip, RF2529)) {
707 if (test_bit(CONFIG_DOUBLE_ANTENNA, &rt2x00dev->flags))
708 rt61pci_config_antenna_2x(rt2x00dev, antenna_tx,
709 antenna_rx);
710 else
711 rt61pci_config_antenna_2529(rt2x00dev, antenna_tx,
712 antenna_rx);
713 }
714 }
715
716 static void rt61pci_config_duration(struct rt2x00_dev *rt2x00dev,
717 const int short_slot_time,
718 const int beacon_int)
719 {
720 u32 reg;
721
722 rt2x00pci_register_read(rt2x00dev, MAC_CSR9, &reg);
723 rt2x00_set_field32(&reg, MAC_CSR9_SLOT_TIME,
724 short_slot_time ? SHORT_SLOT_TIME : SLOT_TIME);
725 rt2x00pci_register_write(rt2x00dev, MAC_CSR9, reg);
726
727 rt2x00pci_register_read(rt2x00dev, MAC_CSR8, &reg);
728 rt2x00_set_field32(&reg, MAC_CSR8_SIFS, SIFS);
729 rt2x00_set_field32(&reg, MAC_CSR8_SIFS_AFTER_RX_OFDM, 3);
730 rt2x00_set_field32(&reg, MAC_CSR8_EIFS, EIFS);
731 rt2x00pci_register_write(rt2x00dev, MAC_CSR8, reg);
732
733 rt2x00pci_register_read(rt2x00dev, TXRX_CSR0, &reg);
734 rt2x00_set_field32(&reg, TXRX_CSR0_TSF_OFFSET, IEEE80211_HEADER);
735 rt2x00pci_register_write(rt2x00dev, TXRX_CSR0, reg);
736
737 rt2x00pci_register_read(rt2x00dev, TXRX_CSR4, &reg);
738 rt2x00_set_field32(&reg, TXRX_CSR4_AUTORESPOND_ENABLE, 1);
739 rt2x00pci_register_write(rt2x00dev, TXRX_CSR4, reg);
740
741 rt2x00pci_register_read(rt2x00dev, TXRX_CSR9, &reg);
742 rt2x00_set_field32(&reg, TXRX_CSR9_BEACON_INTERVAL, beacon_int * 16);
743 rt2x00pci_register_write(rt2x00dev, TXRX_CSR9, reg);
744 }
745
746 static void rt61pci_config(struct rt2x00_dev *rt2x00dev,
747 const unsigned int flags,
748 struct ieee80211_conf *conf)
749 {
750 int short_slot_time = conf->flags & IEEE80211_CONF_SHORT_SLOT_TIME;
751
752 if (flags & CONFIG_UPDATE_PHYMODE)
753 rt61pci_config_phymode(rt2x00dev, conf->phymode);
754 if (flags & CONFIG_UPDATE_CHANNEL)
755 rt61pci_config_channel(rt2x00dev, conf->channel_val,
756 conf->channel, conf->power_level);
757 if ((flags & CONFIG_UPDATE_TXPOWER) && !(flags & CONFIG_UPDATE_CHANNEL))
758 rt61pci_config_txpower(rt2x00dev, conf->power_level);
759 if (flags & CONFIG_UPDATE_ANTENNA)
760 rt61pci_config_antenna(rt2x00dev, conf->antenna_sel_tx,
761 conf->antenna_sel_rx);
762 if (flags & (CONFIG_UPDATE_SLOT_TIME | CONFIG_UPDATE_BEACON_INT))
763 rt61pci_config_duration(rt2x00dev, short_slot_time,
764 conf->beacon_int);
765 }
766
767 /*
768 * LED functions.
769 */
770 static void rt61pci_enable_led(struct rt2x00_dev *rt2x00dev)
771 {
772 u32 reg;
773 u16 led_reg;
774 u8 arg0;
775 u8 arg1;
776
777 rt2x00pci_register_read(rt2x00dev, MAC_CSR14, &reg);
778 rt2x00_set_field32(&reg, MAC_CSR14_ON_PERIOD, 70);
779 rt2x00_set_field32(&reg, MAC_CSR14_OFF_PERIOD, 30);
780 rt2x00pci_register_write(rt2x00dev, MAC_CSR14, reg);
781
782 led_reg = rt2x00dev->led_reg;
783 rt2x00_set_field16(&led_reg, MCU_LEDCS_RADIO_STATUS, 1);
784 if (rt2x00dev->rx_status.phymode == MODE_IEEE80211A)
785 rt2x00_set_field16(&led_reg, MCU_LEDCS_LINK_A_STATUS, 1);
786 else
787 rt2x00_set_field16(&led_reg, MCU_LEDCS_LINK_BG_STATUS, 1);
788
789 arg0 = led_reg & 0xff;
790 arg1 = (led_reg >> 8) & 0xff;
791
792 rt61pci_mcu_request(rt2x00dev, MCU_LED, 0xff, arg0, arg1);
793 }
794
795 static void rt61pci_disable_led(struct rt2x00_dev *rt2x00dev)
796 {
797 u16 led_reg;
798 u8 arg0;
799 u8 arg1;
800
801 led_reg = rt2x00dev->led_reg;
802 rt2x00_set_field16(&led_reg, MCU_LEDCS_RADIO_STATUS, 0);
803 rt2x00_set_field16(&led_reg, MCU_LEDCS_LINK_BG_STATUS, 0);
804 rt2x00_set_field16(&led_reg, MCU_LEDCS_LINK_A_STATUS, 0);
805
806 arg0 = led_reg & 0xff;
807 arg1 = (led_reg >> 8) & 0xff;
808
809 rt61pci_mcu_request(rt2x00dev, MCU_LED, 0xff, arg0, arg1);
810 }
811
812 static void rt61pci_activity_led(struct rt2x00_dev *rt2x00dev, int rssi)
813 {
814 u8 led;
815
816 if (rt2x00dev->led_mode != LED_MODE_SIGNAL_STRENGTH)
817 return;
818
819 /*
820 * Led handling requires a positive value for the rssi,
821 * to do that correctly we need to add the correction.
822 */
823 rssi += rt2x00dev->rssi_offset;
824
825 if (rssi <= 30)
826 led = 0;
827 else if (rssi <= 39)
828 led = 1;
829 else if (rssi <= 49)
830 led = 2;
831 else if (rssi <= 53)
832 led = 3;
833 else if (rssi <= 63)
834 led = 4;
835 else
836 led = 5;
837
838 rt61pci_mcu_request(rt2x00dev, MCU_LED_STRENGTH, 0xff, led, 0);
839 }
840
841 /*
842 * Link tuning
843 */
844 static void rt61pci_link_stats(struct rt2x00_dev *rt2x00dev)
845 {
846 u32 reg;
847
848 /*
849 * Update FCS error count from register.
850 */
851 rt2x00pci_register_read(rt2x00dev, STA_CSR0, &reg);
852 rt2x00dev->link.rx_failed = rt2x00_get_field32(reg, STA_CSR0_FCS_ERROR);
853
854 /*
855 * Update False CCA count from register.
856 */
857 rt2x00pci_register_read(rt2x00dev, STA_CSR1, &reg);
858 rt2x00dev->link.false_cca =
859 rt2x00_get_field32(reg, STA_CSR1_FALSE_CCA_ERROR);
860 }
861
862 static void rt61pci_reset_tuner(struct rt2x00_dev *rt2x00dev)
863 {
864 rt61pci_bbp_write(rt2x00dev, 17, 0x20);
865 rt2x00dev->link.vgc_level = 0x20;
866 }
867
868 static void rt61pci_link_tuner(struct rt2x00_dev *rt2x00dev)
869 {
870 int rssi = rt2x00_get_link_rssi(&rt2x00dev->link);
871 u8 r17;
872 u8 up_bound;
873 u8 low_bound;
874
875 /*
876 * Update Led strength
877 */
878 rt61pci_activity_led(rt2x00dev, rssi);
879
880 rt61pci_bbp_read(rt2x00dev, 17, &r17);
881
882 /*
883 * Determine r17 bounds.
884 */
885 if (rt2x00dev->rx_status.phymode == MODE_IEEE80211A) {
886 low_bound = 0x28;
887 up_bound = 0x48;
888 if (test_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags)) {
889 low_bound += 0x10;
890 up_bound += 0x10;
891 }
892 } else {
893 low_bound = 0x20;
894 up_bound = 0x40;
895 if (test_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags)) {
896 low_bound += 0x10;
897 up_bound += 0x10;
898 }
899 }
900
901 /*
902 * Special big-R17 for very short distance
903 */
904 if (rssi >= -35) {
905 if (r17 != 0x60)
906 rt61pci_bbp_write(rt2x00dev, 17, 0x60);
907 return;
908 }
909
910 /*
911 * Special big-R17 for short distance
912 */
913 if (rssi >= -58) {
914 if (r17 != up_bound)
915 rt61pci_bbp_write(rt2x00dev, 17, up_bound);
916 return;
917 }
918
919 /*
920 * Special big-R17 for middle-short distance
921 */
922 if (rssi >= -66) {
923 low_bound += 0x10;
924 if (r17 != low_bound)
925 rt61pci_bbp_write(rt2x00dev, 17, low_bound);
926 return;
927 }
928
929 /*
930 * Special mid-R17 for middle distance
931 */
932 if (rssi >= -74) {
933 low_bound += 0x08;
934 if (r17 != low_bound)
935 rt61pci_bbp_write(rt2x00dev, 17, low_bound);
936 return;
937 }
938
939 /*
940 * Special case: Change up_bound based on the rssi.
941 * Lower up_bound when rssi is weaker then -74 dBm.
942 */
943 up_bound -= 2 * (-74 - rssi);
944 if (low_bound > up_bound)
945 up_bound = low_bound;
946
947 if (r17 > up_bound) {
948 rt61pci_bbp_write(rt2x00dev, 17, up_bound);
949 return;
950 }
951
952 /*
953 * r17 does not yet exceed upper limit, continue and base
954 * the r17 tuning on the false CCA count.
955 */
956 if (rt2x00dev->link.false_cca > 512 && r17 < up_bound) {
957 if (++r17 > up_bound)
958 r17 = up_bound;
959 rt61pci_bbp_write(rt2x00dev, 17, r17);
960 } else if (rt2x00dev->link.false_cca < 100 && r17 > low_bound) {
961 if (--r17 < low_bound)
962 r17 = low_bound;
963 rt61pci_bbp_write(rt2x00dev, 17, r17);
964 }
965 }
966
967 /*
968 * Firmware name function.
969 */
970 static char *rt61pci_get_firmware_name(struct rt2x00_dev *rt2x00dev)
971 {
972 char *fw_name;
973
974 switch (rt2x00dev->chip.rt) {
975 case RT2561:
976 fw_name = FIRMWARE_RT2561;
977 break;
978 case RT2561s:
979 fw_name = FIRMWARE_RT2561s;
980 break;
981 case RT2661:
982 fw_name = FIRMWARE_RT2661;
983 break;
984 default:
985 fw_name = NULL;
986 break;
987 }
988
989 return fw_name;
990 }
991
992 /*
993 * Initialization functions.
994 */
995 static int rt61pci_load_firmware(struct rt2x00_dev *rt2x00dev, void *data,
996 const size_t len)
997 {
998 int i;
999 u32 reg;
1000
1001 /*
1002 * Wait for stable hardware.
1003 */
1004 for (i = 0; i < 100; i++) {
1005 rt2x00pci_register_read(rt2x00dev, MAC_CSR0, &reg);
1006 if (reg)
1007 break;
1008 msleep(1);
1009 }
1010
1011 if (!reg) {
1012 ERROR(rt2x00dev, "Unstable hardware.\n");
1013 return -EBUSY;
1014 }
1015
1016 /*
1017 * Prepare MCU and mailbox for firmware loading.
1018 */
1019 reg = 0;
1020 rt2x00_set_field32(&reg, MCU_CNTL_CSR_RESET, 1);
1021 rt2x00pci_register_write(rt2x00dev, MCU_CNTL_CSR, reg);
1022 rt2x00pci_register_write(rt2x00dev, M2H_CMD_DONE_CSR, 0xffffffff);
1023 rt2x00pci_register_write(rt2x00dev, H2M_MAILBOX_CSR, 0);
1024 rt2x00pci_register_write(rt2x00dev, HOST_CMD_CSR, 0);
1025
1026 /*
1027 * Write firmware to device.
1028 */
1029 reg = 0;
1030 rt2x00_set_field32(&reg, MCU_CNTL_CSR_RESET, 1);
1031 rt2x00_set_field32(&reg, MCU_CNTL_CSR_SELECT_BANK, 1);
1032 rt2x00pci_register_write(rt2x00dev, MCU_CNTL_CSR, reg);
1033
1034 rt2x00pci_register_multiwrite(rt2x00dev, FIRMWARE_IMAGE_BASE,
1035 data, len);
1036
1037 rt2x00_set_field32(&reg, MCU_CNTL_CSR_SELECT_BANK, 0);
1038 rt2x00pci_register_write(rt2x00dev, MCU_CNTL_CSR, reg);
1039
1040 rt2x00_set_field32(&reg, MCU_CNTL_CSR_RESET, 0);
1041 rt2x00pci_register_write(rt2x00dev, MCU_CNTL_CSR, reg);
1042
1043 for (i = 0; i < 100; i++) {
1044 rt2x00pci_register_read(rt2x00dev, MCU_CNTL_CSR, &reg);
1045 if (rt2x00_get_field32(reg, MCU_CNTL_CSR_READY))
1046 break;
1047 msleep(1);
1048 }
1049
1050 if (i == 100) {
1051 ERROR(rt2x00dev, "MCU Control register not ready.\n");
1052 return -EBUSY;
1053 }
1054
1055 /*
1056 * Reset MAC and BBP registers.
1057 */
1058 reg = 0;
1059 rt2x00_set_field32(&reg, MAC_CSR1_SOFT_RESET, 1);
1060 rt2x00_set_field32(&reg, MAC_CSR1_BBP_RESET, 1);
1061 rt2x00pci_register_write(rt2x00dev, MAC_CSR1, reg);
1062
1063 rt2x00pci_register_read(rt2x00dev, MAC_CSR1, &reg);
1064 rt2x00_set_field32(&reg, MAC_CSR1_SOFT_RESET, 0);
1065 rt2x00_set_field32(&reg, MAC_CSR1_BBP_RESET, 0);
1066 rt2x00pci_register_write(rt2x00dev, MAC_CSR1, reg);
1067
1068 rt2x00pci_register_read(rt2x00dev, MAC_CSR1, &reg);
1069 rt2x00_set_field32(&reg, MAC_CSR1_HOST_READY, 1);
1070 rt2x00pci_register_write(rt2x00dev, MAC_CSR1, reg);
1071
1072 return 0;
1073 }
1074
1075 static void rt61pci_init_rxring(struct rt2x00_dev *rt2x00dev)
1076 {
1077 struct data_ring *ring = rt2x00dev->rx;
1078 struct data_desc *rxd;
1079 unsigned int i;
1080 u32 word;
1081
1082 memset(ring->data_addr, 0x00, rt2x00_get_ring_size(ring));
1083
1084 for (i = 0; i < ring->stats.limit; i++) {
1085 rxd = ring->entry[i].priv;
1086
1087 rt2x00_desc_read(rxd, 5, &word);
1088 rt2x00_set_field32(&word, RXD_W5_BUFFER_PHYSICAL_ADDRESS,
1089 ring->entry[i].data_dma);
1090 rt2x00_desc_write(rxd, 5, word);
1091
1092 rt2x00_desc_read(rxd, 0, &word);
1093 rt2x00_set_field32(&word, RXD_W0_OWNER_NIC, 1);
1094 rt2x00_desc_write(rxd, 0, word);
1095 }
1096
1097 rt2x00_ring_index_clear(rt2x00dev->rx);
1098 }
1099
1100 static void rt61pci_init_txring(struct rt2x00_dev *rt2x00dev, const int queue)
1101 {
1102 struct data_ring *ring = rt2x00lib_get_ring(rt2x00dev, queue);
1103 struct data_desc *txd;
1104 unsigned int i;
1105 u32 word;
1106
1107 memset(ring->data_addr, 0x00, rt2x00_get_ring_size(ring));
1108
1109 for (i = 0; i < ring->stats.limit; i++) {
1110 txd = ring->entry[i].priv;
1111
1112 rt2x00_desc_read(txd, 1, &word);
1113 rt2x00_set_field32(&word, TXD_W1_BUFFER_COUNT, 1);
1114 rt2x00_desc_write(txd, 1, word);
1115
1116 rt2x00_desc_read(txd, 5, &word);
1117 rt2x00_set_field32(&word, TXD_W5_PID_TYPE, queue);
1118 rt2x00_set_field32(&word, TXD_W5_PID_SUBTYPE, i);
1119 rt2x00_desc_write(txd, 5, word);
1120
1121 rt2x00_desc_read(txd, 6, &word);
1122 rt2x00_set_field32(&word, TXD_W6_BUFFER_PHYSICAL_ADDRESS,
1123 ring->entry[i].data_dma);
1124 rt2x00_desc_write(txd, 6, word);
1125
1126 rt2x00_desc_read(txd, 0, &word);
1127 rt2x00_set_field32(&word, TXD_W0_VALID, 0);
1128 rt2x00_set_field32(&word, TXD_W0_OWNER_NIC, 0);
1129 rt2x00_desc_write(txd, 0, word);
1130 }
1131
1132 rt2x00_ring_index_clear(ring);
1133 }
1134
1135 static int rt61pci_init_rings(struct rt2x00_dev *rt2x00dev)
1136 {
1137 u32 reg;
1138
1139 /*
1140 * Initialize rings.
1141 */
1142 rt61pci_init_rxring(rt2x00dev);
1143 rt61pci_init_txring(rt2x00dev, IEEE80211_TX_QUEUE_DATA0);
1144 rt61pci_init_txring(rt2x00dev, IEEE80211_TX_QUEUE_DATA1);
1145 rt61pci_init_txring(rt2x00dev, IEEE80211_TX_QUEUE_DATA2);
1146 rt61pci_init_txring(rt2x00dev, IEEE80211_TX_QUEUE_DATA3);
1147 rt61pci_init_txring(rt2x00dev, IEEE80211_TX_QUEUE_DATA4);
1148
1149 /*
1150 * Initialize registers.
1151 */
1152 rt2x00pci_register_read(rt2x00dev, TX_RING_CSR0, &reg);
1153 rt2x00_set_field32(&reg, TX_RING_CSR0_AC0_RING_SIZE,
1154 rt2x00dev->tx[IEEE80211_TX_QUEUE_DATA0].stats.limit);
1155 rt2x00_set_field32(&reg, TX_RING_CSR0_AC1_RING_SIZE,
1156 rt2x00dev->tx[IEEE80211_TX_QUEUE_DATA1].stats.limit);
1157 rt2x00_set_field32(&reg, TX_RING_CSR0_AC2_RING_SIZE,
1158 rt2x00dev->tx[IEEE80211_TX_QUEUE_DATA2].stats.limit);
1159 rt2x00_set_field32(&reg, TX_RING_CSR0_AC3_RING_SIZE,
1160 rt2x00dev->tx[IEEE80211_TX_QUEUE_DATA3].stats.limit);
1161 rt2x00pci_register_write(rt2x00dev, TX_RING_CSR0, reg);
1162
1163 rt2x00pci_register_read(rt2x00dev, TX_RING_CSR1, &reg);
1164 rt2x00_set_field32(&reg, TX_RING_CSR1_MGMT_RING_SIZE,
1165 rt2x00dev->tx[IEEE80211_TX_QUEUE_DATA4].stats.limit);
1166 rt2x00_set_field32(&reg, TX_RING_CSR1_TXD_SIZE,
1167 rt2x00dev->tx[IEEE80211_TX_QUEUE_DATA0].desc_size /
1168 4);
1169 rt2x00pci_register_write(rt2x00dev, TX_RING_CSR1, reg);
1170
1171 rt2x00pci_register_read(rt2x00dev, AC0_BASE_CSR, &reg);
1172 rt2x00_set_field32(&reg, AC0_BASE_CSR_RING_REGISTER,
1173 rt2x00dev->tx[IEEE80211_TX_QUEUE_DATA0].data_dma);
1174 rt2x00pci_register_write(rt2x00dev, AC0_BASE_CSR, reg);
1175
1176 rt2x00pci_register_read(rt2x00dev, AC1_BASE_CSR, &reg);
1177 rt2x00_set_field32(&reg, AC1_BASE_CSR_RING_REGISTER,
1178 rt2x00dev->tx[IEEE80211_TX_QUEUE_DATA1].data_dma);
1179 rt2x00pci_register_write(rt2x00dev, AC1_BASE_CSR, reg);
1180
1181 rt2x00pci_register_read(rt2x00dev, AC2_BASE_CSR, &reg);
1182 rt2x00_set_field32(&reg, AC2_BASE_CSR_RING_REGISTER,
1183 rt2x00dev->tx[IEEE80211_TX_QUEUE_DATA2].data_dma);
1184 rt2x00pci_register_write(rt2x00dev, AC2_BASE_CSR, reg);
1185
1186 rt2x00pci_register_read(rt2x00dev, AC3_BASE_CSR, &reg);
1187 rt2x00_set_field32(&reg, AC3_BASE_CSR_RING_REGISTER,
1188 rt2x00dev->tx[IEEE80211_TX_QUEUE_DATA3].data_dma);
1189 rt2x00pci_register_write(rt2x00dev, AC3_BASE_CSR, reg);
1190
1191 rt2x00pci_register_read(rt2x00dev, MGMT_BASE_CSR, &reg);
1192 rt2x00_set_field32(&reg, MGMT_BASE_CSR_RING_REGISTER,
1193 rt2x00dev->tx[IEEE80211_TX_QUEUE_DATA4].data_dma);
1194 rt2x00pci_register_write(rt2x00dev, MGMT_BASE_CSR, reg);
1195
1196 rt2x00pci_register_read(rt2x00dev, RX_RING_CSR, &reg);
1197 rt2x00_set_field32(&reg, RX_RING_CSR_RING_SIZE,
1198 rt2x00dev->rx->stats.limit);
1199 rt2x00_set_field32(&reg, RX_RING_CSR_RXD_SIZE,
1200 rt2x00dev->rx->desc_size / 4);
1201 rt2x00_set_field32(&reg, RX_RING_CSR_RXD_WRITEBACK_SIZE, 4);
1202 rt2x00pci_register_write(rt2x00dev, RX_RING_CSR, reg);
1203
1204 rt2x00pci_register_read(rt2x00dev, RX_BASE_CSR, &reg);
1205 rt2x00_set_field32(&reg, RX_BASE_CSR_RING_REGISTER,
1206 rt2x00dev->rx->data_dma);
1207 rt2x00pci_register_write(rt2x00dev, RX_BASE_CSR, reg);
1208
1209 rt2x00pci_register_read(rt2x00dev, TX_DMA_DST_CSR, &reg);
1210 rt2x00_set_field32(&reg, TX_DMA_DST_CSR_DEST_AC0, 2);
1211 rt2x00_set_field32(&reg, TX_DMA_DST_CSR_DEST_AC1, 2);
1212 rt2x00_set_field32(&reg, TX_DMA_DST_CSR_DEST_AC2, 2);
1213 rt2x00_set_field32(&reg, TX_DMA_DST_CSR_DEST_AC3, 2);
1214 rt2x00_set_field32(&reg, TX_DMA_DST_CSR_DEST_MGMT, 0);
1215 rt2x00pci_register_write(rt2x00dev, TX_DMA_DST_CSR, reg);
1216
1217 rt2x00pci_register_read(rt2x00dev, LOAD_TX_RING_CSR, &reg);
1218 rt2x00_set_field32(&reg, LOAD_TX_RING_CSR_LOAD_TXD_AC0, 1);
1219 rt2x00_set_field32(&reg, LOAD_TX_RING_CSR_LOAD_TXD_AC1, 1);
1220 rt2x00_set_field32(&reg, LOAD_TX_RING_CSR_LOAD_TXD_AC2, 1);
1221 rt2x00_set_field32(&reg, LOAD_TX_RING_CSR_LOAD_TXD_AC3, 1);
1222 rt2x00_set_field32(&reg, LOAD_TX_RING_CSR_LOAD_TXD_MGMT, 1);
1223 rt2x00pci_register_write(rt2x00dev, LOAD_TX_RING_CSR, reg);
1224
1225 rt2x00pci_register_read(rt2x00dev, RX_CNTL_CSR, &reg);
1226 rt2x00_set_field32(&reg, RX_CNTL_CSR_LOAD_RXD, 1);
1227 rt2x00pci_register_write(rt2x00dev, RX_CNTL_CSR, reg);
1228
1229 return 0;
1230 }
1231
1232 static int rt61pci_init_registers(struct rt2x00_dev *rt2x00dev)
1233 {
1234 u32 reg;
1235
1236 rt2x00pci_register_read(rt2x00dev, TXRX_CSR0, &reg);
1237 rt2x00_set_field32(&reg, TXRX_CSR0_AUTO_TX_SEQ, 1);
1238 rt2x00_set_field32(&reg, TXRX_CSR0_DISABLE_RX, 0);
1239 rt2x00_set_field32(&reg, TXRX_CSR0_TX_WITHOUT_WAITING, 0);
1240 rt2x00pci_register_write(rt2x00dev, TXRX_CSR0, reg);
1241
1242 rt2x00pci_register_read(rt2x00dev, TXRX_CSR1, &reg);
1243 rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID0, 47); /* CCK Signal */
1244 rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID0_VALID, 1);
1245 rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID1, 30); /* Rssi */
1246 rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID1_VALID, 1);
1247 rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID2, 42); /* OFDM Rate */
1248 rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID2_VALID, 1);
1249 rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID3, 30); /* Rssi */
1250 rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID3_VALID, 1);
1251 rt2x00pci_register_write(rt2x00dev, TXRX_CSR1, reg);
1252
1253 /*
1254 * CCK TXD BBP registers
1255 */
1256 rt2x00pci_register_read(rt2x00dev, TXRX_CSR2, &reg);
1257 rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID0, 13);
1258 rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID0_VALID, 1);
1259 rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID1, 12);
1260 rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID1_VALID, 1);
1261 rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID2, 11);
1262 rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID2_VALID, 1);
1263 rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID3, 10);
1264 rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID3_VALID, 1);
1265 rt2x00pci_register_write(rt2x00dev, TXRX_CSR2, reg);
1266
1267 /*
1268 * OFDM TXD BBP registers
1269 */
1270 rt2x00pci_register_read(rt2x00dev, TXRX_CSR3, &reg);
1271 rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID0, 7);
1272 rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID0_VALID, 1);
1273 rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID1, 6);
1274 rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID1_VALID, 1);
1275 rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID2, 5);
1276 rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID2_VALID, 1);
1277 rt2x00pci_register_write(rt2x00dev, TXRX_CSR3, reg);
1278
1279 rt2x00pci_register_read(rt2x00dev, TXRX_CSR7, &reg);
1280 rt2x00_set_field32(&reg, TXRX_CSR7_ACK_CTS_6MBS, 59);
1281 rt2x00_set_field32(&reg, TXRX_CSR7_ACK_CTS_9MBS, 53);
1282 rt2x00_set_field32(&reg, TXRX_CSR7_ACK_CTS_12MBS, 49);
1283 rt2x00_set_field32(&reg, TXRX_CSR7_ACK_CTS_18MBS, 46);
1284 rt2x00pci_register_write(rt2x00dev, TXRX_CSR7, reg);
1285
1286 rt2x00pci_register_read(rt2x00dev, TXRX_CSR8, &reg);
1287 rt2x00_set_field32(&reg, TXRX_CSR8_ACK_CTS_24MBS, 44);
1288 rt2x00_set_field32(&reg, TXRX_CSR8_ACK_CTS_36MBS, 42);
1289 rt2x00_set_field32(&reg, TXRX_CSR8_ACK_CTS_48MBS, 42);
1290 rt2x00_set_field32(&reg, TXRX_CSR8_ACK_CTS_54MBS, 42);
1291 rt2x00pci_register_write(rt2x00dev, TXRX_CSR8, reg);
1292
1293 rt2x00pci_register_write(rt2x00dev, TXRX_CSR15, 0x0000000f);
1294
1295 rt2x00pci_register_write(rt2x00dev, MAC_CSR6, 0x00000fff);
1296
1297 rt2x00pci_register_read(rt2x00dev, MAC_CSR9, &reg);
1298 rt2x00_set_field32(&reg, MAC_CSR9_CW_SELECT, 0);
1299 rt2x00pci_register_write(rt2x00dev, MAC_CSR9, reg);
1300
1301 rt2x00pci_register_write(rt2x00dev, MAC_CSR10, 0x0000071c);
1302
1303 if (rt2x00dev->ops->lib->set_device_state(rt2x00dev, STATE_AWAKE))
1304 return -EBUSY;
1305
1306 rt2x00pci_register_write(rt2x00dev, MAC_CSR13, 0x0000e000);
1307
1308 /*
1309 * Invalidate all Shared Keys (SEC_CSR0),
1310 * and clear the Shared key Cipher algorithms (SEC_CSR1 & SEC_CSR5)
1311 */
1312 rt2x00pci_register_write(rt2x00dev, SEC_CSR0, 0x00000000);
1313 rt2x00pci_register_write(rt2x00dev, SEC_CSR1, 0x00000000);
1314 rt2x00pci_register_write(rt2x00dev, SEC_CSR5, 0x00000000);
1315
1316 rt2x00pci_register_write(rt2x00dev, PHY_CSR1, 0x000023b0);
1317 rt2x00pci_register_write(rt2x00dev, PHY_CSR5, 0x060a100c);
1318 rt2x00pci_register_write(rt2x00dev, PHY_CSR6, 0x00080606);
1319 rt2x00pci_register_write(rt2x00dev, PHY_CSR7, 0x00000a08);
1320
1321 rt2x00pci_register_write(rt2x00dev, PCI_CFG_CSR, 0x28ca4404);
1322
1323 rt2x00pci_register_write(rt2x00dev, TEST_MODE_CSR, 0x00000200);
1324
1325 rt2x00pci_register_write(rt2x00dev, M2H_CMD_DONE_CSR, 0xffffffff);
1326
1327 rt2x00pci_register_read(rt2x00dev, AC_TXOP_CSR0, &reg);
1328 rt2x00_set_field32(&reg, AC_TXOP_CSR0_AC0_TX_OP, 0);
1329 rt2x00_set_field32(&reg, AC_TXOP_CSR0_AC1_TX_OP, 0);
1330 rt2x00pci_register_write(rt2x00dev, AC_TXOP_CSR0, reg);
1331
1332 rt2x00pci_register_read(rt2x00dev, AC_TXOP_CSR1, &reg);
1333 rt2x00_set_field32(&reg, AC_TXOP_CSR1_AC2_TX_OP, 192);
1334 rt2x00_set_field32(&reg, AC_TXOP_CSR1_AC3_TX_OP, 48);
1335 rt2x00pci_register_write(rt2x00dev, AC_TXOP_CSR1, reg);
1336
1337 /*
1338 * We must clear the error counters.
1339 * These registers are cleared on read,
1340 * so we may pass a useless variable to store the value.
1341 */
1342 rt2x00pci_register_read(rt2x00dev, STA_CSR0, &reg);
1343 rt2x00pci_register_read(rt2x00dev, STA_CSR1, &reg);
1344 rt2x00pci_register_read(rt2x00dev, STA_CSR2, &reg);
1345
1346 /*
1347 * Reset MAC and BBP registers.
1348 */
1349 rt2x00pci_register_read(rt2x00dev, MAC_CSR1, &reg);
1350 rt2x00_set_field32(&reg, MAC_CSR1_SOFT_RESET, 1);
1351 rt2x00_set_field32(&reg, MAC_CSR1_BBP_RESET, 1);
1352 rt2x00pci_register_write(rt2x00dev, MAC_CSR1, reg);
1353
1354 rt2x00pci_register_read(rt2x00dev, MAC_CSR1, &reg);
1355 rt2x00_set_field32(&reg, MAC_CSR1_SOFT_RESET, 0);
1356 rt2x00_set_field32(&reg, MAC_CSR1_BBP_RESET, 0);
1357 rt2x00pci_register_write(rt2x00dev, MAC_CSR1, reg);
1358
1359 rt2x00pci_register_read(rt2x00dev, MAC_CSR1, &reg);
1360 rt2x00_set_field32(&reg, MAC_CSR1_HOST_READY, 1);
1361 rt2x00pci_register_write(rt2x00dev, MAC_CSR1, reg);
1362
1363 return 0;
1364 }
1365
1366 static int rt61pci_init_bbp(struct rt2x00_dev *rt2x00dev)
1367 {
1368 unsigned int i;
1369 u16 eeprom;
1370 u8 reg_id;
1371 u8 value;
1372
1373 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
1374 rt61pci_bbp_read(rt2x00dev, 0, &value);
1375 if ((value != 0xff) && (value != 0x00))
1376 goto continue_csr_init;
1377 NOTICE(rt2x00dev, "Waiting for BBP register.\n");
1378 udelay(REGISTER_BUSY_DELAY);
1379 }
1380
1381 ERROR(rt2x00dev, "BBP register access failed, aborting.\n");
1382 return -EACCES;
1383
1384 continue_csr_init:
1385 rt61pci_bbp_write(rt2x00dev, 3, 0x00);
1386 rt61pci_bbp_write(rt2x00dev, 15, 0x30);
1387 rt61pci_bbp_write(rt2x00dev, 21, 0xc8);
1388 rt61pci_bbp_write(rt2x00dev, 22, 0x38);
1389 rt61pci_bbp_write(rt2x00dev, 23, 0x06);
1390 rt61pci_bbp_write(rt2x00dev, 24, 0xfe);
1391 rt61pci_bbp_write(rt2x00dev, 25, 0x0a);
1392 rt61pci_bbp_write(rt2x00dev, 26, 0x0d);
1393 rt61pci_bbp_write(rt2x00dev, 34, 0x12);
1394 rt61pci_bbp_write(rt2x00dev, 37, 0x07);
1395 rt61pci_bbp_write(rt2x00dev, 39, 0xf8);
1396 rt61pci_bbp_write(rt2x00dev, 41, 0x60);
1397 rt61pci_bbp_write(rt2x00dev, 53, 0x10);
1398 rt61pci_bbp_write(rt2x00dev, 54, 0x18);
1399 rt61pci_bbp_write(rt2x00dev, 60, 0x10);
1400 rt61pci_bbp_write(rt2x00dev, 61, 0x04);
1401 rt61pci_bbp_write(rt2x00dev, 62, 0x04);
1402 rt61pci_bbp_write(rt2x00dev, 75, 0xfe);
1403 rt61pci_bbp_write(rt2x00dev, 86, 0xfe);
1404 rt61pci_bbp_write(rt2x00dev, 88, 0xfe);
1405 rt61pci_bbp_write(rt2x00dev, 90, 0x0f);
1406 rt61pci_bbp_write(rt2x00dev, 99, 0x00);
1407 rt61pci_bbp_write(rt2x00dev, 102, 0x16);
1408 rt61pci_bbp_write(rt2x00dev, 107, 0x04);
1409
1410 DEBUG(rt2x00dev, "Start initialization from EEPROM...\n");
1411 for (i = 0; i < EEPROM_BBP_SIZE; i++) {
1412 rt2x00_eeprom_read(rt2x00dev, EEPROM_BBP_START + i, &eeprom);
1413
1414 if (eeprom != 0xffff && eeprom != 0x0000) {
1415 reg_id = rt2x00_get_field16(eeprom, EEPROM_BBP_REG_ID);
1416 value = rt2x00_get_field16(eeprom, EEPROM_BBP_VALUE);
1417 DEBUG(rt2x00dev, "BBP: 0x%02x, value: 0x%02x.\n",
1418 reg_id, value);
1419 rt61pci_bbp_write(rt2x00dev, reg_id, value);
1420 }
1421 }
1422 DEBUG(rt2x00dev, "...End initialization from EEPROM.\n");
1423
1424 return 0;
1425 }
1426
1427 /*
1428 * Device state switch handlers.
1429 */
1430 static void rt61pci_toggle_rx(struct rt2x00_dev *rt2x00dev,
1431 enum dev_state state)
1432 {
1433 u32 reg;
1434
1435 rt2x00pci_register_read(rt2x00dev, TXRX_CSR0, &reg);
1436 rt2x00_set_field32(&reg, TXRX_CSR0_DISABLE_RX,
1437 state == STATE_RADIO_RX_OFF);
1438 rt2x00pci_register_write(rt2x00dev, TXRX_CSR0, reg);
1439 }
1440
1441 static void rt61pci_toggle_irq(struct rt2x00_dev *rt2x00dev,
1442 enum dev_state state)
1443 {
1444 int mask = (state == STATE_RADIO_IRQ_OFF);
1445 u32 reg;
1446
1447 /*
1448 * When interrupts are being enabled, the interrupt registers
1449 * should clear the register to assure a clean state.
1450 */
1451 if (state == STATE_RADIO_IRQ_ON) {
1452 rt2x00pci_register_read(rt2x00dev, INT_SOURCE_CSR, &reg);
1453 rt2x00pci_register_write(rt2x00dev, INT_SOURCE_CSR, reg);
1454
1455 rt2x00pci_register_read(rt2x00dev, MCU_INT_SOURCE_CSR, &reg);
1456 rt2x00pci_register_write(rt2x00dev, MCU_INT_SOURCE_CSR, reg);
1457 }
1458
1459 /*
1460 * Only toggle the interrupts bits we are going to use.
1461 * Non-checked interrupt bits are disabled by default.
1462 */
1463 rt2x00pci_register_read(rt2x00dev, INT_MASK_CSR, &reg);
1464 rt2x00_set_field32(&reg, INT_MASK_CSR_TXDONE, mask);
1465 rt2x00_set_field32(&reg, INT_MASK_CSR_RXDONE, mask);
1466 rt2x00_set_field32(&reg, INT_MASK_CSR_ENABLE_MITIGATION, mask);
1467 rt2x00_set_field32(&reg, INT_MASK_CSR_MITIGATION_PERIOD, 0xff);
1468 rt2x00pci_register_write(rt2x00dev, INT_MASK_CSR, reg);
1469
1470 rt2x00pci_register_read(rt2x00dev, MCU_INT_MASK_CSR, &reg);
1471 rt2x00_set_field32(&reg, MCU_INT_MASK_CSR_0, mask);
1472 rt2x00_set_field32(&reg, MCU_INT_MASK_CSR_1, mask);
1473 rt2x00_set_field32(&reg, MCU_INT_MASK_CSR_2, mask);
1474 rt2x00_set_field32(&reg, MCU_INT_MASK_CSR_3, mask);
1475 rt2x00_set_field32(&reg, MCU_INT_MASK_CSR_4, mask);
1476 rt2x00_set_field32(&reg, MCU_INT_MASK_CSR_5, mask);
1477 rt2x00_set_field32(&reg, MCU_INT_MASK_CSR_6, mask);
1478 rt2x00_set_field32(&reg, MCU_INT_MASK_CSR_7, mask);
1479 rt2x00pci_register_write(rt2x00dev, MCU_INT_MASK_CSR, reg);
1480 }
1481
1482 static int rt61pci_enable_radio(struct rt2x00_dev *rt2x00dev)
1483 {
1484 u32 reg;
1485
1486 /*
1487 * Initialize all registers.
1488 */
1489 if (rt61pci_init_rings(rt2x00dev) ||
1490 rt61pci_init_registers(rt2x00dev) ||
1491 rt61pci_init_bbp(rt2x00dev)) {
1492 ERROR(rt2x00dev, "Register initialization failed.\n");
1493 return -EIO;
1494 }
1495
1496 /*
1497 * Enable interrupts.
1498 */
1499 rt61pci_toggle_irq(rt2x00dev, STATE_RADIO_IRQ_ON);
1500
1501 /*
1502 * Enable RX.
1503 */
1504 rt2x00pci_register_read(rt2x00dev, RX_CNTL_CSR, &reg);
1505 rt2x00_set_field32(&reg, RX_CNTL_CSR_ENABLE_RX_DMA, 1);
1506 rt2x00pci_register_write(rt2x00dev, RX_CNTL_CSR, reg);
1507
1508 /*
1509 * Enable LED
1510 */
1511 rt61pci_enable_led(rt2x00dev);
1512
1513 return 0;
1514 }
1515
1516 static void rt61pci_disable_radio(struct rt2x00_dev *rt2x00dev)
1517 {
1518 u32 reg;
1519
1520 /*
1521 * Disable LED
1522 */
1523 rt61pci_disable_led(rt2x00dev);
1524
1525 rt2x00pci_register_write(rt2x00dev, MAC_CSR10, 0x00001818);
1526
1527 /*
1528 * Disable synchronisation.
1529 */
1530 rt2x00pci_register_write(rt2x00dev, TXRX_CSR9, 0);
1531
1532 /*
1533 * Cancel RX and TX.
1534 */
1535 rt2x00pci_register_read(rt2x00dev, TX_CNTL_CSR, &reg);
1536 rt2x00_set_field32(&reg, TX_CNTL_CSR_ABORT_TX_AC0, 1);
1537 rt2x00_set_field32(&reg, TX_CNTL_CSR_ABORT_TX_AC1, 1);
1538 rt2x00_set_field32(&reg, TX_CNTL_CSR_ABORT_TX_AC2, 1);
1539 rt2x00_set_field32(&reg, TX_CNTL_CSR_ABORT_TX_AC3, 1);
1540 rt2x00_set_field32(&reg, TX_CNTL_CSR_ABORT_TX_MGMT, 1);
1541 rt2x00pci_register_write(rt2x00dev, TX_CNTL_CSR, reg);
1542
1543 /*
1544 * Disable interrupts.
1545 */
1546 rt61pci_toggle_irq(rt2x00dev, STATE_RADIO_IRQ_OFF);
1547 }
1548
1549 static int rt61pci_set_state(struct rt2x00_dev *rt2x00dev, enum dev_state state)
1550 {
1551 u32 reg;
1552 unsigned int i;
1553 char put_to_sleep;
1554 char current_state;
1555
1556 put_to_sleep = (state != STATE_AWAKE);
1557
1558 rt2x00pci_register_read(rt2x00dev, MAC_CSR12, &reg);
1559 rt2x00_set_field32(&reg, MAC_CSR12_FORCE_WAKEUP, !put_to_sleep);
1560 rt2x00_set_field32(&reg, MAC_CSR12_PUT_TO_SLEEP, put_to_sleep);
1561 rt2x00pci_register_write(rt2x00dev, MAC_CSR12, reg);
1562
1563 /*
1564 * Device is not guaranteed to be in the requested state yet.
1565 * We must wait until the register indicates that the
1566 * device has entered the correct state.
1567 */
1568 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
1569 rt2x00pci_register_read(rt2x00dev, MAC_CSR12, &reg);
1570 current_state =
1571 rt2x00_get_field32(reg, MAC_CSR12_BBP_CURRENT_STATE);
1572 if (current_state == !put_to_sleep)
1573 return 0;
1574 msleep(10);
1575 }
1576
1577 NOTICE(rt2x00dev, "Device failed to enter state %d, "
1578 "current device state %d.\n", !put_to_sleep, current_state);
1579
1580 return -EBUSY;
1581 }
1582
1583 static int rt61pci_set_device_state(struct rt2x00_dev *rt2x00dev,
1584 enum dev_state state)
1585 {
1586 int retval = 0;
1587
1588 switch (state) {
1589 case STATE_RADIO_ON:
1590 retval = rt61pci_enable_radio(rt2x00dev);
1591 break;
1592 case STATE_RADIO_OFF:
1593 rt61pci_disable_radio(rt2x00dev);
1594 break;
1595 case STATE_RADIO_RX_ON:
1596 case STATE_RADIO_RX_OFF:
1597 rt61pci_toggle_rx(rt2x00dev, state);
1598 break;
1599 case STATE_DEEP_SLEEP:
1600 case STATE_SLEEP:
1601 case STATE_STANDBY:
1602 case STATE_AWAKE:
1603 retval = rt61pci_set_state(rt2x00dev, state);
1604 break;
1605 default:
1606 retval = -ENOTSUPP;
1607 break;
1608 }
1609
1610 return retval;
1611 }
1612
1613 /*
1614 * TX descriptor initialization
1615 */
1616 static void rt61pci_write_tx_desc(struct rt2x00_dev *rt2x00dev,
1617 struct data_desc *txd,
1618 struct txdata_entry_desc *desc,
1619 struct ieee80211_hdr *ieee80211hdr,
1620 unsigned int length,
1621 struct ieee80211_tx_control *control)
1622 {
1623 u32 word;
1624
1625 /*
1626 * Start writing the descriptor words.
1627 */
1628 rt2x00_desc_read(txd, 1, &word);
1629 rt2x00_set_field32(&word, TXD_W1_HOST_Q_ID, desc->queue);
1630 rt2x00_set_field32(&word, TXD_W1_AIFSN, desc->aifs);
1631 rt2x00_set_field32(&word, TXD_W1_CWMIN, desc->cw_min);
1632 rt2x00_set_field32(&word, TXD_W1_CWMAX, desc->cw_max);
1633 rt2x00_set_field32(&word, TXD_W1_IV_OFFSET, IEEE80211_HEADER);
1634 rt2x00_set_field32(&word, TXD_W1_HW_SEQUENCE, 1);
1635 rt2x00_desc_write(txd, 1, word);
1636
1637 rt2x00_desc_read(txd, 2, &word);
1638 rt2x00_set_field32(&word, TXD_W2_PLCP_SIGNAL, desc->signal);
1639 rt2x00_set_field32(&word, TXD_W2_PLCP_SERVICE, desc->service);
1640 rt2x00_set_field32(&word, TXD_W2_PLCP_LENGTH_LOW, desc->length_low);
1641 rt2x00_set_field32(&word, TXD_W2_PLCP_LENGTH_HIGH, desc->length_high);
1642 rt2x00_desc_write(txd, 2, word);
1643
1644 rt2x00_desc_read(txd, 5, &word);
1645 rt2x00_set_field32(&word, TXD_W5_TX_POWER,
1646 TXPOWER_TO_DEV(control->power_level));
1647 rt2x00_set_field32(&word, TXD_W5_WAITING_DMA_DONE_INT, 1);
1648 rt2x00_desc_write(txd, 5, word);
1649
1650 rt2x00_desc_read(txd, 11, &word);
1651 rt2x00_set_field32(&word, TXD_W11_BUFFER_LENGTH0, length);
1652 rt2x00_desc_write(txd, 11, word);
1653
1654 rt2x00_desc_read(txd, 0, &word);
1655 rt2x00_set_field32(&word, TXD_W0_OWNER_NIC, 1);
1656 rt2x00_set_field32(&word, TXD_W0_VALID, 1);
1657 rt2x00_set_field32(&word, TXD_W0_MORE_FRAG,
1658 test_bit(ENTRY_TXD_MORE_FRAG, &desc->flags));
1659 rt2x00_set_field32(&word, TXD_W0_ACK,
1660 !(control->flags & IEEE80211_TXCTL_NO_ACK));
1661 rt2x00_set_field32(&word, TXD_W0_TIMESTAMP,
1662 test_bit(ENTRY_TXD_REQ_TIMESTAMP, &desc->flags));
1663 rt2x00_set_field32(&word, TXD_W0_OFDM,
1664 test_bit(ENTRY_TXD_OFDM_RATE, &desc->flags));
1665 rt2x00_set_field32(&word, TXD_W0_IFS, desc->ifs);
1666 rt2x00_set_field32(&word, TXD_W0_RETRY_MODE,
1667 !!(control->flags &
1668 IEEE80211_TXCTL_LONG_RETRY_LIMIT));
1669 rt2x00_set_field32(&word, TXD_W0_TKIP_MIC, 0);
1670 rt2x00_set_field32(&word, TXD_W0_DATABYTE_COUNT, length);
1671 rt2x00_set_field32(&word, TXD_W0_BURST,
1672 test_bit(ENTRY_TXD_BURST, &desc->flags));
1673 rt2x00_set_field32(&word, TXD_W0_CIPHER_ALG, CIPHER_NONE);
1674 rt2x00_desc_write(txd, 0, word);
1675 }
1676
1677 /*
1678 * TX data initialization
1679 */
1680 static void rt61pci_kick_tx_queue(struct rt2x00_dev *rt2x00dev,
1681 unsigned int queue)
1682 {
1683 u32 reg;
1684
1685 if (queue == IEEE80211_TX_QUEUE_BEACON) {
1686 /*
1687 * For Wi-Fi faily generated beacons between participating
1688 * stations. Set TBTT phase adaptive adjustment step to 8us.
1689 */
1690 rt2x00pci_register_write(rt2x00dev, TXRX_CSR10, 0x00001008);
1691
1692 rt2x00pci_register_read(rt2x00dev, TXRX_CSR9, &reg);
1693 if (!rt2x00_get_field32(reg, TXRX_CSR9_BEACON_GEN)) {
1694 rt2x00_set_field32(&reg, TXRX_CSR9_BEACON_GEN, 1);
1695 rt2x00pci_register_write(rt2x00dev, TXRX_CSR9, reg);
1696 }
1697 return;
1698 }
1699
1700 rt2x00pci_register_read(rt2x00dev, TX_CNTL_CSR, &reg);
1701 if (queue == IEEE80211_TX_QUEUE_DATA0)
1702 rt2x00_set_field32(&reg, TX_CNTL_CSR_KICK_TX_AC0, 1);
1703 else if (queue == IEEE80211_TX_QUEUE_DATA1)
1704 rt2x00_set_field32(&reg, TX_CNTL_CSR_KICK_TX_AC1, 1);
1705 else if (queue == IEEE80211_TX_QUEUE_DATA2)
1706 rt2x00_set_field32(&reg, TX_CNTL_CSR_KICK_TX_AC2, 1);
1707 else if (queue == IEEE80211_TX_QUEUE_DATA3)
1708 rt2x00_set_field32(&reg, TX_CNTL_CSR_KICK_TX_AC3, 1);
1709 else if (queue == IEEE80211_TX_QUEUE_DATA4)
1710 rt2x00_set_field32(&reg, TX_CNTL_CSR_KICK_TX_MGMT, 1);
1711 rt2x00pci_register_write(rt2x00dev, TX_CNTL_CSR, reg);
1712 }
1713
1714 /*
1715 * RX control handlers
1716 */
1717 static int rt61pci_agc_to_rssi(struct rt2x00_dev *rt2x00dev, int rxd_w1)
1718 {
1719 u16 eeprom;
1720 u8 offset;
1721 u8 lna;
1722
1723 lna = rt2x00_get_field32(rxd_w1, RXD_W1_RSSI_LNA);
1724 switch (lna) {
1725 case 3:
1726 offset = 90;
1727 break;
1728 case 2:
1729 offset = 74;
1730 break;
1731 case 1:
1732 offset = 64;
1733 break;
1734 default:
1735 return 0;
1736 }
1737
1738 if (rt2x00dev->rx_status.phymode == MODE_IEEE80211A) {
1739 if (test_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags))
1740 offset += 14;
1741
1742 if (lna == 3 || lna == 2)
1743 offset += 10;
1744
1745 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_OFFSET_A, &eeprom);
1746 offset -= rt2x00_get_field16(eeprom, EEPROM_RSSI_OFFSET_A_1);
1747 } else {
1748 if (test_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags))
1749 offset += 14;
1750
1751 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_OFFSET_BG, &eeprom);
1752 offset -= rt2x00_get_field16(eeprom, EEPROM_RSSI_OFFSET_BG_1);
1753 }
1754
1755 return rt2x00_get_field32(rxd_w1, RXD_W1_RSSI_AGC) * 2 - offset;
1756 }
1757
1758 static void rt61pci_fill_rxdone(struct data_entry *entry,
1759 struct rxdata_entry_desc *desc)
1760 {
1761 struct data_desc *rxd = entry->priv;
1762 u32 word0;
1763 u32 word1;
1764
1765 rt2x00_desc_read(rxd, 0, &word0);
1766 rt2x00_desc_read(rxd, 1, &word1);
1767
1768 desc->flags = 0;
1769 if (rt2x00_get_field32(word0, RXD_W0_CRC_ERROR))
1770 desc->flags |= RX_FLAG_FAILED_FCS_CRC;
1771
1772 /*
1773 * Obtain the status about this packet.
1774 */
1775 desc->signal = rt2x00_get_field32(word1, RXD_W1_SIGNAL);
1776 desc->rssi = rt61pci_agc_to_rssi(entry->ring->rt2x00dev, word1);
1777 desc->ofdm = rt2x00_get_field32(word0, RXD_W0_OFDM);
1778 desc->size = rt2x00_get_field32(word0, RXD_W0_DATABYTE_COUNT);
1779
1780 return;
1781 }
1782
1783 /*
1784 * Interrupt functions.
1785 */
1786 static void rt61pci_txdone(struct rt2x00_dev *rt2x00dev)
1787 {
1788 struct data_ring *ring;
1789 struct data_entry *entry;
1790 struct data_desc *txd;
1791 u32 word;
1792 u32 reg;
1793 u32 old_reg;
1794 int type;
1795 int index;
1796 int tx_status;
1797 int retry;
1798
1799 /*
1800 * During each loop we will compare the freshly read
1801 * STA_CSR4 register value with the value read from
1802 * the previous loop. If the 2 values are equal then
1803 * we should stop processing because the chance it
1804 * quite big that the device has been unplugged and
1805 * we risk going into an endless loop.
1806 */
1807 old_reg = 0;
1808
1809 while (1) {
1810 rt2x00pci_register_read(rt2x00dev, STA_CSR4, &reg);
1811 if (!rt2x00_get_field32(reg, STA_CSR4_VALID))
1812 break;
1813
1814 if (old_reg == reg)
1815 break;
1816 old_reg = reg;
1817
1818 /*
1819 * Skip this entry when it contains an invalid
1820 * ring identication number.
1821 */
1822 type = rt2x00_get_field32(reg, STA_CSR4_PID_TYPE);
1823 ring = rt2x00lib_get_ring(rt2x00dev, type);
1824 if (unlikely(!ring))
1825 continue;
1826
1827 /*
1828 * Skip this entry when it contains an invalid
1829 * index number.
1830 */
1831 index = rt2x00_get_field32(reg, STA_CSR4_PID_SUBTYPE);
1832 if (unlikely(index >= ring->stats.limit))
1833 continue;
1834
1835 entry = &ring->entry[index];
1836 txd = entry->priv;
1837 rt2x00_desc_read(txd, 0, &word);
1838
1839 if (rt2x00_get_field32(word, TXD_W0_OWNER_NIC) ||
1840 !rt2x00_get_field32(word, TXD_W0_VALID))
1841 return;
1842
1843 /*
1844 * Obtain the status about this packet.
1845 */
1846 tx_status = rt2x00_get_field32(reg, STA_CSR4_TX_RESULT);
1847 retry = rt2x00_get_field32(reg, STA_CSR4_RETRY_COUNT);
1848
1849 rt2x00lib_txdone(entry, tx_status, retry);
1850
1851 /*
1852 * Make this entry available for reuse.
1853 */
1854 entry->flags = 0;
1855 rt2x00_set_field32(&word, TXD_W0_VALID, 0);
1856 rt2x00_desc_write(txd, 0, word);
1857 rt2x00_ring_index_done_inc(entry->ring);
1858
1859 /*
1860 * If the data ring was full before the txdone handler
1861 * we must make sure the packet queue in the mac80211 stack
1862 * is reenabled when the txdone handler has finished.
1863 */
1864 if (!rt2x00_ring_full(ring))
1865 ieee80211_wake_queue(rt2x00dev->hw,
1866 entry->tx_status.control.queue);
1867 }
1868 }
1869
1870 static irqreturn_t rt61pci_interrupt(int irq, void *dev_instance)
1871 {
1872 struct rt2x00_dev *rt2x00dev = dev_instance;
1873 u32 reg_mcu;
1874 u32 reg;
1875
1876 /*
1877 * Get the interrupt sources & saved to local variable.
1878 * Write register value back to clear pending interrupts.
1879 */
1880 rt2x00pci_register_read(rt2x00dev, MCU_INT_SOURCE_CSR, &reg_mcu);
1881 rt2x00pci_register_write(rt2x00dev, MCU_INT_SOURCE_CSR, reg_mcu);
1882
1883 rt2x00pci_register_read(rt2x00dev, INT_SOURCE_CSR, &reg);
1884 rt2x00pci_register_write(rt2x00dev, INT_SOURCE_CSR, reg);
1885
1886 if (!reg && !reg_mcu)
1887 return IRQ_NONE;
1888
1889 if (!test_bit(DEVICE_ENABLED_RADIO, &rt2x00dev->flags))
1890 return IRQ_HANDLED;
1891
1892 /*
1893 * Handle interrupts, walk through all bits
1894 * and run the tasks, the bits are checked in order of
1895 * priority.
1896 */
1897
1898 /*
1899 * 1 - Rx ring done interrupt.
1900 */
1901 if (rt2x00_get_field32(reg, INT_SOURCE_CSR_RXDONE))
1902 rt2x00pci_rxdone(rt2x00dev);
1903
1904 /*
1905 * 2 - Tx ring done interrupt.
1906 */
1907 if (rt2x00_get_field32(reg, INT_SOURCE_CSR_TXDONE))
1908 rt61pci_txdone(rt2x00dev);
1909
1910 /*
1911 * 3 - Handle MCU command done.
1912 */
1913 if (reg_mcu)
1914 rt2x00pci_register_write(rt2x00dev,
1915 M2H_CMD_DONE_CSR, 0xffffffff);
1916
1917 return IRQ_HANDLED;
1918 }
1919
1920 /*
1921 * Device probe functions.
1922 */
1923 static int rt61pci_validate_eeprom(struct rt2x00_dev *rt2x00dev)
1924 {
1925 struct eeprom_93cx6 eeprom;
1926 u32 reg;
1927 u16 word;
1928 u8 *mac;
1929 s8 value;
1930
1931 rt2x00pci_register_read(rt2x00dev, E2PROM_CSR, &reg);
1932
1933 eeprom.data = rt2x00dev;
1934 eeprom.register_read = rt61pci_eepromregister_read;
1935 eeprom.register_write = rt61pci_eepromregister_write;
1936 eeprom.width = rt2x00_get_field32(reg, E2PROM_CSR_TYPE_93C46) ?
1937 PCI_EEPROM_WIDTH_93C46 : PCI_EEPROM_WIDTH_93C66;
1938 eeprom.reg_data_in = 0;
1939 eeprom.reg_data_out = 0;
1940 eeprom.reg_data_clock = 0;
1941 eeprom.reg_chip_select = 0;
1942
1943 eeprom_93cx6_multiread(&eeprom, EEPROM_BASE, rt2x00dev->eeprom,
1944 EEPROM_SIZE / sizeof(u16));
1945
1946 /*
1947 * Start validation of the data that has been read.
1948 */
1949 mac = rt2x00_eeprom_addr(rt2x00dev, EEPROM_MAC_ADDR_0);
1950 if (!is_valid_ether_addr(mac)) {
1951 DECLARE_MAC_BUF(macbuf);
1952
1953 random_ether_addr(mac);
1954 EEPROM(rt2x00dev, "MAC: %s\n", print_mac(macbuf, mac));
1955 }
1956
1957 rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &word);
1958 if (word == 0xffff) {
1959 rt2x00_set_field16(&word, EEPROM_ANTENNA_NUM, 2);
1960 rt2x00_set_field16(&word, EEPROM_ANTENNA_TX_DEFAULT, 2);
1961 rt2x00_set_field16(&word, EEPROM_ANTENNA_RX_DEFAULT, 2);
1962 rt2x00_set_field16(&word, EEPROM_ANTENNA_FRAME_TYPE, 0);
1963 rt2x00_set_field16(&word, EEPROM_ANTENNA_DYN_TXAGC, 0);
1964 rt2x00_set_field16(&word, EEPROM_ANTENNA_HARDWARE_RADIO, 0);
1965 rt2x00_set_field16(&word, EEPROM_ANTENNA_RF_TYPE, RF5225);
1966 rt2x00_eeprom_write(rt2x00dev, EEPROM_ANTENNA, word);
1967 EEPROM(rt2x00dev, "Antenna: 0x%04x\n", word);
1968 }
1969
1970 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &word);
1971 if (word == 0xffff) {
1972 rt2x00_set_field16(&word, EEPROM_NIC_ENABLE_DIVERSITY, 0);
1973 rt2x00_set_field16(&word, EEPROM_NIC_TX_DIVERSITY, 0);
1974 rt2x00_set_field16(&word, EEPROM_NIC_TX_RX_FIXED, 0);
1975 rt2x00_set_field16(&word, EEPROM_NIC_EXTERNAL_LNA_BG, 0);
1976 rt2x00_set_field16(&word, EEPROM_NIC_CARDBUS_ACCEL, 0);
1977 rt2x00_set_field16(&word, EEPROM_NIC_EXTERNAL_LNA_A, 0);
1978 rt2x00_eeprom_write(rt2x00dev, EEPROM_NIC, word);
1979 EEPROM(rt2x00dev, "NIC: 0x%04x\n", word);
1980 }
1981
1982 rt2x00_eeprom_read(rt2x00dev, EEPROM_LED, &word);
1983 if (word == 0xffff) {
1984 rt2x00_set_field16(&word, EEPROM_LED_LED_MODE,
1985 LED_MODE_DEFAULT);
1986 rt2x00_eeprom_write(rt2x00dev, EEPROM_LED, word);
1987 EEPROM(rt2x00dev, "Led: 0x%04x\n", word);
1988 }
1989
1990 rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &word);
1991 if (word == 0xffff) {
1992 rt2x00_set_field16(&word, EEPROM_FREQ_OFFSET, 0);
1993 rt2x00_set_field16(&word, EEPROM_FREQ_SEQ, 0);
1994 rt2x00_eeprom_write(rt2x00dev, EEPROM_FREQ, word);
1995 EEPROM(rt2x00dev, "Freq: 0x%04x\n", word);
1996 }
1997
1998 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_OFFSET_BG, &word);
1999 if (word == 0xffff) {
2000 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_BG_1, 0);
2001 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_BG_2, 0);
2002 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_OFFSET_BG, word);
2003 EEPROM(rt2x00dev, "RSSI OFFSET BG: 0x%04x\n", word);
2004 } else {
2005 value = rt2x00_get_field16(word, EEPROM_RSSI_OFFSET_BG_1);
2006 if (value < -10 || value > 10)
2007 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_BG_1, 0);
2008 value = rt2x00_get_field16(word, EEPROM_RSSI_OFFSET_BG_2);
2009 if (value < -10 || value > 10)
2010 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_BG_2, 0);
2011 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_OFFSET_BG, word);
2012 }
2013
2014 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_OFFSET_A, &word);
2015 if (word == 0xffff) {
2016 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_A_1, 0);
2017 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_A_2, 0);
2018 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_OFFSET_A, word);
2019 EEPROM(rt2x00dev, "RSSI OFFSET BG: 0x%04x\n", word);
2020 } else {
2021 value = rt2x00_get_field16(word, EEPROM_RSSI_OFFSET_A_1);
2022 if (value < -10 || value > 10)
2023 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_A_1, 0);
2024 value = rt2x00_get_field16(word, EEPROM_RSSI_OFFSET_A_2);
2025 if (value < -10 || value > 10)
2026 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_A_2, 0);
2027 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_OFFSET_A, word);
2028 }
2029
2030 return 0;
2031 }
2032
2033 static int rt61pci_init_eeprom(struct rt2x00_dev *rt2x00dev)
2034 {
2035 u32 reg;
2036 u16 value;
2037 u16 eeprom;
2038 u16 device;
2039
2040 /*
2041 * Read EEPROM word for configuration.
2042 */
2043 rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &eeprom);
2044
2045 /*
2046 * Identify RF chipset.
2047 * To determine the RT chip we have to read the
2048 * PCI header of the device.
2049 */
2050 pci_read_config_word(rt2x00dev_pci(rt2x00dev),
2051 PCI_CONFIG_HEADER_DEVICE, &device);
2052 value = rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RF_TYPE);
2053 rt2x00pci_register_read(rt2x00dev, MAC_CSR0, &reg);
2054 rt2x00_set_chip(rt2x00dev, device, value, reg);
2055
2056 if (!rt2x00_rf(&rt2x00dev->chip, RF5225) &&
2057 !rt2x00_rf(&rt2x00dev->chip, RF5325) &&
2058 !rt2x00_rf(&rt2x00dev->chip, RF2527) &&
2059 !rt2x00_rf(&rt2x00dev->chip, RF2529)) {
2060 ERROR(rt2x00dev, "Invalid RF chipset detected.\n");
2061 return -ENODEV;
2062 }
2063
2064 /*
2065 * Identify default antenna configuration.
2066 */
2067 rt2x00dev->hw->conf.antenna_sel_tx =
2068 rt2x00_get_field16(eeprom, EEPROM_ANTENNA_TX_DEFAULT);
2069 rt2x00dev->hw->conf.antenna_sel_rx =
2070 rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RX_DEFAULT);
2071
2072 /*
2073 * Read the Frame type.
2074 */
2075 if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_FRAME_TYPE))
2076 __set_bit(CONFIG_FRAME_TYPE, &rt2x00dev->flags);
2077
2078 /*
2079 * Determine number of antenna's.
2080 */
2081 if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_NUM) == 2)
2082 __set_bit(CONFIG_DOUBLE_ANTENNA, &rt2x00dev->flags);
2083
2084 /*
2085 * Detect if this device has an hardware controlled radio.
2086 */
2087 #ifdef CONFIG_RT61PCI_RFKILL
2088 if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_HARDWARE_RADIO))
2089 __set_bit(CONFIG_SUPPORT_HW_BUTTON, &rt2x00dev->flags);
2090 #endif /* CONFIG_RT61PCI_RFKILL */
2091
2092 /*
2093 * Read frequency offset and RF programming sequence.
2094 */
2095 rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &eeprom);
2096 if (rt2x00_get_field16(eeprom, EEPROM_FREQ_SEQ))
2097 __set_bit(CONFIG_RF_SEQUENCE, &rt2x00dev->flags);
2098
2099 rt2x00dev->freq_offset = rt2x00_get_field16(eeprom, EEPROM_FREQ_OFFSET);
2100
2101 /*
2102 * Read external LNA informations.
2103 */
2104 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &eeprom);
2105
2106 if (rt2x00_get_field16(eeprom, EEPROM_NIC_EXTERNAL_LNA_A))
2107 __set_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags);
2108 if (rt2x00_get_field16(eeprom, EEPROM_NIC_EXTERNAL_LNA_BG))
2109 __set_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags);
2110
2111 /*
2112 * Store led settings, for correct led behaviour.
2113 * If the eeprom value is invalid,
2114 * switch to default led mode.
2115 */
2116 rt2x00_eeprom_read(rt2x00dev, EEPROM_LED, &eeprom);
2117
2118 rt2x00dev->led_mode = rt2x00_get_field16(eeprom, EEPROM_LED_LED_MODE);
2119
2120 rt2x00_set_field16(&rt2x00dev->led_reg, MCU_LEDCS_LED_MODE,
2121 rt2x00dev->led_mode);
2122 rt2x00_set_field16(&rt2x00dev->led_reg, MCU_LEDCS_POLARITY_GPIO_0,
2123 rt2x00_get_field16(eeprom,
2124 EEPROM_LED_POLARITY_GPIO_0));
2125 rt2x00_set_field16(&rt2x00dev->led_reg, MCU_LEDCS_POLARITY_GPIO_1,
2126 rt2x00_get_field16(eeprom,
2127 EEPROM_LED_POLARITY_GPIO_1));
2128 rt2x00_set_field16(&rt2x00dev->led_reg, MCU_LEDCS_POLARITY_GPIO_2,
2129 rt2x00_get_field16(eeprom,
2130 EEPROM_LED_POLARITY_GPIO_2));
2131 rt2x00_set_field16(&rt2x00dev->led_reg, MCU_LEDCS_POLARITY_GPIO_3,
2132 rt2x00_get_field16(eeprom,
2133 EEPROM_LED_POLARITY_GPIO_3));
2134 rt2x00_set_field16(&rt2x00dev->led_reg, MCU_LEDCS_POLARITY_GPIO_4,
2135 rt2x00_get_field16(eeprom,
2136 EEPROM_LED_POLARITY_GPIO_4));
2137 rt2x00_set_field16(&rt2x00dev->led_reg, MCU_LEDCS_POLARITY_ACT,
2138 rt2x00_get_field16(eeprom, EEPROM_LED_POLARITY_ACT));
2139 rt2x00_set_field16(&rt2x00dev->led_reg, MCU_LEDCS_POLARITY_READY_BG,
2140 rt2x00_get_field16(eeprom,
2141 EEPROM_LED_POLARITY_RDY_G));
2142 rt2x00_set_field16(&rt2x00dev->led_reg, MCU_LEDCS_POLARITY_READY_A,
2143 rt2x00_get_field16(eeprom,
2144 EEPROM_LED_POLARITY_RDY_A));
2145
2146 return 0;
2147 }
2148
2149 /*
2150 * RF value list for RF5225 & RF5325
2151 * Supports: 2.4 GHz & 5.2 GHz, rf_sequence disabled
2152 */
2153 static const struct rf_channel rf_vals_noseq[] = {
2154 { 1, 0x00002ccc, 0x00004786, 0x00068455, 0x000ffa0b },
2155 { 2, 0x00002ccc, 0x00004786, 0x00068455, 0x000ffa1f },
2156 { 3, 0x00002ccc, 0x0000478a, 0x00068455, 0x000ffa0b },
2157 { 4, 0x00002ccc, 0x0000478a, 0x00068455, 0x000ffa1f },
2158 { 5, 0x00002ccc, 0x0000478e, 0x00068455, 0x000ffa0b },
2159 { 6, 0x00002ccc, 0x0000478e, 0x00068455, 0x000ffa1f },
2160 { 7, 0x00002ccc, 0x00004792, 0x00068455, 0x000ffa0b },
2161 { 8, 0x00002ccc, 0x00004792, 0x00068455, 0x000ffa1f },
2162 { 9, 0x00002ccc, 0x00004796, 0x00068455, 0x000ffa0b },
2163 { 10, 0x00002ccc, 0x00004796, 0x00068455, 0x000ffa1f },
2164 { 11, 0x00002ccc, 0x0000479a, 0x00068455, 0x000ffa0b },
2165 { 12, 0x00002ccc, 0x0000479a, 0x00068455, 0x000ffa1f },
2166 { 13, 0x00002ccc, 0x0000479e, 0x00068455, 0x000ffa0b },
2167 { 14, 0x00002ccc, 0x000047a2, 0x00068455, 0x000ffa13 },
2168
2169 /* 802.11 UNI / HyperLan 2 */
2170 { 36, 0x00002ccc, 0x0000499a, 0x0009be55, 0x000ffa23 },
2171 { 40, 0x00002ccc, 0x000049a2, 0x0009be55, 0x000ffa03 },
2172 { 44, 0x00002ccc, 0x000049a6, 0x0009be55, 0x000ffa0b },
2173 { 48, 0x00002ccc, 0x000049aa, 0x0009be55, 0x000ffa13 },
2174 { 52, 0x00002ccc, 0x000049ae, 0x0009ae55, 0x000ffa1b },
2175 { 56, 0x00002ccc, 0x000049b2, 0x0009ae55, 0x000ffa23 },
2176 { 60, 0x00002ccc, 0x000049ba, 0x0009ae55, 0x000ffa03 },
2177 { 64, 0x00002ccc, 0x000049be, 0x0009ae55, 0x000ffa0b },
2178
2179 /* 802.11 HyperLan 2 */
2180 { 100, 0x00002ccc, 0x00004a2a, 0x000bae55, 0x000ffa03 },
2181 { 104, 0x00002ccc, 0x00004a2e, 0x000bae55, 0x000ffa0b },
2182 { 108, 0x00002ccc, 0x00004a32, 0x000bae55, 0x000ffa13 },
2183 { 112, 0x00002ccc, 0x00004a36, 0x000bae55, 0x000ffa1b },
2184 { 116, 0x00002ccc, 0x00004a3a, 0x000bbe55, 0x000ffa23 },
2185 { 120, 0x00002ccc, 0x00004a82, 0x000bbe55, 0x000ffa03 },
2186 { 124, 0x00002ccc, 0x00004a86, 0x000bbe55, 0x000ffa0b },
2187 { 128, 0x00002ccc, 0x00004a8a, 0x000bbe55, 0x000ffa13 },
2188 { 132, 0x00002ccc, 0x00004a8e, 0x000bbe55, 0x000ffa1b },
2189 { 136, 0x00002ccc, 0x00004a92, 0x000bbe55, 0x000ffa23 },
2190
2191 /* 802.11 UNII */
2192 { 140, 0x00002ccc, 0x00004a9a, 0x000bbe55, 0x000ffa03 },
2193 { 149, 0x00002ccc, 0x00004aa2, 0x000bbe55, 0x000ffa1f },
2194 { 153, 0x00002ccc, 0x00004aa6, 0x000bbe55, 0x000ffa27 },
2195 { 157, 0x00002ccc, 0x00004aae, 0x000bbe55, 0x000ffa07 },
2196 { 161, 0x00002ccc, 0x00004ab2, 0x000bbe55, 0x000ffa0f },
2197 { 165, 0x00002ccc, 0x00004ab6, 0x000bbe55, 0x000ffa17 },
2198
2199 /* MMAC(Japan)J52 ch 34,38,42,46 */
2200 { 34, 0x00002ccc, 0x0000499a, 0x0009be55, 0x000ffa0b },
2201 { 38, 0x00002ccc, 0x0000499e, 0x0009be55, 0x000ffa13 },
2202 { 42, 0x00002ccc, 0x000049a2, 0x0009be55, 0x000ffa1b },
2203 { 46, 0x00002ccc, 0x000049a6, 0x0009be55, 0x000ffa23 },
2204 };
2205
2206 /*
2207 * RF value list for RF5225 & RF5325
2208 * Supports: 2.4 GHz & 5.2 GHz, rf_sequence enabled
2209 */
2210 static const struct rf_channel rf_vals_seq[] = {
2211 { 1, 0x00002ccc, 0x00004786, 0x00068455, 0x000ffa0b },
2212 { 2, 0x00002ccc, 0x00004786, 0x00068455, 0x000ffa1f },
2213 { 3, 0x00002ccc, 0x0000478a, 0x00068455, 0x000ffa0b },
2214 { 4, 0x00002ccc, 0x0000478a, 0x00068455, 0x000ffa1f },
2215 { 5, 0x00002ccc, 0x0000478e, 0x00068455, 0x000ffa0b },
2216 { 6, 0x00002ccc, 0x0000478e, 0x00068455, 0x000ffa1f },
2217 { 7, 0x00002ccc, 0x00004792, 0x00068455, 0x000ffa0b },
2218 { 8, 0x00002ccc, 0x00004792, 0x00068455, 0x000ffa1f },
2219 { 9, 0x00002ccc, 0x00004796, 0x00068455, 0x000ffa0b },
2220 { 10, 0x00002ccc, 0x00004796, 0x00068455, 0x000ffa1f },
2221 { 11, 0x00002ccc, 0x0000479a, 0x00068455, 0x000ffa0b },
2222 { 12, 0x00002ccc, 0x0000479a, 0x00068455, 0x000ffa1f },
2223 { 13, 0x00002ccc, 0x0000479e, 0x00068455, 0x000ffa0b },
2224 { 14, 0x00002ccc, 0x000047a2, 0x00068455, 0x000ffa13 },
2225
2226 /* 802.11 UNI / HyperLan 2 */
2227 { 36, 0x00002cd4, 0x0004481a, 0x00098455, 0x000c0a03 },
2228 { 40, 0x00002cd0, 0x00044682, 0x00098455, 0x000c0a03 },
2229 { 44, 0x00002cd0, 0x00044686, 0x00098455, 0x000c0a1b },
2230 { 48, 0x00002cd0, 0x0004468e, 0x00098655, 0x000c0a0b },
2231 { 52, 0x00002cd0, 0x00044692, 0x00098855, 0x000c0a23 },
2232 { 56, 0x00002cd0, 0x0004469a, 0x00098c55, 0x000c0a13 },
2233 { 60, 0x00002cd0, 0x000446a2, 0x00098e55, 0x000c0a03 },
2234 { 64, 0x00002cd0, 0x000446a6, 0x00099255, 0x000c0a1b },
2235
2236 /* 802.11 HyperLan 2 */
2237 { 100, 0x00002cd4, 0x0004489a, 0x000b9855, 0x000c0a03 },
2238 { 104, 0x00002cd4, 0x000448a2, 0x000b9855, 0x000c0a03 },
2239 { 108, 0x00002cd4, 0x000448aa, 0x000b9855, 0x000c0a03 },
2240 { 112, 0x00002cd4, 0x000448b2, 0x000b9a55, 0x000c0a03 },
2241 { 116, 0x00002cd4, 0x000448ba, 0x000b9a55, 0x000c0a03 },
2242 { 120, 0x00002cd0, 0x00044702, 0x000b9a55, 0x000c0a03 },
2243 { 124, 0x00002cd0, 0x00044706, 0x000b9a55, 0x000c0a1b },
2244 { 128, 0x00002cd0, 0x0004470e, 0x000b9c55, 0x000c0a0b },
2245 { 132, 0x00002cd0, 0x00044712, 0x000b9c55, 0x000c0a23 },
2246 { 136, 0x00002cd0, 0x0004471a, 0x000b9e55, 0x000c0a13 },
2247
2248 /* 802.11 UNII */
2249 { 140, 0x00002cd0, 0x00044722, 0x000b9e55, 0x000c0a03 },
2250 { 149, 0x00002cd0, 0x0004472e, 0x000ba255, 0x000c0a1b },
2251 { 153, 0x00002cd0, 0x00044736, 0x000ba255, 0x000c0a0b },
2252 { 157, 0x00002cd4, 0x0004490a, 0x000ba255, 0x000c0a17 },
2253 { 161, 0x00002cd4, 0x00044912, 0x000ba255, 0x000c0a17 },
2254 { 165, 0x00002cd4, 0x0004491a, 0x000ba255, 0x000c0a17 },
2255
2256 /* MMAC(Japan)J52 ch 34,38,42,46 */
2257 { 34, 0x00002ccc, 0x0000499a, 0x0009be55, 0x000c0a0b },
2258 { 38, 0x00002ccc, 0x0000499e, 0x0009be55, 0x000c0a13 },
2259 { 42, 0x00002ccc, 0x000049a2, 0x0009be55, 0x000c0a1b },
2260 { 46, 0x00002ccc, 0x000049a6, 0x0009be55, 0x000c0a23 },
2261 };
2262
2263 static void rt61pci_probe_hw_mode(struct rt2x00_dev *rt2x00dev)
2264 {
2265 struct hw_mode_spec *spec = &rt2x00dev->spec;
2266 u8 *txpower;
2267 unsigned int i;
2268
2269 /*
2270 * Initialize all hw fields.
2271 */
2272 rt2x00dev->hw->flags =
2273 IEEE80211_HW_HOST_GEN_BEACON_TEMPLATE |
2274 IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING;
2275 rt2x00dev->hw->extra_tx_headroom = 0;
2276 rt2x00dev->hw->max_signal = MAX_SIGNAL;
2277 rt2x00dev->hw->max_rssi = MAX_RX_SSI;
2278 rt2x00dev->hw->queues = 5;
2279
2280 SET_IEEE80211_DEV(rt2x00dev->hw, &rt2x00dev_pci(rt2x00dev)->dev);
2281 SET_IEEE80211_PERM_ADDR(rt2x00dev->hw,
2282 rt2x00_eeprom_addr(rt2x00dev,
2283 EEPROM_MAC_ADDR_0));
2284
2285 /*
2286 * Convert tx_power array in eeprom.
2287 */
2288 txpower = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_G_START);
2289 for (i = 0; i < 14; i++)
2290 txpower[i] = TXPOWER_FROM_DEV(txpower[i]);
2291
2292 /*
2293 * Initialize hw_mode information.
2294 */
2295 spec->num_modes = 2;
2296 spec->num_rates = 12;
2297 spec->tx_power_a = NULL;
2298 spec->tx_power_bg = txpower;
2299 spec->tx_power_default = DEFAULT_TXPOWER;
2300
2301 if (!test_bit(CONFIG_RF_SEQUENCE, &rt2x00dev->flags)) {
2302 spec->num_channels = 14;
2303 spec->channels = rf_vals_noseq;
2304 } else {
2305 spec->num_channels = 14;
2306 spec->channels = rf_vals_seq;
2307 }
2308
2309 if (rt2x00_rf(&rt2x00dev->chip, RF5225) ||
2310 rt2x00_rf(&rt2x00dev->chip, RF5325)) {
2311 spec->num_modes = 3;
2312 spec->num_channels = ARRAY_SIZE(rf_vals_seq);
2313
2314 txpower = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_A_START);
2315 for (i = 0; i < 14; i++)
2316 txpower[i] = TXPOWER_FROM_DEV(txpower[i]);
2317
2318 spec->tx_power_a = txpower;
2319 }
2320 }
2321
2322 static int rt61pci_probe_hw(struct rt2x00_dev *rt2x00dev)
2323 {
2324 int retval;
2325
2326 /*
2327 * Allocate eeprom data.
2328 */
2329 retval = rt61pci_validate_eeprom(rt2x00dev);
2330 if (retval)
2331 return retval;
2332
2333 retval = rt61pci_init_eeprom(rt2x00dev);
2334 if (retval)
2335 return retval;
2336
2337 /*
2338 * Initialize hw specifications.
2339 */
2340 rt61pci_probe_hw_mode(rt2x00dev);
2341
2342 /*
2343 * This device requires firmware
2344 */
2345 __set_bit(DRIVER_REQUIRE_FIRMWARE, &rt2x00dev->flags);
2346
2347 /*
2348 * Set the rssi offset.
2349 */
2350 rt2x00dev->rssi_offset = DEFAULT_RSSI_OFFSET;
2351
2352 return 0;
2353 }
2354
2355 /*
2356 * IEEE80211 stack callback functions.
2357 */
2358 static void rt61pci_configure_filter(struct ieee80211_hw *hw,
2359 unsigned int changed_flags,
2360 unsigned int *total_flags,
2361 int mc_count,
2362 struct dev_addr_list *mc_list)
2363 {
2364 struct rt2x00_dev *rt2x00dev = hw->priv;
2365 struct interface *intf = &rt2x00dev->interface;
2366 u32 reg;
2367
2368 /*
2369 * Mask off any flags we are going to ignore from
2370 * the total_flags field.
2371 */
2372 *total_flags &=
2373 FIF_ALLMULTI |
2374 FIF_FCSFAIL |
2375 FIF_PLCPFAIL |
2376 FIF_CONTROL |
2377 FIF_OTHER_BSS |
2378 FIF_PROMISC_IN_BSS;
2379
2380 /*
2381 * Apply some rules to the filters:
2382 * - Some filters imply different filters to be set.
2383 * - Some things we can't filter out at all.
2384 * - Some filters are set based on interface type.
2385 */
2386 if (mc_count)
2387 *total_flags |= FIF_ALLMULTI;
2388 if (*total_flags & FIF_OTHER_BSS ||
2389 *total_flags & FIF_PROMISC_IN_BSS)
2390 *total_flags |= FIF_PROMISC_IN_BSS | FIF_OTHER_BSS;
2391 if (is_interface_type(intf, IEEE80211_IF_TYPE_AP))
2392 *total_flags |= FIF_PROMISC_IN_BSS;
2393
2394 /*
2395 * Check if there is any work left for us.
2396 */
2397 if (intf->filter == *total_flags)
2398 return;
2399 intf->filter = *total_flags;
2400
2401 /*
2402 * Start configuration steps.
2403 * Note that the version error will always be dropped
2404 * and broadcast frames will always be accepted since
2405 * there is no filter for it at this time.
2406 */
2407 rt2x00pci_register_read(rt2x00dev, TXRX_CSR0, &reg);
2408 rt2x00_set_field32(&reg, TXRX_CSR0_DROP_CRC,
2409 !(*total_flags & FIF_FCSFAIL));
2410 rt2x00_set_field32(&reg, TXRX_CSR0_DROP_PHYSICAL,
2411 !(*total_flags & FIF_PLCPFAIL));
2412 rt2x00_set_field32(&reg, TXRX_CSR0_DROP_CONTROL,
2413 !(*total_flags & FIF_CONTROL));
2414 rt2x00_set_field32(&reg, TXRX_CSR0_DROP_NOT_TO_ME,
2415 !(*total_flags & FIF_PROMISC_IN_BSS));
2416 rt2x00_set_field32(&reg, TXRX_CSR0_DROP_TO_DS,
2417 !(*total_flags & FIF_PROMISC_IN_BSS));
2418 rt2x00_set_field32(&reg, TXRX_CSR0_DROP_VERSION_ERROR, 1);
2419 rt2x00_set_field32(&reg, TXRX_CSR0_DROP_MULTICAST,
2420 !(*total_flags & FIF_ALLMULTI));
2421 rt2x00_set_field32(&reg, TXRX_CSR0_DROP_BORADCAST, 0);
2422 rt2x00_set_field32(&reg, TXRX_CSR0_DROP_ACK_CTS, 1);
2423 rt2x00pci_register_write(rt2x00dev, TXRX_CSR0, reg);
2424 }
2425
2426 static int rt61pci_set_retry_limit(struct ieee80211_hw *hw,
2427 u32 short_retry, u32 long_retry)
2428 {
2429 struct rt2x00_dev *rt2x00dev = hw->priv;
2430 u32 reg;
2431
2432 rt2x00pci_register_read(rt2x00dev, TXRX_CSR4, &reg);
2433 rt2x00_set_field32(&reg, TXRX_CSR4_LONG_RETRY_LIMIT, long_retry);
2434 rt2x00_set_field32(&reg, TXRX_CSR4_SHORT_RETRY_LIMIT, short_retry);
2435 rt2x00pci_register_write(rt2x00dev, TXRX_CSR4, reg);
2436
2437 return 0;
2438 }
2439
2440 static u64 rt61pci_get_tsf(struct ieee80211_hw *hw)
2441 {
2442 struct rt2x00_dev *rt2x00dev = hw->priv;
2443 u64 tsf;
2444 u32 reg;
2445
2446 rt2x00pci_register_read(rt2x00dev, TXRX_CSR13, &reg);
2447 tsf = (u64) rt2x00_get_field32(reg, TXRX_CSR13_HIGH_TSFTIMER) << 32;
2448 rt2x00pci_register_read(rt2x00dev, TXRX_CSR12, &reg);
2449 tsf |= rt2x00_get_field32(reg, TXRX_CSR12_LOW_TSFTIMER);
2450
2451 return tsf;
2452 }
2453
2454 static void rt61pci_reset_tsf(struct ieee80211_hw *hw)
2455 {
2456 struct rt2x00_dev *rt2x00dev = hw->priv;
2457
2458 rt2x00pci_register_write(rt2x00dev, TXRX_CSR12, 0);
2459 rt2x00pci_register_write(rt2x00dev, TXRX_CSR13, 0);
2460 }
2461
2462 static int rt61pci_beacon_update(struct ieee80211_hw *hw, struct sk_buff *skb,
2463 struct ieee80211_tx_control *control)
2464 {
2465 struct rt2x00_dev *rt2x00dev = hw->priv;
2466
2467 /*
2468 * Just in case the ieee80211 doesn't set this,
2469 * but we need this queue set for the descriptor
2470 * initialization.
2471 */
2472 control->queue = IEEE80211_TX_QUEUE_BEACON;
2473
2474 /*
2475 * We need to append the descriptor in front of the
2476 * beacon frame.
2477 */
2478 if (skb_headroom(skb) < TXD_DESC_SIZE) {
2479 if (pskb_expand_head(skb, TXD_DESC_SIZE, 0, GFP_ATOMIC)) {
2480 dev_kfree_skb(skb);
2481 return -ENOMEM;
2482 }
2483 }
2484
2485 /*
2486 * First we create the beacon.
2487 */
2488 skb_push(skb, TXD_DESC_SIZE);
2489 rt2x00lib_write_tx_desc(rt2x00dev, (struct data_desc *)skb->data,
2490 (struct ieee80211_hdr *)(skb->data +
2491 TXD_DESC_SIZE),
2492 skb->len - TXD_DESC_SIZE, control);
2493
2494 /*
2495 * Write entire beacon with descriptor to register,
2496 * and kick the beacon generator.
2497 */
2498 rt2x00pci_register_multiwrite(rt2x00dev, HW_BEACON_BASE0,
2499 skb->data, skb->len);
2500 rt61pci_kick_tx_queue(rt2x00dev, IEEE80211_TX_QUEUE_BEACON);
2501
2502 return 0;
2503 }
2504
2505 static const struct ieee80211_ops rt61pci_mac80211_ops = {
2506 .tx = rt2x00mac_tx,
2507 .start = rt2x00mac_start,
2508 .stop = rt2x00mac_stop,
2509 .add_interface = rt2x00mac_add_interface,
2510 .remove_interface = rt2x00mac_remove_interface,
2511 .config = rt2x00mac_config,
2512 .config_interface = rt2x00mac_config_interface,
2513 .configure_filter = rt61pci_configure_filter,
2514 .get_stats = rt2x00mac_get_stats,
2515 .set_retry_limit = rt61pci_set_retry_limit,
2516 .conf_tx = rt2x00mac_conf_tx,
2517 .get_tx_stats = rt2x00mac_get_tx_stats,
2518 .get_tsf = rt61pci_get_tsf,
2519 .reset_tsf = rt61pci_reset_tsf,
2520 .beacon_update = rt61pci_beacon_update,
2521 };
2522
2523 static const struct rt2x00lib_ops rt61pci_rt2x00_ops = {
2524 .irq_handler = rt61pci_interrupt,
2525 .probe_hw = rt61pci_probe_hw,
2526 .get_firmware_name = rt61pci_get_firmware_name,
2527 .load_firmware = rt61pci_load_firmware,
2528 .initialize = rt2x00pci_initialize,
2529 .uninitialize = rt2x00pci_uninitialize,
2530 .set_device_state = rt61pci_set_device_state,
2531 .rfkill_poll = rt61pci_rfkill_poll,
2532 .link_stats = rt61pci_link_stats,
2533 .reset_tuner = rt61pci_reset_tuner,
2534 .link_tuner = rt61pci_link_tuner,
2535 .write_tx_desc = rt61pci_write_tx_desc,
2536 .write_tx_data = rt2x00pci_write_tx_data,
2537 .kick_tx_queue = rt61pci_kick_tx_queue,
2538 .fill_rxdone = rt61pci_fill_rxdone,
2539 .config_mac_addr = rt61pci_config_mac_addr,
2540 .config_bssid = rt61pci_config_bssid,
2541 .config_type = rt61pci_config_type,
2542 .config = rt61pci_config,
2543 };
2544
2545 static const struct rt2x00_ops rt61pci_ops = {
2546 .name = DRV_NAME,
2547 .rxd_size = RXD_DESC_SIZE,
2548 .txd_size = TXD_DESC_SIZE,
2549 .eeprom_size = EEPROM_SIZE,
2550 .rf_size = RF_SIZE,
2551 .lib = &rt61pci_rt2x00_ops,
2552 .hw = &rt61pci_mac80211_ops,
2553 #ifdef CONFIG_RT2X00_LIB_DEBUGFS
2554 .debugfs = &rt61pci_rt2x00debug,
2555 #endif /* CONFIG_RT2X00_LIB_DEBUGFS */
2556 };
2557
2558 /*
2559 * RT61pci module information.
2560 */
2561 static struct pci_device_id rt61pci_device_table[] = {
2562 /* RT2561s */
2563 { PCI_DEVICE(0x1814, 0x0301), PCI_DEVICE_DATA(&rt61pci_ops) },
2564 /* RT2561 v2 */
2565 { PCI_DEVICE(0x1814, 0x0302), PCI_DEVICE_DATA(&rt61pci_ops) },
2566 /* RT2661 */
2567 { PCI_DEVICE(0x1814, 0x0401), PCI_DEVICE_DATA(&rt61pci_ops) },
2568 { 0, }
2569 };
2570
2571 MODULE_AUTHOR(DRV_PROJECT);
2572 MODULE_VERSION(DRV_VERSION);
2573 MODULE_DESCRIPTION("Ralink RT61 PCI & PCMCIA Wireless LAN driver.");
2574 MODULE_SUPPORTED_DEVICE("Ralink RT2561, RT2561s & RT2661 "
2575 "PCI & PCMCIA chipset based cards");
2576 MODULE_DEVICE_TABLE(pci, rt61pci_device_table);
2577 MODULE_FIRMWARE(FIRMWARE_RT2561);
2578 MODULE_FIRMWARE(FIRMWARE_RT2561s);
2579 MODULE_FIRMWARE(FIRMWARE_RT2661);
2580 MODULE_LICENSE("GPL");
2581
2582 static struct pci_driver rt61pci_driver = {
2583 .name = DRV_NAME,
2584 .id_table = rt61pci_device_table,
2585 .probe = rt2x00pci_probe,
2586 .remove = __devexit_p(rt2x00pci_remove),
2587 .suspend = rt2x00pci_suspend,
2588 .resume = rt2x00pci_resume,
2589 };
2590
2591 static int __init rt61pci_init(void)
2592 {
2593 return pci_register_driver(&rt61pci_driver);
2594 }
2595
2596 static void __exit rt61pci_exit(void)
2597 {
2598 pci_unregister_driver(&rt61pci_driver);
2599 }
2600
2601 module_init(rt61pci_init);
2602 module_exit(rt61pci_exit);
Linus' kernel tree