arch/arm/mach-at91/pm.h

   1 /*
   2  * AT91 Power Management
   3  *
   4  * Copyright (C) 2005 David Brownell
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation; either version 2 of the License, or
   9  * (at your option) any later version.
  10  */
  11 #ifndef __ARCH_ARM_MACH_AT91_PM
  12 #define __ARCH_ARM_MACH_AT91_PM
  13
  14 #include <mach/at91_ramc.h>
  15 #include <mach/at91rm9200_sdramc.h>
  16
  17 /*
  18  * The AT91RM9200 goes into self-refresh mode with this command, and will
  19  * terminate self-refresh automatically on the next SDRAM access.
  20  *
  21  * Self-refresh mode is exited as soon as a memory access is made, but we don't
  22  * know for sure when that happens. However, we need to restore the low-power
  23  * mode if it was enabled before going idle. Restoring low-power mode while
  24  * still in self-refresh is "not recommended", but seems to work.
  25  */
  26
  27 static inline void at91rm9200_standby(void)
  28 {
  29         u32 lpr = at91_ramc_read(0, AT91RM9200_SDRAMC_LPR);
  30
  31         asm volatile(
  32                 "b    1f\n\t"
  33                 ".align    5\n\t"
  34                 "1:  mcr    p15, 0, %0, c7, c10, 4\n\t"
  35                 "    str    %0, [%1, %2]\n\t"
  36                 "    str    %3, [%1, %4]\n\t"
  37                 "    mcr    p15, 0, %0, c7, c0, 4\n\t"
  38                 "    str    %5, [%1, %2]"
  39                 :
  40                 : "r" (0), "r" (AT91_BASE_SYS), "r" (AT91RM9200_SDRAMC_LPR),
  41                   "r" (1), "r" (AT91RM9200_SDRAMC_SRR),
  42                   "r" (lpr));
  43 }
  44
  45 /* We manage both DDRAM/SDRAM controllers, we need more than one value to
  46  * remember.
  47  */
  48 static inline void at91sam9g45_standby(void)
  49 {
  50         /* Those two values allow us to delay self-refresh activation
  51          * to the maximum. */
  52         u32 lpr0, lpr1;
  53         u32 saved_lpr0, saved_lpr1;
  54
  55         saved_lpr1 = at91_ramc_read(1, AT91_DDRSDRC_LPR);
  56         lpr1 = saved_lpr1 & ~AT91_DDRSDRC_LPCB;
  57         lpr1 |= AT91_DDRSDRC_LPCB_SELF_REFRESH;
  58
  59         saved_lpr0 = at91_ramc_read(0, AT91_DDRSDRC_LPR);
  60         lpr0 = saved_lpr0 & ~AT91_DDRSDRC_LPCB;
  61         lpr0 |= AT91_DDRSDRC_LPCB_SELF_REFRESH;
  62
  63         /* self-refresh mode now */
  64         at91_ramc_write(0, AT91_DDRSDRC_LPR, lpr0);
  65         at91_ramc_write(1, AT91_DDRSDRC_LPR, lpr1);
  66
  67         cpu_do_idle();
  68
  69         at91_ramc_write(0, AT91_DDRSDRC_LPR, saved_lpr0);
  70         at91_ramc_write(1, AT91_DDRSDRC_LPR, saved_lpr1);
  71 }
  72
  73 /* We manage both DDRAM/SDRAM controllers, we need more than one value to
  74  * remember.
  75  */
  76 static inline void at91sam9263_standby(void)
  77 {
  78         u32 lpr0, lpr1;
  79         u32 saved_lpr0, saved_lpr1;
  80
  81         saved_lpr1 = at91_ramc_read(1, AT91_SDRAMC_LPR);
  82         lpr1 = saved_lpr1 & ~AT91_SDRAMC_LPCB;
  83         lpr1 |= AT91_SDRAMC_LPCB_SELF_REFRESH;
  84
  85         saved_lpr0 = at91_ramc_read(0, AT91_SDRAMC_LPR);
  86         lpr0 = saved_lpr0 & ~AT91_SDRAMC_LPCB;
  87         lpr0 |= AT91_SDRAMC_LPCB_SELF_REFRESH;
  88
  89         /* self-refresh mode now */
  90         at91_ramc_write(0, AT91_SDRAMC_LPR, lpr0);
  91         at91_ramc_write(1, AT91_SDRAMC_LPR, lpr1);
  92
  93         cpu_do_idle();
  94
  95         at91_ramc_write(0, AT91_SDRAMC_LPR, saved_lpr0);
  96         at91_ramc_write(1, AT91_SDRAMC_LPR, saved_lpr1);
  97 }
  98
  99 static inline void at91sam9_standby(void)
 100 {
 101         u32 saved_lpr, lpr;
 102
 103         saved_lpr = at91_ramc_read(0, AT91_SDRAMC_LPR);
 104
 105         lpr = saved_lpr & ~AT91_SDRAMC_LPCB;
 106         at91_ramc_write(0, AT91_SDRAMC_LPR, lpr |
 107                         AT91_SDRAMC_LPCB_SELF_REFRESH);
 108
 109         cpu_do_idle();
 110
 111         at91_ramc_write(0, AT91_SDRAMC_LPR, saved_lpr);
 112 }
 113
 114 #endif