drivers/pci/hotplug/pciehp_hpc.c

   1 /*
   2  * PCI Express PCI Hot Plug Driver
   3  *
   4  * Copyright (C) 1995,2001 Compaq Computer Corporation
   5  * Copyright (C) 2001 Greg Kroah-Hartman (greg@kroah.com)
   6  * Copyright (C) 2001 IBM Corp.
   7  * Copyright (C) 2003-2004 Intel Corporation
   8  *
   9  * All rights reserved.
  10  *
  11  * This program is free software; you can redistribute it and/or modify
  12  * it under the terms of the GNU General Public License as published by
  13  * the Free Software Foundation; either version 2 of the License, or (at
  14  * your option) any later version.
  15  *
  16  * This program is distributed in the hope that it will be useful, but
  17  * WITHOUT ANY WARRANTY; without even the implied warranty of
  18  * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
  19  * NON INFRINGEMENT.  See the GNU General Public License for more
  20  * details.
  21  *
  22  * You should have received a copy of the GNU General Public License
  23  * along with this program; if not, write to the Free Software
  24  * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  25  *
  26  * Send feedback to <greg@kroah.com>,<kristen.c.accardi@intel.com>
  27  *
  28  */
  29
  30 #include <linux/kernel.h>
  31 #include <linux/module.h>
  32 #include <linux/types.h>
  33 #include <linux/signal.h>
  34 #include <linux/jiffies.h>
  35 #include <linux/timer.h>
  36 #include <linux/pci.h>
  37 #include <linux/interrupt.h>
  38 #include <linux/time.h>
  39 #include <linux/slab.h>
  40
  41 #include "../pci.h"
  42 #include "pciehp.h"
  43
  44 static inline int pciehp_readw(struct controller *ctrl, int reg, u16 *value)
  45 {
  46         struct pci_dev *dev = ctrl->pcie->port;
  47         return pci_read_config_word(dev, pci_pcie_cap(dev) + reg, value);
  48 }
  49
  50 static inline int pciehp_readl(struct controller *ctrl, int reg, u32 *value)
  51 {
  52         struct pci_dev *dev = ctrl->pcie->port;
  53         return pci_read_config_dword(dev, pci_pcie_cap(dev) + reg, value);
  54 }
  55
  56 static inline int pciehp_writew(struct controller *ctrl, int reg, u16 value)
  57 {
  58         struct pci_dev *dev = ctrl->pcie->port;
  59         return pci_write_config_word(dev, pci_pcie_cap(dev) + reg, value);
  60 }
  61
  62 static inline int pciehp_writel(struct controller *ctrl, int reg, u32 value)
  63 {
  64         struct pci_dev *dev = ctrl->pcie->port;
  65         return pci_write_config_dword(dev, pci_pcie_cap(dev) + reg, value);
  66 }
  67
  68 /* Power Control Command */
  69 #define POWER_ON        0
  70 #define POWER_OFF       PCI_EXP_SLTCTL_PCC
  71
  72 static irqreturn_t pcie_isr(int irq, void *dev_id);
  73 static void start_int_poll_timer(struct controller *ctrl, int sec);
  74
  75 /* This is the interrupt polling timeout function. */
  76 static void int_poll_timeout(unsigned long data)
  77 {
  78         struct controller *ctrl = (struct controller *)data;
  79
  80         /* Poll for interrupt events.  regs == NULL => polling */
  81         pcie_isr(0, ctrl);
  82
  83         init_timer(&ctrl->poll_timer);
  84         if (!pciehp_poll_time)
  85                 pciehp_poll_time = 2; /* default polling interval is 2 sec */
  86
  87         start_int_poll_timer(ctrl, pciehp_poll_time);
  88 }
  89
  90 /* This function starts the interrupt polling timer. */
  91 static void start_int_poll_timer(struct controller *ctrl, int sec)
  92 {
  93         /* Clamp to sane value */
  94         if ((sec <= 0) || (sec > 60))
  95                 sec = 2;
  96
  97         ctrl->poll_timer.function = &int_poll_timeout;
  98         ctrl->poll_timer.data = (unsigned long)ctrl;
  99         ctrl->poll_timer.expires = jiffies + sec * HZ;
 100         add_timer(&ctrl->poll_timer);
 101 }
 102
 103 static inline int pciehp_request_irq(struct controller *ctrl)
 104 {
 105         int retval, irq = ctrl->pcie->irq;
 106
 107         /* Install interrupt polling timer. Start with 10 sec delay */
 108         if (pciehp_poll_mode) {
 109                 init_timer(&ctrl->poll_timer);
 110                 start_int_poll_timer(ctrl, 10);
 111                 return 0;
 112         }
 113
 114         /* Installs the interrupt handler */
 115         retval = request_irq(irq, pcie_isr, IRQF_SHARED, MY_NAME, ctrl);
 116         if (retval)
 117                 ctrl_err(ctrl, "Cannot get irq %d for the hotplug controller\n",
 118                          irq);
 119         return retval;
 120 }
 121
 122 static inline void pciehp_free_irq(struct controller *ctrl)
 123 {
 124         if (pciehp_poll_mode)
 125                 del_timer_sync(&ctrl->poll_timer);
 126         else
 127                 free_irq(ctrl->pcie->irq, ctrl);
 128 }
 129
 130 static int pcie_poll_cmd(struct controller *ctrl)
 131 {
 132         u16 slot_status;
 133         int err, timeout = 1000;
 134
 135         err = pciehp_readw(ctrl, PCI_EXP_SLTSTA, &slot_status);
 136         if (!err && (slot_status & PCI_EXP_SLTSTA_CC)) {
 137                 pciehp_writew(ctrl, PCI_EXP_SLTSTA, PCI_EXP_SLTSTA_CC);
 138                 return 1;
 139         }
 140         while (timeout > 0) {
 141                 msleep(10);
 142                 timeout -= 10;
 143                 err = pciehp_readw(ctrl, PCI_EXP_SLTSTA, &slot_status);
 144                 if (!err && (slot_status & PCI_EXP_SLTSTA_CC)) {
 145                         pciehp_writew(ctrl, PCI_EXP_SLTSTA, PCI_EXP_SLTSTA_CC);
 146                         return 1;
 147                 }
 148         }
 149         return 0;       /* timeout */
 150 }
 151
 152 static void pcie_wait_cmd(struct controller *ctrl, int poll)
 153 {
 154         unsigned int msecs = pciehp_poll_mode ? 2500 : 1000;
 155         unsigned long timeout = msecs_to_jiffies(msecs);
 156         int rc;
 157
 158         if (poll)
 159                 rc = pcie_poll_cmd(ctrl);
 160         else
 161                 rc = wait_event_timeout(ctrl->queue, !ctrl->cmd_busy, timeout);
 162         if (!rc)
 163                 ctrl_dbg(ctrl, "Command not completed in 1000 msec\n");
 164 }
 165
 166 /**
 167  * pcie_write_cmd - Issue controller command
 168  * @ctrl: controller to which the command is issued
 169  * @cmd:  command value written to slot control register
 170  * @mask: bitmask of slot control register to be modified
 171  */
 172 static int pcie_write_cmd(struct controller *ctrl, u16 cmd, u16 mask)
 173 {
 174         int retval = 0;
 175         u16 slot_status;
 176         u16 slot_ctrl;
 177
 178         mutex_lock(&ctrl->ctrl_lock);
 179
 180         retval = pciehp_readw(ctrl, PCI_EXP_SLTSTA, &slot_status);
 181         if (retval) {
 182                 ctrl_err(ctrl, "%s: Cannot read SLOTSTATUS register\n",
 183                          __func__);
 184                 goto out;
 185         }
 186
 187         if (slot_status & PCI_EXP_SLTSTA_CC) {
 188                 if (!ctrl->no_cmd_complete) {
 189                         /*
 190                          * After 1 sec and CMD_COMPLETED still not set, just
 191                          * proceed forward to issue the next command according
 192                          * to spec. Just print out the error message.
 193                          */
 194                         ctrl_dbg(ctrl, "CMD_COMPLETED not clear after 1 sec\n");
 195                 } else if (!NO_CMD_CMPL(ctrl)) {
 196                         /*
 197                          * This controller semms to notify of command completed
 198                          * event even though it supports none of power
 199                          * controller, attention led, power led and EMI.
 200                          */
 201                         ctrl_dbg(ctrl, "Unexpected CMD_COMPLETED. Need to "
 202                                  "wait for command completed event.\n");
 203                         ctrl->no_cmd_complete = 0;
 204                 } else {
 205                         ctrl_dbg(ctrl, "Unexpected CMD_COMPLETED. Maybe "
 206                                  "the controller is broken.\n");
 207                 }
 208         }
 209
 210         retval = pciehp_readw(ctrl, PCI_EXP_SLTCTL, &slot_ctrl);
 211         if (retval) {
 212                 ctrl_err(ctrl, "%s: Cannot read SLOTCTRL register\n", __func__);
 213                 goto out;
 214         }
 215
 216         slot_ctrl &= ~mask;
 217         slot_ctrl |= (cmd & mask);
 218         ctrl->cmd_busy = 1;
 219         smp_mb();
 220         retval = pciehp_writew(ctrl, PCI_EXP_SLTCTL, slot_ctrl);
 221         if (retval)
 222                 ctrl_err(ctrl, "Cannot write to SLOTCTRL register\n");
 223
 224         /*
 225          * Wait for command completion.
 226          */
 227         if (!retval && !ctrl->no_cmd_complete) {
 228                 int poll = 0;
 229                 /*
 230                  * if hotplug interrupt is not enabled or command
 231                  * completed interrupt is not enabled, we need to poll
 232                  * command completed event.
 233                  */
 234                 if (!(slot_ctrl & PCI_EXP_SLTCTL_HPIE) ||
 235                     !(slot_ctrl & PCI_EXP_SLTCTL_CCIE))
 236                         poll = 1;
 237                 pcie_wait_cmd(ctrl, poll);
 238         }
 239  out:
 240         mutex_unlock(&ctrl->ctrl_lock);
 241         return retval;
 242 }
 243
 244 static bool check_link_active(struct controller *ctrl)
 245 {
 246         bool ret = false;
 247         u16 lnk_status;
 248
 249         if (pciehp_readw(ctrl, PCI_EXP_LNKSTA, &lnk_status))
 250                 return ret;
 251
 252         ret = !!(lnk_status & PCI_EXP_LNKSTA_DLLLA);
 253
 254         if (ret)
 255                 ctrl_dbg(ctrl, "%s: lnk_status = %x\n", __func__, lnk_status);
 256
 257         return ret;
 258 }
 259
 260 static void pcie_wait_link_active(struct controller *ctrl)
 261 {
 262         int timeout = 1000;
 263
 264         if (check_link_active(ctrl))
 265                 return;
 266         while (timeout > 0) {
 267                 msleep(10);
 268                 timeout -= 10;
 269                 if (check_link_active(ctrl))
 270                         return;
 271         }
 272         ctrl_dbg(ctrl, "Data Link Layer Link Active not set in 1000 msec\n");
 273 }
 274
 275 static bool pci_bus_check_dev(struct pci_bus *bus, int devfn)
 276 {
 277         u32 l;
 278         int count = 0;
 279         int delay = 1000, step = 20;
 280         bool found = false;
 281
 282         do {
 283                 found = pci_bus_read_dev_vendor_id(bus, devfn, &l, 0);
 284                 count++;
 285
 286                 if (found)
 287                         break;
 288
 289                 msleep(step);
 290                 delay -= step;
 291         } while (delay > 0);
 292
 293         if (count > 1 && pciehp_debug)
 294                 printk(KERN_DEBUG "pci %04x:%02x:%02x.%d id reading try %d times with interval %d ms to get %08x\n",
 295                         pci_domain_nr(bus), bus->number, PCI_SLOT(devfn),
 296                         PCI_FUNC(devfn), count, step, l);
 297
 298         return found;
 299 }
 300
 301 int pciehp_check_link_status(struct controller *ctrl)
 302 {
 303         u16 lnk_status;
 304         int retval = 0;
 305         bool found = false;
 306
 307         /*
 308          * Data Link Layer Link Active Reporting must be capable for
 309          * hot-plug capable downstream port. But old controller might
 310          * not implement it. In this case, we wait for 1000 ms.
 311          */
 312         if (ctrl->link_active_reporting)
 313                 pcie_wait_link_active(ctrl);
 314         else
 315                 msleep(1000);
 316
 317         /* wait 100ms before read pci conf, and try in 1s */
 318         msleep(100);
 319         found = pci_bus_check_dev(ctrl->pcie->port->subordinate,
 320                                         PCI_DEVFN(0, 0));
 321
 322         retval = pciehp_readw(ctrl, PCI_EXP_LNKSTA, &lnk_status);
 323         if (retval) {
 324                 ctrl_err(ctrl, "Cannot read LNKSTATUS register\n");
 325                 return retval;
 326         }
 327
 328         ctrl_dbg(ctrl, "%s: lnk_status = %x\n", __func__, lnk_status);
 329         if ((lnk_status & PCI_EXP_LNKSTA_LT) ||
 330             !(lnk_status & PCI_EXP_LNKSTA_NLW)) {
 331                 ctrl_err(ctrl, "Link Training Error occurs \n");
 332                 retval = -1;
 333                 return retval;
 334         }
 335
 336         pcie_update_link_speed(ctrl->pcie->port->subordinate, lnk_status);
 337
 338         if (!found && !retval)
 339                 retval = -1;
 340
 341         return retval;
 342 }
 343
 344 int pciehp_get_attention_status(struct slot *slot, u8 *status)
 345 {
 346         struct controller *ctrl = slot->ctrl;
 347         u16 slot_ctrl;
 348         u8 atten_led_state;
 349         int retval = 0;
 350
 351         retval = pciehp_readw(ctrl, PCI_EXP_SLTCTL, &slot_ctrl);
 352         if (retval) {
 353                 ctrl_err(ctrl, "%s: Cannot read SLOTCTRL register\n", __func__);
 354                 return retval;
 355         }
 356
 357         ctrl_dbg(ctrl, "%s: SLOTCTRL %x, value read %x\n", __func__,
 358                  pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, slot_ctrl);
 359
 360         atten_led_state = (slot_ctrl & PCI_EXP_SLTCTL_AIC) >> 6;
 361
 362         switch (atten_led_state) {
 363         case 0:
 364                 *status = 0xFF; /* Reserved */
 365                 break;
 366         case 1:
 367                 *status = 1;    /* On */
 368                 break;
 369         case 2:
 370                 *status = 2;    /* Blink */
 371                 break;
 372         case 3:
 373                 *status = 0;    /* Off */
 374                 break;
 375         default:
 376                 *status = 0xFF;
 377                 break;
 378         }
 379
 380         return 0;
 381 }
 382
 383 int pciehp_get_power_status(struct slot *slot, u8 *status)
 384 {
 385         struct controller *ctrl = slot->ctrl;
 386         u16 slot_ctrl;
 387         u8 pwr_state;
 388         int     retval = 0;
 389
 390         retval = pciehp_readw(ctrl, PCI_EXP_SLTCTL, &slot_ctrl);
 391         if (retval) {
 392                 ctrl_err(ctrl, "%s: Cannot read SLOTCTRL register\n", __func__);
 393                 return retval;
 394         }
 395         ctrl_dbg(ctrl, "%s: SLOTCTRL %x value read %x\n", __func__,
 396                  pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, slot_ctrl);
 397
 398         pwr_state = (slot_ctrl & PCI_EXP_SLTCTL_PCC) >> 10;
 399
 400         switch (pwr_state) {
 401         case 0:
 402                 *status = 1;
 403                 break;
 404         case 1:
 405                 *status = 0;
 406                 break;
 407         default:
 408                 *status = 0xFF;
 409                 break;
 410         }
 411
 412         return retval;
 413 }
 414
 415 int pciehp_get_latch_status(struct slot *slot, u8 *status)
 416 {
 417         struct controller *ctrl = slot->ctrl;
 418         u16 slot_status;
 419         int retval;
 420
 421         retval = pciehp_readw(ctrl, PCI_EXP_SLTSTA, &slot_status);
 422         if (retval) {
 423                 ctrl_err(ctrl, "%s: Cannot read SLOTSTATUS register\n",
 424                          __func__);
 425                 return retval;
 426         }
 427         *status = !!(slot_status & PCI_EXP_SLTSTA_MRLSS);
 428         return 0;
 429 }
 430
 431 int pciehp_get_adapter_status(struct slot *slot, u8 *status)
 432 {
 433         struct controller *ctrl = slot->ctrl;
 434         u16 slot_status;
 435         int retval;
 436
 437         retval = pciehp_readw(ctrl, PCI_EXP_SLTSTA, &slot_status);
 438         if (retval) {
 439                 ctrl_err(ctrl, "%s: Cannot read SLOTSTATUS register\n",
 440                          __func__);
 441                 return retval;
 442         }
 443         *status = !!(slot_status & PCI_EXP_SLTSTA_PDS);
 444         return 0;
 445 }
 446
 447 int pciehp_query_power_fault(struct slot *slot)
 448 {
 449         struct controller *ctrl = slot->ctrl;
 450         u16 slot_status;
 451         int retval;
 452
 453         retval = pciehp_readw(ctrl, PCI_EXP_SLTSTA, &slot_status);
 454         if (retval) {
 455                 ctrl_err(ctrl, "Cannot check for power fault\n");
 456                 return retval;
 457         }
 458         return !!(slot_status & PCI_EXP_SLTSTA_PFD);
 459 }
 460
 461 int pciehp_set_attention_status(struct slot *slot, u8 value)
 462 {
 463         struct controller *ctrl = slot->ctrl;
 464         u16 slot_cmd;
 465         u16 cmd_mask;
 466
 467         cmd_mask = PCI_EXP_SLTCTL_AIC;
 468         switch (value) {
 469         case 0 :        /* turn off */
 470                 slot_cmd = 0x00C0;
 471                 break;
 472         case 1:         /* turn on */
 473                 slot_cmd = 0x0040;
 474                 break;
 475         case 2:         /* turn blink */
 476                 slot_cmd = 0x0080;
 477                 break;
 478         default:
 479                 return -EINVAL;
 480         }
 481         ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__,
 482                  pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, slot_cmd);
 483         return pcie_write_cmd(ctrl, slot_cmd, cmd_mask);
 484 }
 485
 486 void pciehp_green_led_on(struct slot *slot)
 487 {
 488         struct controller *ctrl = slot->ctrl;
 489         u16 slot_cmd;
 490         u16 cmd_mask;
 491
 492         slot_cmd = 0x0100;
 493         cmd_mask = PCI_EXP_SLTCTL_PIC;
 494         pcie_write_cmd(ctrl, slot_cmd, cmd_mask);
 495         ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__,
 496                  pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, slot_cmd);
 497 }
 498
 499 void pciehp_green_led_off(struct slot *slot)
 500 {
 501         struct controller *ctrl = slot->ctrl;
 502         u16 slot_cmd;
 503         u16 cmd_mask;
 504
 505         slot_cmd = 0x0300;
 506         cmd_mask = PCI_EXP_SLTCTL_PIC;
 507         pcie_write_cmd(ctrl, slot_cmd, cmd_mask);
 508         ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__,
 509                  pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, slot_cmd);
 510 }
 511
 512 void pciehp_green_led_blink(struct slot *slot)
 513 {
 514         struct controller *ctrl = slot->ctrl;
 515         u16 slot_cmd;
 516         u16 cmd_mask;
 517
 518         slot_cmd = 0x0200;
 519         cmd_mask = PCI_EXP_SLTCTL_PIC;
 520         pcie_write_cmd(ctrl, slot_cmd, cmd_mask);
 521         ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__,
 522                  pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, slot_cmd);
 523 }
 524
 525 int pciehp_power_on_slot(struct slot * slot)
 526 {
 527         struct controller *ctrl = slot->ctrl;
 528         u16 slot_cmd;
 529         u16 cmd_mask;
 530         u16 slot_status;
 531         int retval = 0;
 532
 533         /* Clear sticky power-fault bit from previous power failures */
 534         retval = pciehp_readw(ctrl, PCI_EXP_SLTSTA, &slot_status);
 535         if (retval) {
 536                 ctrl_err(ctrl, "%s: Cannot read SLOTSTATUS register\n",
 537                          __func__);
 538                 return retval;
 539         }
 540         slot_status &= PCI_EXP_SLTSTA_PFD;
 541         if (slot_status) {
 542                 retval = pciehp_writew(ctrl, PCI_EXP_SLTSTA, slot_status);
 543                 if (retval) {
 544                         ctrl_err(ctrl,
 545                                  "%s: Cannot write to SLOTSTATUS register\n",
 546                                  __func__);
 547                         return retval;
 548                 }
 549         }
 550         ctrl->power_fault_detected = 0;
 551
 552         slot_cmd = POWER_ON;
 553         cmd_mask = PCI_EXP_SLTCTL_PCC;
 554         retval = pcie_write_cmd(ctrl, slot_cmd, cmd_mask);
 555         if (retval) {
 556                 ctrl_err(ctrl, "Write %x command failed!\n", slot_cmd);
 557                 return retval;
 558         }
 559         ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__,
 560                  pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, slot_cmd);
 561
 562         return retval;
 563 }
 564
 565 int pciehp_power_off_slot(struct slot * slot)
 566 {
 567         struct controller *ctrl = slot->ctrl;
 568         u16 slot_cmd;
 569         u16 cmd_mask;
 570         int retval;
 571
 572         slot_cmd = POWER_OFF;
 573         cmd_mask = PCI_EXP_SLTCTL_PCC;
 574         retval = pcie_write_cmd(ctrl, slot_cmd, cmd_mask);
 575         if (retval) {
 576                 ctrl_err(ctrl, "Write command failed!\n");
 577                 return retval;
 578         }
 579         ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__,
 580                  pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, slot_cmd);
 581         return 0;
 582 }
 583
 584 static irqreturn_t pcie_isr(int irq, void *dev_id)
 585 {
 586         struct controller *ctrl = (struct controller *)dev_id;
 587         struct slot *slot = ctrl->slot;
 588         u16 detected, intr_loc;
 589
 590         /*
 591          * In order to guarantee that all interrupt events are
 592          * serviced, we need to re-inspect Slot Status register after
 593          * clearing what is presumed to be the last pending interrupt.
 594          */
 595         intr_loc = 0;
 596         do {
 597                 if (pciehp_readw(ctrl, PCI_EXP_SLTSTA, &detected)) {
 598                         ctrl_err(ctrl, "%s: Cannot read SLOTSTATUS\n",
 599                                  __func__);
 600                         return IRQ_NONE;
 601                 }
 602
 603                 detected &= (PCI_EXP_SLTSTA_ABP | PCI_EXP_SLTSTA_PFD |
 604                              PCI_EXP_SLTSTA_MRLSC | PCI_EXP_SLTSTA_PDC |
 605                              PCI_EXP_SLTSTA_CC);
 606                 detected &= ~intr_loc;
 607                 intr_loc |= detected;
 608                 if (!intr_loc)
 609                         return IRQ_NONE;
 610                 if (detected && pciehp_writew(ctrl, PCI_EXP_SLTSTA, intr_loc)) {
 611                         ctrl_err(ctrl, "%s: Cannot write to SLOTSTATUS\n",
 612                                  __func__);
 613                         return IRQ_NONE;
 614                 }
 615         } while (detected);
 616
 617         ctrl_dbg(ctrl, "%s: intr_loc %x\n", __func__, intr_loc);
 618
 619         /* Check Command Complete Interrupt Pending */
 620         if (intr_loc & PCI_EXP_SLTSTA_CC) {
 621                 ctrl->cmd_busy = 0;
 622                 smp_mb();
 623                 wake_up(&ctrl->queue);
 624         }
 625
 626         if (!(intr_loc & ~PCI_EXP_SLTSTA_CC))
 627                 return IRQ_HANDLED;
 628
 629         /* Check MRL Sensor Changed */
 630         if (intr_loc & PCI_EXP_SLTSTA_MRLSC)
 631                 pciehp_handle_switch_change(slot);
 632
 633         /* Check Attention Button Pressed */
 634         if (intr_loc & PCI_EXP_SLTSTA_ABP)
 635                 pciehp_handle_attention_button(slot);
 636
 637         /* Check Presence Detect Changed */
 638         if (intr_loc & PCI_EXP_SLTSTA_PDC)
 639                 pciehp_handle_presence_change(slot);
 640
 641         /* Check Power Fault Detected */
 642         if ((intr_loc & PCI_EXP_SLTSTA_PFD) && !ctrl->power_fault_detected) {
 643                 ctrl->power_fault_detected = 1;
 644                 pciehp_handle_power_fault(slot);
 645         }
 646         return IRQ_HANDLED;
 647 }
 648
 649 int pciehp_get_max_lnk_width(struct slot *slot,
 650                                  enum pcie_link_width *value)
 651 {
 652         struct controller *ctrl = slot->ctrl;
 653         enum pcie_link_width lnk_wdth;
 654         u32     lnk_cap;
 655         int retval = 0;
 656
 657         retval = pciehp_readl(ctrl, PCI_EXP_LNKCAP, &lnk_cap);
 658         if (retval) {
 659                 ctrl_err(ctrl, "%s: Cannot read LNKCAP register\n", __func__);
 660                 return retval;
 661         }
 662
 663         switch ((lnk_cap & PCI_EXP_LNKSTA_NLW) >> 4){
 664         case 0:
 665                 lnk_wdth = PCIE_LNK_WIDTH_RESRV;
 666                 break;
 667         case 1:
 668                 lnk_wdth = PCIE_LNK_X1;
 669                 break;
 670         case 2:
 671                 lnk_wdth = PCIE_LNK_X2;
 672                 break;
 673         case 4:
 674                 lnk_wdth = PCIE_LNK_X4;
 675                 break;
 676         case 8:
 677                 lnk_wdth = PCIE_LNK_X8;
 678                 break;
 679         case 12:
 680                 lnk_wdth = PCIE_LNK_X12;
 681                 break;
 682         case 16:
 683                 lnk_wdth = PCIE_LNK_X16;
 684                 break;
 685         case 32:
 686                 lnk_wdth = PCIE_LNK_X32;
 687                 break;
 688         default:
 689                 lnk_wdth = PCIE_LNK_WIDTH_UNKNOWN;
 690                 break;
 691         }
 692
 693         *value = lnk_wdth;
 694         ctrl_dbg(ctrl, "Max link width = %d\n", lnk_wdth);
 695
 696         return retval;
 697 }
 698
 699 int pciehp_get_cur_lnk_width(struct slot *slot,
 700                                  enum pcie_link_width *value)
 701 {
 702         struct controller *ctrl = slot->ctrl;
 703         enum pcie_link_width lnk_wdth = PCIE_LNK_WIDTH_UNKNOWN;
 704         int retval = 0;
 705         u16 lnk_status;
 706
 707         retval = pciehp_readw(ctrl, PCI_EXP_LNKSTA, &lnk_status);
 708         if (retval) {
 709                 ctrl_err(ctrl, "%s: Cannot read LNKSTATUS register\n",
 710                          __func__);
 711                 return retval;
 712         }
 713
 714         switch ((lnk_status & PCI_EXP_LNKSTA_NLW) >> 4){
 715         case 0:
 716                 lnk_wdth = PCIE_LNK_WIDTH_RESRV;
 717                 break;
 718         case 1:
 719                 lnk_wdth = PCIE_LNK_X1;
 720                 break;
 721         case 2:
 722                 lnk_wdth = PCIE_LNK_X2;
 723                 break;
 724         case 4:
 725                 lnk_wdth = PCIE_LNK_X4;
 726                 break;
 727         case 8:
 728                 lnk_wdth = PCIE_LNK_X8;
 729                 break;
 730         case 12:
 731                 lnk_wdth = PCIE_LNK_X12;
 732                 break;
 733         case 16:
 734                 lnk_wdth = PCIE_LNK_X16;
 735                 break;
 736         case 32:
 737                 lnk_wdth = PCIE_LNK_X32;
 738                 break;
 739         default:
 740                 lnk_wdth = PCIE_LNK_WIDTH_UNKNOWN;
 741                 break;
 742         }
 743
 744         *value = lnk_wdth;
 745         ctrl_dbg(ctrl, "Current link width = %d\n", lnk_wdth);
 746
 747         return retval;
 748 }
 749
 750 int pcie_enable_notification(struct controller *ctrl)
 751 {
 752         u16 cmd, mask;
 753
 754         /*
 755          * TBD: Power fault detected software notification support.
 756          *
 757          * Power fault detected software notification is not enabled
 758          * now, because it caused power fault detected interrupt storm
 759          * on some machines. On those machines, power fault detected
 760          * bit in the slot status register was set again immediately
 761          * when it is cleared in the interrupt service routine, and
 762          * next power fault detected interrupt was notified again.
 763          */
 764         cmd = PCI_EXP_SLTCTL_PDCE;
 765         if (ATTN_BUTTN(ctrl))
 766                 cmd |= PCI_EXP_SLTCTL_ABPE;
 767         if (MRL_SENS(ctrl))
 768                 cmd |= PCI_EXP_SLTCTL_MRLSCE;
 769         if (!pciehp_poll_mode)
 770                 cmd |= PCI_EXP_SLTCTL_HPIE | PCI_EXP_SLTCTL_CCIE;
 771
 772         mask = (PCI_EXP_SLTCTL_PDCE | PCI_EXP_SLTCTL_ABPE |
 773                 PCI_EXP_SLTCTL_MRLSCE | PCI_EXP_SLTCTL_PFDE |
 774                 PCI_EXP_SLTCTL_HPIE | PCI_EXP_SLTCTL_CCIE);
 775
 776         if (pcie_write_cmd(ctrl, cmd, mask)) {
 777                 ctrl_err(ctrl, "Cannot enable software notification\n");
 778                 return -1;
 779         }
 780         return 0;
 781 }
 782
 783 static void pcie_disable_notification(struct controller *ctrl)
 784 {
 785         u16 mask;
 786         mask = (PCI_EXP_SLTCTL_PDCE | PCI_EXP_SLTCTL_ABPE |
 787                 PCI_EXP_SLTCTL_MRLSCE | PCI_EXP_SLTCTL_PFDE |
 788                 PCI_EXP_SLTCTL_HPIE | PCI_EXP_SLTCTL_CCIE |
 789                 PCI_EXP_SLTCTL_DLLSCE);
 790         if (pcie_write_cmd(ctrl, 0, mask))
 791                 ctrl_warn(ctrl, "Cannot disable software notification\n");
 792 }
 793
 794 int pcie_init_notification(struct controller *ctrl)
 795 {
 796         if (pciehp_request_irq(ctrl))
 797                 return -1;
 798         if (pcie_enable_notification(ctrl)) {
 799                 pciehp_free_irq(ctrl);
 800                 return -1;
 801         }
 802         ctrl->notification_enabled = 1;
 803         return 0;
 804 }
 805
 806 static void pcie_shutdown_notification(struct controller *ctrl)
 807 {
 808         if (ctrl->notification_enabled) {
 809                 pcie_disable_notification(ctrl);
 810                 pciehp_free_irq(ctrl);
 811                 ctrl->notification_enabled = 0;
 812         }
 813 }
 814
 815 static int pcie_init_slot(struct controller *ctrl)
 816 {
 817         struct slot *slot;
 818
 819         slot = kzalloc(sizeof(*slot), GFP_KERNEL);
 820         if (!slot)
 821                 return -ENOMEM;
 822
 823         slot->ctrl = ctrl;
 824         mutex_init(&slot->lock);
 825         INIT_DELAYED_WORK(&slot->work, pciehp_queue_pushbutton_work);
 826         ctrl->slot = slot;
 827         return 0;
 828 }
 829
 830 static void pcie_cleanup_slot(struct controller *ctrl)
 831 {
 832         struct slot *slot = ctrl->slot;
 833         cancel_delayed_work(&slot->work);
 834         flush_workqueue(pciehp_wq);
 835         kfree(slot);
 836 }
 837
 838 static inline void dbg_ctrl(struct controller *ctrl)
 839 {
 840         int i;
 841         u16 reg16;
 842         struct pci_dev *pdev = ctrl->pcie->port;
 843
 844         if (!pciehp_debug)
 845                 return;
 846
 847         ctrl_info(ctrl, "Hotplug Controller:\n");
 848         ctrl_info(ctrl, "  Seg/Bus/Dev/Func/IRQ : %s IRQ %d\n",
 849                   pci_name(pdev), pdev->irq);
 850         ctrl_info(ctrl, "  Vendor ID            : 0x%04x\n", pdev->vendor);
 851         ctrl_info(ctrl, "  Device ID            : 0x%04x\n", pdev->device);
 852         ctrl_info(ctrl, "  Subsystem ID         : 0x%04x\n",
 853                   pdev->subsystem_device);
 854         ctrl_info(ctrl, "  Subsystem Vendor ID  : 0x%04x\n",
 855                   pdev->subsystem_vendor);
 856         ctrl_info(ctrl, "  PCIe Cap offset      : 0x%02x\n",
 857                   pci_pcie_cap(pdev));
 858         for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
 859                 if (!pci_resource_len(pdev, i))
 860                         continue;
 861                 ctrl_info(ctrl, "  PCI resource [%d]     : %pR\n",
 862                           i, &pdev->resource[i]);
 863         }
 864         ctrl_info(ctrl, "Slot Capabilities      : 0x%08x\n", ctrl->slot_cap);
 865         ctrl_info(ctrl, "  Physical Slot Number : %d\n", PSN(ctrl));
 866         ctrl_info(ctrl, "  Attention Button     : %3s\n",
 867                   ATTN_BUTTN(ctrl) ? "yes" : "no");
 868         ctrl_info(ctrl, "  Power Controller     : %3s\n",
 869                   POWER_CTRL(ctrl) ? "yes" : "no");
 870         ctrl_info(ctrl, "  MRL Sensor           : %3s\n",
 871                   MRL_SENS(ctrl)   ? "yes" : "no");
 872         ctrl_info(ctrl, "  Attention Indicator  : %3s\n",
 873                   ATTN_LED(ctrl)   ? "yes" : "no");
 874         ctrl_info(ctrl, "  Power Indicator      : %3s\n",
 875                   PWR_LED(ctrl)    ? "yes" : "no");
 876         ctrl_info(ctrl, "  Hot-Plug Surprise    : %3s\n",
 877                   HP_SUPR_RM(ctrl) ? "yes" : "no");
 878         ctrl_info(ctrl, "  EMI Present          : %3s\n",
 879                   EMI(ctrl)        ? "yes" : "no");
 880         ctrl_info(ctrl, "  Command Completed    : %3s\n",
 881                   NO_CMD_CMPL(ctrl) ? "no" : "yes");
 882         pciehp_readw(ctrl, PCI_EXP_SLTSTA, &reg16);
 883         ctrl_info(ctrl, "Slot Status            : 0x%04x\n", reg16);
 884         pciehp_readw(ctrl, PCI_EXP_SLTCTL, &reg16);
 885         ctrl_info(ctrl, "Slot Control           : 0x%04x\n", reg16);
 886 }
 887
 888 struct controller *pcie_init(struct pcie_device *dev)
 889 {
 890         struct controller *ctrl;
 891         u32 slot_cap, link_cap;
 892         struct pci_dev *pdev = dev->port;
 893
 894         ctrl = kzalloc(sizeof(*ctrl), GFP_KERNEL);
 895         if (!ctrl) {
 896                 dev_err(&dev->device, "%s: Out of memory\n", __func__);
 897                 goto abort;
 898         }
 899         ctrl->pcie = dev;
 900         if (!pci_pcie_cap(pdev)) {
 901                 ctrl_err(ctrl, "Cannot find PCI Express capability\n");
 902                 goto abort_ctrl;
 903         }
 904         if (pciehp_readl(ctrl, PCI_EXP_SLTCAP, &slot_cap)) {
 905                 ctrl_err(ctrl, "Cannot read SLOTCAP register\n");
 906                 goto abort_ctrl;
 907         }
 908
 909         ctrl->slot_cap = slot_cap;
 910         mutex_init(&ctrl->ctrl_lock);
 911         init_waitqueue_head(&ctrl->queue);
 912         dbg_ctrl(ctrl);
 913         /*
 914          * Controller doesn't notify of command completion if the "No
 915          * Command Completed Support" bit is set in Slot Capability
 916          * register or the controller supports none of power
 917          * controller, attention led, power led and EMI.
 918          */
 919         if (NO_CMD_CMPL(ctrl) ||
 920             !(POWER_CTRL(ctrl) | ATTN_LED(ctrl) | PWR_LED(ctrl) | EMI(ctrl)))
 921             ctrl->no_cmd_complete = 1;
 922
 923         /* Check if Data Link Layer Link Active Reporting is implemented */
 924         if (pciehp_readl(ctrl, PCI_EXP_LNKCAP, &link_cap)) {
 925                 ctrl_err(ctrl, "%s: Cannot read LNKCAP register\n", __func__);
 926                 goto abort_ctrl;
 927         }
 928         if (link_cap & PCI_EXP_LNKCAP_DLLLARC) {
 929                 ctrl_dbg(ctrl, "Link Active Reporting supported\n");
 930                 ctrl->link_active_reporting = 1;
 931         }
 932
 933         /* Clear all remaining event bits in Slot Status register */
 934         if (pciehp_writew(ctrl, PCI_EXP_SLTSTA, 0x1f))
 935                 goto abort_ctrl;
 936
 937         /* Disable sotfware notification */
 938         pcie_disable_notification(ctrl);
 939
 940         ctrl_info(ctrl, "HPC vendor_id %x device_id %x ss_vid %x ss_did %x\n",
 941                   pdev->vendor, pdev->device, pdev->subsystem_vendor,
 942                   pdev->subsystem_device);
 943
 944         if (pcie_init_slot(ctrl))
 945                 goto abort_ctrl;
 946
 947         return ctrl;
 948
 949 abort_ctrl:
 950         kfree(ctrl);
 951 abort:
 952         return NULL;
 953 }
 954
 955 void pciehp_release_ctrl(struct controller *ctrl)
 956 {
 957         pcie_shutdown_notification(ctrl);
 958         pcie_cleanup_slot(ctrl);
 959         kfree(ctrl);
 960 }