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tracing: Change tracing_stats_fops to rely on tracing_get_cpu()
[linux-2.6.git] / drivers / video / s3fb.c
blob47ca86c5c6c0b3d1d609a001210e5eb132616076
1 /*
2 * linux/drivers/video/s3fb.c -- Frame buffer device driver for S3 Trio/Virge
3 *
4 * Copyright (c) 2006-2007 Ondrej Zajicek <santiago@crfreenet.org>
5 *
6 * This file is subject to the terms and conditions of the GNU General Public
7 * License. See the file COPYING in the main directory of this archive for
8 * more details.
9 *
10 * Code is based on David Boucher's viafb (http://davesdomain.org.uk/viafb/)
11 * which is based on the code of neofb.
12 */
13
14 #include <linux/module.h>
15 #include <linux/kernel.h>
16 #include <linux/errno.h>
17 #include <linux/string.h>
18 #include <linux/mm.h>
19 #include <linux/tty.h>
20 #include <linux/delay.h>
21 #include <linux/fb.h>
22 #include <linux/svga.h>
23 #include <linux/init.h>
24 #include <linux/pci.h>
25 #include <linux/console.h> /* Why should fb driver call console functions? because console_lock() */
26 #include <video/vga.h>
27
28 #include <linux/i2c.h>
29 #include <linux/i2c-algo-bit.h>
30
31 #ifdef CONFIG_MTRR
32 #include <asm/mtrr.h>
33 #endif
34
35 struct s3fb_info {
36 int chip, rev, mclk_freq;
37 int mtrr_reg;
38 struct vgastate state;
39 struct mutex open_lock;
40 unsigned int ref_count;
41 u32 pseudo_palette[16];
42 #ifdef CONFIG_FB_S3_DDC
43 u8 __iomem *mmio;
44 bool ddc_registered;
45 struct i2c_adapter ddc_adapter;
46 struct i2c_algo_bit_data ddc_algo;
47 #endif
48 };
49
50
51 /* ------------------------------------------------------------------------- */
52
53 static const struct svga_fb_format s3fb_formats[] = {
54 { 0, {0, 6, 0}, {0, 6, 0}, {0, 6, 0}, {0, 0, 0}, 0,
55 FB_TYPE_TEXT, FB_AUX_TEXT_SVGA_STEP4, FB_VISUAL_PSEUDOCOLOR, 8, 16},
56 { 4, {0, 4, 0}, {0, 4, 0}, {0, 4, 0}, {0, 0, 0}, 0,
57 FB_TYPE_PACKED_PIXELS, 0, FB_VISUAL_PSEUDOCOLOR, 8, 16},
58 { 4, {0, 4, 0}, {0, 4, 0}, {0, 4, 0}, {0, 0, 0}, 1,
59 FB_TYPE_INTERLEAVED_PLANES, 1, FB_VISUAL_PSEUDOCOLOR, 8, 16},
60 { 8, {0, 8, 0}, {0, 8, 0}, {0, 8, 0}, {0, 0, 0}, 0,
61 FB_TYPE_PACKED_PIXELS, 0, FB_VISUAL_PSEUDOCOLOR, 4, 8},
62 {16, {10, 5, 0}, {5, 5, 0}, {0, 5, 0}, {0, 0, 0}, 0,
63 FB_TYPE_PACKED_PIXELS, 0, FB_VISUAL_TRUECOLOR, 2, 4},
64 {16, {11, 5, 0}, {5, 6, 0}, {0, 5, 0}, {0, 0, 0}, 0,
65 FB_TYPE_PACKED_PIXELS, 0, FB_VISUAL_TRUECOLOR, 2, 4},
66 {24, {16, 8, 0}, {8, 8, 0}, {0, 8, 0}, {0, 0, 0}, 0,
67 FB_TYPE_PACKED_PIXELS, 0, FB_VISUAL_TRUECOLOR, 1, 2},
68 {32, {16, 8, 0}, {8, 8, 0}, {0, 8, 0}, {0, 0, 0}, 0,
69 FB_TYPE_PACKED_PIXELS, 0, FB_VISUAL_TRUECOLOR, 1, 2},
70 SVGA_FORMAT_END
71 };
72
73
74 static const struct svga_pll s3_pll = {3, 129, 3, 33, 0, 3,
75 35000, 240000, 14318};
76 static const struct svga_pll s3_trio3d_pll = {3, 129, 3, 31, 0, 4,
77 230000, 460000, 14318};
78
79 static const int s3_memsizes[] = {4096, 0, 3072, 8192, 2048, 6144, 1024, 512};
80
81 static const char * const s3_names[] = {"S3 Unknown", "S3 Trio32", "S3 Trio64", "S3 Trio64V+",
82 "S3 Trio64UV+", "S3 Trio64V2/DX", "S3 Trio64V2/GX",
83 "S3 Plato/PX", "S3 Aurora64V+", "S3 Virge",
84 "S3 Virge/VX", "S3 Virge/DX", "S3 Virge/GX",
85 "S3 Virge/GX2", "S3 Virge/GX2+", "",
86 "S3 Trio3D/1X", "S3 Trio3D/2X", "S3 Trio3D/2X",
87 "S3 Trio3D", "S3 Virge/MX"};
88
89 #define CHIP_UNKNOWN 0x00
90 #define CHIP_732_TRIO32 0x01
91 #define CHIP_764_TRIO64 0x02
92 #define CHIP_765_TRIO64VP 0x03
93 #define CHIP_767_TRIO64UVP 0x04
94 #define CHIP_775_TRIO64V2_DX 0x05
95 #define CHIP_785_TRIO64V2_GX 0x06
96 #define CHIP_551_PLATO_PX 0x07
97 #define CHIP_M65_AURORA64VP 0x08
98 #define CHIP_325_VIRGE 0x09
99 #define CHIP_988_VIRGE_VX 0x0A
100 #define CHIP_375_VIRGE_DX 0x0B
101 #define CHIP_385_VIRGE_GX 0x0C
102 #define CHIP_357_VIRGE_GX2 0x0D
103 #define CHIP_359_VIRGE_GX2P 0x0E
104 #define CHIP_360_TRIO3D_1X 0x10
105 #define CHIP_362_TRIO3D_2X 0x11
106 #define CHIP_368_TRIO3D_2X 0x12
107 #define CHIP_365_TRIO3D 0x13
108 #define CHIP_260_VIRGE_MX 0x14
109
110 #define CHIP_XXX_TRIO 0x80
111 #define CHIP_XXX_TRIO64V2_DXGX 0x81
112 #define CHIP_XXX_VIRGE_DXGX 0x82
113 #define CHIP_36X_TRIO3D_1X_2X 0x83
114
115 #define CHIP_UNDECIDED_FLAG 0x80
116 #define CHIP_MASK 0xFF
117
118 #define MMIO_OFFSET 0x1000000
119 #define MMIO_SIZE 0x10000
120
121 /* CRT timing register sets */
122
123 static const struct vga_regset s3_h_total_regs[] = {{0x00, 0, 7}, {0x5D, 0, 0}, VGA_REGSET_END};
124 static const struct vga_regset s3_h_display_regs[] = {{0x01, 0, 7}, {0x5D, 1, 1}, VGA_REGSET_END};
125 static const struct vga_regset s3_h_blank_start_regs[] = {{0x02, 0, 7}, {0x5D, 2, 2}, VGA_REGSET_END};
126 static const struct vga_regset s3_h_blank_end_regs[] = {{0x03, 0, 4}, {0x05, 7, 7}, VGA_REGSET_END};
127 static const struct vga_regset s3_h_sync_start_regs[] = {{0x04, 0, 7}, {0x5D, 4, 4}, VGA_REGSET_END};
128 static const struct vga_regset s3_h_sync_end_regs[] = {{0x05, 0, 4}, VGA_REGSET_END};
129
130 static const struct vga_regset s3_v_total_regs[] = {{0x06, 0, 7}, {0x07, 0, 0}, {0x07, 5, 5}, {0x5E, 0, 0}, VGA_REGSET_END};
131 static const struct vga_regset s3_v_display_regs[] = {{0x12, 0, 7}, {0x07, 1, 1}, {0x07, 6, 6}, {0x5E, 1, 1}, VGA_REGSET_END};
132 static const struct vga_regset s3_v_blank_start_regs[] = {{0x15, 0, 7}, {0x07, 3, 3}, {0x09, 5, 5}, {0x5E, 2, 2}, VGA_REGSET_END};
133 static const struct vga_regset s3_v_blank_end_regs[] = {{0x16, 0, 7}, VGA_REGSET_END};
134 static const struct vga_regset s3_v_sync_start_regs[] = {{0x10, 0, 7}, {0x07, 2, 2}, {0x07, 7, 7}, {0x5E, 4, 4}, VGA_REGSET_END};
135 static const struct vga_regset s3_v_sync_end_regs[] = {{0x11, 0, 3}, VGA_REGSET_END};
136
137 static const struct vga_regset s3_line_compare_regs[] = {{0x18, 0, 7}, {0x07, 4, 4}, {0x09, 6, 6}, {0x5E, 6, 6}, VGA_REGSET_END};
138 static const struct vga_regset s3_start_address_regs[] = {{0x0d, 0, 7}, {0x0c, 0, 7}, {0x69, 0, 4}, VGA_REGSET_END};
139 static const struct vga_regset s3_offset_regs[] = {{0x13, 0, 7}, {0x51, 4, 5}, VGA_REGSET_END}; /* set 0x43 bit 2 to 0 */
140
141 static const struct vga_regset s3_dtpc_regs[] = {{0x3B, 0, 7}, {0x5D, 6, 6}, VGA_REGSET_END};
142
143 static const struct svga_timing_regs s3_timing_regs = {
144 s3_h_total_regs, s3_h_display_regs, s3_h_blank_start_regs,
145 s3_h_blank_end_regs, s3_h_sync_start_regs, s3_h_sync_end_regs,
146 s3_v_total_regs, s3_v_display_regs, s3_v_blank_start_regs,
147 s3_v_blank_end_regs, s3_v_sync_start_regs, s3_v_sync_end_regs,
148 };
149
150
151 /* ------------------------------------------------------------------------- */
152
153 /* Module parameters */
154
155
156 static char *mode_option;
157
158 #ifdef CONFIG_MTRR
159 static int mtrr = 1;
160 #endif
161
162 static int fasttext = 1;
163
164
165 MODULE_AUTHOR("(c) 2006-2007 Ondrej Zajicek <santiago@crfreenet.org>");
166 MODULE_LICENSE("GPL");
167 MODULE_DESCRIPTION("fbdev driver for S3 Trio/Virge");
168
169 module_param(mode_option, charp, 0444);
170 MODULE_PARM_DESC(mode_option, "Default video mode ('640x480-8@60', etc)");
171 module_param_named(mode, mode_option, charp, 0444);
172 MODULE_PARM_DESC(mode, "Default video mode ('640x480-8@60', etc) (deprecated)");
173
174 #ifdef CONFIG_MTRR
175 module_param(mtrr, int, 0444);
176 MODULE_PARM_DESC(mtrr, "Enable write-combining with MTRR (1=enable, 0=disable, default=1)");
177 #endif
178
179 module_param(fasttext, int, 0644);
180 MODULE_PARM_DESC(fasttext, "Enable S3 fast text mode (1=enable, 0=disable, default=1)");
181
182
183 /* ------------------------------------------------------------------------- */
184
185 #ifdef CONFIG_FB_S3_DDC
186
187 #define DDC_REG 0xaa /* Trio 3D/1X/2X */
188 #define DDC_MMIO_REG 0xff20 /* all other chips */
189 #define DDC_SCL_OUT (1 << 0)
190 #define DDC_SDA_OUT (1 << 1)
191 #define DDC_SCL_IN (1 << 2)
192 #define DDC_SDA_IN (1 << 3)
193 #define DDC_DRIVE_EN (1 << 4)
194
195 static bool s3fb_ddc_needs_mmio(int chip)
196 {
197 return !(chip == CHIP_360_TRIO3D_1X ||
198 chip == CHIP_362_TRIO3D_2X ||
199 chip == CHIP_368_TRIO3D_2X);
200 }
201
202 static u8 s3fb_ddc_read(struct s3fb_info *par)
203 {
204 if (s3fb_ddc_needs_mmio(par->chip))
205 return readb(par->mmio + DDC_MMIO_REG);
206 else
207 return vga_rcrt(par->state.vgabase, DDC_REG);
208 }
209
210 static void s3fb_ddc_write(struct s3fb_info *par, u8 val)
211 {
212 if (s3fb_ddc_needs_mmio(par->chip))
213 writeb(val, par->mmio + DDC_MMIO_REG);
214 else
215 vga_wcrt(par->state.vgabase, DDC_REG, val);
216 }
217
218 static void s3fb_ddc_setscl(void *data, int val)
219 {
220 struct s3fb_info *par = data;
221 unsigned char reg;
222
223 reg = s3fb_ddc_read(par) | DDC_DRIVE_EN;
224 if (val)
225 reg |= DDC_SCL_OUT;
226 else
227 reg &= ~DDC_SCL_OUT;
228 s3fb_ddc_write(par, reg);
229 }
230
231 static void s3fb_ddc_setsda(void *data, int val)
232 {
233 struct s3fb_info *par = data;
234 unsigned char reg;
235
236 reg = s3fb_ddc_read(par) | DDC_DRIVE_EN;
237 if (val)
238 reg |= DDC_SDA_OUT;
239 else
240 reg &= ~DDC_SDA_OUT;
241 s3fb_ddc_write(par, reg);
242 }
243
244 static int s3fb_ddc_getscl(void *data)
245 {
246 struct s3fb_info *par = data;
247
248 return !!(s3fb_ddc_read(par) & DDC_SCL_IN);
249 }
250
251 static int s3fb_ddc_getsda(void *data)
252 {
253 struct s3fb_info *par = data;
254
255 return !!(s3fb_ddc_read(par) & DDC_SDA_IN);
256 }
257
258 static int s3fb_setup_ddc_bus(struct fb_info *info)
259 {
260 struct s3fb_info *par = info->par;
261
262 strlcpy(par->ddc_adapter.name, info->fix.id,
263 sizeof(par->ddc_adapter.name));
264 par->ddc_adapter.owner = THIS_MODULE;
265 par->ddc_adapter.class = I2C_CLASS_DDC;
266 par->ddc_adapter.algo_data = &par->ddc_algo;
267 par->ddc_adapter.dev.parent = info->device;
268 par->ddc_algo.setsda = s3fb_ddc_setsda;
269 par->ddc_algo.setscl = s3fb_ddc_setscl;
270 par->ddc_algo.getsda = s3fb_ddc_getsda;
271 par->ddc_algo.getscl = s3fb_ddc_getscl;
272 par->ddc_algo.udelay = 10;
273 par->ddc_algo.timeout = 20;
274 par->ddc_algo.data = par;
275
276 i2c_set_adapdata(&par->ddc_adapter, par);
277
278 /*
279 * some Virge cards have external MUX to switch chip I2C bus between
280 * DDC and extension pins - switch it do DDC
281 */
282 /* vga_wseq(par->state.vgabase, 0x08, 0x06); - not needed, already unlocked */
283 if (par->chip == CHIP_357_VIRGE_GX2 ||
284 par->chip == CHIP_359_VIRGE_GX2P ||
285 par->chip == CHIP_260_VIRGE_MX)
286 svga_wseq_mask(par->state.vgabase, 0x0d, 0x01, 0x03);
287 else
288 svga_wseq_mask(par->state.vgabase, 0x0d, 0x00, 0x03);
289 /* some Virge need this or the DDC is ignored */
290 svga_wcrt_mask(par->state.vgabase, 0x5c, 0x03, 0x03);
291
292 return i2c_bit_add_bus(&par->ddc_adapter);
293 }
294 #endif /* CONFIG_FB_S3_DDC */
295
296
297 /* ------------------------------------------------------------------------- */
298
299 /* Set font in S3 fast text mode */
300
301 static void s3fb_settile_fast(struct fb_info *info, struct fb_tilemap *map)
302 {
303 const u8 *font = map->data;
304 u8 __iomem *fb = (u8 __iomem *) info->screen_base;
305 int i, c;
306
307 if ((map->width != 8) || (map->height != 16) ||
308 (map->depth != 1) || (map->length != 256)) {
309 printk(KERN_ERR "fb%d: unsupported font parameters: width %d, height %d, depth %d, length %d\n",
310 info->node, map->width, map->height, map->depth, map->length);
311 return;
312 }
313
314 fb += 2;
315 for (i = 0; i < map->height; i++) {
316 for (c = 0; c < map->length; c++) {
317 fb_writeb(font[c * map->height + i], fb + c * 4);
318 }
319 fb += 1024;
320 }
321 }
322
323 static void s3fb_tilecursor(struct fb_info *info, struct fb_tilecursor *cursor)
324 {
325 struct s3fb_info *par = info->par;
326
327 svga_tilecursor(par->state.vgabase, info, cursor);
328 }
329
330 static struct fb_tile_ops s3fb_tile_ops = {
331 .fb_settile = svga_settile,
332 .fb_tilecopy = svga_tilecopy,
333 .fb_tilefill = svga_tilefill,
334 .fb_tileblit = svga_tileblit,
335 .fb_tilecursor = s3fb_tilecursor,
336 .fb_get_tilemax = svga_get_tilemax,
337 };
338
339 static struct fb_tile_ops s3fb_fast_tile_ops = {
340 .fb_settile = s3fb_settile_fast,
341 .fb_tilecopy = svga_tilecopy,
342 .fb_tilefill = svga_tilefill,
343 .fb_tileblit = svga_tileblit,
344 .fb_tilecursor = s3fb_tilecursor,
345 .fb_get_tilemax = svga_get_tilemax,
346 };
347
348
349 /* ------------------------------------------------------------------------- */
350
351 /* image data is MSB-first, fb structure is MSB-first too */
352 static inline u32 expand_color(u32 c)
353 {
354 return ((c & 1) | ((c & 2) << 7) | ((c & 4) << 14) | ((c & 8) << 21)) * 0xFF;
355 }
356
357 /* s3fb_iplan_imageblit silently assumes that almost everything is 8-pixel aligned */
358 static void s3fb_iplan_imageblit(struct fb_info *info, const struct fb_image *image)
359 {
360 u32 fg = expand_color(image->fg_color);
361 u32 bg = expand_color(image->bg_color);
362 const u8 *src1, *src;
363 u8 __iomem *dst1;
364 u32 __iomem *dst;
365 u32 val;
366 int x, y;
367
368 src1 = image->data;
369 dst1 = info->screen_base + (image->dy * info->fix.line_length)
370 + ((image->dx / 8) * 4);
371
372 for (y = 0; y < image->height; y++) {
373 src = src1;
374 dst = (u32 __iomem *) dst1;
375 for (x = 0; x < image->width; x += 8) {
376 val = *(src++) * 0x01010101;
377 val = (val & fg) | (~val & bg);
378 fb_writel(val, dst++);
379 }
380 src1 += image->width / 8;
381 dst1 += info->fix.line_length;
382 }
383
384 }
385
386 /* s3fb_iplan_fillrect silently assumes that almost everything is 8-pixel aligned */
387 static void s3fb_iplan_fillrect(struct fb_info *info, const struct fb_fillrect *rect)
388 {
389 u32 fg = expand_color(rect->color);
390 u8 __iomem *dst1;
391 u32 __iomem *dst;
392 int x, y;
393
394 dst1 = info->screen_base + (rect->dy * info->fix.line_length)
395 + ((rect->dx / 8) * 4);
396
397 for (y = 0; y < rect->height; y++) {
398 dst = (u32 __iomem *) dst1;
399 for (x = 0; x < rect->width; x += 8) {
400 fb_writel(fg, dst++);
401 }
402 dst1 += info->fix.line_length;
403 }
404 }
405
406
407 /* image data is MSB-first, fb structure is high-nibble-in-low-byte-first */
408 static inline u32 expand_pixel(u32 c)
409 {
410 return (((c & 1) << 24) | ((c & 2) << 27) | ((c & 4) << 14) | ((c & 8) << 17) |
411 ((c & 16) << 4) | ((c & 32) << 7) | ((c & 64) >> 6) | ((c & 128) >> 3)) * 0xF;
412 }
413
414 /* s3fb_cfb4_imageblit silently assumes that almost everything is 8-pixel aligned */
415 static void s3fb_cfb4_imageblit(struct fb_info *info, const struct fb_image *image)
416 {
417 u32 fg = image->fg_color * 0x11111111;
418 u32 bg = image->bg_color * 0x11111111;
419 const u8 *src1, *src;
420 u8 __iomem *dst1;
421 u32 __iomem *dst;
422 u32 val;
423 int x, y;
424
425 src1 = image->data;
426 dst1 = info->screen_base + (image->dy * info->fix.line_length)
427 + ((image->dx / 8) * 4);
428
429 for (y = 0; y < image->height; y++) {
430 src = src1;
431 dst = (u32 __iomem *) dst1;
432 for (x = 0; x < image->width; x += 8) {
433 val = expand_pixel(*(src++));
434 val = (val & fg) | (~val & bg);
435 fb_writel(val, dst++);
436 }
437 src1 += image->width / 8;
438 dst1 += info->fix.line_length;
439 }
440 }
441
442 static void s3fb_imageblit(struct fb_info *info, const struct fb_image *image)
443 {
444 if ((info->var.bits_per_pixel == 4) && (image->depth == 1)
445 && ((image->width % 8) == 0) && ((image->dx % 8) == 0)) {
446 if (info->fix.type == FB_TYPE_INTERLEAVED_PLANES)
447 s3fb_iplan_imageblit(info, image);
448 else
449 s3fb_cfb4_imageblit(info, image);
450 } else
451 cfb_imageblit(info, image);
452 }
453
454 static void s3fb_fillrect(struct fb_info *info, const struct fb_fillrect *rect)
455 {
456 if ((info->var.bits_per_pixel == 4)
457 && ((rect->width % 8) == 0) && ((rect->dx % 8) == 0)
458 && (info->fix.type == FB_TYPE_INTERLEAVED_PLANES))
459 s3fb_iplan_fillrect(info, rect);
460 else
461 cfb_fillrect(info, rect);
462 }
463
464
465
466 /* ------------------------------------------------------------------------- */
467
468
469 static void s3_set_pixclock(struct fb_info *info, u32 pixclock)
470 {
471 struct s3fb_info *par = info->par;
472 u16 m, n, r;
473 u8 regval;
474 int rv;
475
476 rv = svga_compute_pll((par->chip == CHIP_365_TRIO3D) ? &s3_trio3d_pll : &s3_pll,
477 1000000000 / pixclock, &m, &n, &r, info->node);
478 if (rv < 0) {
479 printk(KERN_ERR "fb%d: cannot set requested pixclock, keeping old value\n", info->node);
480 return;
481 }
482
483 /* Set VGA misc register */
484 regval = vga_r(par->state.vgabase, VGA_MIS_R);
485 vga_w(par->state.vgabase, VGA_MIS_W, regval | VGA_MIS_ENB_PLL_LOAD);
486
487 /* Set S3 clock registers */
488 if (par->chip == CHIP_357_VIRGE_GX2 ||
489 par->chip == CHIP_359_VIRGE_GX2P ||
490 par->chip == CHIP_360_TRIO3D_1X ||
491 par->chip == CHIP_362_TRIO3D_2X ||
492 par->chip == CHIP_368_TRIO3D_2X ||
493 par->chip == CHIP_260_VIRGE_MX) {
494 vga_wseq(par->state.vgabase, 0x12, (n - 2) | ((r & 3) << 6)); /* n and two bits of r */
495 vga_wseq(par->state.vgabase, 0x29, r >> 2); /* remaining highest bit of r */
496 } else
497 vga_wseq(par->state.vgabase, 0x12, (n - 2) | (r << 5));
498 vga_wseq(par->state.vgabase, 0x13, m - 2);
499
500 udelay(1000);
501
502 /* Activate clock - write 0, 1, 0 to seq/15 bit 5 */
503 regval = vga_rseq (par->state.vgabase, 0x15); /* | 0x80; */
504 vga_wseq(par->state.vgabase, 0x15, regval & ~(1<<5));
505 vga_wseq(par->state.vgabase, 0x15, regval | (1<<5));
506 vga_wseq(par->state.vgabase, 0x15, regval & ~(1<<5));
507 }
508
509
510 /* Open framebuffer */
511
512 static int s3fb_open(struct fb_info *info, int user)
513 {
514 struct s3fb_info *par = info->par;
515
516 mutex_lock(&(par->open_lock));
517 if (par->ref_count == 0) {
518 void __iomem *vgabase = par->state.vgabase;
519
520 memset(&(par->state), 0, sizeof(struct vgastate));
521 par->state.vgabase = vgabase;
522 par->state.flags = VGA_SAVE_MODE | VGA_SAVE_FONTS | VGA_SAVE_CMAP;
523 par->state.num_crtc = 0x70;
524 par->state.num_seq = 0x20;
525 save_vga(&(par->state));
526 }
527
528 par->ref_count++;
529 mutex_unlock(&(par->open_lock));
530
531 return 0;
532 }
533
534 /* Close framebuffer */
535
536 static int s3fb_release(struct fb_info *info, int user)
537 {
538 struct s3fb_info *par = info->par;
539
540 mutex_lock(&(par->open_lock));
541 if (par->ref_count == 0) {
542 mutex_unlock(&(par->open_lock));
543 return -EINVAL;
544 }
545
546 if (par->ref_count == 1)
547 restore_vga(&(par->state));
548
549 par->ref_count--;
550 mutex_unlock(&(par->open_lock));
551
552 return 0;
553 }
554
555 /* Validate passed in var */
556
557 static int s3fb_check_var(struct fb_var_screeninfo *var, struct fb_info *info)
558 {
559 struct s3fb_info *par = info->par;
560 int rv, mem, step;
561 u16 m, n, r;
562
563 /* Find appropriate format */
564 rv = svga_match_format (s3fb_formats, var, NULL);
565
566 /* 32bpp mode is not supported on VIRGE VX,
567 24bpp is not supported on others */
568 if ((par->chip == CHIP_988_VIRGE_VX) ? (rv == 7) : (rv == 6))
569 rv = -EINVAL;
570
571 if (rv < 0) {
572 printk(KERN_ERR "fb%d: unsupported mode requested\n", info->node);
573 return rv;
574 }
575
576 /* Do not allow to have real resoulution larger than virtual */
577 if (var->xres > var->xres_virtual)
578 var->xres_virtual = var->xres;
579
580 if (var->yres > var->yres_virtual)
581 var->yres_virtual = var->yres;
582
583 /* Round up xres_virtual to have proper alignment of lines */
584 step = s3fb_formats[rv].xresstep - 1;
585 var->xres_virtual = (var->xres_virtual+step) & ~step;
586
587 /* Check whether have enough memory */
588 mem = ((var->bits_per_pixel * var->xres_virtual) >> 3) * var->yres_virtual;
589 if (mem > info->screen_size) {
590 printk(KERN_ERR "fb%d: not enough framebuffer memory (%d kB requested , %d kB available)\n",
591 info->node, mem >> 10, (unsigned int) (info->screen_size >> 10));
592 return -EINVAL;
593 }
594
595 rv = svga_check_timings (&s3_timing_regs, var, info->node);
596 if (rv < 0) {
597 printk(KERN_ERR "fb%d: invalid timings requested\n", info->node);
598 return rv;
599 }
600
601 rv = svga_compute_pll(&s3_pll, PICOS2KHZ(var->pixclock), &m, &n, &r,
602 info->node);
603 if (rv < 0) {
604 printk(KERN_ERR "fb%d: invalid pixclock value requested\n",
605 info->node);
606 return rv;
607 }
608
609 return 0;
610 }
611
612 /* Set video mode from par */
613
614 static int s3fb_set_par(struct fb_info *info)
615 {
616 struct s3fb_info *par = info->par;
617 u32 value, mode, hmul, offset_value, screen_size, multiplex, dbytes;
618 u32 bpp = info->var.bits_per_pixel;
619 u32 htotal, hsstart;
620
621 if (bpp != 0) {
622 info->fix.ypanstep = 1;
623 info->fix.line_length = (info->var.xres_virtual * bpp) / 8;
624
625 info->flags &= ~FBINFO_MISC_TILEBLITTING;
626 info->tileops = NULL;
627
628 /* in 4bpp supports 8p wide tiles only, any tiles otherwise */
629 info->pixmap.blit_x = (bpp == 4) ? (1 << (8 - 1)) : (~(u32)0);
630 info->pixmap.blit_y = ~(u32)0;
631
632 offset_value = (info->var.xres_virtual * bpp) / 64;
633 screen_size = info->var.yres_virtual * info->fix.line_length;
634 } else {
635 info->fix.ypanstep = 16;
636 info->fix.line_length = 0;
637
638 info->flags |= FBINFO_MISC_TILEBLITTING;
639 info->tileops = fasttext ? &s3fb_fast_tile_ops : &s3fb_tile_ops;
640
641 /* supports 8x16 tiles only */
642 info->pixmap.blit_x = 1 << (8 - 1);
643 info->pixmap.blit_y = 1 << (16 - 1);
644
645 offset_value = info->var.xres_virtual / 16;
646 screen_size = (info->var.xres_virtual * info->var.yres_virtual) / 64;
647 }
648
649 info->var.xoffset = 0;
650 info->var.yoffset = 0;
651 info->var.activate = FB_ACTIVATE_NOW;
652
653 /* Unlock registers */
654 vga_wcrt(par->state.vgabase, 0x38, 0x48);
655 vga_wcrt(par->state.vgabase, 0x39, 0xA5);
656 vga_wseq(par->state.vgabase, 0x08, 0x06);
657 svga_wcrt_mask(par->state.vgabase, 0x11, 0x00, 0x80);
658
659 /* Blank screen and turn off sync */
660 svga_wseq_mask(par->state.vgabase, 0x01, 0x20, 0x20);
661 svga_wcrt_mask(par->state.vgabase, 0x17, 0x00, 0x80);
662
663 /* Set default values */
664 svga_set_default_gfx_regs(par->state.vgabase);
665 svga_set_default_atc_regs(par->state.vgabase);
666 svga_set_default_seq_regs(par->state.vgabase);
667 svga_set_default_crt_regs(par->state.vgabase);
668 svga_wcrt_multi(par->state.vgabase, s3_line_compare_regs, 0xFFFFFFFF);
669 svga_wcrt_multi(par->state.vgabase, s3_start_address_regs, 0);
670
671 /* S3 specific initialization */
672 svga_wcrt_mask(par->state.vgabase, 0x58, 0x10, 0x10); /* enable linear framebuffer */
673 svga_wcrt_mask(par->state.vgabase, 0x31, 0x08, 0x08); /* enable sequencer access to framebuffer above 256 kB */
674
675 /* svga_wcrt_mask(par->state.vgabase, 0x33, 0x08, 0x08); */ /* DDR ? */
676 /* svga_wcrt_mask(par->state.vgabase, 0x43, 0x01, 0x01); */ /* DDR ? */
677 svga_wcrt_mask(par->state.vgabase, 0x33, 0x00, 0x08); /* no DDR ? */
678 svga_wcrt_mask(par->state.vgabase, 0x43, 0x00, 0x01); /* no DDR ? */
679
680 svga_wcrt_mask(par->state.vgabase, 0x5D, 0x00, 0x28); /* Clear strange HSlen bits */
681
682 /* svga_wcrt_mask(par->state.vgabase, 0x58, 0x03, 0x03); */
683
684 /* svga_wcrt_mask(par->state.vgabase, 0x53, 0x12, 0x13); */ /* enable MMIO */
685 /* svga_wcrt_mask(par->state.vgabase, 0x40, 0x08, 0x08); */ /* enable write buffer */
686
687
688 /* Set the offset register */
689 pr_debug("fb%d: offset register : %d\n", info->node, offset_value);
690 svga_wcrt_multi(par->state.vgabase, s3_offset_regs, offset_value);
691
692 if (par->chip != CHIP_357_VIRGE_GX2 &&
693 par->chip != CHIP_359_VIRGE_GX2P &&
694 par->chip != CHIP_360_TRIO3D_1X &&
695 par->chip != CHIP_362_TRIO3D_2X &&
696 par->chip != CHIP_368_TRIO3D_2X &&
697 par->chip != CHIP_260_VIRGE_MX) {
698 vga_wcrt(par->state.vgabase, 0x54, 0x18); /* M parameter */
699 vga_wcrt(par->state.vgabase, 0x60, 0xff); /* N parameter */
700 vga_wcrt(par->state.vgabase, 0x61, 0xff); /* L parameter */
701 vga_wcrt(par->state.vgabase, 0x62, 0xff); /* L parameter */
702 }
703
704 vga_wcrt(par->state.vgabase, 0x3A, 0x35);
705 svga_wattr(par->state.vgabase, 0x33, 0x00);
706
707 if (info->var.vmode & FB_VMODE_DOUBLE)
708 svga_wcrt_mask(par->state.vgabase, 0x09, 0x80, 0x80);
709 else
710 svga_wcrt_mask(par->state.vgabase, 0x09, 0x00, 0x80);
711
712 if (info->var.vmode & FB_VMODE_INTERLACED)
713 svga_wcrt_mask(par->state.vgabase, 0x42, 0x20, 0x20);
714 else
715 svga_wcrt_mask(par->state.vgabase, 0x42, 0x00, 0x20);
716
717 /* Disable hardware graphics cursor */
718 svga_wcrt_mask(par->state.vgabase, 0x45, 0x00, 0x01);
719 /* Disable Streams engine */
720 svga_wcrt_mask(par->state.vgabase, 0x67, 0x00, 0x0C);
721
722 mode = svga_match_format(s3fb_formats, &(info->var), &(info->fix));
723
724 /* S3 virge DX hack */
725 if (par->chip == CHIP_375_VIRGE_DX) {
726 vga_wcrt(par->state.vgabase, 0x86, 0x80);
727 vga_wcrt(par->state.vgabase, 0x90, 0x00);
728 }
729
730 /* S3 virge VX hack */
731 if (par->chip == CHIP_988_VIRGE_VX) {
732 vga_wcrt(par->state.vgabase, 0x50, 0x00);
733 vga_wcrt(par->state.vgabase, 0x67, 0x50);
734 msleep(10); /* screen remains blank sometimes without this */
735 vga_wcrt(par->state.vgabase, 0x63, (mode <= 2) ? 0x90 : 0x09);
736 vga_wcrt(par->state.vgabase, 0x66, 0x90);
737 }
738
739 if (par->chip == CHIP_357_VIRGE_GX2 ||
740 par->chip == CHIP_359_VIRGE_GX2P ||
741 par->chip == CHIP_360_TRIO3D_1X ||
742 par->chip == CHIP_362_TRIO3D_2X ||
743 par->chip == CHIP_368_TRIO3D_2X ||
744 par->chip == CHIP_365_TRIO3D ||
745 par->chip == CHIP_375_VIRGE_DX ||
746 par->chip == CHIP_385_VIRGE_GX ||
747 par->chip == CHIP_260_VIRGE_MX) {
748 dbytes = info->var.xres * ((bpp+7)/8);
749 vga_wcrt(par->state.vgabase, 0x91, (dbytes + 7) / 8);
750 vga_wcrt(par->state.vgabase, 0x90, (((dbytes + 7) / 8) >> 8) | 0x80);
751
752 vga_wcrt(par->state.vgabase, 0x66, 0x81);
753 }
754
755 if (par->chip == CHIP_357_VIRGE_GX2 ||
756 par->chip == CHIP_359_VIRGE_GX2P ||
757 par->chip == CHIP_360_TRIO3D_1X ||
758 par->chip == CHIP_362_TRIO3D_2X ||
759 par->chip == CHIP_368_TRIO3D_2X ||
760 par->chip == CHIP_260_VIRGE_MX)
761 vga_wcrt(par->state.vgabase, 0x34, 0x00);
762 else /* enable Data Transfer Position Control (DTPC) */
763 vga_wcrt(par->state.vgabase, 0x34, 0x10);
764
765 svga_wcrt_mask(par->state.vgabase, 0x31, 0x00, 0x40);
766 multiplex = 0;
767 hmul = 1;
768
769 /* Set mode-specific register values */
770 switch (mode) {
771 case 0:
772 pr_debug("fb%d: text mode\n", info->node);
773 svga_set_textmode_vga_regs(par->state.vgabase);
774
775 /* Set additional registers like in 8-bit mode */
776 svga_wcrt_mask(par->state.vgabase, 0x50, 0x00, 0x30);
777 svga_wcrt_mask(par->state.vgabase, 0x67, 0x00, 0xF0);
778
779 /* Disable enhanced mode */
780 svga_wcrt_mask(par->state.vgabase, 0x3A, 0x00, 0x30);
781
782 if (fasttext) {
783 pr_debug("fb%d: high speed text mode set\n", info->node);
784 svga_wcrt_mask(par->state.vgabase, 0x31, 0x40, 0x40);
785 }
786 break;
787 case 1:
788 pr_debug("fb%d: 4 bit pseudocolor\n", info->node);
789 vga_wgfx(par->state.vgabase, VGA_GFX_MODE, 0x40);
790
791 /* Set additional registers like in 8-bit mode */
792 svga_wcrt_mask(par->state.vgabase, 0x50, 0x00, 0x30);
793 svga_wcrt_mask(par->state.vgabase, 0x67, 0x00, 0xF0);
794
795 /* disable enhanced mode */
796 svga_wcrt_mask(par->state.vgabase, 0x3A, 0x00, 0x30);
797 break;
798 case 2:
799 pr_debug("fb%d: 4 bit pseudocolor, planar\n", info->node);
800
801 /* Set additional registers like in 8-bit mode */
802 svga_wcrt_mask(par->state.vgabase, 0x50, 0x00, 0x30);
803 svga_wcrt_mask(par->state.vgabase, 0x67, 0x00, 0xF0);
804
805 /* disable enhanced mode */
806 svga_wcrt_mask(par->state.vgabase, 0x3A, 0x00, 0x30);
807 break;
808 case 3:
809 pr_debug("fb%d: 8 bit pseudocolor\n", info->node);
810 svga_wcrt_mask(par->state.vgabase, 0x50, 0x00, 0x30);
811 if (info->var.pixclock > 20000 ||
812 par->chip == CHIP_357_VIRGE_GX2 ||
813 par->chip == CHIP_359_VIRGE_GX2P ||
814 par->chip == CHIP_360_TRIO3D_1X ||
815 par->chip == CHIP_362_TRIO3D_2X ||
816 par->chip == CHIP_368_TRIO3D_2X ||
817 par->chip == CHIP_260_VIRGE_MX)
818 svga_wcrt_mask(par->state.vgabase, 0x67, 0x00, 0xF0);
819 else {
820 svga_wcrt_mask(par->state.vgabase, 0x67, 0x10, 0xF0);
821 multiplex = 1;
822 }
823 break;
824 case 4:
825 pr_debug("fb%d: 5/5/5 truecolor\n", info->node);
826 if (par->chip == CHIP_988_VIRGE_VX) {
827 if (info->var.pixclock > 20000)
828 svga_wcrt_mask(par->state.vgabase, 0x67, 0x20, 0xF0);
829 else
830 svga_wcrt_mask(par->state.vgabase, 0x67, 0x30, 0xF0);
831 } else if (par->chip == CHIP_365_TRIO3D) {
832 svga_wcrt_mask(par->state.vgabase, 0x50, 0x10, 0x30);
833 if (info->var.pixclock > 8695) {
834 svga_wcrt_mask(par->state.vgabase, 0x67, 0x30, 0xF0);
835 hmul = 2;
836 } else {
837 svga_wcrt_mask(par->state.vgabase, 0x67, 0x20, 0xF0);
838 multiplex = 1;
839 }
840 } else {
841 svga_wcrt_mask(par->state.vgabase, 0x50, 0x10, 0x30);
842 svga_wcrt_mask(par->state.vgabase, 0x67, 0x30, 0xF0);
843 if (par->chip != CHIP_357_VIRGE_GX2 &&
844 par->chip != CHIP_359_VIRGE_GX2P &&
845 par->chip != CHIP_360_TRIO3D_1X &&
846 par->chip != CHIP_362_TRIO3D_2X &&
847 par->chip != CHIP_368_TRIO3D_2X &&
848 par->chip != CHIP_260_VIRGE_MX)
849 hmul = 2;
850 }
851 break;
852 case 5:
853 pr_debug("fb%d: 5/6/5 truecolor\n", info->node);
854 if (par->chip == CHIP_988_VIRGE_VX) {
855 if (info->var.pixclock > 20000)
856 svga_wcrt_mask(par->state.vgabase, 0x67, 0x40, 0xF0);
857 else
858 svga_wcrt_mask(par->state.vgabase, 0x67, 0x50, 0xF0);
859 } else if (par->chip == CHIP_365_TRIO3D) {
860 svga_wcrt_mask(par->state.vgabase, 0x50, 0x10, 0x30);
861 if (info->var.pixclock > 8695) {
862 svga_wcrt_mask(par->state.vgabase, 0x67, 0x50, 0xF0);
863 hmul = 2;
864 } else {
865 svga_wcrt_mask(par->state.vgabase, 0x67, 0x40, 0xF0);
866 multiplex = 1;
867 }
868 } else {
869 svga_wcrt_mask(par->state.vgabase, 0x50, 0x10, 0x30);
870 svga_wcrt_mask(par->state.vgabase, 0x67, 0x50, 0xF0);
871 if (par->chip != CHIP_357_VIRGE_GX2 &&
872 par->chip != CHIP_359_VIRGE_GX2P &&
873 par->chip != CHIP_360_TRIO3D_1X &&
874 par->chip != CHIP_362_TRIO3D_2X &&
875 par->chip != CHIP_368_TRIO3D_2X &&
876 par->chip != CHIP_260_VIRGE_MX)
877 hmul = 2;
878 }
879 break;
880 case 6:
881 /* VIRGE VX case */
882 pr_debug("fb%d: 8/8/8 truecolor\n", info->node);
883 svga_wcrt_mask(par->state.vgabase, 0x67, 0xD0, 0xF0);
884 break;
885 case 7:
886 pr_debug("fb%d: 8/8/8/8 truecolor\n", info->node);
887 svga_wcrt_mask(par->state.vgabase, 0x50, 0x30, 0x30);
888 svga_wcrt_mask(par->state.vgabase, 0x67, 0xD0, 0xF0);
889 break;
890 default:
891 printk(KERN_ERR "fb%d: unsupported mode - bug\n", info->node);
892 return -EINVAL;
893 }
894
895 if (par->chip != CHIP_988_VIRGE_VX) {
896 svga_wseq_mask(par->state.vgabase, 0x15, multiplex ? 0x10 : 0x00, 0x10);
897 svga_wseq_mask(par->state.vgabase, 0x18, multiplex ? 0x80 : 0x00, 0x80);
898 }
899
900 s3_set_pixclock(info, info->var.pixclock);
901 svga_set_timings(par->state.vgabase, &s3_timing_regs, &(info->var), hmul, 1,
902 (info->var.vmode & FB_VMODE_DOUBLE) ? 2 : 1,
903 (info->var.vmode & FB_VMODE_INTERLACED) ? 2 : 1,
904 hmul, info->node);
905
906 /* Set interlaced mode start/end register */
907 htotal = info->var.xres + info->var.left_margin + info->var.right_margin + info->var.hsync_len;
908 htotal = ((htotal * hmul) / 8) - 5;
909 vga_wcrt(par->state.vgabase, 0x3C, (htotal + 1) / 2);
910
911 /* Set Data Transfer Position */
912 hsstart = ((info->var.xres + info->var.right_margin) * hmul) / 8;
913 /* + 2 is needed for Virge/VX, does no harm on other cards */
914 value = clamp((htotal + hsstart + 1) / 2 + 2, hsstart + 4, htotal + 1);
915 svga_wcrt_multi(par->state.vgabase, s3_dtpc_regs, value);
916
917 memset_io(info->screen_base, 0x00, screen_size);
918 /* Device and screen back on */
919 svga_wcrt_mask(par->state.vgabase, 0x17, 0x80, 0x80);
920 svga_wseq_mask(par->state.vgabase, 0x01, 0x00, 0x20);
921
922 return 0;
923 }
924
925 /* Set a colour register */
926
927 static int s3fb_setcolreg(u_int regno, u_int red, u_int green, u_int blue,
928 u_int transp, struct fb_info *fb)
929 {
930 switch (fb->var.bits_per_pixel) {
931 case 0:
932 case 4:
933 if (regno >= 16)
934 return -EINVAL;
935
936 if ((fb->var.bits_per_pixel == 4) &&
937 (fb->var.nonstd == 0)) {
938 outb(0xF0, VGA_PEL_MSK);
939 outb(regno*16, VGA_PEL_IW);
940 } else {
941 outb(0x0F, VGA_PEL_MSK);
942 outb(regno, VGA_PEL_IW);
943 }
944 outb(red >> 10, VGA_PEL_D);
945 outb(green >> 10, VGA_PEL_D);
946 outb(blue >> 10, VGA_PEL_D);
947 break;
948 case 8:
949 if (regno >= 256)
950 return -EINVAL;
951
952 outb(0xFF, VGA_PEL_MSK);
953 outb(regno, VGA_PEL_IW);
954 outb(red >> 10, VGA_PEL_D);
955 outb(green >> 10, VGA_PEL_D);
956 outb(blue >> 10, VGA_PEL_D);
957 break;
958 case 16:
959 if (regno >= 16)
960 return 0;
961
962 if (fb->var.green.length == 5)
963 ((u32*)fb->pseudo_palette)[regno] = ((red & 0xF800) >> 1) |
964 ((green & 0xF800) >> 6) | ((blue & 0xF800) >> 11);
965 else if (fb->var.green.length == 6)
966 ((u32*)fb->pseudo_palette)[regno] = (red & 0xF800) |
967 ((green & 0xFC00) >> 5) | ((blue & 0xF800) >> 11);
968 else return -EINVAL;
969 break;
970 case 24:
971 case 32:
972 if (regno >= 16)
973 return 0;
974
975 ((u32*)fb->pseudo_palette)[regno] = ((red & 0xFF00) << 8) |
976 (green & 0xFF00) | ((blue & 0xFF00) >> 8);
977 break;
978 default:
979 return -EINVAL;
980 }
981
982 return 0;
983 }
984
985
986 /* Set the display blanking state */
987
988 static int s3fb_blank(int blank_mode, struct fb_info *info)
989 {
990 struct s3fb_info *par = info->par;
991
992 switch (blank_mode) {
993 case FB_BLANK_UNBLANK:
994 pr_debug("fb%d: unblank\n", info->node);
995 svga_wcrt_mask(par->state.vgabase, 0x56, 0x00, 0x06);
996 svga_wseq_mask(par->state.vgabase, 0x01, 0x00, 0x20);
997 break;
998 case FB_BLANK_NORMAL:
999 pr_debug("fb%d: blank\n", info->node);
1000 svga_wcrt_mask(par->state.vgabase, 0x56, 0x00, 0x06);
1001 svga_wseq_mask(par->state.vgabase, 0x01, 0x20, 0x20);
1002 break;
1003 case FB_BLANK_HSYNC_SUSPEND:
1004 pr_debug("fb%d: hsync\n", info->node);
1005 svga_wcrt_mask(par->state.vgabase, 0x56, 0x02, 0x06);
1006 svga_wseq_mask(par->state.vgabase, 0x01, 0x20, 0x20);
1007 break;
1008 case FB_BLANK_VSYNC_SUSPEND:
1009 pr_debug("fb%d: vsync\n", info->node);
1010 svga_wcrt_mask(par->state.vgabase, 0x56, 0x04, 0x06);
1011 svga_wseq_mask(par->state.vgabase, 0x01, 0x20, 0x20);
1012 break;
1013 case FB_BLANK_POWERDOWN:
1014 pr_debug("fb%d: sync down\n", info->node);
1015 svga_wcrt_mask(par->state.vgabase, 0x56, 0x06, 0x06);
1016 svga_wseq_mask(par->state.vgabase, 0x01, 0x20, 0x20);
1017 break;
1018 }
1019
1020 return 0;
1021 }
1022
1023
1024 /* Pan the display */
1025
1026 static int s3fb_pan_display(struct fb_var_screeninfo *var, struct fb_info *info)
1027 {
1028 struct s3fb_info *par = info->par;
1029 unsigned int offset;
1030
1031 /* Calculate the offset */
1032 if (info->var.bits_per_pixel == 0) {
1033 offset = (var->yoffset / 16) * (info->var.xres_virtual / 2)
1034 + (var->xoffset / 2);
1035 offset = offset >> 2;
1036 } else {
1037 offset = (var->yoffset * info->fix.line_length) +
1038 (var->xoffset * info->var.bits_per_pixel / 8);
1039 offset = offset >> 2;
1040 }
1041
1042 /* Set the offset */
1043 svga_wcrt_multi(par->state.vgabase, s3_start_address_regs, offset);
1044
1045 return 0;
1046 }
1047
1048 /* ------------------------------------------------------------------------- */
1049
1050 /* Frame buffer operations */
1051
1052 static struct fb_ops s3fb_ops = {
1053 .owner = THIS_MODULE,
1054 .fb_open = s3fb_open,
1055 .fb_release = s3fb_release,
1056 .fb_check_var = s3fb_check_var,
1057 .fb_set_par = s3fb_set_par,
1058 .fb_setcolreg = s3fb_setcolreg,
1059 .fb_blank = s3fb_blank,
1060 .fb_pan_display = s3fb_pan_display,
1061 .fb_fillrect = s3fb_fillrect,
1062 .fb_copyarea = cfb_copyarea,
1063 .fb_imageblit = s3fb_imageblit,
1064 .fb_get_caps = svga_get_caps,
1065 };
1066
1067 /* ------------------------------------------------------------------------- */
1068
1069 static int s3_identification(struct s3fb_info *par)
1070 {
1071 int chip = par->chip;
1072
1073 if (chip == CHIP_XXX_TRIO) {
1074 u8 cr30 = vga_rcrt(par->state.vgabase, 0x30);
1075 u8 cr2e = vga_rcrt(par->state.vgabase, 0x2e);
1076 u8 cr2f = vga_rcrt(par->state.vgabase, 0x2f);
1077
1078 if ((cr30 == 0xE0) || (cr30 == 0xE1)) {
1079 if (cr2e == 0x10)
1080 return CHIP_732_TRIO32;
1081 if (cr2e == 0x11) {
1082 if (! (cr2f & 0x40))
1083 return CHIP_764_TRIO64;
1084 else
1085 return CHIP_765_TRIO64VP;
1086 }
1087 }
1088 }
1089
1090 if (chip == CHIP_XXX_TRIO64V2_DXGX) {
1091 u8 cr6f = vga_rcrt(par->state.vgabase, 0x6f);
1092
1093 if (! (cr6f & 0x01))
1094 return CHIP_775_TRIO64V2_DX;
1095 else
1096 return CHIP_785_TRIO64V2_GX;
1097 }
1098
1099 if (chip == CHIP_XXX_VIRGE_DXGX) {
1100 u8 cr6f = vga_rcrt(par->state.vgabase, 0x6f);
1101
1102 if (! (cr6f & 0x01))
1103 return CHIP_375_VIRGE_DX;
1104 else
1105 return CHIP_385_VIRGE_GX;
1106 }
1107
1108 if (chip == CHIP_36X_TRIO3D_1X_2X) {
1109 switch (vga_rcrt(par->state.vgabase, 0x2f)) {
1110 case 0x00:
1111 return CHIP_360_TRIO3D_1X;
1112 case 0x01:
1113 return CHIP_362_TRIO3D_2X;
1114 case 0x02:
1115 return CHIP_368_TRIO3D_2X;
1116 }
1117 }
1118
1119 return CHIP_UNKNOWN;
1120 }
1121
1122
1123 /* PCI probe */
1124
1125 static int s3_pci_probe(struct pci_dev *dev, const struct pci_device_id *id)
1126 {
1127 struct pci_bus_region bus_reg;
1128 struct resource vga_res;
1129 struct fb_info *info;
1130 struct s3fb_info *par;
1131 int rc;
1132 u8 regval, cr38, cr39;
1133 bool found = false;
1134
1135 /* Ignore secondary VGA device because there is no VGA arbitration */
1136 if (! svga_primary_device(dev)) {
1137 dev_info(&(dev->dev), "ignoring secondary device\n");
1138 return -ENODEV;
1139 }
1140
1141 /* Allocate and fill driver data structure */
1142 info = framebuffer_alloc(sizeof(struct s3fb_info), &(dev->dev));
1143 if (!info) {
1144 dev_err(&(dev->dev), "cannot allocate memory\n");
1145 return -ENOMEM;
1146 }
1147
1148 par = info->par;
1149 mutex_init(&par->open_lock);
1150
1151 info->flags = FBINFO_PARTIAL_PAN_OK | FBINFO_HWACCEL_YPAN;
1152 info->fbops = &s3fb_ops;
1153
1154 /* Prepare PCI device */
1155 rc = pci_enable_device(dev);
1156 if (rc < 0) {
1157 dev_err(info->device, "cannot enable PCI device\n");
1158 goto err_enable_device;
1159 }
1160
1161 rc = pci_request_regions(dev, "s3fb");
1162 if (rc < 0) {
1163 dev_err(info->device, "cannot reserve framebuffer region\n");
1164 goto err_request_regions;
1165 }
1166
1167
1168 info->fix.smem_start = pci_resource_start(dev, 0);
1169 info->fix.smem_len = pci_resource_len(dev, 0);
1170
1171 /* Map physical IO memory address into kernel space */
1172 info->screen_base = pci_iomap(dev, 0, 0);
1173 if (! info->screen_base) {
1174 rc = -ENOMEM;
1175 dev_err(info->device, "iomap for framebuffer failed\n");
1176 goto err_iomap;
1177 }
1178
1179 bus_reg.start = 0;
1180 bus_reg.end = 64 * 1024;
1181
1182 vga_res.flags = IORESOURCE_IO;
1183
1184 pcibios_bus_to_resource(dev, &vga_res, &bus_reg);
1185
1186 par->state.vgabase = (void __iomem *) vga_res.start;
1187
1188 /* Unlock regs */
1189 cr38 = vga_rcrt(par->state.vgabase, 0x38);
1190 cr39 = vga_rcrt(par->state.vgabase, 0x39);
1191 vga_wseq(par->state.vgabase, 0x08, 0x06);
1192 vga_wcrt(par->state.vgabase, 0x38, 0x48);
1193 vga_wcrt(par->state.vgabase, 0x39, 0xA5);
1194
1195 /* Identify chip type */
1196 par->chip = id->driver_data & CHIP_MASK;
1197 par->rev = vga_rcrt(par->state.vgabase, 0x2f);
1198 if (par->chip & CHIP_UNDECIDED_FLAG)
1199 par->chip = s3_identification(par);
1200
1201 /* Find how many physical memory there is on card */
1202 /* 0x36 register is accessible even if other registers are locked */
1203 regval = vga_rcrt(par->state.vgabase, 0x36);
1204 if (par->chip == CHIP_360_TRIO3D_1X ||
1205 par->chip == CHIP_362_TRIO3D_2X ||
1206 par->chip == CHIP_368_TRIO3D_2X ||
1207 par->chip == CHIP_365_TRIO3D) {
1208 switch ((regval & 0xE0) >> 5) {
1209 case 0: /* 8MB -- only 4MB usable for display */
1210 case 1: /* 4MB with 32-bit bus */
1211 case 2: /* 4MB */
1212 info->screen_size = 4 << 20;
1213 break;
1214 case 4: /* 2MB on 365 Trio3D */
1215 case 6: /* 2MB */
1216 info->screen_size = 2 << 20;
1217 break;
1218 }
1219 } else if (par->chip == CHIP_357_VIRGE_GX2 ||
1220 par->chip == CHIP_359_VIRGE_GX2P ||
1221 par->chip == CHIP_260_VIRGE_MX) {
1222 switch ((regval & 0xC0) >> 6) {
1223 case 1: /* 4MB */
1224 info->screen_size = 4 << 20;
1225 break;
1226 case 3: /* 2MB */
1227 info->screen_size = 2 << 20;
1228 break;
1229 }
1230 } else if (par->chip == CHIP_988_VIRGE_VX) {
1231 switch ((regval & 0x60) >> 5) {
1232 case 0: /* 2MB */
1233 info->screen_size = 2 << 20;
1234 break;
1235 case 1: /* 4MB */
1236 info->screen_size = 4 << 20;
1237 break;
1238 case 2: /* 6MB */
1239 info->screen_size = 6 << 20;
1240 break;
1241 case 3: /* 8MB */
1242 info->screen_size = 8 << 20;
1243 break;
1244 }
1245 /* off-screen memory */
1246 regval = vga_rcrt(par->state.vgabase, 0x37);
1247 switch ((regval & 0x60) >> 5) {
1248 case 1: /* 4MB */
1249 info->screen_size -= 4 << 20;
1250 break;
1251 case 2: /* 2MB */
1252 info->screen_size -= 2 << 20;
1253 break;
1254 }
1255 } else
1256 info->screen_size = s3_memsizes[regval >> 5] << 10;
1257 info->fix.smem_len = info->screen_size;
1258
1259 /* Find MCLK frequency */
1260 regval = vga_rseq(par->state.vgabase, 0x10);
1261 par->mclk_freq = ((vga_rseq(par->state.vgabase, 0x11) + 2) * 14318) / ((regval & 0x1F) + 2);
1262 par->mclk_freq = par->mclk_freq >> (regval >> 5);
1263
1264 /* Restore locks */
1265 vga_wcrt(par->state.vgabase, 0x38, cr38);
1266 vga_wcrt(par->state.vgabase, 0x39, cr39);
1267
1268 strcpy(info->fix.id, s3_names [par->chip]);
1269 info->fix.mmio_start = 0;
1270 info->fix.mmio_len = 0;
1271 info->fix.type = FB_TYPE_PACKED_PIXELS;
1272 info->fix.visual = FB_VISUAL_PSEUDOCOLOR;
1273 info->fix.ypanstep = 0;
1274 info->fix.accel = FB_ACCEL_NONE;
1275 info->pseudo_palette = (void*) (par->pseudo_palette);
1276 info->var.bits_per_pixel = 8;
1277
1278 #ifdef CONFIG_FB_S3_DDC
1279 /* Enable MMIO if needed */
1280 if (s3fb_ddc_needs_mmio(par->chip)) {
1281 par->mmio = ioremap(info->fix.smem_start + MMIO_OFFSET, MMIO_SIZE);
1282 if (par->mmio)
1283 svga_wcrt_mask(par->state.vgabase, 0x53, 0x08, 0x08); /* enable MMIO */
1284 else
1285 dev_err(info->device, "unable to map MMIO at 0x%lx, disabling DDC",
1286 info->fix.smem_start + MMIO_OFFSET);
1287 }
1288 if (!s3fb_ddc_needs_mmio(par->chip) || par->mmio)
1289 if (s3fb_setup_ddc_bus(info) == 0) {
1290 u8 *edid = fb_ddc_read(&par->ddc_adapter);
1291 par->ddc_registered = true;
1292 if (edid) {
1293 fb_edid_to_monspecs(edid, &info->monspecs);
1294 kfree(edid);
1295 if (!info->monspecs.modedb)
1296 dev_err(info->device, "error getting mode database\n");
1297 else {
1298 const struct fb_videomode *m;
1299
1300 fb_videomode_to_modelist(info->monspecs.modedb,
1301 info->monspecs.modedb_len,
1302 &info->modelist);
1303 m = fb_find_best_display(&info->monspecs, &info->modelist);
1304 if (m) {
1305 fb_videomode_to_var(&info->var, m);
1306 /* fill all other info->var's fields */
1307 if (s3fb_check_var(&info->var, info) == 0)
1308 found = true;
1309 }
1310 }
1311 }
1312 }
1313 #endif
1314 if (!mode_option && !found)
1315 mode_option = "640x480-8@60";
1316
1317 /* Prepare startup mode */
1318 if (mode_option) {
1319 rc = fb_find_mode(&info->var, info, mode_option,
1320 info->monspecs.modedb, info->monspecs.modedb_len,
1321 NULL, info->var.bits_per_pixel);
1322 if (!rc || rc == 4) {
1323 rc = -EINVAL;
1324 dev_err(info->device, "mode %s not found\n", mode_option);
1325 fb_destroy_modedb(info->monspecs.modedb);
1326 info->monspecs.modedb = NULL;
1327 goto err_find_mode;
1328 }
1329 }
1330
1331 fb_destroy_modedb(info->monspecs.modedb);
1332 info->monspecs.modedb = NULL;
1333
1334 /* maximize virtual vertical size for fast scrolling */
1335 info->var.yres_virtual = info->fix.smem_len * 8 /
1336 (info->var.bits_per_pixel * info->var.xres_virtual);
1337 if (info->var.yres_virtual < info->var.yres) {
1338 dev_err(info->device, "virtual vertical size smaller than real\n");
1339 goto err_find_mode;
1340 }
1341
1342 /* maximize virtual vertical size for fast scrolling */
1343 info->var.yres_virtual = info->fix.smem_len * 8 /
1344 (info->var.bits_per_pixel * info->var.xres_virtual);
1345 if (info->var.yres_virtual < info->var.yres) {
1346 dev_err(info->device, "virtual vertical size smaller than real\n");
1347 goto err_find_mode;
1348 }
1349
1350 rc = fb_alloc_cmap(&info->cmap, 256, 0);
1351 if (rc < 0) {
1352 dev_err(info->device, "cannot allocate colormap\n");
1353 goto err_alloc_cmap;
1354 }
1355
1356 rc = register_framebuffer(info);
1357 if (rc < 0) {
1358 dev_err(info->device, "cannot register framebuffer\n");
1359 goto err_reg_fb;
1360 }
1361
1362 printk(KERN_INFO "fb%d: %s on %s, %d MB RAM, %d MHz MCLK\n", info->node, info->fix.id,
1363 pci_name(dev), info->fix.smem_len >> 20, (par->mclk_freq + 500) / 1000);
1364
1365 if (par->chip == CHIP_UNKNOWN)
1366 printk(KERN_INFO "fb%d: unknown chip, CR2D=%x, CR2E=%x, CRT2F=%x, CRT30=%x\n",
1367 info->node, vga_rcrt(par->state.vgabase, 0x2d), vga_rcrt(par->state.vgabase, 0x2e),
1368 vga_rcrt(par->state.vgabase, 0x2f), vga_rcrt(par->state.vgabase, 0x30));
1369
1370 /* Record a reference to the driver data */
1371 pci_set_drvdata(dev, info);
1372
1373 #ifdef CONFIG_MTRR
1374 if (mtrr) {
1375 par->mtrr_reg = -1;
1376 par->mtrr_reg = mtrr_add(info->fix.smem_start, info->fix.smem_len, MTRR_TYPE_WRCOMB, 1);
1377 }
1378 #endif
1379
1380 return 0;
1381
1382 /* Error handling */
1383 err_reg_fb:
1384 fb_dealloc_cmap(&info->cmap);
1385 err_alloc_cmap:
1386 err_find_mode:
1387 #ifdef CONFIG_FB_S3_DDC
1388 if (par->ddc_registered)
1389 i2c_del_adapter(&par->ddc_adapter);
1390 if (par->mmio)
1391 iounmap(par->mmio);
1392 #endif
1393 pci_iounmap(dev, info->screen_base);
1394 err_iomap:
1395 pci_release_regions(dev);
1396 err_request_regions:
1397 /* pci_disable_device(dev); */
1398 err_enable_device:
1399 framebuffer_release(info);
1400 return rc;
1401 }
1402
1403
1404 /* PCI remove */
1405
1406 static void s3_pci_remove(struct pci_dev *dev)
1407 {
1408 struct fb_info *info = pci_get_drvdata(dev);
1409 struct s3fb_info __maybe_unused *par = info->par;
1410
1411 if (info) {
1412
1413 #ifdef CONFIG_MTRR
1414 if (par->mtrr_reg >= 0) {
1415 mtrr_del(par->mtrr_reg, 0, 0);
1416 par->mtrr_reg = -1;
1417 }
1418 #endif
1419
1420 unregister_framebuffer(info);
1421 fb_dealloc_cmap(&info->cmap);
1422
1423 #ifdef CONFIG_FB_S3_DDC
1424 if (par->ddc_registered)
1425 i2c_del_adapter(&par->ddc_adapter);
1426 if (par->mmio)
1427 iounmap(par->mmio);
1428 #endif
1429
1430 pci_iounmap(dev, info->screen_base);
1431 pci_release_regions(dev);
1432 /* pci_disable_device(dev); */
1433
1434 pci_set_drvdata(dev, NULL);
1435 framebuffer_release(info);
1436 }
1437 }
1438
1439 /* PCI suspend */
1440
1441 static int s3_pci_suspend(struct pci_dev* dev, pm_message_t state)
1442 {
1443 struct fb_info *info = pci_get_drvdata(dev);
1444 struct s3fb_info *par = info->par;
1445
1446 dev_info(info->device, "suspend\n");
1447
1448 console_lock();
1449 mutex_lock(&(par->open_lock));
1450
1451 if ((state.event == PM_EVENT_FREEZE) || (par->ref_count == 0)) {
1452 mutex_unlock(&(par->open_lock));
1453 console_unlock();
1454 return 0;
1455 }
1456
1457 fb_set_suspend(info, 1);
1458
1459 pci_save_state(dev);
1460 pci_disable_device(dev);
1461 pci_set_power_state(dev, pci_choose_state(dev, state));
1462
1463 mutex_unlock(&(par->open_lock));
1464 console_unlock();
1465
1466 return 0;
1467 }
1468
1469
1470 /* PCI resume */
1471
1472 static int s3_pci_resume(struct pci_dev* dev)
1473 {
1474 struct fb_info *info = pci_get_drvdata(dev);
1475 struct s3fb_info *par = info->par;
1476 int err;
1477
1478 dev_info(info->device, "resume\n");
1479
1480 console_lock();
1481 mutex_lock(&(par->open_lock));
1482
1483 if (par->ref_count == 0) {
1484 mutex_unlock(&(par->open_lock));
1485 console_unlock();
1486 return 0;
1487 }
1488
1489 pci_set_power_state(dev, PCI_D0);
1490 pci_restore_state(dev);
1491 err = pci_enable_device(dev);
1492 if (err) {
1493 mutex_unlock(&(par->open_lock));
1494 console_unlock();
1495 dev_err(info->device, "error %d enabling device for resume\n", err);
1496 return err;
1497 }
1498 pci_set_master(dev);
1499
1500 s3fb_set_par(info);
1501 fb_set_suspend(info, 0);
1502
1503 mutex_unlock(&(par->open_lock));
1504 console_unlock();
1505
1506 return 0;
1507 }
1508
1509
1510 /* List of boards that we are trying to support */
1511
1512 static struct pci_device_id s3_devices[] = {
1513 {PCI_DEVICE(PCI_VENDOR_ID_S3, 0x8810), .driver_data = CHIP_XXX_TRIO},
1514 {PCI_DEVICE(PCI_VENDOR_ID_S3, 0x8811), .driver_data = CHIP_XXX_TRIO},
1515 {PCI_DEVICE(PCI_VENDOR_ID_S3, 0x8812), .driver_data = CHIP_M65_AURORA64VP},
1516 {PCI_DEVICE(PCI_VENDOR_ID_S3, 0x8814), .driver_data = CHIP_767_TRIO64UVP},
1517 {PCI_DEVICE(PCI_VENDOR_ID_S3, 0x8901), .driver_data = CHIP_XXX_TRIO64V2_DXGX},
1518 {PCI_DEVICE(PCI_VENDOR_ID_S3, 0x8902), .driver_data = CHIP_551_PLATO_PX},
1519
1520 {PCI_DEVICE(PCI_VENDOR_ID_S3, 0x5631), .driver_data = CHIP_325_VIRGE},
1521 {PCI_DEVICE(PCI_VENDOR_ID_S3, 0x883D), .driver_data = CHIP_988_VIRGE_VX},
1522 {PCI_DEVICE(PCI_VENDOR_ID_S3, 0x8A01), .driver_data = CHIP_XXX_VIRGE_DXGX},
1523 {PCI_DEVICE(PCI_VENDOR_ID_S3, 0x8A10), .driver_data = CHIP_357_VIRGE_GX2},
1524 {PCI_DEVICE(PCI_VENDOR_ID_S3, 0x8A11), .driver_data = CHIP_359_VIRGE_GX2P},
1525 {PCI_DEVICE(PCI_VENDOR_ID_S3, 0x8A12), .driver_data = CHIP_359_VIRGE_GX2P},
1526 {PCI_DEVICE(PCI_VENDOR_ID_S3, 0x8A13), .driver_data = CHIP_36X_TRIO3D_1X_2X},
1527 {PCI_DEVICE(PCI_VENDOR_ID_S3, 0x8904), .driver_data = CHIP_365_TRIO3D},
1528 {PCI_DEVICE(PCI_VENDOR_ID_S3, 0x8C01), .driver_data = CHIP_260_VIRGE_MX},
1529
1530 {0, 0, 0, 0, 0, 0, 0}
1531 };
1532
1533
1534 MODULE_DEVICE_TABLE(pci, s3_devices);
1535
1536 static struct pci_driver s3fb_pci_driver = {
1537 .name = "s3fb",
1538 .id_table = s3_devices,
1539 .probe = s3_pci_probe,
1540 .remove = s3_pci_remove,
1541 .suspend = s3_pci_suspend,
1542 .resume = s3_pci_resume,
1543 };
1544
1545 /* Parse user specified options */
1546
1547 #ifndef MODULE
1548 static int __init s3fb_setup(char *options)
1549 {
1550 char *opt;
1551
1552 if (!options || !*options)
1553 return 0;
1554
1555 while ((opt = strsep(&options, ",")) != NULL) {
1556
1557 if (!*opt)
1558 continue;
1559 #ifdef CONFIG_MTRR
1560 else if (!strncmp(opt, "mtrr:", 5))
1561 mtrr = simple_strtoul(opt + 5, NULL, 0);
1562 #endif
1563 else if (!strncmp(opt, "fasttext:", 9))
1564 fasttext = simple_strtoul(opt + 9, NULL, 0);
1565 else
1566 mode_option = opt;
1567 }
1568
1569 return 0;
1570 }
1571 #endif
1572
1573 /* Cleanup */
1574
1575 static void __exit s3fb_cleanup(void)
1576 {
1577 pr_debug("s3fb: cleaning up\n");
1578 pci_unregister_driver(&s3fb_pci_driver);
1579 }
1580
1581 /* Driver Initialisation */
1582
1583 static int __init s3fb_init(void)
1584 {
1585
1586 #ifndef MODULE
1587 char *option = NULL;
1588
1589 if (fb_get_options("s3fb", &option))
1590 return -ENODEV;
1591 s3fb_setup(option);
1592 #endif
1593
1594 pr_debug("s3fb: initializing\n");
1595 return pci_register_driver(&s3fb_pci_driver);
1596 }
1597
1598 /* ------------------------------------------------------------------------- */
1599
1600 /* Modularization */
1601
1602 module_init(s3fb_init);
1603 module_exit(s3fb_cleanup);
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