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ethoc: fix warning from 32bit build
[linux-2.6.git] / drivers / net / ethoc.c
blob1d338c6f53146961cb8f7cdbc7e139887f2f2465
1 /*
2 * linux/drivers/net/ethoc.c
3 *
4 * Copyright (C) 2007-2008 Avionic Design Development GmbH
5 * Copyright (C) 2008-2009 Avionic Design GmbH
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 *
11 * Written by Thierry Reding <thierry.reding@avionic-design.de>
12 */
13
14 #include <linux/etherdevice.h>
15 #include <linux/crc32.h>
16 #include <linux/io.h>
17 #include <linux/mii.h>
18 #include <linux/phy.h>
19 #include <linux/platform_device.h>
20 #include <net/ethoc.h>
21
22 static int buffer_size = 0x8000; /* 32 KBytes */
23 module_param(buffer_size, int, 0);
24 MODULE_PARM_DESC(buffer_size, "DMA buffer allocation size");
25
26 /* register offsets */
27 #define MODER 0x00
28 #define INT_SOURCE 0x04
29 #define INT_MASK 0x08
30 #define IPGT 0x0c
31 #define IPGR1 0x10
32 #define IPGR2 0x14
33 #define PACKETLEN 0x18
34 #define COLLCONF 0x1c
35 #define TX_BD_NUM 0x20
36 #define CTRLMODER 0x24
37 #define MIIMODER 0x28
38 #define MIICOMMAND 0x2c
39 #define MIIADDRESS 0x30
40 #define MIITX_DATA 0x34
41 #define MIIRX_DATA 0x38
42 #define MIISTATUS 0x3c
43 #define MAC_ADDR0 0x40
44 #define MAC_ADDR1 0x44
45 #define ETH_HASH0 0x48
46 #define ETH_HASH1 0x4c
47 #define ETH_TXCTRL 0x50
48
49 /* mode register */
50 #define MODER_RXEN (1 << 0) /* receive enable */
51 #define MODER_TXEN (1 << 1) /* transmit enable */
52 #define MODER_NOPRE (1 << 2) /* no preamble */
53 #define MODER_BRO (1 << 3) /* broadcast address */
54 #define MODER_IAM (1 << 4) /* individual address mode */
55 #define MODER_PRO (1 << 5) /* promiscuous mode */
56 #define MODER_IFG (1 << 6) /* interframe gap for incoming frames */
57 #define MODER_LOOP (1 << 7) /* loopback */
58 #define MODER_NBO (1 << 8) /* no back-off */
59 #define MODER_EDE (1 << 9) /* excess defer enable */
60 #define MODER_FULLD (1 << 10) /* full duplex */
61 #define MODER_RESET (1 << 11) /* FIXME: reset (undocumented) */
62 #define MODER_DCRC (1 << 12) /* delayed CRC enable */
63 #define MODER_CRC (1 << 13) /* CRC enable */
64 #define MODER_HUGE (1 << 14) /* huge packets enable */
65 #define MODER_PAD (1 << 15) /* padding enabled */
66 #define MODER_RSM (1 << 16) /* receive small packets */
67
68 /* interrupt source and mask registers */
69 #define INT_MASK_TXF (1 << 0) /* transmit frame */
70 #define INT_MASK_TXE (1 << 1) /* transmit error */
71 #define INT_MASK_RXF (1 << 2) /* receive frame */
72 #define INT_MASK_RXE (1 << 3) /* receive error */
73 #define INT_MASK_BUSY (1 << 4)
74 #define INT_MASK_TXC (1 << 5) /* transmit control frame */
75 #define INT_MASK_RXC (1 << 6) /* receive control frame */
76
77 #define INT_MASK_TX (INT_MASK_TXF | INT_MASK_TXE)
78 #define INT_MASK_RX (INT_MASK_RXF | INT_MASK_RXE)
79
80 #define INT_MASK_ALL ( \
81 INT_MASK_TXF | INT_MASK_TXE | \
82 INT_MASK_RXF | INT_MASK_RXE | \
83 INT_MASK_TXC | INT_MASK_RXC | \
84 INT_MASK_BUSY \
85 )
86
87 /* packet length register */
88 #define PACKETLEN_MIN(min) (((min) & 0xffff) << 16)
89 #define PACKETLEN_MAX(max) (((max) & 0xffff) << 0)
90 #define PACKETLEN_MIN_MAX(min, max) (PACKETLEN_MIN(min) | \
91 PACKETLEN_MAX(max))
92
93 /* transmit buffer number register */
94 #define TX_BD_NUM_VAL(x) (((x) <= 0x80) ? (x) : 0x80)
95
96 /* control module mode register */
97 #define CTRLMODER_PASSALL (1 << 0) /* pass all receive frames */
98 #define CTRLMODER_RXFLOW (1 << 1) /* receive control flow */
99 #define CTRLMODER_TXFLOW (1 << 2) /* transmit control flow */
100
101 /* MII mode register */
102 #define MIIMODER_CLKDIV(x) ((x) & 0xfe) /* needs to be an even number */
103 #define MIIMODER_NOPRE (1 << 8) /* no preamble */
104
105 /* MII command register */
106 #define MIICOMMAND_SCAN (1 << 0) /* scan status */
107 #define MIICOMMAND_READ (1 << 1) /* read status */
108 #define MIICOMMAND_WRITE (1 << 2) /* write control data */
109
110 /* MII address register */
111 #define MIIADDRESS_FIAD(x) (((x) & 0x1f) << 0)
112 #define MIIADDRESS_RGAD(x) (((x) & 0x1f) << 8)
113 #define MIIADDRESS_ADDR(phy, reg) (MIIADDRESS_FIAD(phy) | \
114 MIIADDRESS_RGAD(reg))
115
116 /* MII transmit data register */
117 #define MIITX_DATA_VAL(x) ((x) & 0xffff)
118
119 /* MII receive data register */
120 #define MIIRX_DATA_VAL(x) ((x) & 0xffff)
121
122 /* MII status register */
123 #define MIISTATUS_LINKFAIL (1 << 0)
124 #define MIISTATUS_BUSY (1 << 1)
125 #define MIISTATUS_INVALID (1 << 2)
126
127 /* TX buffer descriptor */
128 #define TX_BD_CS (1 << 0) /* carrier sense lost */
129 #define TX_BD_DF (1 << 1) /* defer indication */
130 #define TX_BD_LC (1 << 2) /* late collision */
131 #define TX_BD_RL (1 << 3) /* retransmission limit */
132 #define TX_BD_RETRY_MASK (0x00f0)
133 #define TX_BD_RETRY(x) (((x) & 0x00f0) >> 4)
134 #define TX_BD_UR (1 << 8) /* transmitter underrun */
135 #define TX_BD_CRC (1 << 11) /* TX CRC enable */
136 #define TX_BD_PAD (1 << 12) /* pad enable for short packets */
137 #define TX_BD_WRAP (1 << 13)
138 #define TX_BD_IRQ (1 << 14) /* interrupt request enable */
139 #define TX_BD_READY (1 << 15) /* TX buffer ready */
140 #define TX_BD_LEN(x) (((x) & 0xffff) << 16)
141 #define TX_BD_LEN_MASK (0xffff << 16)
142
143 #define TX_BD_STATS (TX_BD_CS | TX_BD_DF | TX_BD_LC | \
144 TX_BD_RL | TX_BD_RETRY_MASK | TX_BD_UR)
145
146 /* RX buffer descriptor */
147 #define RX_BD_LC (1 << 0) /* late collision */
148 #define RX_BD_CRC (1 << 1) /* RX CRC error */
149 #define RX_BD_SF (1 << 2) /* short frame */
150 #define RX_BD_TL (1 << 3) /* too long */
151 #define RX_BD_DN (1 << 4) /* dribble nibble */
152 #define RX_BD_IS (1 << 5) /* invalid symbol */
153 #define RX_BD_OR (1 << 6) /* receiver overrun */
154 #define RX_BD_MISS (1 << 7)
155 #define RX_BD_CF (1 << 8) /* control frame */
156 #define RX_BD_WRAP (1 << 13)
157 #define RX_BD_IRQ (1 << 14) /* interrupt request enable */
158 #define RX_BD_EMPTY (1 << 15)
159 #define RX_BD_LEN(x) (((x) & 0xffff) << 16)
160
161 #define RX_BD_STATS (RX_BD_LC | RX_BD_CRC | RX_BD_SF | RX_BD_TL | \
162 RX_BD_DN | RX_BD_IS | RX_BD_OR | RX_BD_MISS)
163
164 #define ETHOC_BUFSIZ 1536
165 #define ETHOC_ZLEN 64
166 #define ETHOC_BD_BASE 0x400
167 #define ETHOC_TIMEOUT (HZ / 2)
168 #define ETHOC_MII_TIMEOUT (1 + (HZ / 5))
169
170 /**
171 * struct ethoc - driver-private device structure
172 * @iobase: pointer to I/O memory region
173 * @membase: pointer to buffer memory region
174 * @dma_alloc: dma allocated buffer size
175 * @num_tx: number of send buffers
176 * @cur_tx: last send buffer written
177 * @dty_tx: last buffer actually sent
178 * @num_rx: number of receive buffers
179 * @cur_rx: current receive buffer
180 * @netdev: pointer to network device structure
181 * @napi: NAPI structure
182 * @stats: network device statistics
183 * @msg_enable: device state flags
184 * @rx_lock: receive lock
185 * @lock: device lock
186 * @phy: attached PHY
187 * @mdio: MDIO bus for PHY access
188 * @phy_id: address of attached PHY
189 */
190 struct ethoc {
191 void __iomem *iobase;
192 void __iomem *membase;
193 int dma_alloc;
194
195 unsigned int num_tx;
196 unsigned int cur_tx;
197 unsigned int dty_tx;
198
199 unsigned int num_rx;
200 unsigned int cur_rx;
201
202 struct net_device *netdev;
203 struct napi_struct napi;
204 struct net_device_stats stats;
205 u32 msg_enable;
206
207 spinlock_t rx_lock;
208 spinlock_t lock;
209
210 struct phy_device *phy;
211 struct mii_bus *mdio;
212 s8 phy_id;
213 };
214
215 /**
216 * struct ethoc_bd - buffer descriptor
217 * @stat: buffer statistics
218 * @addr: physical memory address
219 */
220 struct ethoc_bd {
221 u32 stat;
222 u32 addr;
223 };
224
225 static u32 ethoc_read(struct ethoc *dev, loff_t offset)
226 {
227 return ioread32(dev->iobase + offset);
228 }
229
230 static void ethoc_write(struct ethoc *dev, loff_t offset, u32 data)
231 {
232 iowrite32(data, dev->iobase + offset);
233 }
234
235 static void ethoc_read_bd(struct ethoc *dev, int index, struct ethoc_bd *bd)
236 {
237 loff_t offset = ETHOC_BD_BASE + (index * sizeof(struct ethoc_bd));
238 bd->stat = ethoc_read(dev, offset + 0);
239 bd->addr = ethoc_read(dev, offset + 4);
240 }
241
242 static void ethoc_write_bd(struct ethoc *dev, int index,
243 const struct ethoc_bd *bd)
244 {
245 loff_t offset = ETHOC_BD_BASE + (index * sizeof(struct ethoc_bd));
246 ethoc_write(dev, offset + 0, bd->stat);
247 ethoc_write(dev, offset + 4, bd->addr);
248 }
249
250 static void ethoc_enable_irq(struct ethoc *dev, u32 mask)
251 {
252 u32 imask = ethoc_read(dev, INT_MASK);
253 imask |= mask;
254 ethoc_write(dev, INT_MASK, imask);
255 }
256
257 static void ethoc_disable_irq(struct ethoc *dev, u32 mask)
258 {
259 u32 imask = ethoc_read(dev, INT_MASK);
260 imask &= ~mask;
261 ethoc_write(dev, INT_MASK, imask);
262 }
263
264 static void ethoc_ack_irq(struct ethoc *dev, u32 mask)
265 {
266 ethoc_write(dev, INT_SOURCE, mask);
267 }
268
269 static void ethoc_enable_rx_and_tx(struct ethoc *dev)
270 {
271 u32 mode = ethoc_read(dev, MODER);
272 mode |= MODER_RXEN | MODER_TXEN;
273 ethoc_write(dev, MODER, mode);
274 }
275
276 static void ethoc_disable_rx_and_tx(struct ethoc *dev)
277 {
278 u32 mode = ethoc_read(dev, MODER);
279 mode &= ~(MODER_RXEN | MODER_TXEN);
280 ethoc_write(dev, MODER, mode);
281 }
282
283 static int ethoc_init_ring(struct ethoc *dev)
284 {
285 struct ethoc_bd bd;
286 int i;
287
288 dev->cur_tx = 0;
289 dev->dty_tx = 0;
290 dev->cur_rx = 0;
291
292 /* setup transmission buffers */
293 bd.addr = virt_to_phys(dev->membase);
294 bd.stat = TX_BD_IRQ | TX_BD_CRC;
295
296 for (i = 0; i < dev->num_tx; i++) {
297 if (i == dev->num_tx - 1)
298 bd.stat |= TX_BD_WRAP;
299
300 ethoc_write_bd(dev, i, &bd);
301 bd.addr += ETHOC_BUFSIZ;
302 }
303
304 bd.stat = RX_BD_EMPTY | RX_BD_IRQ;
305
306 for (i = 0; i < dev->num_rx; i++) {
307 if (i == dev->num_rx - 1)
308 bd.stat |= RX_BD_WRAP;
309
310 ethoc_write_bd(dev, dev->num_tx + i, &bd);
311 bd.addr += ETHOC_BUFSIZ;
312 }
313
314 return 0;
315 }
316
317 static int ethoc_reset(struct ethoc *dev)
318 {
319 u32 mode;
320
321 /* TODO: reset controller? */
322
323 ethoc_disable_rx_and_tx(dev);
324
325 /* TODO: setup registers */
326
327 /* enable FCS generation and automatic padding */
328 mode = ethoc_read(dev, MODER);
329 mode |= MODER_CRC | MODER_PAD;
330 ethoc_write(dev, MODER, mode);
331
332 /* set full-duplex mode */
333 mode = ethoc_read(dev, MODER);
334 mode |= MODER_FULLD;
335 ethoc_write(dev, MODER, mode);
336 ethoc_write(dev, IPGT, 0x15);
337
338 ethoc_ack_irq(dev, INT_MASK_ALL);
339 ethoc_enable_irq(dev, INT_MASK_ALL);
340 ethoc_enable_rx_and_tx(dev);
341 return 0;
342 }
343
344 static unsigned int ethoc_update_rx_stats(struct ethoc *dev,
345 struct ethoc_bd *bd)
346 {
347 struct net_device *netdev = dev->netdev;
348 unsigned int ret = 0;
349
350 if (bd->stat & RX_BD_TL) {
351 dev_err(&netdev->dev, "RX: frame too long\n");
352 dev->stats.rx_length_errors++;
353 ret++;
354 }
355
356 if (bd->stat & RX_BD_SF) {
357 dev_err(&netdev->dev, "RX: frame too short\n");
358 dev->stats.rx_length_errors++;
359 ret++;
360 }
361
362 if (bd->stat & RX_BD_DN) {
363 dev_err(&netdev->dev, "RX: dribble nibble\n");
364 dev->stats.rx_frame_errors++;
365 }
366
367 if (bd->stat & RX_BD_CRC) {
368 dev_err(&netdev->dev, "RX: wrong CRC\n");
369 dev->stats.rx_crc_errors++;
370 ret++;
371 }
372
373 if (bd->stat & RX_BD_OR) {
374 dev_err(&netdev->dev, "RX: overrun\n");
375 dev->stats.rx_over_errors++;
376 ret++;
377 }
378
379 if (bd->stat & RX_BD_MISS)
380 dev->stats.rx_missed_errors++;
381
382 if (bd->stat & RX_BD_LC) {
383 dev_err(&netdev->dev, "RX: late collision\n");
384 dev->stats.collisions++;
385 ret++;
386 }
387
388 return ret;
389 }
390
391 static int ethoc_rx(struct net_device *dev, int limit)
392 {
393 struct ethoc *priv = netdev_priv(dev);
394 int count;
395
396 for (count = 0; count < limit; ++count) {
397 unsigned int entry;
398 struct ethoc_bd bd;
399
400 entry = priv->num_tx + (priv->cur_rx % priv->num_rx);
401 ethoc_read_bd(priv, entry, &bd);
402 if (bd.stat & RX_BD_EMPTY)
403 break;
404
405 if (ethoc_update_rx_stats(priv, &bd) == 0) {
406 int size = bd.stat >> 16;
407 struct sk_buff *skb = netdev_alloc_skb(dev, size);
408
409 size -= 4; /* strip the CRC */
410 skb_reserve(skb, 2); /* align TCP/IP header */
411
412 if (likely(skb)) {
413 void *src = phys_to_virt(bd.addr);
414 memcpy_fromio(skb_put(skb, size), src, size);
415 skb->protocol = eth_type_trans(skb, dev);
416 priv->stats.rx_packets++;
417 priv->stats.rx_bytes += size;
418 netif_receive_skb(skb);
419 } else {
420 if (net_ratelimit())
421 dev_warn(&dev->dev, "low on memory - "
422 "packet dropped\n");
423
424 priv->stats.rx_dropped++;
425 break;
426 }
427 }
428
429 /* clear the buffer descriptor so it can be reused */
430 bd.stat &= ~RX_BD_STATS;
431 bd.stat |= RX_BD_EMPTY;
432 ethoc_write_bd(priv, entry, &bd);
433 priv->cur_rx++;
434 }
435
436 return count;
437 }
438
439 static int ethoc_update_tx_stats(struct ethoc *dev, struct ethoc_bd *bd)
440 {
441 struct net_device *netdev = dev->netdev;
442
443 if (bd->stat & TX_BD_LC) {
444 dev_err(&netdev->dev, "TX: late collision\n");
445 dev->stats.tx_window_errors++;
446 }
447
448 if (bd->stat & TX_BD_RL) {
449 dev_err(&netdev->dev, "TX: retransmit limit\n");
450 dev->stats.tx_aborted_errors++;
451 }
452
453 if (bd->stat & TX_BD_UR) {
454 dev_err(&netdev->dev, "TX: underrun\n");
455 dev->stats.tx_fifo_errors++;
456 }
457
458 if (bd->stat & TX_BD_CS) {
459 dev_err(&netdev->dev, "TX: carrier sense lost\n");
460 dev->stats.tx_carrier_errors++;
461 }
462
463 if (bd->stat & TX_BD_STATS)
464 dev->stats.tx_errors++;
465
466 dev->stats.collisions += (bd->stat >> 4) & 0xf;
467 dev->stats.tx_bytes += bd->stat >> 16;
468 dev->stats.tx_packets++;
469 return 0;
470 }
471
472 static void ethoc_tx(struct net_device *dev)
473 {
474 struct ethoc *priv = netdev_priv(dev);
475
476 spin_lock(&priv->lock);
477
478 while (priv->dty_tx != priv->cur_tx) {
479 unsigned int entry = priv->dty_tx % priv->num_tx;
480 struct ethoc_bd bd;
481
482 ethoc_read_bd(priv, entry, &bd);
483 if (bd.stat & TX_BD_READY)
484 break;
485
486 entry = (++priv->dty_tx) % priv->num_tx;
487 (void)ethoc_update_tx_stats(priv, &bd);
488 }
489
490 if ((priv->cur_tx - priv->dty_tx) <= (priv->num_tx / 2))
491 netif_wake_queue(dev);
492
493 ethoc_ack_irq(priv, INT_MASK_TX);
494 spin_unlock(&priv->lock);
495 }
496
497 static irqreturn_t ethoc_interrupt(int irq, void *dev_id)
498 {
499 struct net_device *dev = (struct net_device *)dev_id;
500 struct ethoc *priv = netdev_priv(dev);
501 u32 pending;
502
503 ethoc_disable_irq(priv, INT_MASK_ALL);
504 pending = ethoc_read(priv, INT_SOURCE);
505 if (unlikely(pending == 0)) {
506 ethoc_enable_irq(priv, INT_MASK_ALL);
507 return IRQ_NONE;
508 }
509
510 ethoc_ack_irq(priv, INT_MASK_ALL);
511
512 if (pending & INT_MASK_BUSY) {
513 dev_err(&dev->dev, "packet dropped\n");
514 priv->stats.rx_dropped++;
515 }
516
517 if (pending & INT_MASK_RX) {
518 if (napi_schedule_prep(&priv->napi))
519 __napi_schedule(&priv->napi);
520 } else {
521 ethoc_enable_irq(priv, INT_MASK_RX);
522 }
523
524 if (pending & INT_MASK_TX)
525 ethoc_tx(dev);
526
527 ethoc_enable_irq(priv, INT_MASK_ALL & ~INT_MASK_RX);
528 return IRQ_HANDLED;
529 }
530
531 static int ethoc_get_mac_address(struct net_device *dev, void *addr)
532 {
533 struct ethoc *priv = netdev_priv(dev);
534 u8 *mac = (u8 *)addr;
535 u32 reg;
536
537 reg = ethoc_read(priv, MAC_ADDR0);
538 mac[2] = (reg >> 24) & 0xff;
539 mac[3] = (reg >> 16) & 0xff;
540 mac[4] = (reg >> 8) & 0xff;
541 mac[5] = (reg >> 0) & 0xff;
542
543 reg = ethoc_read(priv, MAC_ADDR1);
544 mac[0] = (reg >> 8) & 0xff;
545 mac[1] = (reg >> 0) & 0xff;
546
547 return 0;
548 }
549
550 static int ethoc_poll(struct napi_struct *napi, int budget)
551 {
552 struct ethoc *priv = container_of(napi, struct ethoc, napi);
553 int work_done = 0;
554
555 work_done = ethoc_rx(priv->netdev, budget);
556 if (work_done < budget) {
557 ethoc_enable_irq(priv, INT_MASK_RX);
558 napi_complete(napi);
559 }
560
561 return work_done;
562 }
563
564 static int ethoc_mdio_read(struct mii_bus *bus, int phy, int reg)
565 {
566 unsigned long timeout = jiffies + ETHOC_MII_TIMEOUT;
567 struct ethoc *priv = bus->priv;
568
569 ethoc_write(priv, MIIADDRESS, MIIADDRESS_ADDR(phy, reg));
570 ethoc_write(priv, MIICOMMAND, MIICOMMAND_READ);
571
572 while (time_before(jiffies, timeout)) {
573 u32 status = ethoc_read(priv, MIISTATUS);
574 if (!(status & MIISTATUS_BUSY)) {
575 u32 data = ethoc_read(priv, MIIRX_DATA);
576 /* reset MII command register */
577 ethoc_write(priv, MIICOMMAND, 0);
578 return data;
579 }
580
581 schedule();
582 }
583
584 return -EBUSY;
585 }
586
587 static int ethoc_mdio_write(struct mii_bus *bus, int phy, int reg, u16 val)
588 {
589 unsigned long timeout = jiffies + ETHOC_MII_TIMEOUT;
590 struct ethoc *priv = bus->priv;
591
592 ethoc_write(priv, MIIADDRESS, MIIADDRESS_ADDR(phy, reg));
593 ethoc_write(priv, MIITX_DATA, val);
594 ethoc_write(priv, MIICOMMAND, MIICOMMAND_WRITE);
595
596 while (time_before(jiffies, timeout)) {
597 u32 stat = ethoc_read(priv, MIISTATUS);
598 if (!(stat & MIISTATUS_BUSY))
599 return 0;
600
601 schedule();
602 }
603
604 return -EBUSY;
605 }
606
607 static int ethoc_mdio_reset(struct mii_bus *bus)
608 {
609 return 0;
610 }
611
612 static void ethoc_mdio_poll(struct net_device *dev)
613 {
614 }
615
616 static int ethoc_mdio_probe(struct net_device *dev)
617 {
618 struct ethoc *priv = netdev_priv(dev);
619 struct phy_device *phy;
620 int i;
621
622 for (i = 0; i < PHY_MAX_ADDR; i++) {
623 phy = priv->mdio->phy_map[i];
624 if (phy) {
625 if (priv->phy_id != -1) {
626 /* attach to specified PHY */
627 if (priv->phy_id == phy->addr)
628 break;
629 } else {
630 /* autoselect PHY if none was specified */
631 if (phy->addr != 0)
632 break;
633 }
634 }
635 }
636
637 if (!phy) {
638 dev_err(&dev->dev, "no PHY found\n");
639 return -ENXIO;
640 }
641
642 phy = phy_connect(dev, dev_name(&phy->dev), &ethoc_mdio_poll, 0,
643 PHY_INTERFACE_MODE_GMII);
644 if (IS_ERR(phy)) {
645 dev_err(&dev->dev, "could not attach to PHY\n");
646 return PTR_ERR(phy);
647 }
648
649 priv->phy = phy;
650 return 0;
651 }
652
653 static int ethoc_open(struct net_device *dev)
654 {
655 struct ethoc *priv = netdev_priv(dev);
656 unsigned int min_tx = 2;
657 unsigned int num_bd;
658 int ret;
659
660 ret = request_irq(dev->irq, ethoc_interrupt, IRQF_SHARED,
661 dev->name, dev);
662 if (ret)
663 return ret;
664
665 /* calculate the number of TX/RX buffers, maximum 128 supported */
666 num_bd = min_t(unsigned int,
667 128, (dev->mem_end - dev->mem_start + 1) / ETHOC_BUFSIZ);
668 priv->num_tx = max(min_tx, num_bd / 4);
669 priv->num_rx = num_bd - priv->num_tx;
670 ethoc_write(priv, TX_BD_NUM, priv->num_tx);
671
672 ethoc_init_ring(priv);
673 ethoc_reset(priv);
674
675 if (netif_queue_stopped(dev)) {
676 dev_dbg(&dev->dev, " resuming queue\n");
677 netif_wake_queue(dev);
678 } else {
679 dev_dbg(&dev->dev, " starting queue\n");
680 netif_start_queue(dev);
681 }
682
683 phy_start(priv->phy);
684 napi_enable(&priv->napi);
685
686 if (netif_msg_ifup(priv)) {
687 dev_info(&dev->dev, "I/O: %08lx Memory: %08lx-%08lx\n",
688 dev->base_addr, dev->mem_start, dev->mem_end);
689 }
690
691 return 0;
692 }
693
694 static int ethoc_stop(struct net_device *dev)
695 {
696 struct ethoc *priv = netdev_priv(dev);
697
698 napi_disable(&priv->napi);
699
700 if (priv->phy)
701 phy_stop(priv->phy);
702
703 ethoc_disable_rx_and_tx(priv);
704 free_irq(dev->irq, dev);
705
706 if (!netif_queue_stopped(dev))
707 netif_stop_queue(dev);
708
709 return 0;
710 }
711
712 static int ethoc_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
713 {
714 struct ethoc *priv = netdev_priv(dev);
715 struct mii_ioctl_data *mdio = if_mii(ifr);
716 struct phy_device *phy = NULL;
717
718 if (!netif_running(dev))
719 return -EINVAL;
720
721 if (cmd != SIOCGMIIPHY) {
722 if (mdio->phy_id >= PHY_MAX_ADDR)
723 return -ERANGE;
724
725 phy = priv->mdio->phy_map[mdio->phy_id];
726 if (!phy)
727 return -ENODEV;
728 } else {
729 phy = priv->phy;
730 }
731
732 return phy_mii_ioctl(phy, mdio, cmd);
733 }
734
735 static int ethoc_config(struct net_device *dev, struct ifmap *map)
736 {
737 return -ENOSYS;
738 }
739
740 static int ethoc_set_mac_address(struct net_device *dev, void *addr)
741 {
742 struct ethoc *priv = netdev_priv(dev);
743 u8 *mac = (u8 *)addr;
744
745 ethoc_write(priv, MAC_ADDR0, (mac[2] << 24) | (mac[3] << 16) |
746 (mac[4] << 8) | (mac[5] << 0));
747 ethoc_write(priv, MAC_ADDR1, (mac[0] << 8) | (mac[1] << 0));
748
749 return 0;
750 }
751
752 static void ethoc_set_multicast_list(struct net_device *dev)
753 {
754 struct ethoc *priv = netdev_priv(dev);
755 u32 mode = ethoc_read(priv, MODER);
756 struct dev_mc_list *mc = NULL;
757 u32 hash[2] = { 0, 0 };
758
759 /* set loopback mode if requested */
760 if (dev->flags & IFF_LOOPBACK)
761 mode |= MODER_LOOP;
762 else
763 mode &= ~MODER_LOOP;
764
765 /* receive broadcast frames if requested */
766 if (dev->flags & IFF_BROADCAST)
767 mode &= ~MODER_BRO;
768 else
769 mode |= MODER_BRO;
770
771 /* enable promiscuous mode if requested */
772 if (dev->flags & IFF_PROMISC)
773 mode |= MODER_PRO;
774 else
775 mode &= ~MODER_PRO;
776
777 ethoc_write(priv, MODER, mode);
778
779 /* receive multicast frames */
780 if (dev->flags & IFF_ALLMULTI) {
781 hash[0] = 0xffffffff;
782 hash[1] = 0xffffffff;
783 } else {
784 for (mc = dev->mc_list; mc; mc = mc->next) {
785 u32 crc = ether_crc(mc->dmi_addrlen, mc->dmi_addr);
786 int bit = (crc >> 26) & 0x3f;
787 hash[bit >> 5] |= 1 << (bit & 0x1f);
788 }
789 }
790
791 ethoc_write(priv, ETH_HASH0, hash[0]);
792 ethoc_write(priv, ETH_HASH1, hash[1]);
793 }
794
795 static int ethoc_change_mtu(struct net_device *dev, int new_mtu)
796 {
797 return -ENOSYS;
798 }
799
800 static void ethoc_tx_timeout(struct net_device *dev)
801 {
802 struct ethoc *priv = netdev_priv(dev);
803 u32 pending = ethoc_read(priv, INT_SOURCE);
804 if (likely(pending))
805 ethoc_interrupt(dev->irq, dev);
806 }
807
808 static struct net_device_stats *ethoc_stats(struct net_device *dev)
809 {
810 struct ethoc *priv = netdev_priv(dev);
811 return &priv->stats;
812 }
813
814 static netdev_tx_t ethoc_start_xmit(struct sk_buff *skb, struct net_device *dev)
815 {
816 struct ethoc *priv = netdev_priv(dev);
817 struct ethoc_bd bd;
818 unsigned int entry;
819 void *dest;
820
821 if (unlikely(skb->len > ETHOC_BUFSIZ)) {
822 priv->stats.tx_errors++;
823 goto out;
824 }
825
826 entry = priv->cur_tx % priv->num_tx;
827 spin_lock_irq(&priv->lock);
828 priv->cur_tx++;
829
830 ethoc_read_bd(priv, entry, &bd);
831 if (unlikely(skb->len < ETHOC_ZLEN))
832 bd.stat |= TX_BD_PAD;
833 else
834 bd.stat &= ~TX_BD_PAD;
835
836 dest = phys_to_virt(bd.addr);
837 memcpy_toio(dest, skb->data, skb->len);
838
839 bd.stat &= ~(TX_BD_STATS | TX_BD_LEN_MASK);
840 bd.stat |= TX_BD_LEN(skb->len);
841 ethoc_write_bd(priv, entry, &bd);
842
843 bd.stat |= TX_BD_READY;
844 ethoc_write_bd(priv, entry, &bd);
845
846 if (priv->cur_tx == (priv->dty_tx + priv->num_tx)) {
847 dev_dbg(&dev->dev, "stopping queue\n");
848 netif_stop_queue(dev);
849 }
850
851 dev->trans_start = jiffies;
852 spin_unlock_irq(&priv->lock);
853 out:
854 dev_kfree_skb(skb);
855 return NETDEV_TX_OK;
856 }
857
858 static const struct net_device_ops ethoc_netdev_ops = {
859 .ndo_open = ethoc_open,
860 .ndo_stop = ethoc_stop,
861 .ndo_do_ioctl = ethoc_ioctl,
862 .ndo_set_config = ethoc_config,
863 .ndo_set_mac_address = ethoc_set_mac_address,
864 .ndo_set_multicast_list = ethoc_set_multicast_list,
865 .ndo_change_mtu = ethoc_change_mtu,
866 .ndo_tx_timeout = ethoc_tx_timeout,
867 .ndo_get_stats = ethoc_stats,
868 .ndo_start_xmit = ethoc_start_xmit,
869 };
870
871 /**
872 * ethoc_probe() - initialize OpenCores ethernet MAC
873 * pdev: platform device
874 */
875 static int ethoc_probe(struct platform_device *pdev)
876 {
877 struct net_device *netdev = NULL;
878 struct resource *res = NULL;
879 struct resource *mmio = NULL;
880 struct resource *mem = NULL;
881 struct ethoc *priv = NULL;
882 unsigned int phy;
883 int ret = 0;
884
885 /* allocate networking device */
886 netdev = alloc_etherdev(sizeof(struct ethoc));
887 if (!netdev) {
888 dev_err(&pdev->dev, "cannot allocate network device\n");
889 ret = -ENOMEM;
890 goto out;
891 }
892
893 SET_NETDEV_DEV(netdev, &pdev->dev);
894 platform_set_drvdata(pdev, netdev);
895
896 /* obtain I/O memory space */
897 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
898 if (!res) {
899 dev_err(&pdev->dev, "cannot obtain I/O memory space\n");
900 ret = -ENXIO;
901 goto free;
902 }
903
904 mmio = devm_request_mem_region(&pdev->dev, res->start,
905 res->end - res->start + 1, res->name);
906 if (!mmio) {
907 dev_err(&pdev->dev, "cannot request I/O memory space\n");
908 ret = -ENXIO;
909 goto free;
910 }
911
912 netdev->base_addr = mmio->start;
913
914 /* obtain buffer memory space */
915 res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
916 if (res) {
917 mem = devm_request_mem_region(&pdev->dev, res->start,
918 res->end - res->start + 1, res->name);
919 if (!mem) {
920 dev_err(&pdev->dev, "cannot request memory space\n");
921 ret = -ENXIO;
922 goto free;
923 }
924
925 netdev->mem_start = mem->start;
926 netdev->mem_end = mem->end;
927 }
928
929
930 /* obtain device IRQ number */
931 res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
932 if (!res) {
933 dev_err(&pdev->dev, "cannot obtain IRQ\n");
934 ret = -ENXIO;
935 goto free;
936 }
937
938 netdev->irq = res->start;
939
940 /* setup driver-private data */
941 priv = netdev_priv(netdev);
942 priv->netdev = netdev;
943 priv->dma_alloc = 0;
944
945 priv->iobase = devm_ioremap_nocache(&pdev->dev, netdev->base_addr,
946 mmio->end - mmio->start + 1);
947 if (!priv->iobase) {
948 dev_err(&pdev->dev, "cannot remap I/O memory space\n");
949 ret = -ENXIO;
950 goto error;
951 }
952
953 if (netdev->mem_end) {
954 priv->membase = devm_ioremap_nocache(&pdev->dev,
955 netdev->mem_start, mem->end - mem->start + 1);
956 if (!priv->membase) {
957 dev_err(&pdev->dev, "cannot remap memory space\n");
958 ret = -ENXIO;
959 goto error;
960 }
961 } else {
962 /* Allocate buffer memory */
963 priv->membase = dma_alloc_coherent(NULL,
964 buffer_size, (void *)&netdev->mem_start,
965 GFP_KERNEL);
966 if (!priv->membase) {
967 dev_err(&pdev->dev, "cannot allocate %dB buffer\n",
968 buffer_size);
969 ret = -ENOMEM;
970 goto error;
971 }
972 netdev->mem_end = netdev->mem_start + buffer_size;
973 priv->dma_alloc = buffer_size;
974 }
975
976 /* Allow the platform setup code to pass in a MAC address. */
977 if (pdev->dev.platform_data) {
978 struct ethoc_platform_data *pdata =
979 (struct ethoc_platform_data *)pdev->dev.platform_data;
980 memcpy(netdev->dev_addr, pdata->hwaddr, IFHWADDRLEN);
981 priv->phy_id = pdata->phy_id;
982 }
983
984 /* Check that the given MAC address is valid. If it isn't, read the
985 * current MAC from the controller. */
986 if (!is_valid_ether_addr(netdev->dev_addr))
987 ethoc_get_mac_address(netdev, netdev->dev_addr);
988
989 /* Check the MAC again for validity, if it still isn't choose and
990 * program a random one. */
991 if (!is_valid_ether_addr(netdev->dev_addr))
992 random_ether_addr(netdev->dev_addr);
993
994 ethoc_set_mac_address(netdev, netdev->dev_addr);
995
996 /* register MII bus */
997 priv->mdio = mdiobus_alloc();
998 if (!priv->mdio) {
999 ret = -ENOMEM;
1000 goto free;
1001 }
1002
1003 priv->mdio->name = "ethoc-mdio";
1004 snprintf(priv->mdio->id, MII_BUS_ID_SIZE, "%s-%d",
1005 priv->mdio->name, pdev->id);
1006 priv->mdio->read = ethoc_mdio_read;
1007 priv->mdio->write = ethoc_mdio_write;
1008 priv->mdio->reset = ethoc_mdio_reset;
1009 priv->mdio->priv = priv;
1010
1011 priv->mdio->irq = kmalloc(sizeof(int) * PHY_MAX_ADDR, GFP_KERNEL);
1012 if (!priv->mdio->irq) {
1013 ret = -ENOMEM;
1014 goto free_mdio;
1015 }
1016
1017 for (phy = 0; phy < PHY_MAX_ADDR; phy++)
1018 priv->mdio->irq[phy] = PHY_POLL;
1019
1020 ret = mdiobus_register(priv->mdio);
1021 if (ret) {
1022 dev_err(&netdev->dev, "failed to register MDIO bus\n");
1023 goto free_mdio;
1024 }
1025
1026 ret = ethoc_mdio_probe(netdev);
1027 if (ret) {
1028 dev_err(&netdev->dev, "failed to probe MDIO bus\n");
1029 goto error;
1030 }
1031
1032 ether_setup(netdev);
1033
1034 /* setup the net_device structure */
1035 netdev->netdev_ops = &ethoc_netdev_ops;
1036 netdev->watchdog_timeo = ETHOC_TIMEOUT;
1037 netdev->features |= 0;
1038
1039 /* setup NAPI */
1040 memset(&priv->napi, 0, sizeof(priv->napi));
1041 netif_napi_add(netdev, &priv->napi, ethoc_poll, 64);
1042
1043 spin_lock_init(&priv->rx_lock);
1044 spin_lock_init(&priv->lock);
1045
1046 ret = register_netdev(netdev);
1047 if (ret < 0) {
1048 dev_err(&netdev->dev, "failed to register interface\n");
1049 goto error;
1050 }
1051
1052 goto out;
1053
1054 error:
1055 mdiobus_unregister(priv->mdio);
1056 free_mdio:
1057 kfree(priv->mdio->irq);
1058 mdiobus_free(priv->mdio);
1059 free:
1060 if (priv->dma_alloc)
1061 dma_free_coherent(NULL, priv->dma_alloc, priv->membase,
1062 netdev->mem_start);
1063 free_netdev(netdev);
1064 out:
1065 return ret;
1066 }
1067
1068 /**
1069 * ethoc_remove() - shutdown OpenCores ethernet MAC
1070 * @pdev: platform device
1071 */
1072 static int ethoc_remove(struct platform_device *pdev)
1073 {
1074 struct net_device *netdev = platform_get_drvdata(pdev);
1075 struct ethoc *priv = netdev_priv(netdev);
1076
1077 platform_set_drvdata(pdev, NULL);
1078
1079 if (netdev) {
1080 phy_disconnect(priv->phy);
1081 priv->phy = NULL;
1082
1083 if (priv->mdio) {
1084 mdiobus_unregister(priv->mdio);
1085 kfree(priv->mdio->irq);
1086 mdiobus_free(priv->mdio);
1087 }
1088 if (priv->dma_alloc)
1089 dma_free_coherent(NULL, priv->dma_alloc, priv->membase,
1090 netdev->mem_start);
1091 unregister_netdev(netdev);
1092 free_netdev(netdev);
1093 }
1094
1095 return 0;
1096 }
1097
1098 #ifdef CONFIG_PM
1099 static int ethoc_suspend(struct platform_device *pdev, pm_message_t state)
1100 {
1101 return -ENOSYS;
1102 }
1103
1104 static int ethoc_resume(struct platform_device *pdev)
1105 {
1106 return -ENOSYS;
1107 }
1108 #else
1109 # define ethoc_suspend NULL
1110 # define ethoc_resume NULL
1111 #endif
1112
1113 static struct platform_driver ethoc_driver = {
1114 .probe = ethoc_probe,
1115 .remove = ethoc_remove,
1116 .suspend = ethoc_suspend,
1117 .resume = ethoc_resume,
1118 .driver = {
1119 .name = "ethoc",
1120 },
1121 };
1122
1123 static int __init ethoc_init(void)
1124 {
1125 return platform_driver_register(&ethoc_driver);
1126 }
1127
1128 static void __exit ethoc_exit(void)
1129 {
1130 platform_driver_unregister(&ethoc_driver);
1131 }
1132
1133 module_init(ethoc_init);
1134 module_exit(ethoc_exit);
1135
1136 MODULE_AUTHOR("Thierry Reding <thierry.reding@avionic-design.de>");
1137 MODULE_DESCRIPTION("OpenCores Ethernet MAC driver");
1138 MODULE_LICENSE("GPL v2");
1139
Linus' kernel tree