1 /*******************************************************************************
2 STMMAC Common Header File
4 Copyright (C) 2007-2009 STMicroelectronics Ltd
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
22 Author: Giuseppe Cavallaro <peppe.cavallaro@st.com>
23 *******************************************************************************/
26 #include <linux/netdevice.h>
28 struct stmmac_extra_stats
{
30 unsigned long tx_underflow ____cacheline_aligned
;
31 unsigned long tx_carrier
;
32 unsigned long tx_losscarrier
;
33 unsigned long tx_heartbeat
;
34 unsigned long tx_deferred
;
35 unsigned long tx_vlan
;
36 unsigned long tx_jabber
;
37 unsigned long tx_frame_flushed
;
38 unsigned long tx_payload_error
;
39 unsigned long tx_ip_header_error
;
41 unsigned long rx_desc
;
42 unsigned long rx_partial
;
43 unsigned long rx_runt
;
44 unsigned long rx_toolong
;
45 unsigned long rx_collision
;
47 unsigned long rx_length
;
49 unsigned long rx_multicast
;
50 unsigned long rx_gmac_overflow
;
51 unsigned long rx_watchdog
;
52 unsigned long da_rx_filter_fail
;
53 unsigned long sa_rx_filter_fail
;
54 unsigned long rx_missed_cntr
;
55 unsigned long rx_overflow_cntr
;
56 unsigned long rx_vlan
;
57 /* Tx/Rx IRQ errors */
58 unsigned long tx_undeflow_irq
;
59 unsigned long tx_process_stopped_irq
;
60 unsigned long tx_jabber_irq
;
61 unsigned long rx_overflow_irq
;
62 unsigned long rx_buf_unav_irq
;
63 unsigned long rx_process_stopped_irq
;
64 unsigned long rx_watchdog_irq
;
65 unsigned long tx_early_irq
;
66 unsigned long fatal_bus_error_irq
;
68 unsigned long threshold
;
69 unsigned long tx_pkt_n
;
70 unsigned long rx_pkt_n
;
72 unsigned long sched_timer_n
;
73 unsigned long normal_irq_n
;
76 #define HASH_TABLE_SIZE 64
77 #define PAUSE_TIME 0x200
79 /* Flow Control defines */
83 #define FLOW_AUTO (FLOW_TX | FLOW_RX)
85 #define SF_DMA_MODE 1 /* DMA STORE-AND-FORWARD Operation Mode */
89 enum rx_frame_status
{ /* IPC status */
95 enum tx_dma_irq_status
{
97 tx_hard_error_bump_tc
= 2,
101 /* GMAC TX FIFO is 8K, Rx FIFO is 16K */
102 #define BUF_SIZE_16KiB 16384
103 #define BUF_SIZE_8KiB 8192
104 #define BUF_SIZE_4KiB 4096
105 #define BUF_SIZE_2KiB 2048
107 /* Power Down and WOL */
108 #define PMT_NOT_SUPPORTED 0
109 #define PMT_SUPPORTED 1
111 /* Common MAC defines */
112 #define MAC_CTRL_REG 0x00000000 /* MAC Control */
113 #define MAC_ENABLE_TX 0x00000008 /* Transmitter Enable */
114 #define MAC_RNABLE_RX 0x00000004 /* Receiver Enable */
116 /* MAC Management Counters register */
117 #define MMC_CONTROL 0x00000100 /* MMC Control */
118 #define MMC_HIGH_INTR 0x00000104 /* MMC High Interrupt */
119 #define MMC_LOW_INTR 0x00000108 /* MMC Low Interrupt */
120 #define MMC_HIGH_INTR_MASK 0x0000010c /* MMC High Interrupt Mask */
121 #define MMC_LOW_INTR_MASK 0x00000110 /* MMC Low Interrupt Mask */
123 #define MMC_CONTROL_MAX_FRM_MASK 0x0003ff8 /* Maximum Frame Size */
124 #define MMC_CONTROL_MAX_FRM_SHIFT 3
125 #define MMC_CONTROL_MAX_FRAME 0x7FF
127 struct stmmac_desc_ops
{
128 /* DMA RX descriptor ring initialization */
129 void (*init_rx_desc
) (struct dma_desc
*p
, unsigned int ring_size
,
131 /* DMA TX descriptor ring initialization */
132 void (*init_tx_desc
) (struct dma_desc
*p
, unsigned int ring_size
);
134 /* Invoked by the xmit function to prepare the tx descriptor */
135 void (*prepare_tx_desc
) (struct dma_desc
*p
, int is_fs
, int len
,
137 /* Set/get the owner of the descriptor */
138 void (*set_tx_owner
) (struct dma_desc
*p
);
139 int (*get_tx_owner
) (struct dma_desc
*p
);
140 /* Invoked by the xmit function to close the tx descriptor */
141 void (*close_tx_desc
) (struct dma_desc
*p
);
142 /* Clean the tx descriptor as soon as the tx irq is received */
143 void (*release_tx_desc
) (struct dma_desc
*p
);
144 /* Clear interrupt on tx frame completion. When this bit is
145 * set an interrupt happens as soon as the frame is transmitted */
146 void (*clear_tx_ic
) (struct dma_desc
*p
);
147 /* Last tx segment reports the transmit status */
148 int (*get_tx_ls
) (struct dma_desc
*p
);
149 /* Return the transmit status looking at the TDES1 */
150 int (*tx_status
) (void *data
, struct stmmac_extra_stats
*x
,
151 struct dma_desc
*p
, unsigned long ioaddr
);
152 /* Get the buffer size from the descriptor */
153 int (*get_tx_len
) (struct dma_desc
*p
);
154 /* Handle extra events on specific interrupts hw dependent */
155 int (*get_rx_owner
) (struct dma_desc
*p
);
156 void (*set_rx_owner
) (struct dma_desc
*p
);
157 /* Get the receive frame size */
158 int (*get_rx_frame_len
) (struct dma_desc
*p
);
159 /* Return the reception status looking at the RDES1 */
160 int (*rx_status
) (void *data
, struct stmmac_extra_stats
*x
,
164 struct stmmac_dma_ops
{
165 /* DMA core initialization */
166 int (*init
) (unsigned long ioaddr
, int pbl
, u32 dma_tx
, u32 dma_rx
);
167 /* Dump DMA registers */
168 void (*dump_regs
) (unsigned long ioaddr
);
169 /* Set tx/rx threshold in the csr6 register
170 * An invalid value enables the store-and-forward mode */
171 void (*dma_mode
) (unsigned long ioaddr
, int txmode
, int rxmode
);
172 /* To track extra statistic (if supported) */
173 void (*dma_diagnostic_fr
) (void *data
, struct stmmac_extra_stats
*x
,
174 unsigned long ioaddr
);
175 void (*enable_dma_transmission
) (unsigned long ioaddr
);
176 void (*enable_dma_irq
) (unsigned long ioaddr
);
177 void (*disable_dma_irq
) (unsigned long ioaddr
);
178 void (*start_tx
) (unsigned long ioaddr
);
179 void (*stop_tx
) (unsigned long ioaddr
);
180 void (*start_rx
) (unsigned long ioaddr
);
181 void (*stop_rx
) (unsigned long ioaddr
);
182 int (*dma_interrupt
) (unsigned long ioaddr
,
183 struct stmmac_extra_stats
*x
);
187 /* MAC core initialization */
188 void (*core_init
) (unsigned long ioaddr
) ____cacheline_aligned
;
189 /* Dump MAC registers */
190 void (*dump_regs
) (unsigned long ioaddr
);
191 /* Handle extra events on specific interrupts hw dependent */
192 void (*host_irq_status
) (unsigned long ioaddr
);
193 /* Multicast filter setting */
194 void (*set_filter
) (struct net_device
*dev
);
195 /* Flow control setting */
196 void (*flow_ctrl
) (unsigned long ioaddr
, unsigned int duplex
,
197 unsigned int fc
, unsigned int pause_time
);
198 /* Set power management mode (e.g. magic frame) */
199 void (*pmt
) (unsigned long ioaddr
, unsigned long mode
);
200 /* Set/Get Unicast MAC addresses */
201 void (*set_umac_addr
) (unsigned long ioaddr
, unsigned char *addr
,
203 void (*get_umac_addr
) (unsigned long ioaddr
, unsigned char *addr
,
214 unsigned int addr
; /* MII Address */
215 unsigned int data
; /* MII Data */
218 struct mac_device_info
{
219 struct stmmac_ops
*mac
;
220 struct stmmac_desc_ops
*desc
;
221 struct stmmac_dma_ops
*dma
;
222 unsigned int pmt
; /* support Power-Down */
223 struct mii_regs mii
; /* MII register Addresses */
224 struct mac_link link
;
227 struct mac_device_info
*dwmac1000_setup(unsigned long addr
);
228 struct mac_device_info
*dwmac100_setup(unsigned long addr
);
230 extern void stmmac_set_mac_addr(unsigned long ioaddr
, u8 addr
[6],
231 unsigned int high
, unsigned int low
);
232 extern void stmmac_get_mac_addr(unsigned long ioaddr
, unsigned char *addr
,
233 unsigned int high
, unsigned int low
);