2 * Fast Ethernet Controller (FEC) driver for Motorola MPC8xx.
3 * Copyright (c) 1997 Dan Malek (dmalek@jlc.net)
5 * Right now, I am very wasteful with the buffers. I allocate memory
6 * pages and then divide them into 2K frame buffers. This way I know I
7 * have buffers large enough to hold one frame within one buffer descriptor.
8 * Once I get this working, I will use 64 or 128 byte CPM buffers, which
9 * will be much more memory efficient and will easily handle lots of
12 * Much better multiple PHY support by Magnus Damm.
13 * Copyright (c) 2000 Ericsson Radio Systems AB.
15 * Support for FEC controller of ColdFire processors.
16 * Copyright (c) 2001-2005 Greg Ungerer (gerg@snapgear.com)
18 * Bug fixes and cleanup by Philippe De Muyter (phdm@macqel.be)
19 * Copyright (c) 2004-2006 Macq Electronique SA.
22 #include <linux/module.h>
23 #include <linux/kernel.h>
24 #include <linux/string.h>
25 #include <linux/ptrace.h>
26 #include <linux/errno.h>
27 #include <linux/ioport.h>
28 #include <linux/slab.h>
29 #include <linux/interrupt.h>
30 #include <linux/pci.h>
31 #include <linux/init.h>
32 #include <linux/delay.h>
33 #include <linux/netdevice.h>
34 #include <linux/etherdevice.h>
35 #include <linux/skbuff.h>
36 #include <linux/spinlock.h>
37 #include <linux/workqueue.h>
38 #include <linux/bitops.h>
40 #include <linux/irq.h>
41 #include <linux/clk.h>
42 #include <linux/platform_device.h>
44 #include <asm/cacheflush.h>
46 #ifndef CONFIG_ARCH_MXC
47 #include <asm/coldfire.h>
48 #include <asm/mcfsim.h>
53 #ifdef CONFIG_ARCH_MXC
54 #include <mach/hardware.h>
55 #define FEC_ALIGNMENT 0xf
57 #define FEC_ALIGNMENT 0x3
61 * Define the fixed address of the FEC hardware.
63 #if defined(CONFIG_M5272)
64 #define HAVE_mii_link_interrupt
66 static unsigned char fec_mac_default
[] = {
67 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
71 * Some hardware gets it MAC address out of local flash memory.
72 * if this is non-zero then assume it is the address to get MAC from.
74 #if defined(CONFIG_NETtel)
75 #define FEC_FLASHMAC 0xf0006006
76 #elif defined(CONFIG_GILBARCONAP) || defined(CONFIG_SCALES)
77 #define FEC_FLASHMAC 0xf0006000
78 #elif defined(CONFIG_CANCam)
79 #define FEC_FLASHMAC 0xf0020000
80 #elif defined (CONFIG_M5272C3)
81 #define FEC_FLASHMAC (0xffe04000 + 4)
82 #elif defined(CONFIG_MOD5272)
83 #define FEC_FLASHMAC 0xffc0406b
85 #define FEC_FLASHMAC 0
87 #endif /* CONFIG_M5272 */
89 /* Forward declarations of some structures to support different PHYs */
93 void (*funct
)(uint mii_reg
, struct net_device
*dev
);
100 const phy_cmd_t
*config
;
101 const phy_cmd_t
*startup
;
102 const phy_cmd_t
*ack_int
;
103 const phy_cmd_t
*shutdown
;
106 /* The number of Tx and Rx buffers. These are allocated from the page
107 * pool. The code may assume these are power of two, so it it best
108 * to keep them that size.
109 * We don't need to allocate pages for the transmitter. We just use
110 * the skbuffer directly.
112 #define FEC_ENET_RX_PAGES 8
113 #define FEC_ENET_RX_FRSIZE 2048
114 #define FEC_ENET_RX_FRPPG (PAGE_SIZE / FEC_ENET_RX_FRSIZE)
115 #define RX_RING_SIZE (FEC_ENET_RX_FRPPG * FEC_ENET_RX_PAGES)
116 #define FEC_ENET_TX_FRSIZE 2048
117 #define FEC_ENET_TX_FRPPG (PAGE_SIZE / FEC_ENET_TX_FRSIZE)
118 #define TX_RING_SIZE 16 /* Must be power of two */
119 #define TX_RING_MOD_MASK 15 /* for this to work */
121 #if (((RX_RING_SIZE + TX_RING_SIZE) * 8) > PAGE_SIZE)
122 #error "FEC: descriptor ring size constants too large"
125 /* Interrupt events/masks. */
126 #define FEC_ENET_HBERR ((uint)0x80000000) /* Heartbeat error */
127 #define FEC_ENET_BABR ((uint)0x40000000) /* Babbling receiver */
128 #define FEC_ENET_BABT ((uint)0x20000000) /* Babbling transmitter */
129 #define FEC_ENET_GRA ((uint)0x10000000) /* Graceful stop complete */
130 #define FEC_ENET_TXF ((uint)0x08000000) /* Full frame transmitted */
131 #define FEC_ENET_TXB ((uint)0x04000000) /* A buffer was transmitted */
132 #define FEC_ENET_RXF ((uint)0x02000000) /* Full frame received */
133 #define FEC_ENET_RXB ((uint)0x01000000) /* A buffer was received */
134 #define FEC_ENET_MII ((uint)0x00800000) /* MII interrupt */
135 #define FEC_ENET_EBERR ((uint)0x00400000) /* SDMA bus error */
137 /* The FEC stores dest/src/type, data, and checksum for receive packets.
139 #define PKT_MAXBUF_SIZE 1518
140 #define PKT_MINBUF_SIZE 64
141 #define PKT_MAXBLR_SIZE 1520
145 * The 5270/5271/5280/5282/532x RX control register also contains maximum frame
146 * size bits. Other FEC hardware does not, so we need to take that into
147 * account when setting it.
149 #if defined(CONFIG_M523x) || defined(CONFIG_M527x) || defined(CONFIG_M528x) || \
150 defined(CONFIG_M520x) || defined(CONFIG_M532x) || defined(CONFIG_ARCH_MXC)
151 #define OPT_FRAME_SIZE (PKT_MAXBUF_SIZE << 16)
153 #define OPT_FRAME_SIZE 0
156 /* The FEC buffer descriptors track the ring buffers. The rx_bd_base and
157 * tx_bd_base always point to the base of the buffer descriptors. The
158 * cur_rx and cur_tx point to the currently available buffer.
159 * The dirty_tx tracks the current buffer that is being sent by the
160 * controller. The cur_tx and dirty_tx are equal under both completely
161 * empty and completely full conditions. The empty/ready indicator in
162 * the buffer descriptor determines the actual condition.
164 struct fec_enet_private
{
165 /* Hardware registers of the FEC device */
168 struct net_device
*netdev
;
172 /* The saved address of a sent-in-place packet/buffer, for skfree(). */
173 unsigned char *tx_bounce
[TX_RING_SIZE
];
174 struct sk_buff
* tx_skbuff
[TX_RING_SIZE
];
175 struct sk_buff
* rx_skbuff
[RX_RING_SIZE
];
179 /* CPM dual port RAM relative addresses */
181 /* Address of Rx and Tx buffers */
182 struct bufdesc
*rx_bd_base
;
183 struct bufdesc
*tx_bd_base
;
184 /* The next free ring entry */
185 struct bufdesc
*cur_rx
, *cur_tx
;
186 /* The ring entries to be free()ed */
187 struct bufdesc
*dirty_tx
;
190 /* hold while accessing the HW like ringbuffer for tx/rx but not MAC */
192 /* hold while accessing the mii_list_t() elements */
199 phy_info_t
const *phy
;
200 struct work_struct phy_task
;
203 uint mii_phy_task_queued
;
214 static void fec_enet_mii(struct net_device
*dev
);
215 static irqreturn_t
fec_enet_interrupt(int irq
, void * dev_id
);
216 static void fec_enet_tx(struct net_device
*dev
);
217 static void fec_enet_rx(struct net_device
*dev
);
218 static int fec_enet_close(struct net_device
*dev
);
219 static void fec_restart(struct net_device
*dev
, int duplex
);
220 static void fec_stop(struct net_device
*dev
);
223 /* MII processing. We keep this as simple as possible. Requests are
224 * placed on the list (if there is room). When the request is finished
225 * by the MII, an optional function may be called.
227 typedef struct mii_list
{
229 void (*mii_func
)(uint val
, struct net_device
*dev
);
230 struct mii_list
*mii_next
;
234 static mii_list_t mii_cmds
[NMII
];
235 static mii_list_t
*mii_free
;
236 static mii_list_t
*mii_head
;
237 static mii_list_t
*mii_tail
;
239 static int mii_queue(struct net_device
*dev
, int request
,
240 void (*func
)(uint
, struct net_device
*));
242 /* Make MII read/write commands for the FEC */
243 #define mk_mii_read(REG) (0x60020000 | ((REG & 0x1f) << 18))
244 #define mk_mii_write(REG, VAL) (0x50020000 | ((REG & 0x1f) << 18) | \
248 /* Transmitter timeout */
249 #define TX_TIMEOUT (2 * HZ)
251 /* Register definitions for the PHY */
253 #define MII_REG_CR 0 /* Control Register */
254 #define MII_REG_SR 1 /* Status Register */
255 #define MII_REG_PHYIR1 2 /* PHY Identification Register 1 */
256 #define MII_REG_PHYIR2 3 /* PHY Identification Register 2 */
257 #define MII_REG_ANAR 4 /* A-N Advertisement Register */
258 #define MII_REG_ANLPAR 5 /* A-N Link Partner Ability Register */
259 #define MII_REG_ANER 6 /* A-N Expansion Register */
260 #define MII_REG_ANNPTR 7 /* A-N Next Page Transmit Register */
261 #define MII_REG_ANLPRNPR 8 /* A-N Link Partner Received Next Page Reg. */
263 /* values for phy_status */
265 #define PHY_CONF_ANE 0x0001 /* 1 auto-negotiation enabled */
266 #define PHY_CONF_LOOP 0x0002 /* 1 loopback mode enabled */
267 #define PHY_CONF_SPMASK 0x00f0 /* mask for speed */
268 #define PHY_CONF_10HDX 0x0010 /* 10 Mbit half duplex supported */
269 #define PHY_CONF_10FDX 0x0020 /* 10 Mbit full duplex supported */
270 #define PHY_CONF_100HDX 0x0040 /* 100 Mbit half duplex supported */
271 #define PHY_CONF_100FDX 0x0080 /* 100 Mbit full duplex supported */
273 #define PHY_STAT_LINK 0x0100 /* 1 up - 0 down */
274 #define PHY_STAT_FAULT 0x0200 /* 1 remote fault */
275 #define PHY_STAT_ANC 0x0400 /* 1 auto-negotiation complete */
276 #define PHY_STAT_SPMASK 0xf000 /* mask for speed */
277 #define PHY_STAT_10HDX 0x1000 /* 10 Mbit half duplex selected */
278 #define PHY_STAT_10FDX 0x2000 /* 10 Mbit full duplex selected */
279 #define PHY_STAT_100HDX 0x4000 /* 100 Mbit half duplex selected */
280 #define PHY_STAT_100FDX 0x8000 /* 100 Mbit full duplex selected */
284 fec_enet_start_xmit(struct sk_buff
*skb
, struct net_device
*dev
)
286 struct fec_enet_private
*fep
= netdev_priv(dev
);
289 unsigned short status
;
293 /* Link is down or autonegotiation is in progress. */
294 return NETDEV_TX_BUSY
;
297 spin_lock_irqsave(&fep
->hw_lock
, flags
);
298 /* Fill in a Tx ring entry */
301 status
= bdp
->cbd_sc
;
303 if (status
& BD_ENET_TX_READY
) {
304 /* Ooops. All transmit buffers are full. Bail out.
305 * This should not happen, since dev->tbusy should be set.
307 printk("%s: tx queue full!.\n", dev
->name
);
308 spin_unlock_irqrestore(&fep
->hw_lock
, flags
);
309 return NETDEV_TX_BUSY
;
312 /* Clear all of the status flags */
313 status
&= ~BD_ENET_TX_STATS
;
315 /* Set buffer length and buffer pointer */
317 bdp
->cbd_datlen
= skb
->len
;
320 * On some FEC implementations data must be aligned on
321 * 4-byte boundaries. Use bounce buffers to copy data
322 * and get it aligned. Ugh.
324 if (((unsigned long) bufaddr
) & FEC_ALIGNMENT
) {
326 index
= bdp
- fep
->tx_bd_base
;
327 memcpy(fep
->tx_bounce
[index
], (void *)skb
->data
, skb
->len
);
328 bufaddr
= fep
->tx_bounce
[index
];
331 /* Save skb pointer */
332 fep
->tx_skbuff
[fep
->skb_cur
] = skb
;
334 dev
->stats
.tx_bytes
+= skb
->len
;
335 fep
->skb_cur
= (fep
->skb_cur
+1) & TX_RING_MOD_MASK
;
337 /* Push the data cache so the CPM does not get stale memory
340 bdp
->cbd_bufaddr
= dma_map_single(&dev
->dev
, bufaddr
,
341 FEC_ENET_TX_FRSIZE
, DMA_TO_DEVICE
);
343 /* Send it on its way. Tell FEC it's ready, interrupt when done,
344 * it's the last BD of the frame, and to put the CRC on the end.
346 status
|= (BD_ENET_TX_READY
| BD_ENET_TX_INTR
347 | BD_ENET_TX_LAST
| BD_ENET_TX_TC
);
348 bdp
->cbd_sc
= status
;
350 dev
->trans_start
= jiffies
;
352 /* Trigger transmission start */
353 writel(0, fep
->hwp
+ FEC_X_DES_ACTIVE
);
355 /* If this was the last BD in the ring, start at the beginning again. */
356 if (status
& BD_ENET_TX_WRAP
)
357 bdp
= fep
->tx_bd_base
;
361 if (bdp
== fep
->dirty_tx
) {
363 netif_stop_queue(dev
);
368 spin_unlock_irqrestore(&fep
->hw_lock
, flags
);
374 fec_timeout(struct net_device
*dev
)
376 struct fec_enet_private
*fep
= netdev_priv(dev
);
378 dev
->stats
.tx_errors
++;
380 fec_restart(dev
, fep
->full_duplex
);
381 netif_wake_queue(dev
);
385 fec_enet_interrupt(int irq
, void * dev_id
)
387 struct net_device
*dev
= dev_id
;
388 struct fec_enet_private
*fep
= netdev_priv(dev
);
390 irqreturn_t ret
= IRQ_NONE
;
393 int_events
= readl(fep
->hwp
+ FEC_IEVENT
);
394 writel(int_events
, fep
->hwp
+ FEC_IEVENT
);
396 if (int_events
& FEC_ENET_RXF
) {
401 /* Transmit OK, or non-fatal error. Update the buffer
402 * descriptors. FEC handles all errors, we just discover
403 * them as part of the transmit process.
405 if (int_events
& FEC_ENET_TXF
) {
410 if (int_events
& FEC_ENET_MII
) {
415 } while (int_events
);
422 fec_enet_tx(struct net_device
*dev
)
424 struct fec_enet_private
*fep
;
426 unsigned short status
;
429 fep
= netdev_priv(dev
);
430 spin_lock(&fep
->hw_lock
);
433 while (((status
= bdp
->cbd_sc
) & BD_ENET_TX_READY
) == 0) {
434 if (bdp
== fep
->cur_tx
&& fep
->tx_full
== 0)
437 dma_unmap_single(&dev
->dev
, bdp
->cbd_bufaddr
, FEC_ENET_TX_FRSIZE
, DMA_TO_DEVICE
);
438 bdp
->cbd_bufaddr
= 0;
440 skb
= fep
->tx_skbuff
[fep
->skb_dirty
];
441 /* Check for errors. */
442 if (status
& (BD_ENET_TX_HB
| BD_ENET_TX_LC
|
443 BD_ENET_TX_RL
| BD_ENET_TX_UN
|
445 dev
->stats
.tx_errors
++;
446 if (status
& BD_ENET_TX_HB
) /* No heartbeat */
447 dev
->stats
.tx_heartbeat_errors
++;
448 if (status
& BD_ENET_TX_LC
) /* Late collision */
449 dev
->stats
.tx_window_errors
++;
450 if (status
& BD_ENET_TX_RL
) /* Retrans limit */
451 dev
->stats
.tx_aborted_errors
++;
452 if (status
& BD_ENET_TX_UN
) /* Underrun */
453 dev
->stats
.tx_fifo_errors
++;
454 if (status
& BD_ENET_TX_CSL
) /* Carrier lost */
455 dev
->stats
.tx_carrier_errors
++;
457 dev
->stats
.tx_packets
++;
460 if (status
& BD_ENET_TX_READY
)
461 printk("HEY! Enet xmit interrupt and TX_READY.\n");
463 /* Deferred means some collisions occurred during transmit,
464 * but we eventually sent the packet OK.
466 if (status
& BD_ENET_TX_DEF
)
467 dev
->stats
.collisions
++;
469 /* Free the sk buffer associated with this last transmit */
470 dev_kfree_skb_any(skb
);
471 fep
->tx_skbuff
[fep
->skb_dirty
] = NULL
;
472 fep
->skb_dirty
= (fep
->skb_dirty
+ 1) & TX_RING_MOD_MASK
;
474 /* Update pointer to next buffer descriptor to be transmitted */
475 if (status
& BD_ENET_TX_WRAP
)
476 bdp
= fep
->tx_bd_base
;
480 /* Since we have freed up a buffer, the ring is no longer full
484 if (netif_queue_stopped(dev
))
485 netif_wake_queue(dev
);
489 spin_unlock(&fep
->hw_lock
);
493 /* During a receive, the cur_rx points to the current incoming buffer.
494 * When we update through the ring, if the next incoming buffer has
495 * not been given to the system, we just set the empty indicator,
496 * effectively tossing the packet.
499 fec_enet_rx(struct net_device
*dev
)
501 struct fec_enet_private
*fep
= netdev_priv(dev
);
503 unsigned short status
;
512 spin_lock(&fep
->hw_lock
);
514 /* First, grab all of the stats for the incoming packet.
515 * These get messed up if we get called due to a busy condition.
519 while (!((status
= bdp
->cbd_sc
) & BD_ENET_RX_EMPTY
)) {
521 /* Since we have allocated space to hold a complete frame,
522 * the last indicator should be set.
524 if ((status
& BD_ENET_RX_LAST
) == 0)
525 printk("FEC ENET: rcv is not +last\n");
528 goto rx_processing_done
;
530 /* Check for errors. */
531 if (status
& (BD_ENET_RX_LG
| BD_ENET_RX_SH
| BD_ENET_RX_NO
|
532 BD_ENET_RX_CR
| BD_ENET_RX_OV
)) {
533 dev
->stats
.rx_errors
++;
534 if (status
& (BD_ENET_RX_LG
| BD_ENET_RX_SH
)) {
535 /* Frame too long or too short. */
536 dev
->stats
.rx_length_errors
++;
538 if (status
& BD_ENET_RX_NO
) /* Frame alignment */
539 dev
->stats
.rx_frame_errors
++;
540 if (status
& BD_ENET_RX_CR
) /* CRC Error */
541 dev
->stats
.rx_crc_errors
++;
542 if (status
& BD_ENET_RX_OV
) /* FIFO overrun */
543 dev
->stats
.rx_fifo_errors
++;
546 /* Report late collisions as a frame error.
547 * On this error, the BD is closed, but we don't know what we
548 * have in the buffer. So, just drop this frame on the floor.
550 if (status
& BD_ENET_RX_CL
) {
551 dev
->stats
.rx_errors
++;
552 dev
->stats
.rx_frame_errors
++;
553 goto rx_processing_done
;
556 /* Process the incoming frame. */
557 dev
->stats
.rx_packets
++;
558 pkt_len
= bdp
->cbd_datlen
;
559 dev
->stats
.rx_bytes
+= pkt_len
;
560 data
= (__u8
*)__va(bdp
->cbd_bufaddr
);
562 dma_unmap_single(NULL
, bdp
->cbd_bufaddr
, bdp
->cbd_datlen
,
565 /* This does 16 byte alignment, exactly what we need.
566 * The packet length includes FCS, but we don't want to
567 * include that when passing upstream as it messes up
568 * bridging applications.
570 skb
= dev_alloc_skb(pkt_len
- 4 + NET_IP_ALIGN
);
572 if (unlikely(!skb
)) {
573 printk("%s: Memory squeeze, dropping packet.\n",
575 dev
->stats
.rx_dropped
++;
577 skb_reserve(skb
, NET_IP_ALIGN
);
578 skb_put(skb
, pkt_len
- 4); /* Make room */
579 skb_copy_to_linear_data(skb
, data
, pkt_len
- 4);
580 skb
->protocol
= eth_type_trans(skb
, dev
);
584 bdp
->cbd_bufaddr
= dma_map_single(NULL
, data
, bdp
->cbd_datlen
,
587 /* Clear the status flags for this buffer */
588 status
&= ~BD_ENET_RX_STATS
;
590 /* Mark the buffer empty */
591 status
|= BD_ENET_RX_EMPTY
;
592 bdp
->cbd_sc
= status
;
594 /* Update BD pointer to next entry */
595 if (status
& BD_ENET_RX_WRAP
)
596 bdp
= fep
->rx_bd_base
;
599 /* Doing this here will keep the FEC running while we process
600 * incoming frames. On a heavily loaded network, we should be
601 * able to keep up at the expense of system resources.
603 writel(0, fep
->hwp
+ FEC_R_DES_ACTIVE
);
607 spin_unlock(&fep
->hw_lock
);
610 /* called from interrupt context */
612 fec_enet_mii(struct net_device
*dev
)
614 struct fec_enet_private
*fep
;
617 fep
= netdev_priv(dev
);
618 spin_lock(&fep
->mii_lock
);
620 if ((mip
= mii_head
) == NULL
) {
621 printk("MII and no head!\n");
625 if (mip
->mii_func
!= NULL
)
626 (*(mip
->mii_func
))(readl(fep
->hwp
+ FEC_MII_DATA
), dev
);
628 mii_head
= mip
->mii_next
;
629 mip
->mii_next
= mii_free
;
632 if ((mip
= mii_head
) != NULL
)
633 writel(mip
->mii_regval
, fep
->hwp
+ FEC_MII_DATA
);
636 spin_unlock(&fep
->mii_lock
);
640 mii_queue_unlocked(struct net_device
*dev
, int regval
,
641 void (*func
)(uint
, struct net_device
*))
643 struct fec_enet_private
*fep
;
647 /* Add PHY address to register command */
648 fep
= netdev_priv(dev
);
650 regval
|= fep
->phy_addr
<< 23;
653 if ((mip
= mii_free
) != NULL
) {
654 mii_free
= mip
->mii_next
;
655 mip
->mii_regval
= regval
;
656 mip
->mii_func
= func
;
657 mip
->mii_next
= NULL
;
659 mii_tail
->mii_next
= mip
;
662 mii_head
= mii_tail
= mip
;
663 writel(regval
, fep
->hwp
+ FEC_MII_DATA
);
673 mii_queue(struct net_device
*dev
, int regval
,
674 void (*func
)(uint
, struct net_device
*))
676 struct fec_enet_private
*fep
;
679 fep
= netdev_priv(dev
);
680 spin_lock_irqsave(&fep
->mii_lock
, flags
);
681 retval
= mii_queue_unlocked(dev
, regval
, func
);
682 spin_unlock_irqrestore(&fep
->mii_lock
, flags
);
686 static void mii_do_cmd(struct net_device
*dev
, const phy_cmd_t
*c
)
691 for (; c
->mii_data
!= mk_mii_end
; c
++)
692 mii_queue(dev
, c
->mii_data
, c
->funct
);
695 static void mii_parse_sr(uint mii_reg
, struct net_device
*dev
)
697 struct fec_enet_private
*fep
= netdev_priv(dev
);
698 volatile uint
*s
= &(fep
->phy_status
);
701 status
= *s
& ~(PHY_STAT_LINK
| PHY_STAT_FAULT
| PHY_STAT_ANC
);
703 if (mii_reg
& 0x0004)
704 status
|= PHY_STAT_LINK
;
705 if (mii_reg
& 0x0010)
706 status
|= PHY_STAT_FAULT
;
707 if (mii_reg
& 0x0020)
708 status
|= PHY_STAT_ANC
;
712 static void mii_parse_cr(uint mii_reg
, struct net_device
*dev
)
714 struct fec_enet_private
*fep
= netdev_priv(dev
);
715 volatile uint
*s
= &(fep
->phy_status
);
718 status
= *s
& ~(PHY_CONF_ANE
| PHY_CONF_LOOP
);
720 if (mii_reg
& 0x1000)
721 status
|= PHY_CONF_ANE
;
722 if (mii_reg
& 0x4000)
723 status
|= PHY_CONF_LOOP
;
727 static void mii_parse_anar(uint mii_reg
, struct net_device
*dev
)
729 struct fec_enet_private
*fep
= netdev_priv(dev
);
730 volatile uint
*s
= &(fep
->phy_status
);
733 status
= *s
& ~(PHY_CONF_SPMASK
);
735 if (mii_reg
& 0x0020)
736 status
|= PHY_CONF_10HDX
;
737 if (mii_reg
& 0x0040)
738 status
|= PHY_CONF_10FDX
;
739 if (mii_reg
& 0x0080)
740 status
|= PHY_CONF_100HDX
;
741 if (mii_reg
& 0x00100)
742 status
|= PHY_CONF_100FDX
;
746 /* ------------------------------------------------------------------------- */
747 /* The Level one LXT970 is used by many boards */
749 #define MII_LXT970_MIRROR 16 /* Mirror register */
750 #define MII_LXT970_IER 17 /* Interrupt Enable Register */
751 #define MII_LXT970_ISR 18 /* Interrupt Status Register */
752 #define MII_LXT970_CONFIG 19 /* Configuration Register */
753 #define MII_LXT970_CSR 20 /* Chip Status Register */
755 static void mii_parse_lxt970_csr(uint mii_reg
, struct net_device
*dev
)
757 struct fec_enet_private
*fep
= netdev_priv(dev
);
758 volatile uint
*s
= &(fep
->phy_status
);
761 status
= *s
& ~(PHY_STAT_SPMASK
);
762 if (mii_reg
& 0x0800) {
763 if (mii_reg
& 0x1000)
764 status
|= PHY_STAT_100FDX
;
766 status
|= PHY_STAT_100HDX
;
768 if (mii_reg
& 0x1000)
769 status
|= PHY_STAT_10FDX
;
771 status
|= PHY_STAT_10HDX
;
776 static phy_cmd_t
const phy_cmd_lxt970_config
[] = {
777 { mk_mii_read(MII_REG_CR
), mii_parse_cr
},
778 { mk_mii_read(MII_REG_ANAR
), mii_parse_anar
},
781 static phy_cmd_t
const phy_cmd_lxt970_startup
[] = { /* enable interrupts */
782 { mk_mii_write(MII_LXT970_IER
, 0x0002), NULL
},
783 { mk_mii_write(MII_REG_CR
, 0x1200), NULL
}, /* autonegotiate */
786 static phy_cmd_t
const phy_cmd_lxt970_ack_int
[] = {
787 /* read SR and ISR to acknowledge */
788 { mk_mii_read(MII_REG_SR
), mii_parse_sr
},
789 { mk_mii_read(MII_LXT970_ISR
), NULL
},
791 /* find out the current status */
792 { mk_mii_read(MII_LXT970_CSR
), mii_parse_lxt970_csr
},
795 static phy_cmd_t
const phy_cmd_lxt970_shutdown
[] = { /* disable interrupts */
796 { mk_mii_write(MII_LXT970_IER
, 0x0000), NULL
},
799 static phy_info_t
const phy_info_lxt970
= {
802 .config
= phy_cmd_lxt970_config
,
803 .startup
= phy_cmd_lxt970_startup
,
804 .ack_int
= phy_cmd_lxt970_ack_int
,
805 .shutdown
= phy_cmd_lxt970_shutdown
808 /* ------------------------------------------------------------------------- */
809 /* The Level one LXT971 is used on some of my custom boards */
811 /* register definitions for the 971 */
813 #define MII_LXT971_PCR 16 /* Port Control Register */
814 #define MII_LXT971_SR2 17 /* Status Register 2 */
815 #define MII_LXT971_IER 18 /* Interrupt Enable Register */
816 #define MII_LXT971_ISR 19 /* Interrupt Status Register */
817 #define MII_LXT971_LCR 20 /* LED Control Register */
818 #define MII_LXT971_TCR 30 /* Transmit Control Register */
821 * I had some nice ideas of running the MDIO faster...
822 * The 971 should support 8MHz and I tried it, but things acted really
823 * weird, so 2.5 MHz ought to be enough for anyone...
826 static void mii_parse_lxt971_sr2(uint mii_reg
, struct net_device
*dev
)
828 struct fec_enet_private
*fep
= netdev_priv(dev
);
829 volatile uint
*s
= &(fep
->phy_status
);
832 status
= *s
& ~(PHY_STAT_SPMASK
| PHY_STAT_LINK
| PHY_STAT_ANC
);
834 if (mii_reg
& 0x0400) {
836 status
|= PHY_STAT_LINK
;
840 if (mii_reg
& 0x0080)
841 status
|= PHY_STAT_ANC
;
842 if (mii_reg
& 0x4000) {
843 if (mii_reg
& 0x0200)
844 status
|= PHY_STAT_100FDX
;
846 status
|= PHY_STAT_100HDX
;
848 if (mii_reg
& 0x0200)
849 status
|= PHY_STAT_10FDX
;
851 status
|= PHY_STAT_10HDX
;
853 if (mii_reg
& 0x0008)
854 status
|= PHY_STAT_FAULT
;
859 static phy_cmd_t
const phy_cmd_lxt971_config
[] = {
860 /* limit to 10MBit because my prototype board
861 * doesn't work with 100. */
862 { mk_mii_read(MII_REG_CR
), mii_parse_cr
},
863 { mk_mii_read(MII_REG_ANAR
), mii_parse_anar
},
864 { mk_mii_read(MII_LXT971_SR2
), mii_parse_lxt971_sr2
},
867 static phy_cmd_t
const phy_cmd_lxt971_startup
[] = { /* enable interrupts */
868 { mk_mii_write(MII_LXT971_IER
, 0x00f2), NULL
},
869 { mk_mii_write(MII_REG_CR
, 0x1200), NULL
}, /* autonegotiate */
870 { mk_mii_write(MII_LXT971_LCR
, 0xd422), NULL
}, /* LED config */
871 /* Somehow does the 971 tell me that the link is down
872 * the first read after power-up.
873 * read here to get a valid value in ack_int */
874 { mk_mii_read(MII_REG_SR
), mii_parse_sr
},
877 static phy_cmd_t
const phy_cmd_lxt971_ack_int
[] = {
878 /* acknowledge the int before reading status ! */
879 { mk_mii_read(MII_LXT971_ISR
), NULL
},
880 /* find out the current status */
881 { mk_mii_read(MII_REG_SR
), mii_parse_sr
},
882 { mk_mii_read(MII_LXT971_SR2
), mii_parse_lxt971_sr2
},
885 static phy_cmd_t
const phy_cmd_lxt971_shutdown
[] = { /* disable interrupts */
886 { mk_mii_write(MII_LXT971_IER
, 0x0000), NULL
},
889 static phy_info_t
const phy_info_lxt971
= {
892 .config
= phy_cmd_lxt971_config
,
893 .startup
= phy_cmd_lxt971_startup
,
894 .ack_int
= phy_cmd_lxt971_ack_int
,
895 .shutdown
= phy_cmd_lxt971_shutdown
898 /* ------------------------------------------------------------------------- */
899 /* The Quality Semiconductor QS6612 is used on the RPX CLLF */
901 /* register definitions */
903 #define MII_QS6612_MCR 17 /* Mode Control Register */
904 #define MII_QS6612_FTR 27 /* Factory Test Register */
905 #define MII_QS6612_MCO 28 /* Misc. Control Register */
906 #define MII_QS6612_ISR 29 /* Interrupt Source Register */
907 #define MII_QS6612_IMR 30 /* Interrupt Mask Register */
908 #define MII_QS6612_PCR 31 /* 100BaseTx PHY Control Reg. */
910 static void mii_parse_qs6612_pcr(uint mii_reg
, struct net_device
*dev
)
912 struct fec_enet_private
*fep
= netdev_priv(dev
);
913 volatile uint
*s
= &(fep
->phy_status
);
916 status
= *s
& ~(PHY_STAT_SPMASK
);
918 switch((mii_reg
>> 2) & 7) {
919 case 1: status
|= PHY_STAT_10HDX
; break;
920 case 2: status
|= PHY_STAT_100HDX
; break;
921 case 5: status
|= PHY_STAT_10FDX
; break;
922 case 6: status
|= PHY_STAT_100FDX
; break;
928 static phy_cmd_t
const phy_cmd_qs6612_config
[] = {
929 /* The PHY powers up isolated on the RPX,
930 * so send a command to allow operation.
932 { mk_mii_write(MII_QS6612_PCR
, 0x0dc0), NULL
},
934 /* parse cr and anar to get some info */
935 { mk_mii_read(MII_REG_CR
), mii_parse_cr
},
936 { mk_mii_read(MII_REG_ANAR
), mii_parse_anar
},
939 static phy_cmd_t
const phy_cmd_qs6612_startup
[] = { /* enable interrupts */
940 { mk_mii_write(MII_QS6612_IMR
, 0x003a), NULL
},
941 { mk_mii_write(MII_REG_CR
, 0x1200), NULL
}, /* autonegotiate */
944 static phy_cmd_t
const phy_cmd_qs6612_ack_int
[] = {
945 /* we need to read ISR, SR and ANER to acknowledge */
946 { mk_mii_read(MII_QS6612_ISR
), NULL
},
947 { mk_mii_read(MII_REG_SR
), mii_parse_sr
},
948 { mk_mii_read(MII_REG_ANER
), NULL
},
950 /* read pcr to get info */
951 { mk_mii_read(MII_QS6612_PCR
), mii_parse_qs6612_pcr
},
954 static phy_cmd_t
const phy_cmd_qs6612_shutdown
[] = { /* disable interrupts */
955 { mk_mii_write(MII_QS6612_IMR
, 0x0000), NULL
},
958 static phy_info_t
const phy_info_qs6612
= {
961 .config
= phy_cmd_qs6612_config
,
962 .startup
= phy_cmd_qs6612_startup
,
963 .ack_int
= phy_cmd_qs6612_ack_int
,
964 .shutdown
= phy_cmd_qs6612_shutdown
967 /* ------------------------------------------------------------------------- */
968 /* AMD AM79C874 phy */
970 /* register definitions for the 874 */
972 #define MII_AM79C874_MFR 16 /* Miscellaneous Feature Register */
973 #define MII_AM79C874_ICSR 17 /* Interrupt/Status Register */
974 #define MII_AM79C874_DR 18 /* Diagnostic Register */
975 #define MII_AM79C874_PMLR 19 /* Power and Loopback Register */
976 #define MII_AM79C874_MCR 21 /* ModeControl Register */
977 #define MII_AM79C874_DC 23 /* Disconnect Counter */
978 #define MII_AM79C874_REC 24 /* Recieve Error Counter */
980 static void mii_parse_am79c874_dr(uint mii_reg
, struct net_device
*dev
)
982 struct fec_enet_private
*fep
= netdev_priv(dev
);
983 volatile uint
*s
= &(fep
->phy_status
);
986 status
= *s
& ~(PHY_STAT_SPMASK
| PHY_STAT_ANC
);
988 if (mii_reg
& 0x0080)
989 status
|= PHY_STAT_ANC
;
990 if (mii_reg
& 0x0400)
991 status
|= ((mii_reg
& 0x0800) ? PHY_STAT_100FDX
: PHY_STAT_100HDX
);
993 status
|= ((mii_reg
& 0x0800) ? PHY_STAT_10FDX
: PHY_STAT_10HDX
);
998 static phy_cmd_t
const phy_cmd_am79c874_config
[] = {
999 { mk_mii_read(MII_REG_CR
), mii_parse_cr
},
1000 { mk_mii_read(MII_REG_ANAR
), mii_parse_anar
},
1001 { mk_mii_read(MII_AM79C874_DR
), mii_parse_am79c874_dr
},
1004 static phy_cmd_t
const phy_cmd_am79c874_startup
[] = { /* enable interrupts */
1005 { mk_mii_write(MII_AM79C874_ICSR
, 0xff00), NULL
},
1006 { mk_mii_write(MII_REG_CR
, 0x1200), NULL
}, /* autonegotiate */
1007 { mk_mii_read(MII_REG_SR
), mii_parse_sr
},
1010 static phy_cmd_t
const phy_cmd_am79c874_ack_int
[] = {
1011 /* find out the current status */
1012 { mk_mii_read(MII_REG_SR
), mii_parse_sr
},
1013 { mk_mii_read(MII_AM79C874_DR
), mii_parse_am79c874_dr
},
1014 /* we only need to read ISR to acknowledge */
1015 { mk_mii_read(MII_AM79C874_ICSR
), NULL
},
1018 static phy_cmd_t
const phy_cmd_am79c874_shutdown
[] = { /* disable interrupts */
1019 { mk_mii_write(MII_AM79C874_ICSR
, 0x0000), NULL
},
1022 static phy_info_t
const phy_info_am79c874
= {
1025 .config
= phy_cmd_am79c874_config
,
1026 .startup
= phy_cmd_am79c874_startup
,
1027 .ack_int
= phy_cmd_am79c874_ack_int
,
1028 .shutdown
= phy_cmd_am79c874_shutdown
1032 /* ------------------------------------------------------------------------- */
1033 /* Kendin KS8721BL phy */
1035 /* register definitions for the 8721 */
1037 #define MII_KS8721BL_RXERCR 21
1038 #define MII_KS8721BL_ICSR 27
1039 #define MII_KS8721BL_PHYCR 31
1041 static phy_cmd_t
const phy_cmd_ks8721bl_config
[] = {
1042 { mk_mii_read(MII_REG_CR
), mii_parse_cr
},
1043 { mk_mii_read(MII_REG_ANAR
), mii_parse_anar
},
1046 static phy_cmd_t
const phy_cmd_ks8721bl_startup
[] = { /* enable interrupts */
1047 { mk_mii_write(MII_KS8721BL_ICSR
, 0xff00), NULL
},
1048 { mk_mii_write(MII_REG_CR
, 0x1200), NULL
}, /* autonegotiate */
1049 { mk_mii_read(MII_REG_SR
), mii_parse_sr
},
1052 static phy_cmd_t
const phy_cmd_ks8721bl_ack_int
[] = {
1053 /* find out the current status */
1054 { mk_mii_read(MII_REG_SR
), mii_parse_sr
},
1055 /* we only need to read ISR to acknowledge */
1056 { mk_mii_read(MII_KS8721BL_ICSR
), NULL
},
1059 static phy_cmd_t
const phy_cmd_ks8721bl_shutdown
[] = { /* disable interrupts */
1060 { mk_mii_write(MII_KS8721BL_ICSR
, 0x0000), NULL
},
1063 static phy_info_t
const phy_info_ks8721bl
= {
1066 .config
= phy_cmd_ks8721bl_config
,
1067 .startup
= phy_cmd_ks8721bl_startup
,
1068 .ack_int
= phy_cmd_ks8721bl_ack_int
,
1069 .shutdown
= phy_cmd_ks8721bl_shutdown
1072 /* ------------------------------------------------------------------------- */
1073 /* register definitions for the DP83848 */
1075 #define MII_DP8384X_PHYSTST 16 /* PHY Status Register */
1077 static void mii_parse_dp8384x_sr2(uint mii_reg
, struct net_device
*dev
)
1079 struct fec_enet_private
*fep
= netdev_priv(dev
);
1080 volatile uint
*s
= &(fep
->phy_status
);
1082 *s
&= ~(PHY_STAT_SPMASK
| PHY_STAT_LINK
| PHY_STAT_ANC
);
1085 if (mii_reg
& 0x0001) {
1087 *s
|= PHY_STAT_LINK
;
1090 /* Status of link */
1091 if (mii_reg
& 0x0010) /* Autonegotioation complete */
1093 if (mii_reg
& 0x0002) { /* 10MBps? */
1094 if (mii_reg
& 0x0004) /* Full Duplex? */
1095 *s
|= PHY_STAT_10FDX
;
1097 *s
|= PHY_STAT_10HDX
;
1098 } else { /* 100 Mbps? */
1099 if (mii_reg
& 0x0004) /* Full Duplex? */
1100 *s
|= PHY_STAT_100FDX
;
1102 *s
|= PHY_STAT_100HDX
;
1104 if (mii_reg
& 0x0008)
1105 *s
|= PHY_STAT_FAULT
;
1108 static phy_info_t phy_info_dp83848
= {
1112 (const phy_cmd_t
[]) { /* config */
1113 { mk_mii_read(MII_REG_CR
), mii_parse_cr
},
1114 { mk_mii_read(MII_REG_ANAR
), mii_parse_anar
},
1115 { mk_mii_read(MII_DP8384X_PHYSTST
), mii_parse_dp8384x_sr2
},
1118 (const phy_cmd_t
[]) { /* startup - enable interrupts */
1119 { mk_mii_write(MII_REG_CR
, 0x1200), NULL
}, /* autonegotiate */
1120 { mk_mii_read(MII_REG_SR
), mii_parse_sr
},
1123 (const phy_cmd_t
[]) { /* ack_int - never happens, no interrupt */
1126 (const phy_cmd_t
[]) { /* shutdown */
1131 static phy_info_t phy_info_lan8700
= {
1134 (const phy_cmd_t
[]) { /* config */
1135 { mk_mii_read(MII_REG_CR
), mii_parse_cr
},
1136 { mk_mii_read(MII_REG_ANAR
), mii_parse_anar
},
1139 (const phy_cmd_t
[]) { /* startup */
1140 { mk_mii_write(MII_REG_CR
, 0x1200), NULL
}, /* autonegotiate */
1141 { mk_mii_read(MII_REG_SR
), mii_parse_sr
},
1144 (const phy_cmd_t
[]) { /* act_int */
1147 (const phy_cmd_t
[]) { /* shutdown */
1151 /* ------------------------------------------------------------------------- */
1153 static phy_info_t
const * const phy_info
[] = {
1164 /* ------------------------------------------------------------------------- */
1165 #ifdef HAVE_mii_link_interrupt
1167 mii_link_interrupt(int irq
, void * dev_id
);
1170 * This is specific to the MII interrupt setup of the M5272EVB.
1172 static void __inline__
fec_request_mii_intr(struct net_device
*dev
)
1174 if (request_irq(66, mii_link_interrupt
, IRQF_DISABLED
, "fec(MII)", dev
) != 0)
1175 printk("FEC: Could not allocate fec(MII) IRQ(66)!\n");
1178 static void __inline__
fec_disable_phy_intr(struct net_device
*dev
)
1185 static void __inline__
fec_get_mac(struct net_device
*dev
)
1187 struct fec_enet_private
*fep
= netdev_priv(dev
);
1188 unsigned char *iap
, tmpaddr
[ETH_ALEN
];
1192 * Get MAC address from FLASH.
1193 * If it is all 1's or 0's, use the default.
1195 iap
= (unsigned char *)FEC_FLASHMAC
;
1196 if ((iap
[0] == 0) && (iap
[1] == 0) && (iap
[2] == 0) &&
1197 (iap
[3] == 0) && (iap
[4] == 0) && (iap
[5] == 0))
1198 iap
= fec_mac_default
;
1199 if ((iap
[0] == 0xff) && (iap
[1] == 0xff) && (iap
[2] == 0xff) &&
1200 (iap
[3] == 0xff) && (iap
[4] == 0xff) && (iap
[5] == 0xff))
1201 iap
= fec_mac_default
;
1203 *((unsigned long *) &tmpaddr
[0]) = readl(fep
->hwp
+ FEC_ADDR_LOW
);
1204 *((unsigned short *) &tmpaddr
[4]) = (readl(fep
->hwp
+ FEC_ADDR_HIGH
) >> 16);
1208 memcpy(dev
->dev_addr
, iap
, ETH_ALEN
);
1210 /* Adjust MAC if using default MAC address */
1211 if (iap
== fec_mac_default
)
1212 dev
->dev_addr
[ETH_ALEN
-1] = fec_mac_default
[ETH_ALEN
-1] + fep
->index
;
1216 /* ------------------------------------------------------------------------- */
1218 static void mii_display_status(struct net_device
*dev
)
1220 struct fec_enet_private
*fep
= netdev_priv(dev
);
1221 volatile uint
*s
= &(fep
->phy_status
);
1223 if (!fep
->link
&& !fep
->old_link
) {
1224 /* Link is still down - don't print anything */
1228 printk("%s: status: ", dev
->name
);
1231 printk("link down");
1235 switch(*s
& PHY_STAT_SPMASK
) {
1236 case PHY_STAT_100FDX
: printk(", 100MBit Full Duplex"); break;
1237 case PHY_STAT_100HDX
: printk(", 100MBit Half Duplex"); break;
1238 case PHY_STAT_10FDX
: printk(", 10MBit Full Duplex"); break;
1239 case PHY_STAT_10HDX
: printk(", 10MBit Half Duplex"); break;
1241 printk(", Unknown speed/duplex");
1244 if (*s
& PHY_STAT_ANC
)
1245 printk(", auto-negotiation complete");
1248 if (*s
& PHY_STAT_FAULT
)
1249 printk(", remote fault");
1254 static void mii_display_config(struct work_struct
*work
)
1256 struct fec_enet_private
*fep
= container_of(work
, struct fec_enet_private
, phy_task
);
1257 struct net_device
*dev
= fep
->netdev
;
1258 uint status
= fep
->phy_status
;
1261 ** When we get here, phy_task is already removed from
1262 ** the workqueue. It is thus safe to allow to reuse it.
1264 fep
->mii_phy_task_queued
= 0;
1265 printk("%s: config: auto-negotiation ", dev
->name
);
1267 if (status
& PHY_CONF_ANE
)
1272 if (status
& PHY_CONF_100FDX
)
1274 if (status
& PHY_CONF_100HDX
)
1276 if (status
& PHY_CONF_10FDX
)
1278 if (status
& PHY_CONF_10HDX
)
1280 if (!(status
& PHY_CONF_SPMASK
))
1281 printk(", No speed/duplex selected?");
1283 if (status
& PHY_CONF_LOOP
)
1284 printk(", loopback enabled");
1288 fep
->sequence_done
= 1;
1291 static void mii_relink(struct work_struct
*work
)
1293 struct fec_enet_private
*fep
= container_of(work
, struct fec_enet_private
, phy_task
);
1294 struct net_device
*dev
= fep
->netdev
;
1298 ** When we get here, phy_task is already removed from
1299 ** the workqueue. It is thus safe to allow to reuse it.
1301 fep
->mii_phy_task_queued
= 0;
1302 fep
->link
= (fep
->phy_status
& PHY_STAT_LINK
) ? 1 : 0;
1303 mii_display_status(dev
);
1304 fep
->old_link
= fep
->link
;
1309 & (PHY_STAT_100FDX
| PHY_STAT_10FDX
))
1311 fec_restart(dev
, duplex
);
1316 /* mii_queue_relink is called in interrupt context from mii_link_interrupt */
1317 static void mii_queue_relink(uint mii_reg
, struct net_device
*dev
)
1319 struct fec_enet_private
*fep
= netdev_priv(dev
);
1322 * We cannot queue phy_task twice in the workqueue. It
1323 * would cause an endless loop in the workqueue.
1324 * Fortunately, if the last mii_relink entry has not yet been
1325 * executed now, it will do the job for the current interrupt,
1326 * which is just what we want.
1328 if (fep
->mii_phy_task_queued
)
1331 fep
->mii_phy_task_queued
= 1;
1332 INIT_WORK(&fep
->phy_task
, mii_relink
);
1333 schedule_work(&fep
->phy_task
);
1336 /* mii_queue_config is called in interrupt context from fec_enet_mii */
1337 static void mii_queue_config(uint mii_reg
, struct net_device
*dev
)
1339 struct fec_enet_private
*fep
= netdev_priv(dev
);
1341 if (fep
->mii_phy_task_queued
)
1344 fep
->mii_phy_task_queued
= 1;
1345 INIT_WORK(&fep
->phy_task
, mii_display_config
);
1346 schedule_work(&fep
->phy_task
);
1349 phy_cmd_t
const phy_cmd_relink
[] = {
1350 { mk_mii_read(MII_REG_CR
), mii_queue_relink
},
1353 phy_cmd_t
const phy_cmd_config
[] = {
1354 { mk_mii_read(MII_REG_CR
), mii_queue_config
},
1358 /* Read remainder of PHY ID. */
1360 mii_discover_phy3(uint mii_reg
, struct net_device
*dev
)
1362 struct fec_enet_private
*fep
;
1365 fep
= netdev_priv(dev
);
1366 fep
->phy_id
|= (mii_reg
& 0xffff);
1367 printk("fec: PHY @ 0x%x, ID 0x%08x", fep
->phy_addr
, fep
->phy_id
);
1369 for(i
= 0; phy_info
[i
]; i
++) {
1370 if(phy_info
[i
]->id
== (fep
->phy_id
>> 4))
1375 printk(" -- %s\n", phy_info
[i
]->name
);
1377 printk(" -- unknown PHY!\n");
1379 fep
->phy
= phy_info
[i
];
1380 fep
->phy_id_done
= 1;
1383 /* Scan all of the MII PHY addresses looking for someone to respond
1384 * with a valid ID. This usually happens quickly.
1387 mii_discover_phy(uint mii_reg
, struct net_device
*dev
)
1389 struct fec_enet_private
*fep
;
1392 fep
= netdev_priv(dev
);
1394 if (fep
->phy_addr
< 32) {
1395 if ((phytype
= (mii_reg
& 0xffff)) != 0xffff && phytype
!= 0) {
1397 /* Got first part of ID, now get remainder */
1398 fep
->phy_id
= phytype
<< 16;
1399 mii_queue_unlocked(dev
, mk_mii_read(MII_REG_PHYIR2
),
1403 mii_queue_unlocked(dev
, mk_mii_read(MII_REG_PHYIR1
),
1407 printk("FEC: No PHY device found.\n");
1408 /* Disable external MII interface */
1409 writel(0, fep
->hwp
+ FEC_MII_SPEED
);
1411 #ifdef HAVE_mii_link_interrupt
1412 fec_disable_phy_intr(dev
);
1417 /* This interrupt occurs when the PHY detects a link change */
1418 #ifdef HAVE_mii_link_interrupt
1420 mii_link_interrupt(int irq
, void * dev_id
)
1422 struct net_device
*dev
= dev_id
;
1423 struct fec_enet_private
*fep
= netdev_priv(dev
);
1425 mii_do_cmd(dev
, fep
->phy
->ack_int
);
1426 mii_do_cmd(dev
, phy_cmd_relink
); /* restart and display status */
1432 static void fec_enet_free_buffers(struct net_device
*dev
)
1434 struct fec_enet_private
*fep
= netdev_priv(dev
);
1436 struct sk_buff
*skb
;
1437 struct bufdesc
*bdp
;
1439 bdp
= fep
->rx_bd_base
;
1440 for (i
= 0; i
< RX_RING_SIZE
; i
++) {
1441 skb
= fep
->rx_skbuff
[i
];
1443 if (bdp
->cbd_bufaddr
)
1444 dma_unmap_single(&dev
->dev
, bdp
->cbd_bufaddr
,
1445 FEC_ENET_RX_FRSIZE
, DMA_FROM_DEVICE
);
1451 bdp
= fep
->tx_bd_base
;
1452 for (i
= 0; i
< TX_RING_SIZE
; i
++)
1453 kfree(fep
->tx_bounce
[i
]);
1456 static int fec_enet_alloc_buffers(struct net_device
*dev
)
1458 struct fec_enet_private
*fep
= netdev_priv(dev
);
1460 struct sk_buff
*skb
;
1461 struct bufdesc
*bdp
;
1463 bdp
= fep
->rx_bd_base
;
1464 for (i
= 0; i
< RX_RING_SIZE
; i
++) {
1465 skb
= dev_alloc_skb(FEC_ENET_RX_FRSIZE
);
1467 fec_enet_free_buffers(dev
);
1470 fep
->rx_skbuff
[i
] = skb
;
1472 bdp
->cbd_bufaddr
= dma_map_single(&dev
->dev
, skb
->data
,
1473 FEC_ENET_RX_FRSIZE
, DMA_FROM_DEVICE
);
1474 bdp
->cbd_sc
= BD_ENET_RX_EMPTY
;
1478 /* Set the last buffer to wrap. */
1480 bdp
->cbd_sc
|= BD_SC_WRAP
;
1482 bdp
= fep
->tx_bd_base
;
1483 for (i
= 0; i
< TX_RING_SIZE
; i
++) {
1484 fep
->tx_bounce
[i
] = kmalloc(FEC_ENET_TX_FRSIZE
, GFP_KERNEL
);
1487 bdp
->cbd_bufaddr
= 0;
1491 /* Set the last buffer to wrap. */
1493 bdp
->cbd_sc
|= BD_SC_WRAP
;
1499 fec_enet_open(struct net_device
*dev
)
1501 struct fec_enet_private
*fep
= netdev_priv(dev
);
1504 /* I should reset the ring buffers here, but I don't yet know
1505 * a simple way to do that.
1508 ret
= fec_enet_alloc_buffers(dev
);
1512 fep
->sequence_done
= 0;
1515 fec_restart(dev
, 1);
1518 mii_do_cmd(dev
, fep
->phy
->ack_int
);
1519 mii_do_cmd(dev
, fep
->phy
->config
);
1520 mii_do_cmd(dev
, phy_cmd_config
); /* display configuration */
1522 /* Poll until the PHY tells us its configuration
1524 * Request is initiated by mii_do_cmd above, but answer
1525 * comes by interrupt.
1526 * This should take about 25 usec per register at 2.5 MHz,
1527 * and we read approximately 5 registers.
1529 while(!fep
->sequence_done
)
1532 mii_do_cmd(dev
, fep
->phy
->startup
);
1535 /* Set the initial link state to true. A lot of hardware
1536 * based on this device does not implement a PHY interrupt,
1537 * so we are never notified of link change.
1541 netif_start_queue(dev
);
1547 fec_enet_close(struct net_device
*dev
)
1549 struct fec_enet_private
*fep
= netdev_priv(dev
);
1551 /* Don't know what to do yet. */
1553 netif_stop_queue(dev
);
1556 fec_enet_free_buffers(dev
);
1561 /* Set or clear the multicast filter for this adaptor.
1562 * Skeleton taken from sunlance driver.
1563 * The CPM Ethernet implementation allows Multicast as well as individual
1564 * MAC address filtering. Some of the drivers check to make sure it is
1565 * a group multicast address, and discard those that are not. I guess I
1566 * will do the same for now, but just remove the test if you want
1567 * individual filtering as well (do the upper net layers want or support
1568 * this kind of feature?).
1571 #define HASH_BITS 6 /* #bits in hash */
1572 #define CRC32_POLY 0xEDB88320
1574 static void set_multicast_list(struct net_device
*dev
)
1576 struct fec_enet_private
*fep
= netdev_priv(dev
);
1577 struct dev_mc_list
*dmi
;
1578 unsigned int i
, j
, bit
, data
, crc
, tmp
;
1581 if (dev
->flags
& IFF_PROMISC
) {
1582 tmp
= readl(fep
->hwp
+ FEC_R_CNTRL
);
1584 writel(tmp
, fep
->hwp
+ FEC_R_CNTRL
);
1588 tmp
= readl(fep
->hwp
+ FEC_R_CNTRL
);
1590 writel(tmp
, fep
->hwp
+ FEC_R_CNTRL
);
1592 if (dev
->flags
& IFF_ALLMULTI
) {
1593 /* Catch all multicast addresses, so set the
1596 writel(0xffffffff, fep
->hwp
+ FEC_GRP_HASH_TABLE_HIGH
);
1597 writel(0xffffffff, fep
->hwp
+ FEC_GRP_HASH_TABLE_LOW
);
1602 /* Clear filter and add the addresses in hash register
1604 writel(0, fep
->hwp
+ FEC_GRP_HASH_TABLE_HIGH
);
1605 writel(0, fep
->hwp
+ FEC_GRP_HASH_TABLE_LOW
);
1609 for (j
= 0; j
< netdev_mc_count(dev
); j
++, dmi
= dmi
->next
) {
1610 /* Only support group multicast for now */
1611 if (!(dmi
->dmi_addr
[0] & 1))
1614 /* calculate crc32 value of mac address */
1617 for (i
= 0; i
< dmi
->dmi_addrlen
; i
++) {
1618 data
= dmi
->dmi_addr
[i
];
1619 for (bit
= 0; bit
< 8; bit
++, data
>>= 1) {
1621 (((crc
^ data
) & 1) ? CRC32_POLY
: 0);
1625 /* only upper 6 bits (HASH_BITS) are used
1626 * which point to specific bit in he hash registers
1628 hash
= (crc
>> (32 - HASH_BITS
)) & 0x3f;
1631 tmp
= readl(fep
->hwp
+ FEC_GRP_HASH_TABLE_HIGH
);
1632 tmp
|= 1 << (hash
- 32);
1633 writel(tmp
, fep
->hwp
+ FEC_GRP_HASH_TABLE_HIGH
);
1635 tmp
= readl(fep
->hwp
+ FEC_GRP_HASH_TABLE_LOW
);
1637 writel(tmp
, fep
->hwp
+ FEC_GRP_HASH_TABLE_LOW
);
1642 /* Set a MAC change in hardware. */
1644 fec_set_mac_address(struct net_device
*dev
, void *p
)
1646 struct fec_enet_private
*fep
= netdev_priv(dev
);
1647 struct sockaddr
*addr
= p
;
1649 if (!is_valid_ether_addr(addr
->sa_data
))
1650 return -EADDRNOTAVAIL
;
1652 memcpy(dev
->dev_addr
, addr
->sa_data
, dev
->addr_len
);
1654 writel(dev
->dev_addr
[3] | (dev
->dev_addr
[2] << 8) |
1655 (dev
->dev_addr
[1] << 16) | (dev
->dev_addr
[0] << 24),
1656 fep
->hwp
+ FEC_ADDR_LOW
);
1657 writel((dev
->dev_addr
[5] << 16) | (dev
->dev_addr
[4] << 24),
1658 fep
+ FEC_ADDR_HIGH
);
1662 static const struct net_device_ops fec_netdev_ops
= {
1663 .ndo_open
= fec_enet_open
,
1664 .ndo_stop
= fec_enet_close
,
1665 .ndo_start_xmit
= fec_enet_start_xmit
,
1666 .ndo_set_multicast_list
= set_multicast_list
,
1667 .ndo_change_mtu
= eth_change_mtu
,
1668 .ndo_validate_addr
= eth_validate_addr
,
1669 .ndo_tx_timeout
= fec_timeout
,
1670 .ndo_set_mac_address
= fec_set_mac_address
,
1674 * XXX: We need to clean up on failure exits here.
1676 * index is only used in legacy code
1678 static int fec_enet_init(struct net_device
*dev
, int index
)
1680 struct fec_enet_private
*fep
= netdev_priv(dev
);
1681 struct bufdesc
*cbd_base
;
1682 struct bufdesc
*bdp
;
1685 /* Allocate memory for buffer descriptors. */
1686 cbd_base
= dma_alloc_coherent(NULL
, PAGE_SIZE
, &fep
->bd_dma
,
1689 printk("FEC: allocate descriptor memory failed?\n");
1693 spin_lock_init(&fep
->hw_lock
);
1694 spin_lock_init(&fep
->mii_lock
);
1697 fep
->hwp
= (void __iomem
*)dev
->base_addr
;
1700 /* Set the Ethernet address */
1706 l
= readl(fep
->hwp
+ FEC_ADDR_LOW
);
1707 dev
->dev_addr
[0] = (unsigned char)((l
& 0xFF000000) >> 24);
1708 dev
->dev_addr
[1] = (unsigned char)((l
& 0x00FF0000) >> 16);
1709 dev
->dev_addr
[2] = (unsigned char)((l
& 0x0000FF00) >> 8);
1710 dev
->dev_addr
[3] = (unsigned char)((l
& 0x000000FF) >> 0);
1711 l
= readl(fep
->hwp
+ FEC_ADDR_HIGH
);
1712 dev
->dev_addr
[4] = (unsigned char)((l
& 0xFF000000) >> 24);
1713 dev
->dev_addr
[5] = (unsigned char)((l
& 0x00FF0000) >> 16);
1717 /* Set receive and transmit descriptor base. */
1718 fep
->rx_bd_base
= cbd_base
;
1719 fep
->tx_bd_base
= cbd_base
+ RX_RING_SIZE
;
1721 #ifdef HAVE_mii_link_interrupt
1722 fec_request_mii_intr(dev
);
1724 /* The FEC Ethernet specific entries in the device structure */
1725 dev
->watchdog_timeo
= TX_TIMEOUT
;
1726 dev
->netdev_ops
= &fec_netdev_ops
;
1728 for (i
=0; i
<NMII
-1; i
++)
1729 mii_cmds
[i
].mii_next
= &mii_cmds
[i
+1];
1730 mii_free
= mii_cmds
;
1732 /* Set MII speed to 2.5 MHz */
1733 fep
->phy_speed
= ((((clk_get_rate(fep
->clk
) / 2 + 4999999)
1734 / 2500000) / 2) & 0x3F) << 1;
1736 /* Initialize the receive buffer descriptors. */
1737 bdp
= fep
->rx_bd_base
;
1738 for (i
= 0; i
< RX_RING_SIZE
; i
++) {
1740 /* Initialize the BD for every fragment in the page. */
1745 /* Set the last buffer to wrap */
1747 bdp
->cbd_sc
|= BD_SC_WRAP
;
1749 /* ...and the same for transmit */
1750 bdp
= fep
->tx_bd_base
;
1751 for (i
= 0; i
< TX_RING_SIZE
; i
++) {
1753 /* Initialize the BD for every fragment in the page. */
1755 bdp
->cbd_bufaddr
= 0;
1759 /* Set the last buffer to wrap */
1761 bdp
->cbd_sc
|= BD_SC_WRAP
;
1763 fec_restart(dev
, 0);
1765 /* Queue up command to detect the PHY and initialize the
1766 * remainder of the interface.
1768 fep
->phy_id_done
= 0;
1770 mii_queue(dev
, mk_mii_read(MII_REG_PHYIR1
), mii_discover_phy
);
1775 /* This function is called to start or restart the FEC during a link
1776 * change. This only happens when switching between half and full
1780 fec_restart(struct net_device
*dev
, int duplex
)
1782 struct fec_enet_private
*fep
= netdev_priv(dev
);
1785 /* Whack a reset. We should wait for this. */
1786 writel(1, fep
->hwp
+ FEC_ECNTRL
);
1789 /* Clear any outstanding interrupt. */
1790 writel(0xffc00000, fep
->hwp
+ FEC_IEVENT
);
1792 /* Reset all multicast. */
1793 writel(0, fep
->hwp
+ FEC_GRP_HASH_TABLE_HIGH
);
1794 writel(0, fep
->hwp
+ FEC_GRP_HASH_TABLE_LOW
);
1795 #ifndef CONFIG_M5272
1796 writel(0, fep
->hwp
+ FEC_HASH_TABLE_HIGH
);
1797 writel(0, fep
->hwp
+ FEC_HASH_TABLE_LOW
);
1800 /* Set maximum receive buffer size. */
1801 writel(PKT_MAXBLR_SIZE
, fep
->hwp
+ FEC_R_BUFF_SIZE
);
1803 /* Set receive and transmit descriptor base. */
1804 writel(fep
->bd_dma
, fep
->hwp
+ FEC_R_DES_START
);
1805 writel((unsigned long)fep
->bd_dma
+ sizeof(struct bufdesc
) * RX_RING_SIZE
,
1806 fep
->hwp
+ FEC_X_DES_START
);
1808 fep
->dirty_tx
= fep
->cur_tx
= fep
->tx_bd_base
;
1809 fep
->cur_rx
= fep
->rx_bd_base
;
1811 /* Reset SKB transmit buffers. */
1812 fep
->skb_cur
= fep
->skb_dirty
= 0;
1813 for (i
= 0; i
<= TX_RING_MOD_MASK
; i
++) {
1814 if (fep
->tx_skbuff
[i
]) {
1815 dev_kfree_skb_any(fep
->tx_skbuff
[i
]);
1816 fep
->tx_skbuff
[i
] = NULL
;
1820 /* Enable MII mode */
1822 /* MII enable / FD enable */
1823 writel(OPT_FRAME_SIZE
| 0x04, fep
->hwp
+ FEC_R_CNTRL
);
1824 writel(0x04, fep
->hwp
+ FEC_X_CNTRL
);
1826 /* MII enable / No Rcv on Xmit */
1827 writel(OPT_FRAME_SIZE
| 0x06, fep
->hwp
+ FEC_R_CNTRL
);
1828 writel(0x0, fep
->hwp
+ FEC_X_CNTRL
);
1830 fep
->full_duplex
= duplex
;
1833 writel(fep
->phy_speed
, fep
->hwp
+ FEC_MII_SPEED
);
1835 /* And last, enable the transmit and receive processing */
1836 writel(2, fep
->hwp
+ FEC_ECNTRL
);
1837 writel(0, fep
->hwp
+ FEC_R_DES_ACTIVE
);
1839 /* Enable interrupts we wish to service */
1840 writel(FEC_ENET_TXF
| FEC_ENET_RXF
| FEC_ENET_MII
,
1841 fep
->hwp
+ FEC_IMASK
);
1845 fec_stop(struct net_device
*dev
)
1847 struct fec_enet_private
*fep
= netdev_priv(dev
);
1849 /* We cannot expect a graceful transmit stop without link !!! */
1851 writel(1, fep
->hwp
+ FEC_X_CNTRL
); /* Graceful transmit stop */
1853 if (!(readl(fep
->hwp
+ FEC_IEVENT
) & FEC_ENET_GRA
))
1854 printk("fec_stop : Graceful transmit stop did not complete !\n");
1857 /* Whack a reset. We should wait for this. */
1858 writel(1, fep
->hwp
+ FEC_ECNTRL
);
1861 /* Clear outstanding MII command interrupts. */
1862 writel(FEC_ENET_MII
, fep
->hwp
+ FEC_IEVENT
);
1864 writel(FEC_ENET_MII
, fep
->hwp
+ FEC_IMASK
);
1865 writel(fep
->phy_speed
, fep
->hwp
+ FEC_MII_SPEED
);
1868 static int __devinit
1869 fec_probe(struct platform_device
*pdev
)
1871 struct fec_enet_private
*fep
;
1872 struct net_device
*ndev
;
1873 int i
, irq
, ret
= 0;
1876 r
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
1880 r
= request_mem_region(r
->start
, resource_size(r
), pdev
->name
);
1884 /* Init network device */
1885 ndev
= alloc_etherdev(sizeof(struct fec_enet_private
));
1889 SET_NETDEV_DEV(ndev
, &pdev
->dev
);
1891 /* setup board info structure */
1892 fep
= netdev_priv(ndev
);
1893 memset(fep
, 0, sizeof(*fep
));
1895 ndev
->base_addr
= (unsigned long)ioremap(r
->start
, resource_size(r
));
1897 if (!ndev
->base_addr
) {
1899 goto failed_ioremap
;
1902 platform_set_drvdata(pdev
, ndev
);
1904 /* This device has up to three irqs on some platforms */
1905 for (i
= 0; i
< 3; i
++) {
1906 irq
= platform_get_irq(pdev
, i
);
1909 ret
= request_irq(irq
, fec_enet_interrupt
, IRQF_DISABLED
, pdev
->name
, ndev
);
1912 irq
= platform_get_irq(pdev
, i
);
1913 free_irq(irq
, ndev
);
1920 fep
->clk
= clk_get(&pdev
->dev
, "fec_clk");
1921 if (IS_ERR(fep
->clk
)) {
1922 ret
= PTR_ERR(fep
->clk
);
1925 clk_enable(fep
->clk
);
1927 ret
= fec_enet_init(ndev
, 0);
1931 ret
= register_netdev(ndev
);
1933 goto failed_register
;
1939 clk_disable(fep
->clk
);
1942 for (i
= 0; i
< 3; i
++) {
1943 irq
= platform_get_irq(pdev
, i
);
1945 free_irq(irq
, ndev
);
1948 iounmap((void __iomem
*)ndev
->base_addr
);
1955 static int __devexit
1956 fec_drv_remove(struct platform_device
*pdev
)
1958 struct net_device
*ndev
= platform_get_drvdata(pdev
);
1959 struct fec_enet_private
*fep
= netdev_priv(ndev
);
1961 platform_set_drvdata(pdev
, NULL
);
1964 clk_disable(fep
->clk
);
1966 iounmap((void __iomem
*)ndev
->base_addr
);
1967 unregister_netdev(ndev
);
1973 fec_suspend(struct platform_device
*dev
, pm_message_t state
)
1975 struct net_device
*ndev
= platform_get_drvdata(dev
);
1976 struct fec_enet_private
*fep
;
1979 fep
= netdev_priv(ndev
);
1980 if (netif_running(ndev
)) {
1981 netif_device_detach(ndev
);
1989 fec_resume(struct platform_device
*dev
)
1991 struct net_device
*ndev
= platform_get_drvdata(dev
);
1994 if (netif_running(ndev
)) {
1995 fec_enet_init(ndev
, 0);
1996 netif_device_attach(ndev
);
2002 static struct platform_driver fec_driver
= {
2005 .owner
= THIS_MODULE
,
2008 .remove
= __devexit_p(fec_drv_remove
),
2009 .suspend
= fec_suspend
,
2010 .resume
= fec_resume
,
2014 fec_enet_module_init(void)
2016 printk(KERN_INFO
"FEC Ethernet Driver\n");
2018 return platform_driver_register(&fec_driver
);
2022 fec_enet_cleanup(void)
2024 platform_driver_unregister(&fec_driver
);
2027 module_exit(fec_enet_cleanup
);
2028 module_init(fec_enet_module_init
);
2030 MODULE_LICENSE("GPL");