2 * Blackfin CPLB initialization
4 * Copyright 2004-2007 Analog Devices Inc.
6 * Bugs: Enter bugs at http://blackfin.uclinux.org/
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, see the file COPYING, or write
20 * to the Free Software Foundation, Inc.,
21 * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
23 #include <linux/module.h>
25 #include <asm/blackfin.h>
26 #include <asm/cacheflush.h>
28 #include <asm/cplbinit.h>
30 u_long icplb_tables
[NR_CPUS
][CPLB_TBL_ENTRIES
+1];
31 u_long dcplb_tables
[NR_CPUS
][CPLB_TBL_ENTRIES
+1];
33 #ifdef CONFIG_CPLB_SWITCH_TAB_L1
34 #define PDT_ATTR __attribute__((l1_data))
39 u_long ipdt_tables
[NR_CPUS
][MAX_SWITCH_I_CPLBS
+1] PDT_ATTR
;
40 u_long dpdt_tables
[NR_CPUS
][MAX_SWITCH_D_CPLBS
+1] PDT_ATTR
;
41 #ifdef CONFIG_CPLB_INFO
42 u_long ipdt_swapcount_tables
[NR_CPUS
][MAX_SWITCH_I_CPLBS
] PDT_ATTR
;
43 u_long dpdt_swapcount_tables
[NR_CPUS
][MAX_SWITCH_D_CPLBS
] PDT_ATTR
;
47 struct cplb_tab init_i
;
48 struct cplb_tab init_d
;
49 struct cplb_tab switch_i
;
50 struct cplb_tab switch_d
;
53 #if defined(CONFIG_BFIN_DCACHE) || defined(CONFIG_BFIN_ICACHE)
54 static struct cplb_desc cplb_data
[] = {
59 .attr
= INITIAL_T
| SWITCH_T
| I_CPLB
| D_CPLB
,
62 #if defined(CONFIG_DEBUG_HUNT_FOR_ZERO)
67 .name
= "Zero Pointer Guard Page",
70 .start
= 0, /* dyanmic */
71 .end
= 0, /* dynamic */
73 .attr
= INITIAL_T
| SWITCH_T
| I_CPLB
,
77 .name
= "L1 I-Memory",
80 .start
= 0, /* dynamic */
81 .end
= 0, /* dynamic */
83 .attr
= INITIAL_T
| SWITCH_T
| D_CPLB
,
86 #if ((L1_DATA_A_LENGTH > 0) || (L1_DATA_B_LENGTH > 0))
91 .name
= "L1 D-Memory",
95 .end
= L2_START
+ L2_LENGTH
,
100 .valid
= (L2_LENGTH
> 0),
105 .end
= 0, /* dynamic */
107 .attr
= INITIAL_T
| SWITCH_T
| I_CPLB
| D_CPLB
,
108 .i_conf
= SDRAM_IGENERIC
,
109 .d_conf
= SDRAM_DGENERIC
,
111 .name
= "Kernel Memory",
114 .start
= 0, /* dynamic */
115 .end
= 0, /* dynamic */
117 .attr
= INITIAL_T
| SWITCH_T
| D_CPLB
,
118 .i_conf
= SDRAM_IGENERIC
,
119 .d_conf
= SDRAM_DNON_CHBL
,
121 .name
= "uClinux MTD Memory",
124 .start
= 0, /* dynamic */
125 .end
= 0, /* dynamic */
127 .attr
= INITIAL_T
| SWITCH_T
| D_CPLB
,
128 .d_conf
= SDRAM_DNON_CHBL
,
130 .name
= "Uncached DMA Zone",
133 .start
= 0, /* dynamic */
134 .end
= 0, /* dynamic */
136 .attr
= SWITCH_T
| D_CPLB
,
137 .i_conf
= 0, /* dynamic */
138 .d_conf
= 0, /* dynamic */
140 .name
= "Reserved Memory",
143 .start
= ASYNC_BANK0_BASE
,
144 .end
= ASYNC_BANK3_BASE
+ ASYNC_BANK3_SIZE
,
146 .attr
= SWITCH_T
| D_CPLB
,
147 .d_conf
= SDRAM_EBIU
,
149 .name
= "Asynchronous Memory Banks",
152 .start
= BOOT_ROM_START
,
153 .end
= BOOT_ROM_START
+ BOOT_ROM_LENGTH
,
155 .attr
= SWITCH_T
| I_CPLB
| D_CPLB
,
156 .i_conf
= SDRAM_IGENERIC
,
157 .d_conf
= SDRAM_DGENERIC
,
159 .name
= "On-Chip BootROM",
163 static bool __init
lock_kernel_check(u32 start
, u32 end
)
165 if (start
>= (u32
)_end
|| end
<= (u32
)_stext
)
168 /* This cplb block overlapped with kernel area. */
172 static unsigned short __init
173 fill_cplbtab(struct cplb_tab
*table
,
174 unsigned long start
, unsigned long end
,
175 unsigned long block_size
, unsigned long cplb_data
)
179 switch (block_size
) {
195 cplb_data
= (cplb_data
& ~(3 << 16)) | (i
<< 16);
197 while ((start
< end
) && (table
->pos
< table
->size
)) {
199 table
->tab
[table
->pos
++] = start
;
201 if (lock_kernel_check(start
, start
+ block_size
))
202 table
->tab
[table
->pos
++] =
203 cplb_data
| CPLB_LOCK
| CPLB_DIRTY
;
205 table
->tab
[table
->pos
++] = cplb_data
;
212 static unsigned short __init
213 close_cplbtab(struct cplb_tab
*table
)
216 while (table
->pos
< table
->size
) {
218 table
->tab
[table
->pos
++] = 0;
219 table
->tab
[table
->pos
++] = 0; /* !CPLB_VALID */
224 /* helper function */
226 __fill_code_cplbtab(struct cplb_tab
*t
, int i
, u32 a_start
, u32 a_end
)
228 if (cplb_data
[i
].psize
) {
233 cplb_data
[i
].i_conf
);
235 #if defined(CONFIG_BFIN_ICACHE)
236 if (ANOMALY_05000263
&& i
== SDRAM_KERN
) {
241 cplb_data
[i
].i_conf
);
249 cplb_data
[i
].i_conf
);
254 cplb_data
[i
].i_conf
);
255 fill_cplbtab(t
, a_end
,
258 cplb_data
[i
].i_conf
);
264 __fill_data_cplbtab(struct cplb_tab
*t
, int i
, u32 a_start
, u32 a_end
)
266 if (cplb_data
[i
].psize
) {
271 cplb_data
[i
].d_conf
);
276 cplb_data
[i
].d_conf
);
277 fill_cplbtab(t
, a_start
,
279 cplb_data
[i
].d_conf
);
280 fill_cplbtab(t
, a_end
,
283 cplb_data
[i
].d_conf
);
287 void __init
generate_cplb_tables_cpu(unsigned int cpu
)
291 u32 a_start
, a_end
, as
, ae
, as_1m
;
293 struct cplb_tab
*t_i
= NULL
;
294 struct cplb_tab
*t_d
= NULL
;
297 printk(KERN_INFO
"NOMPU: setting up cplb tables for global access\n");
299 cplb
.init_i
.size
= CPLB_TBL_ENTRIES
;
300 cplb
.init_d
.size
= CPLB_TBL_ENTRIES
;
301 cplb
.switch_i
.size
= MAX_SWITCH_I_CPLBS
;
302 cplb
.switch_d
.size
= MAX_SWITCH_D_CPLBS
;
306 cplb
.switch_i
.pos
= 0;
307 cplb
.switch_d
.pos
= 0;
309 cplb
.init_i
.tab
= icplb_tables
[cpu
];
310 cplb
.init_d
.tab
= dcplb_tables
[cpu
];
311 cplb
.switch_i
.tab
= ipdt_tables
[cpu
];
312 cplb
.switch_d
.tab
= dpdt_tables
[cpu
];
314 cplb_data
[L1I_MEM
].start
= get_l1_code_start_cpu(cpu
);
315 cplb_data
[L1I_MEM
].end
= cplb_data
[L1I_MEM
].start
+ L1_CODE_LENGTH
;
316 cplb_data
[L1D_MEM
].start
= get_l1_data_a_start_cpu(cpu
);
317 cplb_data
[L1D_MEM
].end
= get_l1_data_b_start_cpu(cpu
) + L1_DATA_B_LENGTH
;
318 cplb_data
[SDRAM_KERN
].end
= memory_end
;
320 #ifdef CONFIG_MTD_UCLINUX
321 cplb_data
[SDRAM_RAM_MTD
].start
= memory_mtd_start
;
322 cplb_data
[SDRAM_RAM_MTD
].end
= memory_mtd_start
+ mtd_size
;
323 cplb_data
[SDRAM_RAM_MTD
].valid
= mtd_size
> 0;
324 # if defined(CONFIG_ROMFS_FS)
325 cplb_data
[SDRAM_RAM_MTD
].attr
|= I_CPLB
;
328 * The ROMFS_FS size is often not multiple of 1MB.
329 * This can cause multiple CPLB sets covering the same memory area.
330 * This will then cause multiple CPLB hit exceptions.
331 * Workaround: We ensure a contiguous memory area by extending the kernel
332 * memory section over the mtd section.
333 * For ROMFS_FS memory must be covered with ICPLBs anyways.
334 * So there is no difference between kernel and mtd memory setup.
337 cplb_data
[SDRAM_KERN
].end
= memory_mtd_start
+ mtd_size
;;
338 cplb_data
[SDRAM_RAM_MTD
].valid
= 0;
342 cplb_data
[SDRAM_RAM_MTD
].valid
= 0;
345 cplb_data
[SDRAM_DMAZ
].start
= _ramend
- DMA_UNCACHED_REGION
;
346 cplb_data
[SDRAM_DMAZ
].end
= _ramend
;
348 cplb_data
[RES_MEM
].start
= _ramend
;
349 cplb_data
[RES_MEM
].end
= physical_mem_end
;
351 if (reserved_mem_dcache_on
)
352 cplb_data
[RES_MEM
].d_conf
= SDRAM_DGENERIC
;
354 cplb_data
[RES_MEM
].d_conf
= SDRAM_DNON_CHBL
;
356 if (reserved_mem_icache_on
)
357 cplb_data
[RES_MEM
].i_conf
= SDRAM_IGENERIC
;
359 cplb_data
[RES_MEM
].i_conf
= SDRAM_INON_CHBL
;
361 for (i
= ZERO_P
; i
< ARRAY_SIZE(cplb_data
); ++i
) {
362 if (!cplb_data
[i
].valid
)
365 as_1m
= cplb_data
[i
].start
% SIZE_1M
;
367 /* We need to make sure all sections are properly 1M aligned
368 * However between Kernel Memory and the Kernel mtd section, depending on the
369 * rootfs size, there can be overlapping memory areas.
372 if (as_1m
&& i
!= L1I_MEM
&& i
!= L1D_MEM
) {
373 #ifdef CONFIG_MTD_UCLINUX
374 if (i
== SDRAM_RAM_MTD
) {
375 if ((cplb_data
[SDRAM_KERN
].end
+ 1) > cplb_data
[SDRAM_RAM_MTD
].start
)
376 cplb_data
[SDRAM_RAM_MTD
].start
= (cplb_data
[i
].start
& (-2*SIZE_1M
)) + SIZE_1M
;
378 cplb_data
[SDRAM_RAM_MTD
].start
= (cplb_data
[i
].start
& (-2*SIZE_1M
));
381 printk(KERN_WARNING
"Unaligned Start of %s at 0x%X\n",
382 cplb_data
[i
].name
, cplb_data
[i
].start
);
385 as
= cplb_data
[i
].start
% SIZE_4M
;
386 ae
= cplb_data
[i
].end
% SIZE_4M
;
389 a_start
= cplb_data
[i
].start
+ (SIZE_4M
- (as
));
391 a_start
= cplb_data
[i
].start
;
393 a_end
= cplb_data
[i
].end
- ae
;
395 for (j
= INITIAL_T
; j
<= SWITCH_T
; j
++) {
399 if (cplb_data
[i
].attr
& INITIAL_T
) {
407 if (cplb_data
[i
].attr
& SWITCH_T
) {
408 t_i
= &cplb
.switch_i
;
409 t_d
= &cplb
.switch_d
;
421 if (cplb_data
[i
].attr
& I_CPLB
)
422 __fill_code_cplbtab(t_i
, i
, a_start
, a_end
);
424 if (cplb_data
[i
].attr
& D_CPLB
)
425 __fill_data_cplbtab(t_d
, i
, a_start
, a_end
);
431 close_cplbtab(&cplb
.init_i
);
432 close_cplbtab(&cplb
.init_d
);
434 cplb
.init_i
.tab
[cplb
.init_i
.pos
] = -1;
435 cplb
.init_d
.tab
[cplb
.init_d
.pos
] = -1;
436 cplb
.switch_i
.tab
[cplb
.switch_i
.pos
] = -1;
437 cplb
.switch_d
.tab
[cplb
.switch_d
.pos
] = -1;