1 /******************************************************************************
3 * Copyright(c) 2003 - 2011 Intel Corporation. All rights reserved.
5 * Portions of this file are derived from the ipw3945 project, as well
6 * as portions of the ieee80211 subsystem header files.
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of version 2 of the GNU General Public License as
10 * published by the Free Software Foundation.
12 * This program is distributed in the hope that it will be useful, but WITHOUT
13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
17 * You should have received a copy of the GNU General Public License along with
18 * this program; if not, write to the Free Software Foundation, Inc.,
19 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
21 * The full GNU General Public License is included in this distribution in the
22 * file called LICENSE.
24 * Contact Information:
25 * Intel Linux Wireless <ilw@linux.intel.com>
26 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
28 *****************************************************************************/
30 #include <linux/etherdevice.h>
31 #include <linux/sched.h>
32 #include <linux/slab.h>
33 #include <net/mac80211.h>
34 #include "iwl-eeprom.h"
40 #include "iwl-helpers.h"
43 * iwl_txq_update_write_ptr - Send new write index to hardware
45 void iwl_txq_update_write_ptr(struct iwl_priv
*priv
, struct iwl_tx_queue
*txq
)
48 int txq_id
= txq
->q
.id
;
50 if (txq
->need_update
== 0)
53 if (priv
->cfg
->base_params
->shadow_reg_enable
) {
54 /* shadow register enabled */
55 iwl_write32(priv
, HBUS_TARG_WRPTR
,
56 txq
->q
.write_ptr
| (txq_id
<< 8));
58 /* if we're trying to save power */
59 if (test_bit(STATUS_POWER_PMI
, &priv
->status
)) {
60 /* wake up nic if it's powered down ...
61 * uCode will wake up, and interrupt us again, so next
62 * time we'll skip this part. */
63 reg
= iwl_read32(priv
, CSR_UCODE_DRV_GP1
);
65 if (reg
& CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP
) {
67 "Tx queue %d requesting wakeup,"
68 " GP1 = 0x%x\n", txq_id
, reg
);
69 iwl_set_bit(priv
, CSR_GP_CNTRL
,
70 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ
);
74 iwl_write_direct32(priv
, HBUS_TARG_WRPTR
,
75 txq
->q
.write_ptr
| (txq_id
<< 8));
78 * else not in power-save mode,
79 * uCode will never sleep when we're
80 * trying to tx (during RFKILL, we're not trying to tx).
83 iwl_write32(priv
, HBUS_TARG_WRPTR
,
84 txq
->q
.write_ptr
| (txq_id
<< 8));
89 static inline dma_addr_t
iwl_tfd_tb_get_addr(struct iwl_tfd
*tfd
, u8 idx
)
91 struct iwl_tfd_tb
*tb
= &tfd
->tbs
[idx
];
93 dma_addr_t addr
= get_unaligned_le32(&tb
->lo
);
94 if (sizeof(dma_addr_t
) > sizeof(u32
))
96 ((dma_addr_t
)(le16_to_cpu(tb
->hi_n_len
) & 0xF) << 16) << 16;
101 static inline u16
iwl_tfd_tb_get_len(struct iwl_tfd
*tfd
, u8 idx
)
103 struct iwl_tfd_tb
*tb
= &tfd
->tbs
[idx
];
105 return le16_to_cpu(tb
->hi_n_len
) >> 4;
108 static inline void iwl_tfd_set_tb(struct iwl_tfd
*tfd
, u8 idx
,
109 dma_addr_t addr
, u16 len
)
111 struct iwl_tfd_tb
*tb
= &tfd
->tbs
[idx
];
112 u16 hi_n_len
= len
<< 4;
114 put_unaligned_le32(addr
, &tb
->lo
);
115 if (sizeof(dma_addr_t
) > sizeof(u32
))
116 hi_n_len
|= ((addr
>> 16) >> 16) & 0xF;
118 tb
->hi_n_len
= cpu_to_le16(hi_n_len
);
120 tfd
->num_tbs
= idx
+ 1;
123 static inline u8
iwl_tfd_get_num_tbs(struct iwl_tfd
*tfd
)
125 return tfd
->num_tbs
& 0x1f;
129 * iwlagn_txq_free_tfd - Free all chunks referenced by TFD [txq->q.read_ptr]
130 * @priv - driver private data
133 * Does NOT advance any TFD circular buffer read/write indexes
134 * Does NOT free the TFD itself (which is within circular buffer)
136 void iwlagn_txq_free_tfd(struct iwl_priv
*priv
, struct iwl_tx_queue
*txq
)
138 struct iwl_tfd
*tfd_tmp
= (struct iwl_tfd
*)txq
->tfds
;
140 struct pci_dev
*dev
= priv
->pci_dev
;
141 int index
= txq
->q
.read_ptr
;
145 tfd
= &tfd_tmp
[index
];
147 /* Sanity check on number of chunks */
148 num_tbs
= iwl_tfd_get_num_tbs(tfd
);
150 if (num_tbs
>= IWL_NUM_OF_TBS
) {
151 IWL_ERR(priv
, "Too many chunks: %i\n", num_tbs
);
152 /* @todo issue fatal error, it is quite serious situation */
158 pci_unmap_single(dev
,
159 dma_unmap_addr(&txq
->meta
[index
], mapping
),
160 dma_unmap_len(&txq
->meta
[index
], len
),
161 PCI_DMA_BIDIRECTIONAL
);
163 /* Unmap chunks, if any. */
164 for (i
= 1; i
< num_tbs
; i
++)
165 pci_unmap_single(dev
, iwl_tfd_tb_get_addr(tfd
, i
),
166 iwl_tfd_tb_get_len(tfd
, i
), PCI_DMA_TODEVICE
);
172 skb
= txq
->txb
[txq
->q
.read_ptr
].skb
;
174 /* can be called from irqs-disabled context */
176 dev_kfree_skb_any(skb
);
177 txq
->txb
[txq
->q
.read_ptr
].skb
= NULL
;
182 int iwlagn_txq_attach_buf_to_tfd(struct iwl_priv
*priv
,
183 struct iwl_tx_queue
*txq
,
184 dma_addr_t addr
, u16 len
,
188 struct iwl_tfd
*tfd
, *tfd_tmp
;
192 tfd_tmp
= (struct iwl_tfd
*)txq
->tfds
;
193 tfd
= &tfd_tmp
[q
->write_ptr
];
196 memset(tfd
, 0, sizeof(*tfd
));
198 num_tbs
= iwl_tfd_get_num_tbs(tfd
);
200 /* Each TFD can point to a maximum 20 Tx buffers */
201 if (num_tbs
>= IWL_NUM_OF_TBS
) {
202 IWL_ERR(priv
, "Error can not send more than %d chunks\n",
207 if (WARN_ON(addr
& ~DMA_BIT_MASK(36)))
210 if (unlikely(addr
& ~IWL_TX_DMA_MASK
))
211 IWL_ERR(priv
, "Unaligned address = %llx\n",
212 (unsigned long long)addr
);
214 iwl_tfd_set_tb(tfd
, num_tbs
, addr
, len
);
220 * Tell nic where to find circular buffer of Tx Frame Descriptors for
221 * given Tx queue, and enable the DMA channel used for that queue.
223 * supports up to 16 Tx queues in DRAM, mapped to up to 8 Tx DMA
224 * channels supported in hardware.
226 static int iwlagn_tx_queue_init(struct iwl_priv
*priv
, struct iwl_tx_queue
*txq
)
228 int txq_id
= txq
->q
.id
;
230 /* Circular buffer (TFD queue in DRAM) physical base address */
231 iwl_write_direct32(priv
, FH_MEM_CBBC_QUEUE(txq_id
),
232 txq
->q
.dma_addr
>> 8);
238 * iwl_tx_queue_unmap - Unmap any remaining DMA mappings and free skb's
240 void iwl_tx_queue_unmap(struct iwl_priv
*priv
, int txq_id
)
242 struct iwl_tx_queue
*txq
= &priv
->txq
[txq_id
];
243 struct iwl_queue
*q
= &txq
->q
;
248 while (q
->write_ptr
!= q
->read_ptr
) {
249 iwlagn_txq_free_tfd(priv
, txq
);
250 q
->read_ptr
= iwl_queue_inc_wrap(q
->read_ptr
, q
->n_bd
);
255 * iwl_tx_queue_free - Deallocate DMA queue.
256 * @txq: Transmit queue to deallocate.
258 * Empty queue by removing and destroying all BD's.
260 * 0-fill, but do not free "txq" descriptor structure.
262 void iwl_tx_queue_free(struct iwl_priv
*priv
, int txq_id
)
264 struct iwl_tx_queue
*txq
= &priv
->txq
[txq_id
];
265 struct device
*dev
= &priv
->pci_dev
->dev
;
268 iwl_tx_queue_unmap(priv
, txq_id
);
270 /* De-alloc array of command/tx buffers */
271 for (i
= 0; i
< TFD_TX_CMD_SLOTS
; i
++)
274 /* De-alloc circular buffer of TFDs */
276 dma_free_coherent(dev
, priv
->hw_params
.tfd_size
*
277 txq
->q
.n_bd
, txq
->tfds
, txq
->q
.dma_addr
);
279 /* De-alloc array of per-TFD driver data */
283 /* deallocate arrays */
289 /* 0-fill queue descriptor structure */
290 memset(txq
, 0, sizeof(*txq
));
294 * iwl_cmd_queue_unmap - Unmap any remaining DMA mappings from command queue
296 void iwl_cmd_queue_unmap(struct iwl_priv
*priv
)
298 struct iwl_tx_queue
*txq
= &priv
->txq
[priv
->cmd_queue
];
299 struct iwl_queue
*q
= &txq
->q
;
305 while (q
->read_ptr
!= q
->write_ptr
) {
306 i
= get_cmd_index(q
, q
->read_ptr
, 0);
308 if (txq
->meta
[i
].flags
& CMD_MAPPED
) {
309 pci_unmap_single(priv
->pci_dev
,
310 dma_unmap_addr(&txq
->meta
[i
], mapping
),
311 dma_unmap_len(&txq
->meta
[i
], len
),
312 PCI_DMA_BIDIRECTIONAL
);
313 txq
->meta
[i
].flags
= 0;
316 q
->read_ptr
= iwl_queue_inc_wrap(q
->read_ptr
, q
->n_bd
);
320 if (txq
->meta
[i
].flags
& CMD_MAPPED
) {
321 pci_unmap_single(priv
->pci_dev
,
322 dma_unmap_addr(&txq
->meta
[i
], mapping
),
323 dma_unmap_len(&txq
->meta
[i
], len
),
324 PCI_DMA_BIDIRECTIONAL
);
325 txq
->meta
[i
].flags
= 0;
330 * iwl_cmd_queue_free - Deallocate DMA queue.
331 * @txq: Transmit queue to deallocate.
333 * Empty queue by removing and destroying all BD's.
335 * 0-fill, but do not free "txq" descriptor structure.
337 void iwl_cmd_queue_free(struct iwl_priv
*priv
)
339 struct iwl_tx_queue
*txq
= &priv
->txq
[priv
->cmd_queue
];
340 struct device
*dev
= &priv
->pci_dev
->dev
;
343 iwl_cmd_queue_unmap(priv
);
345 /* De-alloc array of command/tx buffers */
346 for (i
= 0; i
<= TFD_CMD_SLOTS
; i
++)
349 /* De-alloc circular buffer of TFDs */
351 dma_free_coherent(dev
, priv
->hw_params
.tfd_size
* txq
->q
.n_bd
,
352 txq
->tfds
, txq
->q
.dma_addr
);
354 /* deallocate arrays */
360 /* 0-fill queue descriptor structure */
361 memset(txq
, 0, sizeof(*txq
));
364 /*************** DMA-QUEUE-GENERAL-FUNCTIONS *****
367 * Theory of operation
369 * A Tx or Rx queue resides in host DRAM, and is comprised of a circular buffer
370 * of buffer descriptors, each of which points to one or more data buffers for
371 * the device to read from or fill. Driver and device exchange status of each
372 * queue via "read" and "write" pointers. Driver keeps minimum of 2 empty
373 * entries in each circular buffer, to protect against confusing empty and full
376 * The device reads or writes the data in the queues via the device's several
377 * DMA/FIFO channels. Each queue is mapped to a single DMA channel.
379 * For Tx queue, there are low mark and high mark limits. If, after queuing
380 * the packet for Tx, free space become < low mark, Tx queue stopped. When
381 * reclaiming packets (on 'tx done IRQ), if free space become > high mark,
384 ***************************************************/
386 int iwl_queue_space(const struct iwl_queue
*q
)
388 int s
= q
->read_ptr
- q
->write_ptr
;
390 if (q
->read_ptr
> q
->write_ptr
)
395 /* keep some reserve to not confuse empty and full situations */
404 * iwl_queue_init - Initialize queue's high/low-water and read/write indexes
406 static int iwl_queue_init(struct iwl_priv
*priv
, struct iwl_queue
*q
,
407 int count
, int slots_num
, u32 id
)
410 q
->n_window
= slots_num
;
413 /* count must be power-of-two size, otherwise iwl_queue_inc_wrap
414 * and iwl_queue_dec_wrap are broken. */
415 if (WARN_ON(!is_power_of_2(count
)))
418 /* slots_num must be power-of-two size, otherwise
419 * get_cmd_index is broken. */
420 if (WARN_ON(!is_power_of_2(slots_num
)))
423 q
->low_mark
= q
->n_window
/ 4;
427 q
->high_mark
= q
->n_window
/ 8;
428 if (q
->high_mark
< 2)
431 q
->write_ptr
= q
->read_ptr
= 0;
437 * iwl_tx_queue_alloc - Alloc driver data and TFD CB for one Tx/cmd queue
439 static int iwl_tx_queue_alloc(struct iwl_priv
*priv
,
440 struct iwl_tx_queue
*txq
, u32 id
)
442 struct device
*dev
= &priv
->pci_dev
->dev
;
443 size_t tfd_sz
= priv
->hw_params
.tfd_size
* TFD_QUEUE_SIZE_MAX
;
445 /* Driver private data, only for Tx (not command) queues,
446 * not shared with device. */
447 if (id
!= priv
->cmd_queue
) {
448 txq
->txb
= kzalloc(sizeof(txq
->txb
[0]) *
449 TFD_QUEUE_SIZE_MAX
, GFP_KERNEL
);
451 IWL_ERR(priv
, "kmalloc for auxiliary BD "
452 "structures failed\n");
459 /* Circular buffer of transmit frame descriptors (TFDs),
460 * shared with device */
461 txq
->tfds
= dma_alloc_coherent(dev
, tfd_sz
, &txq
->q
.dma_addr
,
464 IWL_ERR(priv
, "pci_alloc_consistent(%zd) failed\n", tfd_sz
);
479 * iwl_tx_queue_init - Allocate and initialize one tx/cmd queue
481 int iwl_tx_queue_init(struct iwl_priv
*priv
, struct iwl_tx_queue
*txq
,
482 int slots_num
, u32 txq_id
)
486 int actual_slots
= slots_num
;
489 * Alloc buffer array for commands (Tx or other types of commands).
490 * For the command queue (#4/#9), allocate command space + one big
491 * command for scan, since scan command is very huge; the system will
492 * not have two scans at the same time, so only one is needed.
493 * For normal Tx queues (all other queues), no super-size command
496 if (txq_id
== priv
->cmd_queue
)
499 txq
->meta
= kzalloc(sizeof(struct iwl_cmd_meta
) * actual_slots
,
501 txq
->cmd
= kzalloc(sizeof(struct iwl_device_cmd
*) * actual_slots
,
504 if (!txq
->meta
|| !txq
->cmd
)
505 goto out_free_arrays
;
507 len
= sizeof(struct iwl_device_cmd
);
508 for (i
= 0; i
< actual_slots
; i
++) {
509 /* only happens for cmd queue */
511 len
= IWL_MAX_CMD_SIZE
;
513 txq
->cmd
[i
] = kmalloc(len
, GFP_KERNEL
);
518 /* Alloc driver data array and TFD circular buffer */
519 ret
= iwl_tx_queue_alloc(priv
, txq
, txq_id
);
523 txq
->need_update
= 0;
526 * For the default queues 0-3, set up the swq_id
527 * already -- all others need to get one later
528 * (if they need one at all).
531 iwl_set_swq_id(txq
, txq_id
, txq_id
);
533 /* TFD_QUEUE_SIZE_MAX must be power-of-two size, otherwise
534 * iwl_queue_inc_wrap and iwl_queue_dec_wrap are broken. */
535 BUILD_BUG_ON(TFD_QUEUE_SIZE_MAX
& (TFD_QUEUE_SIZE_MAX
- 1));
537 /* Initialize queue's high/low-water marks, and head/tail indexes */
538 ret
= iwl_queue_init(priv
, &txq
->q
, TFD_QUEUE_SIZE_MAX
, slots_num
, txq_id
);
542 /* Tell device where to find queue */
543 iwlagn_tx_queue_init(priv
, txq
);
547 for (i
= 0; i
< actual_slots
; i
++)
556 void iwl_tx_queue_reset(struct iwl_priv
*priv
, struct iwl_tx_queue
*txq
,
557 int slots_num
, u32 txq_id
)
559 int actual_slots
= slots_num
;
561 if (txq_id
== priv
->cmd_queue
)
564 memset(txq
->meta
, 0, sizeof(struct iwl_cmd_meta
) * actual_slots
);
566 txq
->need_update
= 0;
568 /* Initialize queue's high/low-water marks, and head/tail indexes */
569 iwl_queue_init(priv
, &txq
->q
, TFD_QUEUE_SIZE_MAX
, slots_num
, txq_id
);
571 /* Tell device where to find queue */
572 iwlagn_tx_queue_init(priv
, txq
);
575 /*************** HOST COMMAND QUEUE FUNCTIONS *****/
578 * iwl_enqueue_hcmd - enqueue a uCode command
579 * @priv: device private data point
580 * @cmd: a point to the ucode command structure
582 * The function returns < 0 values to indicate the operation is
583 * failed. On success, it turns the index (> 0) of command in the
586 int iwl_enqueue_hcmd(struct iwl_priv
*priv
, struct iwl_host_cmd
*cmd
)
588 struct iwl_tx_queue
*txq
= &priv
->txq
[priv
->cmd_queue
];
589 struct iwl_queue
*q
= &txq
->q
;
590 struct iwl_device_cmd
*out_cmd
;
591 struct iwl_cmd_meta
*out_meta
;
592 dma_addr_t phys_addr
;
596 bool is_ct_kill
= false;
598 fix_size
= (u16
)(cmd
->len
[0] + sizeof(out_cmd
->hdr
));
601 * If any of the command structures end up being larger than
602 * the TFD_MAX_PAYLOAD_SIZE, and it sent as a 'small' command then
603 * we will need to increase the size of the TFD entries
604 * Also, check to see if command buffer should not exceed the size
605 * of device_cmd and max_cmd_size.
607 if (WARN_ON((fix_size
> TFD_MAX_PAYLOAD_SIZE
) &&
608 !(cmd
->flags
& CMD_SIZE_HUGE
)))
611 if (WARN_ON(fix_size
> IWL_MAX_CMD_SIZE
))
614 if (iwl_is_rfkill(priv
) || iwl_is_ctkill(priv
)) {
615 IWL_WARN(priv
, "Not sending command - %s KILL\n",
616 iwl_is_rfkill(priv
) ? "RF" : "CT");
621 * As we only have a single huge buffer, check that the command
622 * is synchronous (otherwise buffers could end up being reused).
625 if (WARN_ON((cmd
->flags
& CMD_ASYNC
) && (cmd
->flags
& CMD_SIZE_HUGE
)))
628 spin_lock_irqsave(&priv
->hcmd_lock
, flags
);
630 if (iwl_queue_space(q
) < ((cmd
->flags
& CMD_ASYNC
) ? 2 : 1)) {
631 spin_unlock_irqrestore(&priv
->hcmd_lock
, flags
);
633 IWL_ERR(priv
, "No space in command queue\n");
634 is_ct_kill
= iwl_check_for_ct_kill(priv
);
636 IWL_ERR(priv
, "Restarting adapter due to queue full\n");
637 iwlagn_fw_error(priv
, false);
642 idx
= get_cmd_index(q
, q
->write_ptr
, cmd
->flags
& CMD_SIZE_HUGE
);
643 out_cmd
= txq
->cmd
[idx
];
644 out_meta
= &txq
->meta
[idx
];
646 if (WARN_ON(out_meta
->flags
& CMD_MAPPED
)) {
647 spin_unlock_irqrestore(&priv
->hcmd_lock
, flags
);
651 memset(out_meta
, 0, sizeof(*out_meta
)); /* re-initialize to NULL */
652 if (cmd
->flags
& CMD_WANT_SKB
)
653 out_meta
->source
= cmd
;
654 if (cmd
->flags
& CMD_ASYNC
)
655 out_meta
->callback
= cmd
->callback
;
657 out_cmd
->hdr
.cmd
= cmd
->id
;
658 memcpy(&out_cmd
->cmd
.payload
, cmd
->data
[0], cmd
->len
[0]);
660 /* At this point, the out_cmd now has all of the incoming cmd
663 out_cmd
->hdr
.flags
= 0;
664 out_cmd
->hdr
.sequence
= cpu_to_le16(QUEUE_TO_SEQ(priv
->cmd_queue
) |
665 INDEX_TO_SEQ(q
->write_ptr
));
666 if (cmd
->flags
& CMD_SIZE_HUGE
)
667 out_cmd
->hdr
.sequence
|= SEQ_HUGE_FRAME
;
669 #ifdef CONFIG_IWLWIFI_DEBUG
670 switch (out_cmd
->hdr
.cmd
) {
671 case REPLY_TX_LINK_QUALITY_CMD
:
672 case SENSITIVITY_CMD
:
673 IWL_DEBUG_HC_DUMP(priv
, "Sending command %s (#%x), seq: 0x%04X, "
674 "%d bytes at %d[%d]:%d\n",
675 get_cmd_string(out_cmd
->hdr
.cmd
),
677 le16_to_cpu(out_cmd
->hdr
.sequence
), fix_size
,
678 q
->write_ptr
, idx
, priv
->cmd_queue
);
681 IWL_DEBUG_HC(priv
, "Sending command %s (#%x), seq: 0x%04X, "
682 "%d bytes at %d[%d]:%d\n",
683 get_cmd_string(out_cmd
->hdr
.cmd
),
685 le16_to_cpu(out_cmd
->hdr
.sequence
), fix_size
,
686 q
->write_ptr
, idx
, priv
->cmd_queue
);
689 phys_addr
= pci_map_single(priv
->pci_dev
, &out_cmd
->hdr
,
690 fix_size
, PCI_DMA_BIDIRECTIONAL
);
691 if (unlikely(pci_dma_mapping_error(priv
->pci_dev
, phys_addr
))) {
696 dma_unmap_addr_set(out_meta
, mapping
, phys_addr
);
697 dma_unmap_len_set(out_meta
, len
, fix_size
);
699 out_meta
->flags
= cmd
->flags
| CMD_MAPPED
;
701 txq
->need_update
= 1;
703 trace_iwlwifi_dev_hcmd(priv
, &out_cmd
->hdr
, fix_size
, cmd
->flags
);
705 iwlagn_txq_attach_buf_to_tfd(priv
, txq
, phys_addr
, fix_size
, 1);
707 /* Increment and update queue's write index */
708 q
->write_ptr
= iwl_queue_inc_wrap(q
->write_ptr
, q
->n_bd
);
709 iwl_txq_update_write_ptr(priv
, txq
);
712 spin_unlock_irqrestore(&priv
->hcmd_lock
, flags
);
717 * iwl_hcmd_queue_reclaim - Reclaim TX command queue entries already Tx'd
719 * When FW advances 'R' index, all entries between old and new 'R' index
720 * need to be reclaimed. As result, some free space forms. If there is
721 * enough free space (> low mark), wake the stack that feeds us.
723 static void iwl_hcmd_queue_reclaim(struct iwl_priv
*priv
, int txq_id
,
724 int idx
, int cmd_idx
)
726 struct iwl_tx_queue
*txq
= &priv
->txq
[txq_id
];
727 struct iwl_queue
*q
= &txq
->q
;
730 if ((idx
>= q
->n_bd
) || (iwl_queue_used(q
, idx
) == 0)) {
731 IWL_ERR(priv
, "Read index for DMA queue txq id (%d), index %d, "
732 "is out of range [0-%d] %d %d.\n", txq_id
,
733 idx
, q
->n_bd
, q
->write_ptr
, q
->read_ptr
);
737 for (idx
= iwl_queue_inc_wrap(idx
, q
->n_bd
); q
->read_ptr
!= idx
;
738 q
->read_ptr
= iwl_queue_inc_wrap(q
->read_ptr
, q
->n_bd
)) {
741 IWL_ERR(priv
, "HCMD skipped: index (%d) %d %d\n", idx
,
742 q
->write_ptr
, q
->read_ptr
);
743 iwlagn_fw_error(priv
, false);
750 * iwl_tx_cmd_complete - Pull unused buffers off the queue and reclaim them
751 * @rxb: Rx buffer to reclaim
753 * If an Rx buffer has an async callback associated with it the callback
754 * will be executed. The attached skb (if present) will only be freed
755 * if the callback returns 1
757 void iwl_tx_cmd_complete(struct iwl_priv
*priv
, struct iwl_rx_mem_buffer
*rxb
)
759 struct iwl_rx_packet
*pkt
= rxb_addr(rxb
);
760 u16 sequence
= le16_to_cpu(pkt
->hdr
.sequence
);
761 int txq_id
= SEQ_TO_QUEUE(sequence
);
762 int index
= SEQ_TO_INDEX(sequence
);
764 bool huge
= !!(pkt
->hdr
.sequence
& SEQ_HUGE_FRAME
);
765 struct iwl_device_cmd
*cmd
;
766 struct iwl_cmd_meta
*meta
;
767 struct iwl_tx_queue
*txq
= &priv
->txq
[priv
->cmd_queue
];
770 /* If a Tx command is being handled and it isn't in the actual
771 * command queue then there a command routing bug has been introduced
772 * in the queue management code. */
773 if (WARN(txq_id
!= priv
->cmd_queue
,
774 "wrong command queue %d (should be %d), sequence 0x%X readp=%d writep=%d\n",
775 txq_id
, priv
->cmd_queue
, sequence
,
776 priv
->txq
[priv
->cmd_queue
].q
.read_ptr
,
777 priv
->txq
[priv
->cmd_queue
].q
.write_ptr
)) {
778 iwl_print_hex_error(priv
, pkt
, 32);
782 cmd_index
= get_cmd_index(&txq
->q
, index
, huge
);
783 cmd
= txq
->cmd
[cmd_index
];
784 meta
= &txq
->meta
[cmd_index
];
786 pci_unmap_single(priv
->pci_dev
,
787 dma_unmap_addr(meta
, mapping
),
788 dma_unmap_len(meta
, len
),
789 PCI_DMA_BIDIRECTIONAL
);
791 /* Input error checking is done when commands are added to queue. */
792 if (meta
->flags
& CMD_WANT_SKB
) {
793 meta
->source
->reply_page
= (unsigned long)rxb_addr(rxb
);
795 } else if (meta
->callback
)
796 meta
->callback(priv
, cmd
, pkt
);
798 spin_lock_irqsave(&priv
->hcmd_lock
, flags
);
800 iwl_hcmd_queue_reclaim(priv
, txq_id
, index
, cmd_index
);
802 if (!(meta
->flags
& CMD_ASYNC
)) {
803 clear_bit(STATUS_HCMD_ACTIVE
, &priv
->status
);
804 IWL_DEBUG_INFO(priv
, "Clearing HCMD_ACTIVE for command %s\n",
805 get_cmd_string(cmd
->hdr
.cmd
));
806 wake_up_interruptible(&priv
->wait_command_queue
);
809 /* Mark as unmapped */
812 spin_unlock_irqrestore(&priv
->hcmd_lock
, flags
);