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iwlagn: remove unused pad argument
[linux-2.6.git] / drivers / net / wireless / iwlwifi / iwl-agn-tx.c
blob9acf0e9d7bda045aaade7bc7dcb7f2a8555daa11
1 /******************************************************************************
2 *
3 * GPL LICENSE SUMMARY
4 *
5 * Copyright(c) 2008 - 2011 Intel Corporation. All rights reserved.
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of version 2 of the GNU General Public License as
9 * published by the Free Software Foundation.
10 *
11 * This program is distributed in the hope that it will be useful, but
12 * WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110,
19 * USA
20 *
21 * The full GNU General Public License is included in this distribution
22 * in the file called LICENSE.GPL.
23 *
24 * Contact Information:
25 * Intel Linux Wireless <ilw@linux.intel.com>
26 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
27 *
28 *****************************************************************************/
29
30 #include <linux/kernel.h>
31 #include <linux/module.h>
32 #include <linux/init.h>
33 #include <linux/sched.h>
34
35 #include "iwl-dev.h"
36 #include "iwl-core.h"
37 #include "iwl-sta.h"
38 #include "iwl-io.h"
39 #include "iwl-helpers.h"
40 #include "iwl-agn-hw.h"
41 #include "iwl-agn.h"
42
43 /*
44 * mac80211 queues, ACs, hardware queues, FIFOs.
45 *
46 * Cf. http://wireless.kernel.org/en/developers/Documentation/mac80211/queues
47 *
48 * Mac80211 uses the following numbers, which we get as from it
49 * by way of skb_get_queue_mapping(skb):
50 *
51 * VO 0
52 * VI 1
53 * BE 2
54 * BK 3
55 *
56 *
57 * Regular (not A-MPDU) frames are put into hardware queues corresponding
58 * to the FIFOs, see comments in iwl-prph.h. Aggregated frames get their
59 * own queue per aggregation session (RA/TID combination), such queues are
60 * set up to map into FIFOs too, for which we need an AC->FIFO mapping. In
61 * order to map frames to the right queue, we also need an AC->hw queue
62 * mapping. This is implemented here.
63 *
64 * Due to the way hw queues are set up (by the hw specific modules like
65 * iwl-4965.c, iwl-5000.c etc.), the AC->hw queue mapping is the identity
66 * mapping.
67 */
68
69 static const u8 tid_to_ac[] = {
70 IEEE80211_AC_BE,
71 IEEE80211_AC_BK,
72 IEEE80211_AC_BK,
73 IEEE80211_AC_BE,
74 IEEE80211_AC_VI,
75 IEEE80211_AC_VI,
76 IEEE80211_AC_VO,
77 IEEE80211_AC_VO
78 };
79
80 static inline int get_ac_from_tid(u16 tid)
81 {
82 if (likely(tid < ARRAY_SIZE(tid_to_ac)))
83 return tid_to_ac[tid];
84
85 /* no support for TIDs 8-15 yet */
86 return -EINVAL;
87 }
88
89 static inline int get_fifo_from_tid(struct iwl_rxon_context *ctx, u16 tid)
90 {
91 if (likely(tid < ARRAY_SIZE(tid_to_ac)))
92 return ctx->ac_to_fifo[tid_to_ac[tid]];
93
94 /* no support for TIDs 8-15 yet */
95 return -EINVAL;
96 }
97
98 /**
99 * iwlagn_txq_update_byte_cnt_tbl - Set up entry in Tx byte-count array
100 */
101 static void iwlagn_txq_update_byte_cnt_tbl(struct iwl_priv *priv,
102 struct iwl_tx_queue *txq,
103 u16 byte_cnt)
104 {
105 struct iwlagn_scd_bc_tbl *scd_bc_tbl = priv->scd_bc_tbls.addr;
106 int write_ptr = txq->q.write_ptr;
107 int txq_id = txq->q.id;
108 u8 sec_ctl = 0;
109 u8 sta_id = 0;
110 u16 len = byte_cnt + IWL_TX_CRC_SIZE + IWL_TX_DELIMITER_SIZE;
111 __le16 bc_ent;
112
113 WARN_ON(len > 0xFFF || write_ptr >= TFD_QUEUE_SIZE_MAX);
114
115 sta_id = txq->cmd[txq->q.write_ptr]->cmd.tx.sta_id;
116 sec_ctl = txq->cmd[txq->q.write_ptr]->cmd.tx.sec_ctl;
117
118 switch (sec_ctl & TX_CMD_SEC_MSK) {
119 case TX_CMD_SEC_CCM:
120 len += CCMP_MIC_LEN;
121 break;
122 case TX_CMD_SEC_TKIP:
123 len += TKIP_ICV_LEN;
124 break;
125 case TX_CMD_SEC_WEP:
126 len += WEP_IV_LEN + WEP_ICV_LEN;
127 break;
128 }
129
130 bc_ent = cpu_to_le16((len & 0xFFF) | (sta_id << 12));
131
132 scd_bc_tbl[txq_id].tfd_offset[write_ptr] = bc_ent;
133
134 if (write_ptr < TFD_QUEUE_SIZE_BC_DUP)
135 scd_bc_tbl[txq_id].
136 tfd_offset[TFD_QUEUE_SIZE_MAX + write_ptr] = bc_ent;
137 }
138
139 static void iwlagn_txq_inval_byte_cnt_tbl(struct iwl_priv *priv,
140 struct iwl_tx_queue *txq)
141 {
142 struct iwlagn_scd_bc_tbl *scd_bc_tbl = priv->scd_bc_tbls.addr;
143 int txq_id = txq->q.id;
144 int read_ptr = txq->q.read_ptr;
145 u8 sta_id = 0;
146 __le16 bc_ent;
147
148 WARN_ON(read_ptr >= TFD_QUEUE_SIZE_MAX);
149
150 if (txq_id != priv->cmd_queue)
151 sta_id = txq->cmd[read_ptr]->cmd.tx.sta_id;
152
153 bc_ent = cpu_to_le16(1 | (sta_id << 12));
154 scd_bc_tbl[txq_id].tfd_offset[read_ptr] = bc_ent;
155
156 if (read_ptr < TFD_QUEUE_SIZE_BC_DUP)
157 scd_bc_tbl[txq_id].
158 tfd_offset[TFD_QUEUE_SIZE_MAX + read_ptr] = bc_ent;
159 }
160
161 static int iwlagn_tx_queue_set_q2ratid(struct iwl_priv *priv, u16 ra_tid,
162 u16 txq_id)
163 {
164 u32 tbl_dw_addr;
165 u32 tbl_dw;
166 u16 scd_q2ratid;
167
168 scd_q2ratid = ra_tid & IWL_SCD_QUEUE_RA_TID_MAP_RATID_MSK;
169
170 tbl_dw_addr = priv->scd_base_addr +
171 IWLAGN_SCD_TRANSLATE_TBL_OFFSET_QUEUE(txq_id);
172
173 tbl_dw = iwl_read_targ_mem(priv, tbl_dw_addr);
174
175 if (txq_id & 0x1)
176 tbl_dw = (scd_q2ratid << 16) | (tbl_dw & 0x0000FFFF);
177 else
178 tbl_dw = scd_q2ratid | (tbl_dw & 0xFFFF0000);
179
180 iwl_write_targ_mem(priv, tbl_dw_addr, tbl_dw);
181
182 return 0;
183 }
184
185 static void iwlagn_tx_queue_stop_scheduler(struct iwl_priv *priv, u16 txq_id)
186 {
187 /* Simply stop the queue, but don't change any configuration;
188 * the SCD_ACT_EN bit is the write-enable mask for the ACTIVE bit. */
189 iwl_write_prph(priv,
190 IWLAGN_SCD_QUEUE_STATUS_BITS(txq_id),
191 (0 << IWLAGN_SCD_QUEUE_STTS_REG_POS_ACTIVE)|
192 (1 << IWLAGN_SCD_QUEUE_STTS_REG_POS_SCD_ACT_EN));
193 }
194
195 void iwlagn_set_wr_ptrs(struct iwl_priv *priv,
196 int txq_id, u32 index)
197 {
198 iwl_write_direct32(priv, HBUS_TARG_WRPTR,
199 (index & 0xff) | (txq_id << 8));
200 iwl_write_prph(priv, IWLAGN_SCD_QUEUE_RDPTR(txq_id), index);
201 }
202
203 void iwlagn_tx_queue_set_status(struct iwl_priv *priv,
204 struct iwl_tx_queue *txq,
205 int tx_fifo_id, int scd_retry)
206 {
207 int txq_id = txq->q.id;
208 int active = test_bit(txq_id, &priv->txq_ctx_active_msk) ? 1 : 0;
209
210 iwl_write_prph(priv, IWLAGN_SCD_QUEUE_STATUS_BITS(txq_id),
211 (active << IWLAGN_SCD_QUEUE_STTS_REG_POS_ACTIVE) |
212 (tx_fifo_id << IWLAGN_SCD_QUEUE_STTS_REG_POS_TXF) |
213 (1 << IWLAGN_SCD_QUEUE_STTS_REG_POS_WSL) |
214 IWLAGN_SCD_QUEUE_STTS_REG_MSK);
215
216 txq->sched_retry = scd_retry;
217
218 IWL_DEBUG_INFO(priv, "%s %s Queue %d on FIFO %d\n",
219 active ? "Activate" : "Deactivate",
220 scd_retry ? "BA" : "AC/CMD", txq_id, tx_fifo_id);
221 }
222
223 static int iwlagn_txq_agg_enable(struct iwl_priv *priv, int txq_id, int sta_id, int tid)
224 {
225 if ((IWLAGN_FIRST_AMPDU_QUEUE > txq_id) ||
226 (IWLAGN_FIRST_AMPDU_QUEUE +
227 priv->cfg->base_params->num_of_ampdu_queues <= txq_id)) {
228 IWL_WARN(priv,
229 "queue number out of range: %d, must be %d to %d\n",
230 txq_id, IWLAGN_FIRST_AMPDU_QUEUE,
231 IWLAGN_FIRST_AMPDU_QUEUE +
232 priv->cfg->base_params->num_of_ampdu_queues - 1);
233 return -EINVAL;
234 }
235
236 /* Modify device's station table to Tx this TID */
237 return iwl_sta_tx_modify_enable_tid(priv, sta_id, tid);
238 }
239
240 void iwlagn_txq_agg_queue_setup(struct iwl_priv *priv,
241 struct ieee80211_sta *sta,
242 int tid, int frame_limit)
243 {
244 int sta_id, tx_fifo, txq_id, ssn_idx;
245 u16 ra_tid;
246 unsigned long flags;
247 struct iwl_tid_data *tid_data;
248
249 sta_id = iwl_sta_id(sta);
250 if (WARN_ON(sta_id == IWL_INVALID_STATION))
251 return;
252 if (WARN_ON(tid >= MAX_TID_COUNT))
253 return;
254
255 spin_lock_irqsave(&priv->sta_lock, flags);
256 tid_data = &priv->stations[sta_id].tid[tid];
257 ssn_idx = SEQ_TO_SN(tid_data->seq_number);
258 txq_id = tid_data->agg.txq_id;
259 tx_fifo = tid_data->agg.tx_fifo;
260 spin_unlock_irqrestore(&priv->sta_lock, flags);
261
262 ra_tid = BUILD_RAxTID(sta_id, tid);
263
264 spin_lock_irqsave(&priv->lock, flags);
265
266 /* Stop this Tx queue before configuring it */
267 iwlagn_tx_queue_stop_scheduler(priv, txq_id);
268
269 /* Map receiver-address / traffic-ID to this queue */
270 iwlagn_tx_queue_set_q2ratid(priv, ra_tid, txq_id);
271
272 /* Set this queue as a chain-building queue */
273 iwl_set_bits_prph(priv, IWLAGN_SCD_QUEUECHAIN_SEL, (1<<txq_id));
274
275 /* enable aggregations for the queue */
276 iwl_set_bits_prph(priv, IWLAGN_SCD_AGGR_SEL, (1<<txq_id));
277
278 /* Place first TFD at index corresponding to start sequence number.
279 * Assumes that ssn_idx is valid (!= 0xFFF) */
280 priv->txq[txq_id].q.read_ptr = (ssn_idx & 0xff);
281 priv->txq[txq_id].q.write_ptr = (ssn_idx & 0xff);
282 iwlagn_set_wr_ptrs(priv, txq_id, ssn_idx);
283
284 /* Set up Tx window size and frame limit for this queue */
285 iwl_write_targ_mem(priv, priv->scd_base_addr +
286 IWLAGN_SCD_CONTEXT_QUEUE_OFFSET(txq_id) +
287 sizeof(u32),
288 ((frame_limit <<
289 IWLAGN_SCD_QUEUE_CTX_REG2_WIN_SIZE_POS) &
290 IWLAGN_SCD_QUEUE_CTX_REG2_WIN_SIZE_MSK) |
291 ((frame_limit <<
292 IWLAGN_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_POS) &
293 IWLAGN_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_MSK));
294
295 iwl_set_bits_prph(priv, IWLAGN_SCD_INTERRUPT_MASK, (1 << txq_id));
296
297 /* Set up Status area in SRAM, map to Tx DMA/FIFO, activate the queue */
298 iwlagn_tx_queue_set_status(priv, &priv->txq[txq_id], tx_fifo, 1);
299
300 spin_unlock_irqrestore(&priv->lock, flags);
301 }
302
303 static int iwlagn_txq_agg_disable(struct iwl_priv *priv, u16 txq_id,
304 u16 ssn_idx, u8 tx_fifo)
305 {
306 if ((IWLAGN_FIRST_AMPDU_QUEUE > txq_id) ||
307 (IWLAGN_FIRST_AMPDU_QUEUE +
308 priv->cfg->base_params->num_of_ampdu_queues <= txq_id)) {
309 IWL_ERR(priv,
310 "queue number out of range: %d, must be %d to %d\n",
311 txq_id, IWLAGN_FIRST_AMPDU_QUEUE,
312 IWLAGN_FIRST_AMPDU_QUEUE +
313 priv->cfg->base_params->num_of_ampdu_queues - 1);
314 return -EINVAL;
315 }
316
317 iwlagn_tx_queue_stop_scheduler(priv, txq_id);
318
319 iwl_clear_bits_prph(priv, IWLAGN_SCD_AGGR_SEL, (1 << txq_id));
320
321 priv->txq[txq_id].q.read_ptr = (ssn_idx & 0xff);
322 priv->txq[txq_id].q.write_ptr = (ssn_idx & 0xff);
323 /* supposes that ssn_idx is valid (!= 0xFFF) */
324 iwlagn_set_wr_ptrs(priv, txq_id, ssn_idx);
325
326 iwl_clear_bits_prph(priv, IWLAGN_SCD_INTERRUPT_MASK, (1 << txq_id));
327 iwl_txq_ctx_deactivate(priv, txq_id);
328 iwlagn_tx_queue_set_status(priv, &priv->txq[txq_id], tx_fifo, 0);
329
330 return 0;
331 }
332
333 /*
334 * Activate/Deactivate Tx DMA/FIFO channels according tx fifos mask
335 * must be called under priv->lock and mac access
336 */
337 void iwlagn_txq_set_sched(struct iwl_priv *priv, u32 mask)
338 {
339 iwl_write_prph(priv, IWLAGN_SCD_TXFACT, mask);
340 }
341
342 /*
343 * handle build REPLY_TX command notification.
344 */
345 static void iwlagn_tx_cmd_build_basic(struct iwl_priv *priv,
346 struct sk_buff *skb,
347 struct iwl_tx_cmd *tx_cmd,
348 struct ieee80211_tx_info *info,
349 struct ieee80211_hdr *hdr,
350 u8 std_id)
351 {
352 __le16 fc = hdr->frame_control;
353 __le32 tx_flags = tx_cmd->tx_flags;
354
355 tx_cmd->stop_time.life_time = TX_CMD_LIFE_TIME_INFINITE;
356 if (!(info->flags & IEEE80211_TX_CTL_NO_ACK)) {
357 tx_flags |= TX_CMD_FLG_ACK_MSK;
358 if (ieee80211_is_mgmt(fc))
359 tx_flags |= TX_CMD_FLG_SEQ_CTL_MSK;
360 if (ieee80211_is_probe_resp(fc) &&
361 !(le16_to_cpu(hdr->seq_ctrl) & 0xf))
362 tx_flags |= TX_CMD_FLG_TSF_MSK;
363 } else {
364 tx_flags &= (~TX_CMD_FLG_ACK_MSK);
365 tx_flags |= TX_CMD_FLG_SEQ_CTL_MSK;
366 }
367
368 if (ieee80211_is_back_req(fc))
369 tx_flags |= TX_CMD_FLG_ACK_MSK | TX_CMD_FLG_IMM_BA_RSP_MASK;
370 else if (info->band == IEEE80211_BAND_2GHZ &&
371 priv->cfg->bt_params &&
372 priv->cfg->bt_params->advanced_bt_coexist &&
373 (ieee80211_is_auth(fc) || ieee80211_is_assoc_req(fc) ||
374 ieee80211_is_reassoc_req(fc) ||
375 skb->protocol == cpu_to_be16(ETH_P_PAE)))
376 tx_flags |= TX_CMD_FLG_IGNORE_BT;
377
378
379 tx_cmd->sta_id = std_id;
380 if (ieee80211_has_morefrags(fc))
381 tx_flags |= TX_CMD_FLG_MORE_FRAG_MSK;
382
383 if (ieee80211_is_data_qos(fc)) {
384 u8 *qc = ieee80211_get_qos_ctl(hdr);
385 tx_cmd->tid_tspec = qc[0] & 0xf;
386 tx_flags &= ~TX_CMD_FLG_SEQ_CTL_MSK;
387 } else {
388 tx_flags |= TX_CMD_FLG_SEQ_CTL_MSK;
389 }
390
391 priv->cfg->ops->utils->tx_cmd_protection(priv, info, fc, &tx_flags);
392
393 tx_flags &= ~(TX_CMD_FLG_ANT_SEL_MSK);
394 if (ieee80211_is_mgmt(fc)) {
395 if (ieee80211_is_assoc_req(fc) || ieee80211_is_reassoc_req(fc))
396 tx_cmd->timeout.pm_frame_timeout = cpu_to_le16(3);
397 else
398 tx_cmd->timeout.pm_frame_timeout = cpu_to_le16(2);
399 } else {
400 tx_cmd->timeout.pm_frame_timeout = 0;
401 }
402
403 tx_cmd->driver_txop = 0;
404 tx_cmd->tx_flags = tx_flags;
405 tx_cmd->next_frame_len = 0;
406 }
407
408 #define RTS_DFAULT_RETRY_LIMIT 60
409
410 static void iwlagn_tx_cmd_build_rate(struct iwl_priv *priv,
411 struct iwl_tx_cmd *tx_cmd,
412 struct ieee80211_tx_info *info,
413 __le16 fc)
414 {
415 u32 rate_flags;
416 int rate_idx;
417 u8 rts_retry_limit;
418 u8 data_retry_limit;
419 u8 rate_plcp;
420
421 /* Set retry limit on DATA packets and Probe Responses*/
422 if (ieee80211_is_probe_resp(fc))
423 data_retry_limit = 3;
424 else
425 data_retry_limit = IWLAGN_DEFAULT_TX_RETRY;
426 tx_cmd->data_retry_limit = data_retry_limit;
427
428 /* Set retry limit on RTS packets */
429 rts_retry_limit = RTS_DFAULT_RETRY_LIMIT;
430 if (data_retry_limit < rts_retry_limit)
431 rts_retry_limit = data_retry_limit;
432 tx_cmd->rts_retry_limit = rts_retry_limit;
433
434 /* DATA packets will use the uCode station table for rate/antenna
435 * selection */
436 if (ieee80211_is_data(fc)) {
437 tx_cmd->initial_rate_index = 0;
438 tx_cmd->tx_flags |= TX_CMD_FLG_STA_RATE_MSK;
439 return;
440 }
441
442 /**
443 * If the current TX rate stored in mac80211 has the MCS bit set, it's
444 * not really a TX rate. Thus, we use the lowest supported rate for
445 * this band. Also use the lowest supported rate if the stored rate
446 * index is invalid.
447 */
448 rate_idx = info->control.rates[0].idx;
449 if (info->control.rates[0].flags & IEEE80211_TX_RC_MCS ||
450 (rate_idx < 0) || (rate_idx > IWL_RATE_COUNT_LEGACY))
451 rate_idx = rate_lowest_index(&priv->bands[info->band],
452 info->control.sta);
453 /* For 5 GHZ band, remap mac80211 rate indices into driver indices */
454 if (info->band == IEEE80211_BAND_5GHZ)
455 rate_idx += IWL_FIRST_OFDM_RATE;
456 /* Get PLCP rate for tx_cmd->rate_n_flags */
457 rate_plcp = iwl_rates[rate_idx].plcp;
458 /* Zero out flags for this packet */
459 rate_flags = 0;
460
461 /* Set CCK flag as needed */
462 if ((rate_idx >= IWL_FIRST_CCK_RATE) && (rate_idx <= IWL_LAST_CCK_RATE))
463 rate_flags |= RATE_MCS_CCK_MSK;
464
465 /* Set up antennas */
466 if (priv->cfg->bt_params &&
467 priv->cfg->bt_params->advanced_bt_coexist &&
468 priv->bt_full_concurrent) {
469 /* operated as 1x1 in full concurrency mode */
470 priv->mgmt_tx_ant = iwl_toggle_tx_ant(priv, priv->mgmt_tx_ant,
471 first_antenna(priv->hw_params.valid_tx_ant));
472 } else
473 priv->mgmt_tx_ant = iwl_toggle_tx_ant(priv, priv->mgmt_tx_ant,
474 priv->hw_params.valid_tx_ant);
475 rate_flags |= iwl_ant_idx_to_flags(priv->mgmt_tx_ant);
476
477 /* Set the rate in the TX cmd */
478 tx_cmd->rate_n_flags = iwl_hw_set_rate_n_flags(rate_plcp, rate_flags);
479 }
480
481 static void iwlagn_tx_cmd_build_hwcrypto(struct iwl_priv *priv,
482 struct ieee80211_tx_info *info,
483 struct iwl_tx_cmd *tx_cmd,
484 struct sk_buff *skb_frag,
485 int sta_id)
486 {
487 struct ieee80211_key_conf *keyconf = info->control.hw_key;
488
489 switch (keyconf->cipher) {
490 case WLAN_CIPHER_SUITE_CCMP:
491 tx_cmd->sec_ctl = TX_CMD_SEC_CCM;
492 memcpy(tx_cmd->key, keyconf->key, keyconf->keylen);
493 if (info->flags & IEEE80211_TX_CTL_AMPDU)
494 tx_cmd->tx_flags |= TX_CMD_FLG_AGG_CCMP_MSK;
495 IWL_DEBUG_TX(priv, "tx_cmd with AES hwcrypto\n");
496 break;
497
498 case WLAN_CIPHER_SUITE_TKIP:
499 tx_cmd->sec_ctl = TX_CMD_SEC_TKIP;
500 ieee80211_get_tkip_key(keyconf, skb_frag,
501 IEEE80211_TKIP_P2_KEY, tx_cmd->key);
502 IWL_DEBUG_TX(priv, "tx_cmd with tkip hwcrypto\n");
503 break;
504
505 case WLAN_CIPHER_SUITE_WEP104:
506 tx_cmd->sec_ctl |= TX_CMD_SEC_KEY128;
507 /* fall through */
508 case WLAN_CIPHER_SUITE_WEP40:
509 tx_cmd->sec_ctl |= (TX_CMD_SEC_WEP |
510 (keyconf->keyidx & TX_CMD_SEC_MSK) << TX_CMD_SEC_SHIFT);
511
512 memcpy(&tx_cmd->key[3], keyconf->key, keyconf->keylen);
513
514 IWL_DEBUG_TX(priv, "Configuring packet for WEP encryption "
515 "with key %d\n", keyconf->keyidx);
516 break;
517
518 default:
519 IWL_ERR(priv, "Unknown encode cipher %x\n", keyconf->cipher);
520 break;
521 }
522 }
523
524 /*
525 * start REPLY_TX command process
526 */
527 int iwlagn_tx_skb(struct iwl_priv *priv, struct sk_buff *skb)
528 {
529 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
530 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
531 struct ieee80211_sta *sta = info->control.sta;
532 struct iwl_station_priv *sta_priv = NULL;
533 struct iwl_tx_queue *txq;
534 struct iwl_queue *q;
535 struct iwl_device_cmd *out_cmd;
536 struct iwl_cmd_meta *out_meta;
537 struct iwl_tx_cmd *tx_cmd;
538 struct iwl_rxon_context *ctx = &priv->contexts[IWL_RXON_CTX_BSS];
539 int txq_id;
540 dma_addr_t phys_addr = 0;
541 dma_addr_t txcmd_phys;
542 dma_addr_t scratch_phys;
543 u16 len, firstlen, secondlen;
544 u16 seq_number = 0;
545 __le16 fc;
546 u8 hdr_len;
547 u8 sta_id;
548 u8 wait_write_ptr = 0;
549 u8 tid = 0;
550 u8 *qc = NULL;
551 unsigned long flags;
552 bool is_agg = false;
553
554 /*
555 * If the frame needs to go out off-channel, then
556 * we'll have put the PAN context to that channel,
557 * so make the frame go out there.
558 */
559 if (info->flags & IEEE80211_TX_CTL_TX_OFFCHAN)
560 ctx = &priv->contexts[IWL_RXON_CTX_PAN];
561 else if (info->control.vif)
562 ctx = iwl_rxon_ctx_from_vif(info->control.vif);
563
564 spin_lock_irqsave(&priv->lock, flags);
565 if (iwl_is_rfkill(priv)) {
566 IWL_DEBUG_DROP(priv, "Dropping - RF KILL\n");
567 goto drop_unlock_priv;
568 }
569
570 fc = hdr->frame_control;
571
572 #ifdef CONFIG_IWLWIFI_DEBUG
573 if (ieee80211_is_auth(fc))
574 IWL_DEBUG_TX(priv, "Sending AUTH frame\n");
575 else if (ieee80211_is_assoc_req(fc))
576 IWL_DEBUG_TX(priv, "Sending ASSOC frame\n");
577 else if (ieee80211_is_reassoc_req(fc))
578 IWL_DEBUG_TX(priv, "Sending REASSOC frame\n");
579 #endif
580
581 hdr_len = ieee80211_hdrlen(fc);
582
583 /* Find index into station table for destination station */
584 sta_id = iwl_sta_id_or_broadcast(priv, ctx, info->control.sta);
585 if (sta_id == IWL_INVALID_STATION) {
586 IWL_DEBUG_DROP(priv, "Dropping - INVALID STATION: %pM\n",
587 hdr->addr1);
588 goto drop_unlock_priv;
589 }
590
591 IWL_DEBUG_TX(priv, "station Id %d\n", sta_id);
592
593 if (sta)
594 sta_priv = (void *)sta->drv_priv;
595
596 if (sta_priv && sta_priv->asleep &&
597 (info->flags & IEEE80211_TX_CTL_PSPOLL_RESPONSE)) {
598 /*
599 * This sends an asynchronous command to the device,
600 * but we can rely on it being processed before the
601 * next frame is processed -- and the next frame to
602 * this station is the one that will consume this
603 * counter.
604 * For now set the counter to just 1 since we do not
605 * support uAPSD yet.
606 */
607 iwl_sta_modify_sleep_tx_count(priv, sta_id, 1);
608 }
609
610 /*
611 * Send this frame after DTIM -- there's a special queue
612 * reserved for this for contexts that support AP mode.
613 */
614 if (info->flags & IEEE80211_TX_CTL_SEND_AFTER_DTIM) {
615 txq_id = ctx->mcast_queue;
616 /*
617 * The microcode will clear the more data
618 * bit in the last frame it transmits.
619 */
620 hdr->frame_control |=
621 cpu_to_le16(IEEE80211_FCTL_MOREDATA);
622 } else
623 txq_id = ctx->ac_to_queue[skb_get_queue_mapping(skb)];
624
625 /* irqs already disabled/saved above when locking priv->lock */
626 spin_lock(&priv->sta_lock);
627
628 if (ieee80211_is_data_qos(fc)) {
629 qc = ieee80211_get_qos_ctl(hdr);
630 tid = qc[0] & IEEE80211_QOS_CTL_TID_MASK;
631
632 if (WARN_ON_ONCE(tid >= MAX_TID_COUNT))
633 goto drop_unlock_sta;
634
635 seq_number = priv->stations[sta_id].tid[tid].seq_number;
636 seq_number &= IEEE80211_SCTL_SEQ;
637 hdr->seq_ctrl = hdr->seq_ctrl &
638 cpu_to_le16(IEEE80211_SCTL_FRAG);
639 hdr->seq_ctrl |= cpu_to_le16(seq_number);
640 seq_number += 0x10;
641 /* aggregation is on for this <sta,tid> */
642 if (info->flags & IEEE80211_TX_CTL_AMPDU &&
643 priv->stations[sta_id].tid[tid].agg.state == IWL_AGG_ON) {
644 txq_id = priv->stations[sta_id].tid[tid].agg.txq_id;
645 is_agg = true;
646 }
647 }
648
649 txq = &priv->txq[txq_id];
650 q = &txq->q;
651
652 if (unlikely(iwl_queue_space(q) < q->high_mark))
653 goto drop_unlock_sta;
654
655 /* Set up driver data for this TFD */
656 memset(&(txq->txb[q->write_ptr]), 0, sizeof(struct iwl_tx_info));
657 txq->txb[q->write_ptr].skb = skb;
658 txq->txb[q->write_ptr].ctx = ctx;
659
660 /* Set up first empty entry in queue's array of Tx/cmd buffers */
661 out_cmd = txq->cmd[q->write_ptr];
662 out_meta = &txq->meta[q->write_ptr];
663 tx_cmd = &out_cmd->cmd.tx;
664 memset(&out_cmd->hdr, 0, sizeof(out_cmd->hdr));
665 memset(tx_cmd, 0, sizeof(struct iwl_tx_cmd));
666
667 /*
668 * Set up the Tx-command (not MAC!) header.
669 * Store the chosen Tx queue and TFD index within the sequence field;
670 * after Tx, uCode's Tx response will return this value so driver can
671 * locate the frame within the tx queue and do post-tx processing.
672 */
673 out_cmd->hdr.cmd = REPLY_TX;
674 out_cmd->hdr.sequence = cpu_to_le16((u16)(QUEUE_TO_SEQ(txq_id) |
675 INDEX_TO_SEQ(q->write_ptr)));
676
677 /* Copy MAC header from skb into command buffer */
678 memcpy(tx_cmd->hdr, hdr, hdr_len);
679
680
681 /* Total # bytes to be transmitted */
682 len = (u16)skb->len;
683 tx_cmd->len = cpu_to_le16(len);
684
685 if (info->control.hw_key)
686 iwlagn_tx_cmd_build_hwcrypto(priv, info, tx_cmd, skb, sta_id);
687
688 /* TODO need this for burst mode later on */
689 iwlagn_tx_cmd_build_basic(priv, skb, tx_cmd, info, hdr, sta_id);
690 iwl_dbg_log_tx_data_frame(priv, len, hdr);
691
692 iwlagn_tx_cmd_build_rate(priv, tx_cmd, info, fc);
693
694 iwl_update_stats(priv, true, fc, len);
695 /*
696 * Use the first empty entry in this queue's command buffer array
697 * to contain the Tx command and MAC header concatenated together
698 * (payload data will be in another buffer).
699 * Size of this varies, due to varying MAC header length.
700 * If end is not dword aligned, we'll have 2 extra bytes at the end
701 * of the MAC header (device reads on dword boundaries).
702 * We'll tell device about this padding later.
703 */
704 len = sizeof(struct iwl_tx_cmd) +
705 sizeof(struct iwl_cmd_header) + hdr_len;
706 firstlen = (len + 3) & ~3;
707
708 /* Tell NIC about any 2-byte padding after MAC header */
709 if (firstlen != len)
710 tx_cmd->tx_flags |= TX_CMD_FLG_MH_PAD_MSK;
711
712 /* Physical address of this Tx command's header (not MAC header!),
713 * within command buffer array. */
714 txcmd_phys = pci_map_single(priv->pci_dev,
715 &out_cmd->hdr, firstlen,
716 PCI_DMA_BIDIRECTIONAL);
717 if (unlikely(pci_dma_mapping_error(priv->pci_dev, txcmd_phys)))
718 goto drop_unlock_sta;
719 dma_unmap_addr_set(out_meta, mapping, txcmd_phys);
720 dma_unmap_len_set(out_meta, len, firstlen);
721
722 if (!ieee80211_has_morefrags(hdr->frame_control)) {
723 txq->need_update = 1;
724 } else {
725 wait_write_ptr = 1;
726 txq->need_update = 0;
727 }
728
729 /* Set up TFD's 2nd entry to point directly to remainder of skb,
730 * if any (802.11 null frames have no payload). */
731 secondlen = skb->len - hdr_len;
732 if (secondlen > 0) {
733 phys_addr = pci_map_single(priv->pci_dev, skb->data + hdr_len,
734 secondlen, PCI_DMA_TODEVICE);
735 if (unlikely(pci_dma_mapping_error(priv->pci_dev, phys_addr))) {
736 pci_unmap_single(priv->pci_dev,
737 dma_unmap_addr(out_meta, mapping),
738 dma_unmap_len(out_meta, len),
739 PCI_DMA_BIDIRECTIONAL);
740 goto drop_unlock_sta;
741 }
742 }
743
744 if (ieee80211_is_data_qos(fc)) {
745 priv->stations[sta_id].tid[tid].tfds_in_queue++;
746 if (!ieee80211_has_morefrags(fc))
747 priv->stations[sta_id].tid[tid].seq_number = seq_number;
748 }
749
750 spin_unlock(&priv->sta_lock);
751
752 /* Attach buffers to TFD */
753 iwlagn_txq_attach_buf_to_tfd(priv, txq, txcmd_phys, firstlen, 1);
754 if (secondlen > 0)
755 iwlagn_txq_attach_buf_to_tfd(priv, txq, phys_addr,
756 secondlen, 0);
757
758 scratch_phys = txcmd_phys + sizeof(struct iwl_cmd_header) +
759 offsetof(struct iwl_tx_cmd, scratch);
760
761 /* take back ownership of DMA buffer to enable update */
762 pci_dma_sync_single_for_cpu(priv->pci_dev, txcmd_phys,
763 firstlen, PCI_DMA_BIDIRECTIONAL);
764 tx_cmd->dram_lsb_ptr = cpu_to_le32(scratch_phys);
765 tx_cmd->dram_msb_ptr = iwl_get_dma_hi_addr(scratch_phys);
766
767 IWL_DEBUG_TX(priv, "sequence nr = 0X%x\n",
768 le16_to_cpu(out_cmd->hdr.sequence));
769 IWL_DEBUG_TX(priv, "tx_flags = 0X%x\n", le32_to_cpu(tx_cmd->tx_flags));
770 iwl_print_hex_dump(priv, IWL_DL_TX, (u8 *)tx_cmd, sizeof(*tx_cmd));
771 iwl_print_hex_dump(priv, IWL_DL_TX, (u8 *)tx_cmd->hdr, hdr_len);
772
773 /* Set up entry for this TFD in Tx byte-count array */
774 if (info->flags & IEEE80211_TX_CTL_AMPDU)
775 iwlagn_txq_update_byte_cnt_tbl(priv, txq,
776 le16_to_cpu(tx_cmd->len));
777
778 pci_dma_sync_single_for_device(priv->pci_dev, txcmd_phys,
779 firstlen, PCI_DMA_BIDIRECTIONAL);
780
781 trace_iwlwifi_dev_tx(priv,
782 &((struct iwl_tfd *)txq->tfds)[txq->q.write_ptr],
783 sizeof(struct iwl_tfd),
784 &out_cmd->hdr, firstlen,
785 skb->data + hdr_len, secondlen);
786
787 /* Tell device the write index *just past* this latest filled TFD */
788 q->write_ptr = iwl_queue_inc_wrap(q->write_ptr, q->n_bd);
789 iwl_txq_update_write_ptr(priv, txq);
790 spin_unlock_irqrestore(&priv->lock, flags);
791
792 /*
793 * At this point the frame is "transmitted" successfully
794 * and we will get a TX status notification eventually,
795 * regardless of the value of ret. "ret" only indicates
796 * whether or not we should update the write pointer.
797 */
798
799 /*
800 * Avoid atomic ops if it isn't an associated client.
801 * Also, if this is a packet for aggregation, don't
802 * increase the counter because the ucode will stop
803 * aggregation queues when their respective station
804 * goes to sleep.
805 */
806 if (sta_priv && sta_priv->client && !is_agg)
807 atomic_inc(&sta_priv->pending_frames);
808
809 if ((iwl_queue_space(q) < q->high_mark) && priv->mac80211_registered) {
810 if (wait_write_ptr) {
811 spin_lock_irqsave(&priv->lock, flags);
812 txq->need_update = 1;
813 iwl_txq_update_write_ptr(priv, txq);
814 spin_unlock_irqrestore(&priv->lock, flags);
815 } else {
816 iwl_stop_queue(priv, txq);
817 }
818 }
819
820 return 0;
821
822 drop_unlock_sta:
823 spin_unlock(&priv->sta_lock);
824 drop_unlock_priv:
825 spin_unlock_irqrestore(&priv->lock, flags);
826 return -1;
827 }
828
829 static inline int iwlagn_alloc_dma_ptr(struct iwl_priv *priv,
830 struct iwl_dma_ptr *ptr, size_t size)
831 {
832 ptr->addr = dma_alloc_coherent(&priv->pci_dev->dev, size, &ptr->dma,
833 GFP_KERNEL);
834 if (!ptr->addr)
835 return -ENOMEM;
836 ptr->size = size;
837 return 0;
838 }
839
840 static inline void iwlagn_free_dma_ptr(struct iwl_priv *priv,
841 struct iwl_dma_ptr *ptr)
842 {
843 if (unlikely(!ptr->addr))
844 return;
845
846 dma_free_coherent(&priv->pci_dev->dev, ptr->size, ptr->addr, ptr->dma);
847 memset(ptr, 0, sizeof(*ptr));
848 }
849
850 /**
851 * iwlagn_hw_txq_ctx_free - Free TXQ Context
852 *
853 * Destroy all TX DMA queues and structures
854 */
855 void iwlagn_hw_txq_ctx_free(struct iwl_priv *priv)
856 {
857 int txq_id;
858
859 /* Tx queues */
860 if (priv->txq) {
861 for (txq_id = 0; txq_id < priv->hw_params.max_txq_num; txq_id++)
862 if (txq_id == priv->cmd_queue)
863 iwl_cmd_queue_free(priv);
864 else
865 iwl_tx_queue_free(priv, txq_id);
866 }
867 iwlagn_free_dma_ptr(priv, &priv->kw);
868
869 iwlagn_free_dma_ptr(priv, &priv->scd_bc_tbls);
870
871 /* free tx queue structure */
872 iwl_free_txq_mem(priv);
873 }
874
875 /**
876 * iwlagn_txq_ctx_alloc - allocate TX queue context
877 * Allocate all Tx DMA structures and initialize them
878 *
879 * @param priv
880 * @return error code
881 */
882 int iwlagn_txq_ctx_alloc(struct iwl_priv *priv)
883 {
884 int ret;
885 int txq_id, slots_num;
886 unsigned long flags;
887
888 /* Free all tx/cmd queues and keep-warm buffer */
889 iwlagn_hw_txq_ctx_free(priv);
890
891 ret = iwlagn_alloc_dma_ptr(priv, &priv->scd_bc_tbls,
892 priv->hw_params.scd_bc_tbls_size);
893 if (ret) {
894 IWL_ERR(priv, "Scheduler BC Table allocation failed\n");
895 goto error_bc_tbls;
896 }
897 /* Alloc keep-warm buffer */
898 ret = iwlagn_alloc_dma_ptr(priv, &priv->kw, IWL_KW_SIZE);
899 if (ret) {
900 IWL_ERR(priv, "Keep Warm allocation failed\n");
901 goto error_kw;
902 }
903
904 /* allocate tx queue structure */
905 ret = iwl_alloc_txq_mem(priv);
906 if (ret)
907 goto error;
908
909 spin_lock_irqsave(&priv->lock, flags);
910
911 /* Turn off all Tx DMA fifos */
912 iwlagn_txq_set_sched(priv, 0);
913
914 /* Tell NIC where to find the "keep warm" buffer */
915 iwl_write_direct32(priv, FH_KW_MEM_ADDR_REG, priv->kw.dma >> 4);
916
917 spin_unlock_irqrestore(&priv->lock, flags);
918
919 /* Alloc and init all Tx queues, including the command queue (#4/#9) */
920 for (txq_id = 0; txq_id < priv->hw_params.max_txq_num; txq_id++) {
921 slots_num = (txq_id == priv->cmd_queue) ?
922 TFD_CMD_SLOTS : TFD_TX_CMD_SLOTS;
923 ret = iwl_tx_queue_init(priv, &priv->txq[txq_id], slots_num,
924 txq_id);
925 if (ret) {
926 IWL_ERR(priv, "Tx %d queue init failed\n", txq_id);
927 goto error;
928 }
929 }
930
931 return ret;
932
933 error:
934 iwlagn_hw_txq_ctx_free(priv);
935 iwlagn_free_dma_ptr(priv, &priv->kw);
936 error_kw:
937 iwlagn_free_dma_ptr(priv, &priv->scd_bc_tbls);
938 error_bc_tbls:
939 return ret;
940 }
941
942 void iwlagn_txq_ctx_reset(struct iwl_priv *priv)
943 {
944 int txq_id, slots_num;
945 unsigned long flags;
946
947 spin_lock_irqsave(&priv->lock, flags);
948
949 /* Turn off all Tx DMA fifos */
950 iwlagn_txq_set_sched(priv, 0);
951
952 /* Tell NIC where to find the "keep warm" buffer */
953 iwl_write_direct32(priv, FH_KW_MEM_ADDR_REG, priv->kw.dma >> 4);
954
955 spin_unlock_irqrestore(&priv->lock, flags);
956
957 /* Alloc and init all Tx queues, including the command queue (#4) */
958 for (txq_id = 0; txq_id < priv->hw_params.max_txq_num; txq_id++) {
959 slots_num = txq_id == priv->cmd_queue ?
960 TFD_CMD_SLOTS : TFD_TX_CMD_SLOTS;
961 iwl_tx_queue_reset(priv, &priv->txq[txq_id], slots_num, txq_id);
962 }
963 }
964
965 /**
966 * iwlagn_txq_ctx_stop - Stop all Tx DMA channels
967 */
968 void iwlagn_txq_ctx_stop(struct iwl_priv *priv)
969 {
970 int ch, txq_id;
971 unsigned long flags;
972
973 /* Turn off all Tx DMA fifos */
974 spin_lock_irqsave(&priv->lock, flags);
975
976 iwlagn_txq_set_sched(priv, 0);
977
978 /* Stop each Tx DMA channel, and wait for it to be idle */
979 for (ch = 0; ch < priv->hw_params.dma_chnl_num; ch++) {
980 iwl_write_direct32(priv, FH_TCSR_CHNL_TX_CONFIG_REG(ch), 0x0);
981 if (iwl_poll_direct_bit(priv, FH_TSSR_TX_STATUS_REG,
982 FH_TSSR_TX_STATUS_REG_MSK_CHNL_IDLE(ch),
983 1000))
984 IWL_ERR(priv, "Failing on timeout while stopping"
985 " DMA channel %d [0x%08x]", ch,
986 iwl_read_direct32(priv, FH_TSSR_TX_STATUS_REG));
987 }
988 spin_unlock_irqrestore(&priv->lock, flags);
989
990 if (!priv->txq)
991 return;
992
993 /* Unmap DMA from host system and free skb's */
994 for (txq_id = 0; txq_id < priv->hw_params.max_txq_num; txq_id++)
995 if (txq_id == priv->cmd_queue)
996 iwl_cmd_queue_unmap(priv);
997 else
998 iwl_tx_queue_unmap(priv, txq_id);
999 }
1000
1001 /*
1002 * Find first available (lowest unused) Tx Queue, mark it "active".
1003 * Called only when finding queue for aggregation.
1004 * Should never return anything < 7, because they should already
1005 * be in use as EDCA AC (0-3), Command (4), reserved (5, 6)
1006 */
1007 static int iwlagn_txq_ctx_activate_free(struct iwl_priv *priv)
1008 {
1009 int txq_id;
1010
1011 for (txq_id = 0; txq_id < priv->hw_params.max_txq_num; txq_id++)
1012 if (!test_and_set_bit(txq_id, &priv->txq_ctx_active_msk))
1013 return txq_id;
1014 return -1;
1015 }
1016
1017 int iwlagn_tx_agg_start(struct iwl_priv *priv, struct ieee80211_vif *vif,
1018 struct ieee80211_sta *sta, u16 tid, u16 *ssn)
1019 {
1020 int sta_id;
1021 int tx_fifo;
1022 int txq_id;
1023 int ret;
1024 unsigned long flags;
1025 struct iwl_tid_data *tid_data;
1026
1027 tx_fifo = get_fifo_from_tid(iwl_rxon_ctx_from_vif(vif), tid);
1028 if (unlikely(tx_fifo < 0))
1029 return tx_fifo;
1030
1031 IWL_WARN(priv, "%s on ra = %pM tid = %d\n",
1032 __func__, sta->addr, tid);
1033
1034 sta_id = iwl_sta_id(sta);
1035 if (sta_id == IWL_INVALID_STATION) {
1036 IWL_ERR(priv, "Start AGG on invalid station\n");
1037 return -ENXIO;
1038 }
1039 if (unlikely(tid >= MAX_TID_COUNT))
1040 return -EINVAL;
1041
1042 if (priv->stations[sta_id].tid[tid].agg.state != IWL_AGG_OFF) {
1043 IWL_ERR(priv, "Start AGG when state is not IWL_AGG_OFF !\n");
1044 return -ENXIO;
1045 }
1046
1047 txq_id = iwlagn_txq_ctx_activate_free(priv);
1048 if (txq_id == -1) {
1049 IWL_ERR(priv, "No free aggregation queue available\n");
1050 return -ENXIO;
1051 }
1052
1053 spin_lock_irqsave(&priv->sta_lock, flags);
1054 tid_data = &priv->stations[sta_id].tid[tid];
1055 *ssn = SEQ_TO_SN(tid_data->seq_number);
1056 tid_data->agg.txq_id = txq_id;
1057 tid_data->agg.tx_fifo = tx_fifo;
1058 iwl_set_swq_id(&priv->txq[txq_id], get_ac_from_tid(tid), txq_id);
1059 spin_unlock_irqrestore(&priv->sta_lock, flags);
1060
1061 ret = iwlagn_txq_agg_enable(priv, txq_id, sta_id, tid);
1062 if (ret)
1063 return ret;
1064
1065 spin_lock_irqsave(&priv->sta_lock, flags);
1066 tid_data = &priv->stations[sta_id].tid[tid];
1067 if (tid_data->tfds_in_queue == 0) {
1068 IWL_DEBUG_HT(priv, "HW queue is empty\n");
1069 tid_data->agg.state = IWL_AGG_ON;
1070 ieee80211_start_tx_ba_cb_irqsafe(vif, sta->addr, tid);
1071 } else {
1072 IWL_DEBUG_HT(priv, "HW queue is NOT empty: %d packets in HW queue\n",
1073 tid_data->tfds_in_queue);
1074 tid_data->agg.state = IWL_EMPTYING_HW_QUEUE_ADDBA;
1075 }
1076 spin_unlock_irqrestore(&priv->sta_lock, flags);
1077 return ret;
1078 }
1079
1080 int iwlagn_tx_agg_stop(struct iwl_priv *priv, struct ieee80211_vif *vif,
1081 struct ieee80211_sta *sta, u16 tid)
1082 {
1083 int tx_fifo_id, txq_id, sta_id, ssn;
1084 struct iwl_tid_data *tid_data;
1085 int write_ptr, read_ptr;
1086 unsigned long flags;
1087
1088 tx_fifo_id = get_fifo_from_tid(iwl_rxon_ctx_from_vif(vif), tid);
1089 if (unlikely(tx_fifo_id < 0))
1090 return tx_fifo_id;
1091
1092 sta_id = iwl_sta_id(sta);
1093
1094 if (sta_id == IWL_INVALID_STATION) {
1095 IWL_ERR(priv, "Invalid station for AGG tid %d\n", tid);
1096 return -ENXIO;
1097 }
1098
1099 spin_lock_irqsave(&priv->sta_lock, flags);
1100
1101 tid_data = &priv->stations[sta_id].tid[tid];
1102 ssn = (tid_data->seq_number & IEEE80211_SCTL_SEQ) >> 4;
1103 txq_id = tid_data->agg.txq_id;
1104
1105 switch (priv->stations[sta_id].tid[tid].agg.state) {
1106 case IWL_EMPTYING_HW_QUEUE_ADDBA:
1107 /*
1108 * This can happen if the peer stops aggregation
1109 * again before we've had a chance to drain the
1110 * queue we selected previously, i.e. before the
1111 * session was really started completely.
1112 */
1113 IWL_DEBUG_HT(priv, "AGG stop before setup done\n");
1114 goto turn_off;
1115 case IWL_AGG_ON:
1116 break;
1117 default:
1118 IWL_WARN(priv, "Stopping AGG while state not ON or starting\n");
1119 }
1120
1121 write_ptr = priv->txq[txq_id].q.write_ptr;
1122 read_ptr = priv->txq[txq_id].q.read_ptr;
1123
1124 /* The queue is not empty */
1125 if (write_ptr != read_ptr) {
1126 IWL_DEBUG_HT(priv, "Stopping a non empty AGG HW QUEUE\n");
1127 priv->stations[sta_id].tid[tid].agg.state =
1128 IWL_EMPTYING_HW_QUEUE_DELBA;
1129 spin_unlock_irqrestore(&priv->sta_lock, flags);
1130 return 0;
1131 }
1132
1133 IWL_DEBUG_HT(priv, "HW queue is empty\n");
1134 turn_off:
1135 priv->stations[sta_id].tid[tid].agg.state = IWL_AGG_OFF;
1136
1137 /* do not restore/save irqs */
1138 spin_unlock(&priv->sta_lock);
1139 spin_lock(&priv->lock);
1140
1141 /*
1142 * the only reason this call can fail is queue number out of range,
1143 * which can happen if uCode is reloaded and all the station
1144 * information are lost. if it is outside the range, there is no need
1145 * to deactivate the uCode queue, just return "success" to allow
1146 * mac80211 to clean up it own data.
1147 */
1148 iwlagn_txq_agg_disable(priv, txq_id, ssn, tx_fifo_id);
1149 spin_unlock_irqrestore(&priv->lock, flags);
1150
1151 ieee80211_stop_tx_ba_cb_irqsafe(vif, sta->addr, tid);
1152
1153 return 0;
1154 }
1155
1156 int iwlagn_txq_check_empty(struct iwl_priv *priv,
1157 int sta_id, u8 tid, int txq_id)
1158 {
1159 struct iwl_queue *q = &priv->txq[txq_id].q;
1160 u8 *addr = priv->stations[sta_id].sta.sta.addr;
1161 struct iwl_tid_data *tid_data = &priv->stations[sta_id].tid[tid];
1162 struct iwl_rxon_context *ctx;
1163
1164 ctx = &priv->contexts[priv->stations[sta_id].ctxid];
1165
1166 lockdep_assert_held(&priv->sta_lock);
1167
1168 switch (priv->stations[sta_id].tid[tid].agg.state) {
1169 case IWL_EMPTYING_HW_QUEUE_DELBA:
1170 /* We are reclaiming the last packet of the */
1171 /* aggregated HW queue */
1172 if ((txq_id == tid_data->agg.txq_id) &&
1173 (q->read_ptr == q->write_ptr)) {
1174 u16 ssn = SEQ_TO_SN(tid_data->seq_number);
1175 int tx_fifo = get_fifo_from_tid(ctx, tid);
1176 IWL_DEBUG_HT(priv, "HW queue empty: continue DELBA flow\n");
1177 iwlagn_txq_agg_disable(priv, txq_id, ssn, tx_fifo);
1178 tid_data->agg.state = IWL_AGG_OFF;
1179 ieee80211_stop_tx_ba_cb_irqsafe(ctx->vif, addr, tid);
1180 }
1181 break;
1182 case IWL_EMPTYING_HW_QUEUE_ADDBA:
1183 /* We are reclaiming the last packet of the queue */
1184 if (tid_data->tfds_in_queue == 0) {
1185 IWL_DEBUG_HT(priv, "HW queue empty: continue ADDBA flow\n");
1186 tid_data->agg.state = IWL_AGG_ON;
1187 ieee80211_start_tx_ba_cb_irqsafe(ctx->vif, addr, tid);
1188 }
1189 break;
1190 }
1191
1192 return 0;
1193 }
1194
1195 static void iwlagn_non_agg_tx_status(struct iwl_priv *priv,
1196 struct iwl_rxon_context *ctx,
1197 const u8 *addr1)
1198 {
1199 struct ieee80211_sta *sta;
1200 struct iwl_station_priv *sta_priv;
1201
1202 rcu_read_lock();
1203 sta = ieee80211_find_sta(ctx->vif, addr1);
1204 if (sta) {
1205 sta_priv = (void *)sta->drv_priv;
1206 /* avoid atomic ops if this isn't a client */
1207 if (sta_priv->client &&
1208 atomic_dec_return(&sta_priv->pending_frames) == 0)
1209 ieee80211_sta_block_awake(priv->hw, sta, false);
1210 }
1211 rcu_read_unlock();
1212 }
1213
1214 static void iwlagn_tx_status(struct iwl_priv *priv, struct iwl_tx_info *tx_info,
1215 bool is_agg)
1216 {
1217 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) tx_info->skb->data;
1218
1219 if (!is_agg)
1220 iwlagn_non_agg_tx_status(priv, tx_info->ctx, hdr->addr1);
1221
1222 ieee80211_tx_status_irqsafe(priv->hw, tx_info->skb);
1223 }
1224
1225 int iwlagn_tx_queue_reclaim(struct iwl_priv *priv, int txq_id, int index)
1226 {
1227 struct iwl_tx_queue *txq = &priv->txq[txq_id];
1228 struct iwl_queue *q = &txq->q;
1229 struct iwl_tx_info *tx_info;
1230 int nfreed = 0;
1231 struct ieee80211_hdr *hdr;
1232
1233 if ((index >= q->n_bd) || (iwl_queue_used(q, index) == 0)) {
1234 IWL_ERR(priv, "Read index for DMA queue txq id (%d), index %d, "
1235 "is out of range [0-%d] %d %d.\n", txq_id,
1236 index, q->n_bd, q->write_ptr, q->read_ptr);
1237 return 0;
1238 }
1239
1240 for (index = iwl_queue_inc_wrap(index, q->n_bd);
1241 q->read_ptr != index;
1242 q->read_ptr = iwl_queue_inc_wrap(q->read_ptr, q->n_bd)) {
1243
1244 tx_info = &txq->txb[txq->q.read_ptr];
1245
1246 if (WARN_ON_ONCE(tx_info->skb == NULL))
1247 continue;
1248
1249 hdr = (struct ieee80211_hdr *)tx_info->skb->data;
1250 if (ieee80211_is_data_qos(hdr->frame_control))
1251 nfreed++;
1252
1253 iwlagn_tx_status(priv, tx_info,
1254 txq_id >= IWLAGN_FIRST_AMPDU_QUEUE);
1255 tx_info->skb = NULL;
1256
1257 iwlagn_txq_inval_byte_cnt_tbl(priv, txq);
1258
1259 iwlagn_txq_free_tfd(priv, txq);
1260 }
1261 return nfreed;
1262 }
1263
1264 /**
1265 * iwlagn_tx_status_reply_compressed_ba - Update tx status from block-ack
1266 *
1267 * Go through block-ack's bitmap of ACK'd frames, update driver's record of
1268 * ACK vs. not. This gets sent to mac80211, then to rate scaling algo.
1269 */
1270 static int iwlagn_tx_status_reply_compressed_ba(struct iwl_priv *priv,
1271 struct iwl_ht_agg *agg,
1272 struct iwl_compressed_ba_resp *ba_resp)
1273
1274 {
1275 int sh;
1276 u16 seq_ctl = le16_to_cpu(ba_resp->seq_ctl);
1277 u16 scd_flow = le16_to_cpu(ba_resp->scd_flow);
1278 struct ieee80211_tx_info *info;
1279 u64 bitmap, sent_bitmap;
1280
1281 if (unlikely(!agg->wait_for_ba)) {
1282 if (unlikely(ba_resp->bitmap))
1283 IWL_ERR(priv, "Received BA when not expected\n");
1284 return -EINVAL;
1285 }
1286
1287 /* Mark that the expected block-ack response arrived */
1288 agg->wait_for_ba = 0;
1289 IWL_DEBUG_TX_REPLY(priv, "BA %d %d\n", agg->start_idx, ba_resp->seq_ctl);
1290
1291 /* Calculate shift to align block-ack bits with our Tx window bits */
1292 sh = agg->start_idx - SEQ_TO_INDEX(seq_ctl >> 4);
1293 if (sh < 0)
1294 sh += 0x100;
1295
1296 /*
1297 * Check for success or failure according to the
1298 * transmitted bitmap and block-ack bitmap
1299 */
1300 bitmap = le64_to_cpu(ba_resp->bitmap) >> sh;
1301 sent_bitmap = bitmap & agg->bitmap;
1302
1303 /* Sanity check values reported by uCode */
1304 if (ba_resp->txed_2_done > ba_resp->txed) {
1305 IWL_DEBUG_TX_REPLY(priv,
1306 "bogus sent(%d) and ack(%d) count\n",
1307 ba_resp->txed, ba_resp->txed_2_done);
1308 /*
1309 * set txed_2_done = txed,
1310 * so it won't impact rate scale
1311 */
1312 ba_resp->txed = ba_resp->txed_2_done;
1313 }
1314 IWL_DEBUG_HT(priv, "agg frames sent:%d, acked:%d\n",
1315 ba_resp->txed, ba_resp->txed_2_done);
1316
1317 /* Find the first ACKed frame to store the TX status */
1318 while (sent_bitmap && !(sent_bitmap & 1)) {
1319 agg->start_idx = (agg->start_idx + 1) & 0xff;
1320 sent_bitmap >>= 1;
1321 }
1322
1323 info = IEEE80211_SKB_CB(priv->txq[scd_flow].txb[agg->start_idx].skb);
1324 memset(&info->status, 0, sizeof(info->status));
1325 info->flags |= IEEE80211_TX_STAT_ACK;
1326 info->flags |= IEEE80211_TX_STAT_AMPDU;
1327 info->status.ampdu_ack_len = ba_resp->txed_2_done;
1328 info->status.ampdu_len = ba_resp->txed;
1329 iwlagn_hwrate_to_tx_control(priv, agg->rate_n_flags, info);
1330
1331 return 0;
1332 }
1333
1334 /**
1335 * translate ucode response to mac80211 tx status control values
1336 */
1337 void iwlagn_hwrate_to_tx_control(struct iwl_priv *priv, u32 rate_n_flags,
1338 struct ieee80211_tx_info *info)
1339 {
1340 struct ieee80211_tx_rate *r = &info->control.rates[0];
1341
1342 info->antenna_sel_tx =
1343 ((rate_n_flags & RATE_MCS_ANT_ABC_MSK) >> RATE_MCS_ANT_POS);
1344 if (rate_n_flags & RATE_MCS_HT_MSK)
1345 r->flags |= IEEE80211_TX_RC_MCS;
1346 if (rate_n_flags & RATE_MCS_GF_MSK)
1347 r->flags |= IEEE80211_TX_RC_GREEN_FIELD;
1348 if (rate_n_flags & RATE_MCS_HT40_MSK)
1349 r->flags |= IEEE80211_TX_RC_40_MHZ_WIDTH;
1350 if (rate_n_flags & RATE_MCS_DUP_MSK)
1351 r->flags |= IEEE80211_TX_RC_DUP_DATA;
1352 if (rate_n_flags & RATE_MCS_SGI_MSK)
1353 r->flags |= IEEE80211_TX_RC_SHORT_GI;
1354 r->idx = iwlagn_hwrate_to_mac80211_idx(rate_n_flags, info->band);
1355 }
1356
1357 /**
1358 * iwlagn_rx_reply_compressed_ba - Handler for REPLY_COMPRESSED_BA
1359 *
1360 * Handles block-acknowledge notification from device, which reports success
1361 * of frames sent via aggregation.
1362 */
1363 void iwlagn_rx_reply_compressed_ba(struct iwl_priv *priv,
1364 struct iwl_rx_mem_buffer *rxb)
1365 {
1366 struct iwl_rx_packet *pkt = rxb_addr(rxb);
1367 struct iwl_compressed_ba_resp *ba_resp = &pkt->u.compressed_ba;
1368 struct iwl_tx_queue *txq = NULL;
1369 struct iwl_ht_agg *agg;
1370 int index;
1371 int sta_id;
1372 int tid;
1373 unsigned long flags;
1374
1375 /* "flow" corresponds to Tx queue */
1376 u16 scd_flow = le16_to_cpu(ba_resp->scd_flow);
1377
1378 /* "ssn" is start of block-ack Tx window, corresponds to index
1379 * (in Tx queue's circular buffer) of first TFD/frame in window */
1380 u16 ba_resp_scd_ssn = le16_to_cpu(ba_resp->scd_ssn);
1381
1382 if (scd_flow >= priv->hw_params.max_txq_num) {
1383 IWL_ERR(priv,
1384 "BUG_ON scd_flow is bigger than number of queues\n");
1385 return;
1386 }
1387
1388 txq = &priv->txq[scd_flow];
1389 sta_id = ba_resp->sta_id;
1390 tid = ba_resp->tid;
1391 agg = &priv->stations[sta_id].tid[tid].agg;
1392 if (unlikely(agg->txq_id != scd_flow)) {
1393 /*
1394 * FIXME: this is a uCode bug which need to be addressed,
1395 * log the information and return for now!
1396 * since it is possible happen very often and in order
1397 * not to fill the syslog, don't enable the logging by default
1398 */
1399 IWL_DEBUG_TX_REPLY(priv,
1400 "BA scd_flow %d does not match txq_id %d\n",
1401 scd_flow, agg->txq_id);
1402 return;
1403 }
1404
1405 /* Find index just before block-ack window */
1406 index = iwl_queue_dec_wrap(ba_resp_scd_ssn & 0xff, txq->q.n_bd);
1407
1408 spin_lock_irqsave(&priv->sta_lock, flags);
1409
1410 IWL_DEBUG_TX_REPLY(priv, "REPLY_COMPRESSED_BA [%d] Received from %pM, "
1411 "sta_id = %d\n",
1412 agg->wait_for_ba,
1413 (u8 *) &ba_resp->sta_addr_lo32,
1414 ba_resp->sta_id);
1415 IWL_DEBUG_TX_REPLY(priv, "TID = %d, SeqCtl = %d, bitmap = 0x%llx, scd_flow = "
1416 "%d, scd_ssn = %d\n",
1417 ba_resp->tid,
1418 ba_resp->seq_ctl,
1419 (unsigned long long)le64_to_cpu(ba_resp->bitmap),
1420 ba_resp->scd_flow,
1421 ba_resp->scd_ssn);
1422 IWL_DEBUG_TX_REPLY(priv, "DAT start_idx = %d, bitmap = 0x%llx\n",
1423 agg->start_idx,
1424 (unsigned long long)agg->bitmap);
1425
1426 /* Update driver's record of ACK vs. not for each frame in window */
1427 iwlagn_tx_status_reply_compressed_ba(priv, agg, ba_resp);
1428
1429 /* Release all TFDs before the SSN, i.e. all TFDs in front of
1430 * block-ack window (we assume that they've been successfully
1431 * transmitted ... if not, it's too late anyway). */
1432 if (txq->q.read_ptr != (ba_resp_scd_ssn & 0xff)) {
1433 /* calculate mac80211 ampdu sw queue to wake */
1434 int freed = iwlagn_tx_queue_reclaim(priv, scd_flow, index);
1435 iwl_free_tfds_in_queue(priv, sta_id, tid, freed);
1436
1437 if ((iwl_queue_space(&txq->q) > txq->q.low_mark) &&
1438 priv->mac80211_registered &&
1439 (agg->state != IWL_EMPTYING_HW_QUEUE_DELBA))
1440 iwl_wake_queue(priv, txq);
1441
1442 iwlagn_txq_check_empty(priv, sta_id, tid, scd_flow);
1443 }
1444
1445 spin_unlock_irqrestore(&priv->sta_lock, flags);
1446 }
1447
1448 #ifdef CONFIG_IWLWIFI_DEBUG
1449 const char *iwl_get_tx_fail_reason(u32 status)
1450 {
1451 #define TX_STATUS_FAIL(x) case TX_STATUS_FAIL_ ## x: return #x
1452 #define TX_STATUS_POSTPONE(x) case TX_STATUS_POSTPONE_ ## x: return #x
1453
1454 switch (status & TX_STATUS_MSK) {
1455 case TX_STATUS_SUCCESS:
1456 return "SUCCESS";
1457 TX_STATUS_POSTPONE(DELAY);
1458 TX_STATUS_POSTPONE(FEW_BYTES);
1459 TX_STATUS_POSTPONE(BT_PRIO);
1460 TX_STATUS_POSTPONE(QUIET_PERIOD);
1461 TX_STATUS_POSTPONE(CALC_TTAK);
1462 TX_STATUS_FAIL(INTERNAL_CROSSED_RETRY);
1463 TX_STATUS_FAIL(SHORT_LIMIT);
1464 TX_STATUS_FAIL(LONG_LIMIT);
1465 TX_STATUS_FAIL(FIFO_UNDERRUN);
1466 TX_STATUS_FAIL(DRAIN_FLOW);
1467 TX_STATUS_FAIL(RFKILL_FLUSH);
1468 TX_STATUS_FAIL(LIFE_EXPIRE);
1469 TX_STATUS_FAIL(DEST_PS);
1470 TX_STATUS_FAIL(HOST_ABORTED);
1471 TX_STATUS_FAIL(BT_RETRY);
1472 TX_STATUS_FAIL(STA_INVALID);
1473 TX_STATUS_FAIL(FRAG_DROPPED);
1474 TX_STATUS_FAIL(TID_DISABLE);
1475 TX_STATUS_FAIL(FIFO_FLUSHED);
1476 TX_STATUS_FAIL(INSUFFICIENT_CF_POLL);
1477 TX_STATUS_FAIL(PASSIVE_NO_RX);
1478 TX_STATUS_FAIL(NO_BEACON_ON_RADAR);
1479 }
1480
1481 return "UNKNOWN";
1482
1483 #undef TX_STATUS_FAIL
1484 #undef TX_STATUS_POSTPONE
1485 }
1486 #endif /* CONFIG_IWLWIFI_DEBUG */
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