1 /*******************************************************************************
3 Intel 10 Gigabit PCI Express Linux driver
4 Copyright(c) 1999 - 2011 Intel Corporation.
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
26 *******************************************************************************/
28 #include <linux/pci.h>
29 #include <linux/delay.h>
30 #include <linux/sched.h>
33 #include "ixgbe_phy.h"
34 #include "ixgbe_mbx.h"
36 #define IXGBE_82599_MAX_TX_QUEUES 128
37 #define IXGBE_82599_MAX_RX_QUEUES 128
38 #define IXGBE_82599_RAR_ENTRIES 128
39 #define IXGBE_82599_MC_TBL_SIZE 128
40 #define IXGBE_82599_VFT_TBL_SIZE 128
42 static void ixgbe_disable_tx_laser_multispeed_fiber(struct ixgbe_hw
*hw
);
43 static void ixgbe_enable_tx_laser_multispeed_fiber(struct ixgbe_hw
*hw
);
44 static void ixgbe_flap_tx_laser_multispeed_fiber(struct ixgbe_hw
*hw
);
45 static s32
ixgbe_setup_mac_link_multispeed_fiber(struct ixgbe_hw
*hw
,
46 ixgbe_link_speed speed
,
48 bool autoneg_wait_to_complete
);
49 static s32
ixgbe_setup_mac_link_smartspeed(struct ixgbe_hw
*hw
,
50 ixgbe_link_speed speed
,
52 bool autoneg_wait_to_complete
);
53 static s32
ixgbe_start_mac_link_82599(struct ixgbe_hw
*hw
,
54 bool autoneg_wait_to_complete
);
55 static s32
ixgbe_setup_mac_link_82599(struct ixgbe_hw
*hw
,
56 ixgbe_link_speed speed
,
58 bool autoneg_wait_to_complete
);
59 static s32
ixgbe_setup_copper_link_82599(struct ixgbe_hw
*hw
,
60 ixgbe_link_speed speed
,
62 bool autoneg_wait_to_complete
);
63 static s32
ixgbe_verify_fw_version_82599(struct ixgbe_hw
*hw
);
64 static bool ixgbe_verify_lesm_fw_enabled_82599(struct ixgbe_hw
*hw
);
66 static void ixgbe_init_mac_link_ops_82599(struct ixgbe_hw
*hw
)
68 struct ixgbe_mac_info
*mac
= &hw
->mac
;
70 /* enable the laser control functions for SFP+ fiber */
71 if (mac
->ops
.get_media_type(hw
) == ixgbe_media_type_fiber
) {
72 mac
->ops
.disable_tx_laser
=
73 &ixgbe_disable_tx_laser_multispeed_fiber
;
74 mac
->ops
.enable_tx_laser
=
75 &ixgbe_enable_tx_laser_multispeed_fiber
;
76 mac
->ops
.flap_tx_laser
= &ixgbe_flap_tx_laser_multispeed_fiber
;
78 mac
->ops
.disable_tx_laser
= NULL
;
79 mac
->ops
.enable_tx_laser
= NULL
;
80 mac
->ops
.flap_tx_laser
= NULL
;
83 if (hw
->phy
.multispeed_fiber
) {
84 /* Set up dual speed SFP+ support */
85 mac
->ops
.setup_link
= &ixgbe_setup_mac_link_multispeed_fiber
;
87 if ((mac
->ops
.get_media_type(hw
) ==
88 ixgbe_media_type_backplane
) &&
89 (hw
->phy
.smart_speed
== ixgbe_smart_speed_auto
||
90 hw
->phy
.smart_speed
== ixgbe_smart_speed_on
) &&
91 !ixgbe_verify_lesm_fw_enabled_82599(hw
))
92 mac
->ops
.setup_link
= &ixgbe_setup_mac_link_smartspeed
;
94 mac
->ops
.setup_link
= &ixgbe_setup_mac_link_82599
;
98 static s32
ixgbe_setup_sfp_modules_82599(struct ixgbe_hw
*hw
)
103 u16 list_offset
, data_offset
, data_value
;
105 if (hw
->phy
.sfp_type
!= ixgbe_sfp_type_unknown
) {
106 ixgbe_init_mac_link_ops_82599(hw
);
108 hw
->phy
.ops
.reset
= NULL
;
110 ret_val
= ixgbe_get_sfp_init_sequence_offsets(hw
, &list_offset
,
116 /* PHY config will finish before releasing the semaphore */
117 ret_val
= hw
->mac
.ops
.acquire_swfw_sync(hw
,
118 IXGBE_GSSR_MAC_CSR_SM
);
120 ret_val
= IXGBE_ERR_SWFW_SYNC
;
124 hw
->eeprom
.ops
.read(hw
, ++data_offset
, &data_value
);
125 while (data_value
!= 0xffff) {
126 IXGBE_WRITE_REG(hw
, IXGBE_CORECTL
, data_value
);
127 IXGBE_WRITE_FLUSH(hw
);
128 hw
->eeprom
.ops
.read(hw
, ++data_offset
, &data_value
);
131 /* Release the semaphore */
132 ixgbe_release_swfw_sync(hw
, IXGBE_GSSR_MAC_CSR_SM
);
134 * Delay obtaining semaphore again to allow FW access,
135 * semaphore_delay is in ms usleep_range needs us.
137 usleep_range(hw
->eeprom
.semaphore_delay
* 1000,
138 hw
->eeprom
.semaphore_delay
* 2000);
140 /* Now restart DSP by setting Restart_AN and clearing LMS */
141 IXGBE_WRITE_REG(hw
, IXGBE_AUTOC
, ((IXGBE_READ_REG(hw
,
142 IXGBE_AUTOC
) & ~IXGBE_AUTOC_LMS_MASK
) |
143 IXGBE_AUTOC_AN_RESTART
));
145 /* Wait for AN to leave state 0 */
146 for (i
= 0; i
< 10; i
++) {
147 usleep_range(4000, 8000);
148 reg_anlp1
= IXGBE_READ_REG(hw
, IXGBE_ANLP1
);
149 if (reg_anlp1
& IXGBE_ANLP1_AN_STATE_MASK
)
152 if (!(reg_anlp1
& IXGBE_ANLP1_AN_STATE_MASK
)) {
153 hw_dbg(hw
, "sfp module setup not complete\n");
154 ret_val
= IXGBE_ERR_SFP_SETUP_NOT_COMPLETE
;
158 /* Restart DSP by setting Restart_AN and return to SFI mode */
159 IXGBE_WRITE_REG(hw
, IXGBE_AUTOC
, (IXGBE_READ_REG(hw
,
160 IXGBE_AUTOC
) | IXGBE_AUTOC_LMS_10G_SERIAL
|
161 IXGBE_AUTOC_AN_RESTART
));
168 static s32
ixgbe_get_invariants_82599(struct ixgbe_hw
*hw
)
170 struct ixgbe_mac_info
*mac
= &hw
->mac
;
172 ixgbe_init_mac_link_ops_82599(hw
);
174 mac
->mcft_size
= IXGBE_82599_MC_TBL_SIZE
;
175 mac
->vft_size
= IXGBE_82599_VFT_TBL_SIZE
;
176 mac
->num_rar_entries
= IXGBE_82599_RAR_ENTRIES
;
177 mac
->max_rx_queues
= IXGBE_82599_MAX_RX_QUEUES
;
178 mac
->max_tx_queues
= IXGBE_82599_MAX_TX_QUEUES
;
179 mac
->max_msix_vectors
= ixgbe_get_pcie_msix_count_generic(hw
);
185 * ixgbe_init_phy_ops_82599 - PHY/SFP specific init
186 * @hw: pointer to hardware structure
188 * Initialize any function pointers that were not able to be
189 * set during get_invariants because the PHY/SFP type was
190 * not known. Perform the SFP init if necessary.
193 static s32
ixgbe_init_phy_ops_82599(struct ixgbe_hw
*hw
)
195 struct ixgbe_mac_info
*mac
= &hw
->mac
;
196 struct ixgbe_phy_info
*phy
= &hw
->phy
;
199 /* Identify the PHY or SFP module */
200 ret_val
= phy
->ops
.identify(hw
);
202 /* Setup function pointers based on detected SFP module and speeds */
203 ixgbe_init_mac_link_ops_82599(hw
);
205 /* If copper media, overwrite with copper function pointers */
206 if (mac
->ops
.get_media_type(hw
) == ixgbe_media_type_copper
) {
207 mac
->ops
.setup_link
= &ixgbe_setup_copper_link_82599
;
208 mac
->ops
.get_link_capabilities
=
209 &ixgbe_get_copper_link_capabilities_generic
;
212 /* Set necessary function pointers based on phy type */
213 switch (hw
->phy
.type
) {
215 phy
->ops
.check_link
= &ixgbe_check_phy_link_tnx
;
216 phy
->ops
.get_firmware_version
=
217 &ixgbe_get_phy_firmware_version_tnx
;
220 phy
->ops
.get_firmware_version
=
221 &ixgbe_get_phy_firmware_version_generic
;
231 * ixgbe_get_link_capabilities_82599 - Determines link capabilities
232 * @hw: pointer to hardware structure
233 * @speed: pointer to link speed
234 * @negotiation: true when autoneg or autotry is enabled
236 * Determines the link capabilities by reading the AUTOC register.
238 static s32
ixgbe_get_link_capabilities_82599(struct ixgbe_hw
*hw
,
239 ixgbe_link_speed
*speed
,
245 /* Determine 1G link capabilities off of SFP+ type */
246 if (hw
->phy
.sfp_type
== ixgbe_sfp_type_1g_cu_core0
||
247 hw
->phy
.sfp_type
== ixgbe_sfp_type_1g_cu_core1
) {
248 *speed
= IXGBE_LINK_SPEED_1GB_FULL
;
254 * Determine link capabilities based on the stored value of AUTOC,
255 * which represents EEPROM defaults. If AUTOC value has not been
256 * stored, use the current register value.
258 if (hw
->mac
.orig_link_settings_stored
)
259 autoc
= hw
->mac
.orig_autoc
;
261 autoc
= IXGBE_READ_REG(hw
, IXGBE_AUTOC
);
263 switch (autoc
& IXGBE_AUTOC_LMS_MASK
) {
264 case IXGBE_AUTOC_LMS_1G_LINK_NO_AN
:
265 *speed
= IXGBE_LINK_SPEED_1GB_FULL
;
266 *negotiation
= false;
269 case IXGBE_AUTOC_LMS_10G_LINK_NO_AN
:
270 *speed
= IXGBE_LINK_SPEED_10GB_FULL
;
271 *negotiation
= false;
274 case IXGBE_AUTOC_LMS_1G_AN
:
275 *speed
= IXGBE_LINK_SPEED_1GB_FULL
;
279 case IXGBE_AUTOC_LMS_10G_SERIAL
:
280 *speed
= IXGBE_LINK_SPEED_10GB_FULL
;
281 *negotiation
= false;
284 case IXGBE_AUTOC_LMS_KX4_KX_KR
:
285 case IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN
:
286 *speed
= IXGBE_LINK_SPEED_UNKNOWN
;
287 if (autoc
& IXGBE_AUTOC_KR_SUPP
)
288 *speed
|= IXGBE_LINK_SPEED_10GB_FULL
;
289 if (autoc
& IXGBE_AUTOC_KX4_SUPP
)
290 *speed
|= IXGBE_LINK_SPEED_10GB_FULL
;
291 if (autoc
& IXGBE_AUTOC_KX_SUPP
)
292 *speed
|= IXGBE_LINK_SPEED_1GB_FULL
;
296 case IXGBE_AUTOC_LMS_KX4_KX_KR_SGMII
:
297 *speed
= IXGBE_LINK_SPEED_100_FULL
;
298 if (autoc
& IXGBE_AUTOC_KR_SUPP
)
299 *speed
|= IXGBE_LINK_SPEED_10GB_FULL
;
300 if (autoc
& IXGBE_AUTOC_KX4_SUPP
)
301 *speed
|= IXGBE_LINK_SPEED_10GB_FULL
;
302 if (autoc
& IXGBE_AUTOC_KX_SUPP
)
303 *speed
|= IXGBE_LINK_SPEED_1GB_FULL
;
307 case IXGBE_AUTOC_LMS_SGMII_1G_100M
:
308 *speed
= IXGBE_LINK_SPEED_1GB_FULL
| IXGBE_LINK_SPEED_100_FULL
;
309 *negotiation
= false;
313 status
= IXGBE_ERR_LINK_SETUP
;
318 if (hw
->phy
.multispeed_fiber
) {
319 *speed
|= IXGBE_LINK_SPEED_10GB_FULL
|
320 IXGBE_LINK_SPEED_1GB_FULL
;
329 * ixgbe_get_media_type_82599 - Get media type
330 * @hw: pointer to hardware structure
332 * Returns the media type (fiber, copper, backplane)
334 static enum ixgbe_media_type
ixgbe_get_media_type_82599(struct ixgbe_hw
*hw
)
336 enum ixgbe_media_type media_type
;
338 /* Detect if there is a copper PHY attached. */
339 switch (hw
->phy
.type
) {
340 case ixgbe_phy_cu_unknown
:
343 media_type
= ixgbe_media_type_copper
;
349 switch (hw
->device_id
) {
350 case IXGBE_DEV_ID_82599_KX4
:
351 case IXGBE_DEV_ID_82599_KX4_MEZZ
:
352 case IXGBE_DEV_ID_82599_COMBO_BACKPLANE
:
353 case IXGBE_DEV_ID_82599_KR
:
354 case IXGBE_DEV_ID_82599_BACKPLANE_FCOE
:
355 case IXGBE_DEV_ID_82599_XAUI_LOM
:
356 /* Default device ID is mezzanine card KX/KX4 */
357 media_type
= ixgbe_media_type_backplane
;
359 case IXGBE_DEV_ID_82599_SFP
:
360 case IXGBE_DEV_ID_82599_SFP_FCOE
:
361 case IXGBE_DEV_ID_82599_SFP_EM
:
362 case IXGBE_DEV_ID_82599_SFP_SF2
:
363 media_type
= ixgbe_media_type_fiber
;
365 case IXGBE_DEV_ID_82599_CX4
:
366 media_type
= ixgbe_media_type_cx4
;
368 case IXGBE_DEV_ID_82599_T3_LOM
:
369 media_type
= ixgbe_media_type_copper
;
372 media_type
= ixgbe_media_type_unknown
;
380 * ixgbe_start_mac_link_82599 - Setup MAC link settings
381 * @hw: pointer to hardware structure
382 * @autoneg_wait_to_complete: true when waiting for completion is needed
384 * Configures link settings based on values in the ixgbe_hw struct.
385 * Restarts the link. Performs autonegotiation if needed.
387 static s32
ixgbe_start_mac_link_82599(struct ixgbe_hw
*hw
,
388 bool autoneg_wait_to_complete
)
396 autoc_reg
= IXGBE_READ_REG(hw
, IXGBE_AUTOC
);
397 autoc_reg
|= IXGBE_AUTOC_AN_RESTART
;
398 IXGBE_WRITE_REG(hw
, IXGBE_AUTOC
, autoc_reg
);
400 /* Only poll for autoneg to complete if specified to do so */
401 if (autoneg_wait_to_complete
) {
402 if ((autoc_reg
& IXGBE_AUTOC_LMS_MASK
) ==
403 IXGBE_AUTOC_LMS_KX4_KX_KR
||
404 (autoc_reg
& IXGBE_AUTOC_LMS_MASK
) ==
405 IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN
||
406 (autoc_reg
& IXGBE_AUTOC_LMS_MASK
) ==
407 IXGBE_AUTOC_LMS_KX4_KX_KR_SGMII
) {
408 links_reg
= 0; /* Just in case Autoneg time = 0 */
409 for (i
= 0; i
< IXGBE_AUTO_NEG_TIME
; i
++) {
410 links_reg
= IXGBE_READ_REG(hw
, IXGBE_LINKS
);
411 if (links_reg
& IXGBE_LINKS_KX_AN_COMP
)
415 if (!(links_reg
& IXGBE_LINKS_KX_AN_COMP
)) {
416 status
= IXGBE_ERR_AUTONEG_NOT_COMPLETE
;
417 hw_dbg(hw
, "Autoneg did not complete.\n");
422 /* Add delay to filter out noises during initial link setup */
429 * ixgbe_disable_tx_laser_multispeed_fiber - Disable Tx laser
430 * @hw: pointer to hardware structure
432 * The base drivers may require better control over SFP+ module
433 * PHY states. This includes selectively shutting down the Tx
434 * laser on the PHY, effectively halting physical link.
436 static void ixgbe_disable_tx_laser_multispeed_fiber(struct ixgbe_hw
*hw
)
438 u32 esdp_reg
= IXGBE_READ_REG(hw
, IXGBE_ESDP
);
440 /* Disable tx laser; allow 100us to go dark per spec */
441 esdp_reg
|= IXGBE_ESDP_SDP3
;
442 IXGBE_WRITE_REG(hw
, IXGBE_ESDP
, esdp_reg
);
443 IXGBE_WRITE_FLUSH(hw
);
448 * ixgbe_enable_tx_laser_multispeed_fiber - Enable Tx laser
449 * @hw: pointer to hardware structure
451 * The base drivers may require better control over SFP+ module
452 * PHY states. This includes selectively turning on the Tx
453 * laser on the PHY, effectively starting physical link.
455 static void ixgbe_enable_tx_laser_multispeed_fiber(struct ixgbe_hw
*hw
)
457 u32 esdp_reg
= IXGBE_READ_REG(hw
, IXGBE_ESDP
);
459 /* Enable tx laser; allow 100ms to light up */
460 esdp_reg
&= ~IXGBE_ESDP_SDP3
;
461 IXGBE_WRITE_REG(hw
, IXGBE_ESDP
, esdp_reg
);
462 IXGBE_WRITE_FLUSH(hw
);
467 * ixgbe_flap_tx_laser_multispeed_fiber - Flap Tx laser
468 * @hw: pointer to hardware structure
470 * When the driver changes the link speeds that it can support,
471 * it sets autotry_restart to true to indicate that we need to
472 * initiate a new autotry session with the link partner. To do
473 * so, we set the speed then disable and re-enable the tx laser, to
474 * alert the link partner that it also needs to restart autotry on its
475 * end. This is consistent with true clause 37 autoneg, which also
476 * involves a loss of signal.
478 static void ixgbe_flap_tx_laser_multispeed_fiber(struct ixgbe_hw
*hw
)
480 if (hw
->mac
.autotry_restart
) {
481 ixgbe_disable_tx_laser_multispeed_fiber(hw
);
482 ixgbe_enable_tx_laser_multispeed_fiber(hw
);
483 hw
->mac
.autotry_restart
= false;
488 * ixgbe_setup_mac_link_multispeed_fiber - Set MAC link speed
489 * @hw: pointer to hardware structure
490 * @speed: new link speed
491 * @autoneg: true if autonegotiation enabled
492 * @autoneg_wait_to_complete: true when waiting for completion is needed
494 * Set the link speed in the AUTOC register and restarts link.
496 s32
ixgbe_setup_mac_link_multispeed_fiber(struct ixgbe_hw
*hw
,
497 ixgbe_link_speed speed
,
499 bool autoneg_wait_to_complete
)
502 ixgbe_link_speed link_speed
= IXGBE_LINK_SPEED_UNKNOWN
;
503 ixgbe_link_speed highest_link_speed
= IXGBE_LINK_SPEED_UNKNOWN
;
505 u32 esdp_reg
= IXGBE_READ_REG(hw
, IXGBE_ESDP
);
507 bool link_up
= false;
510 /* Mask off requested but non-supported speeds */
511 status
= hw
->mac
.ops
.get_link_capabilities(hw
, &link_speed
,
519 * Try each speed one by one, highest priority first. We do this in
520 * software because 10gb fiber doesn't support speed autonegotiation.
522 if (speed
& IXGBE_LINK_SPEED_10GB_FULL
) {
524 highest_link_speed
= IXGBE_LINK_SPEED_10GB_FULL
;
526 /* If we already have link at this speed, just jump out */
527 status
= hw
->mac
.ops
.check_link(hw
, &link_speed
, &link_up
,
532 if ((link_speed
== IXGBE_LINK_SPEED_10GB_FULL
) && link_up
)
535 /* Set the module link speed */
536 esdp_reg
|= (IXGBE_ESDP_SDP5_DIR
| IXGBE_ESDP_SDP5
);
537 IXGBE_WRITE_REG(hw
, IXGBE_ESDP
, esdp_reg
);
538 IXGBE_WRITE_FLUSH(hw
);
540 /* Allow module to change analog characteristics (1G->10G) */
543 status
= ixgbe_setup_mac_link_82599(hw
,
544 IXGBE_LINK_SPEED_10GB_FULL
,
546 autoneg_wait_to_complete
);
550 /* Flap the tx laser if it has not already been done */
551 hw
->mac
.ops
.flap_tx_laser(hw
);
554 * Wait for the controller to acquire link. Per IEEE 802.3ap,
555 * Section 73.10.2, we may have to wait up to 500ms if KR is
556 * attempted. 82599 uses the same timing for 10g SFI.
558 for (i
= 0; i
< 5; i
++) {
559 /* Wait for the link partner to also set speed */
562 /* If we have link, just jump out */
563 status
= hw
->mac
.ops
.check_link(hw
, &link_speed
,
573 if (speed
& IXGBE_LINK_SPEED_1GB_FULL
) {
575 if (highest_link_speed
== IXGBE_LINK_SPEED_UNKNOWN
)
576 highest_link_speed
= IXGBE_LINK_SPEED_1GB_FULL
;
578 /* If we already have link at this speed, just jump out */
579 status
= hw
->mac
.ops
.check_link(hw
, &link_speed
, &link_up
,
584 if ((link_speed
== IXGBE_LINK_SPEED_1GB_FULL
) && link_up
)
587 /* Set the module link speed */
588 esdp_reg
&= ~IXGBE_ESDP_SDP5
;
589 esdp_reg
|= IXGBE_ESDP_SDP5_DIR
;
590 IXGBE_WRITE_REG(hw
, IXGBE_ESDP
, esdp_reg
);
591 IXGBE_WRITE_FLUSH(hw
);
593 /* Allow module to change analog characteristics (10G->1G) */
596 status
= ixgbe_setup_mac_link_82599(hw
,
597 IXGBE_LINK_SPEED_1GB_FULL
,
599 autoneg_wait_to_complete
);
603 /* Flap the tx laser if it has not already been done */
604 hw
->mac
.ops
.flap_tx_laser(hw
);
606 /* Wait for the link partner to also set speed */
609 /* If we have link, just jump out */
610 status
= hw
->mac
.ops
.check_link(hw
, &link_speed
, &link_up
,
620 * We didn't get link. Configure back to the highest speed we tried,
621 * (if there was more than one). We call ourselves back with just the
622 * single highest speed that the user requested.
625 status
= ixgbe_setup_mac_link_multispeed_fiber(hw
,
628 autoneg_wait_to_complete
);
631 /* Set autoneg_advertised value based on input link speed */
632 hw
->phy
.autoneg_advertised
= 0;
634 if (speed
& IXGBE_LINK_SPEED_10GB_FULL
)
635 hw
->phy
.autoneg_advertised
|= IXGBE_LINK_SPEED_10GB_FULL
;
637 if (speed
& IXGBE_LINK_SPEED_1GB_FULL
)
638 hw
->phy
.autoneg_advertised
|= IXGBE_LINK_SPEED_1GB_FULL
;
644 * ixgbe_setup_mac_link_smartspeed - Set MAC link speed using SmartSpeed
645 * @hw: pointer to hardware structure
646 * @speed: new link speed
647 * @autoneg: true if autonegotiation enabled
648 * @autoneg_wait_to_complete: true when waiting for completion is needed
650 * Implements the Intel SmartSpeed algorithm.
652 static s32
ixgbe_setup_mac_link_smartspeed(struct ixgbe_hw
*hw
,
653 ixgbe_link_speed speed
, bool autoneg
,
654 bool autoneg_wait_to_complete
)
657 ixgbe_link_speed link_speed
= IXGBE_LINK_SPEED_UNKNOWN
;
659 bool link_up
= false;
660 u32 autoc_reg
= IXGBE_READ_REG(hw
, IXGBE_AUTOC
);
662 /* Set autoneg_advertised value based on input link speed */
663 hw
->phy
.autoneg_advertised
= 0;
665 if (speed
& IXGBE_LINK_SPEED_10GB_FULL
)
666 hw
->phy
.autoneg_advertised
|= IXGBE_LINK_SPEED_10GB_FULL
;
668 if (speed
& IXGBE_LINK_SPEED_1GB_FULL
)
669 hw
->phy
.autoneg_advertised
|= IXGBE_LINK_SPEED_1GB_FULL
;
671 if (speed
& IXGBE_LINK_SPEED_100_FULL
)
672 hw
->phy
.autoneg_advertised
|= IXGBE_LINK_SPEED_100_FULL
;
675 * Implement Intel SmartSpeed algorithm. SmartSpeed will reduce the
676 * autoneg advertisement if link is unable to be established at the
677 * highest negotiated rate. This can sometimes happen due to integrity
678 * issues with the physical media connection.
681 /* First, try to get link with full advertisement */
682 hw
->phy
.smart_speed_active
= false;
683 for (j
= 0; j
< IXGBE_SMARTSPEED_MAX_RETRIES
; j
++) {
684 status
= ixgbe_setup_mac_link_82599(hw
, speed
, autoneg
,
685 autoneg_wait_to_complete
);
690 * Wait for the controller to acquire link. Per IEEE 802.3ap,
691 * Section 73.10.2, we may have to wait up to 500ms if KR is
692 * attempted, or 200ms if KX/KX4/BX/BX4 is attempted, per
693 * Table 9 in the AN MAS.
695 for (i
= 0; i
< 5; i
++) {
698 /* If we have link, just jump out */
699 status
= hw
->mac
.ops
.check_link(hw
, &link_speed
,
710 * We didn't get link. If we advertised KR plus one of KX4/KX
711 * (or BX4/BX), then disable KR and try again.
713 if (((autoc_reg
& IXGBE_AUTOC_KR_SUPP
) == 0) ||
714 ((autoc_reg
& IXGBE_AUTOC_KX4_KX_SUPP_MASK
) == 0))
717 /* Turn SmartSpeed on to disable KR support */
718 hw
->phy
.smart_speed_active
= true;
719 status
= ixgbe_setup_mac_link_82599(hw
, speed
, autoneg
,
720 autoneg_wait_to_complete
);
725 * Wait for the controller to acquire link. 600ms will allow for
726 * the AN link_fail_inhibit_timer as well for multiple cycles of
727 * parallel detect, both 10g and 1g. This allows for the maximum
728 * connect attempts as defined in the AN MAS table 73-7.
730 for (i
= 0; i
< 6; i
++) {
733 /* If we have link, just jump out */
734 status
= hw
->mac
.ops
.check_link(hw
, &link_speed
,
743 /* We didn't get link. Turn SmartSpeed back off. */
744 hw
->phy
.smart_speed_active
= false;
745 status
= ixgbe_setup_mac_link_82599(hw
, speed
, autoneg
,
746 autoneg_wait_to_complete
);
749 if (link_up
&& (link_speed
== IXGBE_LINK_SPEED_1GB_FULL
))
750 hw_dbg(hw
, "Smartspeed has downgraded the link speed from "
751 "the maximum advertised\n");
756 * ixgbe_setup_mac_link_82599 - Set MAC link speed
757 * @hw: pointer to hardware structure
758 * @speed: new link speed
759 * @autoneg: true if autonegotiation enabled
760 * @autoneg_wait_to_complete: true when waiting for completion is needed
762 * Set the link speed in the AUTOC register and restarts link.
764 static s32
ixgbe_setup_mac_link_82599(struct ixgbe_hw
*hw
,
765 ixgbe_link_speed speed
, bool autoneg
,
766 bool autoneg_wait_to_complete
)
769 u32 autoc
= IXGBE_READ_REG(hw
, IXGBE_AUTOC
);
770 u32 autoc2
= IXGBE_READ_REG(hw
, IXGBE_AUTOC2
);
771 u32 start_autoc
= autoc
;
773 u32 link_mode
= autoc
& IXGBE_AUTOC_LMS_MASK
;
774 u32 pma_pmd_1g
= autoc
& IXGBE_AUTOC_1G_PMA_PMD_MASK
;
775 u32 pma_pmd_10g_serial
= autoc2
& IXGBE_AUTOC2_10G_SERIAL_PMA_PMD_MASK
;
778 ixgbe_link_speed link_capabilities
= IXGBE_LINK_SPEED_UNKNOWN
;
780 /* Check to see if speed passed in is supported. */
781 hw
->mac
.ops
.get_link_capabilities(hw
, &link_capabilities
, &autoneg
);
785 speed
&= link_capabilities
;
787 if (speed
== IXGBE_LINK_SPEED_UNKNOWN
) {
788 status
= IXGBE_ERR_LINK_SETUP
;
792 /* Use stored value (EEPROM defaults) of AUTOC to find KR/KX4 support*/
793 if (hw
->mac
.orig_link_settings_stored
)
794 orig_autoc
= hw
->mac
.orig_autoc
;
798 if (link_mode
== IXGBE_AUTOC_LMS_KX4_KX_KR
||
799 link_mode
== IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN
||
800 link_mode
== IXGBE_AUTOC_LMS_KX4_KX_KR_SGMII
) {
801 /* Set KX4/KX/KR support according to speed requested */
802 autoc
&= ~(IXGBE_AUTOC_KX4_KX_SUPP_MASK
| IXGBE_AUTOC_KR_SUPP
);
803 if (speed
& IXGBE_LINK_SPEED_10GB_FULL
)
804 if (orig_autoc
& IXGBE_AUTOC_KX4_SUPP
)
805 autoc
|= IXGBE_AUTOC_KX4_SUPP
;
806 if ((orig_autoc
& IXGBE_AUTOC_KR_SUPP
) &&
807 (hw
->phy
.smart_speed_active
== false))
808 autoc
|= IXGBE_AUTOC_KR_SUPP
;
809 if (speed
& IXGBE_LINK_SPEED_1GB_FULL
)
810 autoc
|= IXGBE_AUTOC_KX_SUPP
;
811 } else if ((pma_pmd_1g
== IXGBE_AUTOC_1G_SFI
) &&
812 (link_mode
== IXGBE_AUTOC_LMS_1G_LINK_NO_AN
||
813 link_mode
== IXGBE_AUTOC_LMS_1G_AN
)) {
814 /* Switch from 1G SFI to 10G SFI if requested */
815 if ((speed
== IXGBE_LINK_SPEED_10GB_FULL
) &&
816 (pma_pmd_10g_serial
== IXGBE_AUTOC2_10G_SFI
)) {
817 autoc
&= ~IXGBE_AUTOC_LMS_MASK
;
818 autoc
|= IXGBE_AUTOC_LMS_10G_SERIAL
;
820 } else if ((pma_pmd_10g_serial
== IXGBE_AUTOC2_10G_SFI
) &&
821 (link_mode
== IXGBE_AUTOC_LMS_10G_SERIAL
)) {
822 /* Switch from 10G SFI to 1G SFI if requested */
823 if ((speed
== IXGBE_LINK_SPEED_1GB_FULL
) &&
824 (pma_pmd_1g
== IXGBE_AUTOC_1G_SFI
)) {
825 autoc
&= ~IXGBE_AUTOC_LMS_MASK
;
827 autoc
|= IXGBE_AUTOC_LMS_1G_AN
;
829 autoc
|= IXGBE_AUTOC_LMS_1G_LINK_NO_AN
;
833 if (autoc
!= start_autoc
) {
835 autoc
|= IXGBE_AUTOC_AN_RESTART
;
836 IXGBE_WRITE_REG(hw
, IXGBE_AUTOC
, autoc
);
838 /* Only poll for autoneg to complete if specified to do so */
839 if (autoneg_wait_to_complete
) {
840 if (link_mode
== IXGBE_AUTOC_LMS_KX4_KX_KR
||
841 link_mode
== IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN
||
842 link_mode
== IXGBE_AUTOC_LMS_KX4_KX_KR_SGMII
) {
843 links_reg
= 0; /*Just in case Autoneg time=0*/
844 for (i
= 0; i
< IXGBE_AUTO_NEG_TIME
; i
++) {
846 IXGBE_READ_REG(hw
, IXGBE_LINKS
);
847 if (links_reg
& IXGBE_LINKS_KX_AN_COMP
)
851 if (!(links_reg
& IXGBE_LINKS_KX_AN_COMP
)) {
853 IXGBE_ERR_AUTONEG_NOT_COMPLETE
;
854 hw_dbg(hw
, "Autoneg did not "
860 /* Add delay to filter out noises during initial link setup */
869 * ixgbe_setup_copper_link_82599 - Set the PHY autoneg advertised field
870 * @hw: pointer to hardware structure
871 * @speed: new link speed
872 * @autoneg: true if autonegotiation enabled
873 * @autoneg_wait_to_complete: true if waiting is needed to complete
875 * Restarts link on PHY and MAC based on settings passed in.
877 static s32
ixgbe_setup_copper_link_82599(struct ixgbe_hw
*hw
,
878 ixgbe_link_speed speed
,
880 bool autoneg_wait_to_complete
)
884 /* Setup the PHY according to input speed */
885 status
= hw
->phy
.ops
.setup_link_speed(hw
, speed
, autoneg
,
886 autoneg_wait_to_complete
);
888 ixgbe_start_mac_link_82599(hw
, autoneg_wait_to_complete
);
894 * ixgbe_reset_hw_82599 - Perform hardware reset
895 * @hw: pointer to hardware structure
897 * Resets the hardware by resetting the transmit and receive units, masks
898 * and clears all interrupts, perform a PHY reset, and perform a link (MAC)
901 static s32
ixgbe_reset_hw_82599(struct ixgbe_hw
*hw
)
909 /* Call adapter stop to disable tx/rx and clear interrupts */
910 hw
->mac
.ops
.stop_adapter(hw
);
912 /* PHY ops must be identified and initialized prior to reset */
914 /* Identify PHY and related function pointers */
915 status
= hw
->phy
.ops
.init(hw
);
917 if (status
== IXGBE_ERR_SFP_NOT_SUPPORTED
)
920 /* Setup SFP module if there is one present. */
921 if (hw
->phy
.sfp_setup_needed
) {
922 status
= hw
->mac
.ops
.setup_sfp(hw
);
923 hw
->phy
.sfp_setup_needed
= false;
926 if (status
== IXGBE_ERR_SFP_NOT_SUPPORTED
)
930 if (hw
->phy
.reset_disable
== false && hw
->phy
.ops
.reset
!= NULL
)
931 hw
->phy
.ops
.reset(hw
);
934 * Prevent the PCI-E bus from from hanging by disabling PCI-E master
935 * access and verify no pending requests before reset
937 ixgbe_disable_pcie_master(hw
);
941 * Issue global reset to the MAC. This needs to be a SW reset.
942 * If link reset is used, it might reset the MAC when mng is using it
944 ctrl
= IXGBE_READ_REG(hw
, IXGBE_CTRL
);
945 IXGBE_WRITE_REG(hw
, IXGBE_CTRL
, (ctrl
| IXGBE_CTRL_RST
));
946 IXGBE_WRITE_FLUSH(hw
);
948 /* Poll for reset bit to self-clear indicating reset is complete */
949 for (i
= 0; i
< 10; i
++) {
951 ctrl
= IXGBE_READ_REG(hw
, IXGBE_CTRL
);
952 if (!(ctrl
& IXGBE_CTRL_RST
))
955 if (ctrl
& IXGBE_CTRL_RST
) {
956 status
= IXGBE_ERR_RESET_FAILED
;
957 hw_dbg(hw
, "Reset polling failed to complete.\n");
961 * Double resets are required for recovery from certain error
962 * conditions. Between resets, it is necessary to stall to allow time
963 * for any pending HW events to complete. We use 1usec since that is
964 * what is needed for ixgbe_disable_pcie_master(). The second reset
965 * then clears out any effects of those events.
967 if (hw
->mac
.flags
& IXGBE_FLAGS_DOUBLE_RESET_REQUIRED
) {
968 hw
->mac
.flags
&= ~IXGBE_FLAGS_DOUBLE_RESET_REQUIRED
;
976 * Store the original AUTOC/AUTOC2 values if they have not been
977 * stored off yet. Otherwise restore the stored original
978 * values since the reset operation sets back to defaults.
980 autoc
= IXGBE_READ_REG(hw
, IXGBE_AUTOC
);
981 autoc2
= IXGBE_READ_REG(hw
, IXGBE_AUTOC2
);
982 if (hw
->mac
.orig_link_settings_stored
== false) {
983 hw
->mac
.orig_autoc
= autoc
;
984 hw
->mac
.orig_autoc2
= autoc2
;
985 hw
->mac
.orig_link_settings_stored
= true;
987 if (autoc
!= hw
->mac
.orig_autoc
)
988 IXGBE_WRITE_REG(hw
, IXGBE_AUTOC
, (hw
->mac
.orig_autoc
|
989 IXGBE_AUTOC_AN_RESTART
));
991 if ((autoc2
& IXGBE_AUTOC2_UPPER_MASK
) !=
992 (hw
->mac
.orig_autoc2
& IXGBE_AUTOC2_UPPER_MASK
)) {
993 autoc2
&= ~IXGBE_AUTOC2_UPPER_MASK
;
994 autoc2
|= (hw
->mac
.orig_autoc2
&
995 IXGBE_AUTOC2_UPPER_MASK
);
996 IXGBE_WRITE_REG(hw
, IXGBE_AUTOC2
, autoc2
);
1000 /* Store the permanent mac address */
1001 hw
->mac
.ops
.get_mac_addr(hw
, hw
->mac
.perm_addr
);
1004 * Store MAC address from RAR0, clear receive address registers, and
1005 * clear the multicast table. Also reset num_rar_entries to 128,
1006 * since we modify this value when programming the SAN MAC address.
1008 hw
->mac
.num_rar_entries
= 128;
1009 hw
->mac
.ops
.init_rx_addrs(hw
);
1011 /* Store the permanent SAN mac address */
1012 hw
->mac
.ops
.get_san_mac_addr(hw
, hw
->mac
.san_addr
);
1014 /* Add the SAN MAC address to the RAR only if it's a valid address */
1015 if (ixgbe_validate_mac_addr(hw
->mac
.san_addr
) == 0) {
1016 hw
->mac
.ops
.set_rar(hw
, hw
->mac
.num_rar_entries
- 1,
1017 hw
->mac
.san_addr
, 0, IXGBE_RAH_AV
);
1019 /* Reserve the last RAR for the SAN MAC address */
1020 hw
->mac
.num_rar_entries
--;
1023 /* Store the alternative WWNN/WWPN prefix */
1024 hw
->mac
.ops
.get_wwn_prefix(hw
, &hw
->mac
.wwnn_prefix
,
1025 &hw
->mac
.wwpn_prefix
);
1032 * ixgbe_reinit_fdir_tables_82599 - Reinitialize Flow Director tables.
1033 * @hw: pointer to hardware structure
1035 s32
ixgbe_reinit_fdir_tables_82599(struct ixgbe_hw
*hw
)
1038 u32 fdirctrl
= IXGBE_READ_REG(hw
, IXGBE_FDIRCTRL
);
1039 fdirctrl
&= ~IXGBE_FDIRCTRL_INIT_DONE
;
1042 * Before starting reinitialization process,
1043 * FDIRCMD.CMD must be zero.
1045 for (i
= 0; i
< IXGBE_FDIRCMD_CMD_POLL
; i
++) {
1046 if (!(IXGBE_READ_REG(hw
, IXGBE_FDIRCMD
) &
1047 IXGBE_FDIRCMD_CMD_MASK
))
1051 if (i
>= IXGBE_FDIRCMD_CMD_POLL
) {
1052 hw_dbg(hw
, "Flow Director previous command isn't complete, "
1053 "aborting table re-initialization.\n");
1054 return IXGBE_ERR_FDIR_REINIT_FAILED
;
1057 IXGBE_WRITE_REG(hw
, IXGBE_FDIRFREE
, 0);
1058 IXGBE_WRITE_FLUSH(hw
);
1060 * 82599 adapters flow director init flow cannot be restarted,
1061 * Workaround 82599 silicon errata by performing the following steps
1062 * before re-writing the FDIRCTRL control register with the same value.
1063 * - write 1 to bit 8 of FDIRCMD register &
1064 * - write 0 to bit 8 of FDIRCMD register
1066 IXGBE_WRITE_REG(hw
, IXGBE_FDIRCMD
,
1067 (IXGBE_READ_REG(hw
, IXGBE_FDIRCMD
) |
1068 IXGBE_FDIRCMD_CLEARHT
));
1069 IXGBE_WRITE_FLUSH(hw
);
1070 IXGBE_WRITE_REG(hw
, IXGBE_FDIRCMD
,
1071 (IXGBE_READ_REG(hw
, IXGBE_FDIRCMD
) &
1072 ~IXGBE_FDIRCMD_CLEARHT
));
1073 IXGBE_WRITE_FLUSH(hw
);
1075 * Clear FDIR Hash register to clear any leftover hashes
1076 * waiting to be programmed.
1078 IXGBE_WRITE_REG(hw
, IXGBE_FDIRHASH
, 0x00);
1079 IXGBE_WRITE_FLUSH(hw
);
1081 IXGBE_WRITE_REG(hw
, IXGBE_FDIRCTRL
, fdirctrl
);
1082 IXGBE_WRITE_FLUSH(hw
);
1084 /* Poll init-done after we write FDIRCTRL register */
1085 for (i
= 0; i
< IXGBE_FDIR_INIT_DONE_POLL
; i
++) {
1086 if (IXGBE_READ_REG(hw
, IXGBE_FDIRCTRL
) &
1087 IXGBE_FDIRCTRL_INIT_DONE
)
1091 if (i
>= IXGBE_FDIR_INIT_DONE_POLL
) {
1092 hw_dbg(hw
, "Flow Director Signature poll time exceeded!\n");
1093 return IXGBE_ERR_FDIR_REINIT_FAILED
;
1096 /* Clear FDIR statistics registers (read to clear) */
1097 IXGBE_READ_REG(hw
, IXGBE_FDIRUSTAT
);
1098 IXGBE_READ_REG(hw
, IXGBE_FDIRFSTAT
);
1099 IXGBE_READ_REG(hw
, IXGBE_FDIRMATCH
);
1100 IXGBE_READ_REG(hw
, IXGBE_FDIRMISS
);
1101 IXGBE_READ_REG(hw
, IXGBE_FDIRLEN
);
1107 * ixgbe_init_fdir_signature_82599 - Initialize Flow Director signature filters
1108 * @hw: pointer to hardware structure
1109 * @pballoc: which mode to allocate filters with
1111 s32
ixgbe_init_fdir_signature_82599(struct ixgbe_hw
*hw
, u32 pballoc
)
1118 * Before enabling Flow Director, the Rx Packet Buffer size
1119 * must be reduced. The new value is the current size minus
1120 * flow director memory usage size.
1122 pbsize
= (1 << (IXGBE_FDIR_PBALLOC_SIZE_SHIFT
+ pballoc
));
1123 IXGBE_WRITE_REG(hw
, IXGBE_RXPBSIZE(0),
1124 (IXGBE_READ_REG(hw
, IXGBE_RXPBSIZE(0)) - pbsize
));
1127 * The defaults in the HW for RX PB 1-7 are not zero and so should be
1128 * initialized to zero for non DCB mode otherwise actual total RX PB
1129 * would be bigger than programmed and filter space would run into
1132 for (i
= 1; i
< 8; i
++)
1133 IXGBE_WRITE_REG(hw
, IXGBE_RXPBSIZE(i
), 0);
1135 /* Send interrupt when 64 filters are left */
1136 fdirctrl
|= 4 << IXGBE_FDIRCTRL_FULL_THRESH_SHIFT
;
1138 /* Set the maximum length per hash bucket to 0xA filters */
1139 fdirctrl
|= 0xA << IXGBE_FDIRCTRL_MAX_LENGTH_SHIFT
;
1142 case IXGBE_FDIR_PBALLOC_64K
:
1143 /* 8k - 1 signature filters */
1144 fdirctrl
|= IXGBE_FDIRCTRL_PBALLOC_64K
;
1146 case IXGBE_FDIR_PBALLOC_128K
:
1147 /* 16k - 1 signature filters */
1148 fdirctrl
|= IXGBE_FDIRCTRL_PBALLOC_128K
;
1150 case IXGBE_FDIR_PBALLOC_256K
:
1151 /* 32k - 1 signature filters */
1152 fdirctrl
|= IXGBE_FDIRCTRL_PBALLOC_256K
;
1156 return IXGBE_ERR_CONFIG
;
1159 /* Move the flexible bytes to use the ethertype - shift 6 words */
1160 fdirctrl
|= (0x6 << IXGBE_FDIRCTRL_FLEX_SHIFT
);
1163 /* Prime the keys for hashing */
1164 IXGBE_WRITE_REG(hw
, IXGBE_FDIRHKEY
, IXGBE_ATR_BUCKET_HASH_KEY
);
1165 IXGBE_WRITE_REG(hw
, IXGBE_FDIRSKEY
, IXGBE_ATR_SIGNATURE_HASH_KEY
);
1168 * Poll init-done after we write the register. Estimated times:
1169 * 10G: PBALLOC = 11b, timing is 60us
1170 * 1G: PBALLOC = 11b, timing is 600us
1171 * 100M: PBALLOC = 11b, timing is 6ms
1173 * Multiple these timings by 4 if under full Rx load
1175 * So we'll poll for IXGBE_FDIR_INIT_DONE_POLL times, sleeping for
1176 * 1 msec per poll time. If we're at line rate and drop to 100M, then
1177 * this might not finish in our poll time, but we can live with that
1180 IXGBE_WRITE_REG(hw
, IXGBE_FDIRCTRL
, fdirctrl
);
1181 IXGBE_WRITE_FLUSH(hw
);
1182 for (i
= 0; i
< IXGBE_FDIR_INIT_DONE_POLL
; i
++) {
1183 if (IXGBE_READ_REG(hw
, IXGBE_FDIRCTRL
) &
1184 IXGBE_FDIRCTRL_INIT_DONE
)
1186 usleep_range(1000, 2000);
1188 if (i
>= IXGBE_FDIR_INIT_DONE_POLL
)
1189 hw_dbg(hw
, "Flow Director Signature poll time exceeded!\n");
1195 * ixgbe_init_fdir_perfect_82599 - Initialize Flow Director perfect filters
1196 * @hw: pointer to hardware structure
1197 * @pballoc: which mode to allocate filters with
1199 s32
ixgbe_init_fdir_perfect_82599(struct ixgbe_hw
*hw
, u32 pballoc
)
1206 * Before enabling Flow Director, the Rx Packet Buffer size
1207 * must be reduced. The new value is the current size minus
1208 * flow director memory usage size.
1210 pbsize
= (1 << (IXGBE_FDIR_PBALLOC_SIZE_SHIFT
+ pballoc
));
1211 IXGBE_WRITE_REG(hw
, IXGBE_RXPBSIZE(0),
1212 (IXGBE_READ_REG(hw
, IXGBE_RXPBSIZE(0)) - pbsize
));
1215 * The defaults in the HW for RX PB 1-7 are not zero and so should be
1216 * initialized to zero for non DCB mode otherwise actual total RX PB
1217 * would be bigger than programmed and filter space would run into
1220 for (i
= 1; i
< 8; i
++)
1221 IXGBE_WRITE_REG(hw
, IXGBE_RXPBSIZE(i
), 0);
1223 /* Send interrupt when 64 filters are left */
1224 fdirctrl
|= 4 << IXGBE_FDIRCTRL_FULL_THRESH_SHIFT
;
1226 /* Initialize the drop queue to Rx queue 127 */
1227 fdirctrl
|= (127 << IXGBE_FDIRCTRL_DROP_Q_SHIFT
);
1230 case IXGBE_FDIR_PBALLOC_64K
:
1231 /* 2k - 1 perfect filters */
1232 fdirctrl
|= IXGBE_FDIRCTRL_PBALLOC_64K
;
1234 case IXGBE_FDIR_PBALLOC_128K
:
1235 /* 4k - 1 perfect filters */
1236 fdirctrl
|= IXGBE_FDIRCTRL_PBALLOC_128K
;
1238 case IXGBE_FDIR_PBALLOC_256K
:
1239 /* 8k - 1 perfect filters */
1240 fdirctrl
|= IXGBE_FDIRCTRL_PBALLOC_256K
;
1244 return IXGBE_ERR_CONFIG
;
1247 /* Turn perfect match filtering on */
1248 fdirctrl
|= IXGBE_FDIRCTRL_PERFECT_MATCH
;
1249 fdirctrl
|= IXGBE_FDIRCTRL_REPORT_STATUS
;
1251 /* Move the flexible bytes to use the ethertype - shift 6 words */
1252 fdirctrl
|= (0x6 << IXGBE_FDIRCTRL_FLEX_SHIFT
);
1254 /* Prime the keys for hashing */
1255 IXGBE_WRITE_REG(hw
, IXGBE_FDIRHKEY
, IXGBE_ATR_BUCKET_HASH_KEY
);
1256 IXGBE_WRITE_REG(hw
, IXGBE_FDIRSKEY
, IXGBE_ATR_SIGNATURE_HASH_KEY
);
1259 * Poll init-done after we write the register. Estimated times:
1260 * 10G: PBALLOC = 11b, timing is 60us
1261 * 1G: PBALLOC = 11b, timing is 600us
1262 * 100M: PBALLOC = 11b, timing is 6ms
1264 * Multiple these timings by 4 if under full Rx load
1266 * So we'll poll for IXGBE_FDIR_INIT_DONE_POLL times, sleeping for
1267 * 1 msec per poll time. If we're at line rate and drop to 100M, then
1268 * this might not finish in our poll time, but we can live with that
1272 /* Set the maximum length per hash bucket to 0xA filters */
1273 fdirctrl
|= (0xA << IXGBE_FDIRCTRL_MAX_LENGTH_SHIFT
);
1275 IXGBE_WRITE_REG(hw
, IXGBE_FDIRCTRL
, fdirctrl
);
1276 IXGBE_WRITE_FLUSH(hw
);
1277 for (i
= 0; i
< IXGBE_FDIR_INIT_DONE_POLL
; i
++) {
1278 if (IXGBE_READ_REG(hw
, IXGBE_FDIRCTRL
) &
1279 IXGBE_FDIRCTRL_INIT_DONE
)
1281 usleep_range(1000, 2000);
1283 if (i
>= IXGBE_FDIR_INIT_DONE_POLL
)
1284 hw_dbg(hw
, "Flow Director Perfect poll time exceeded!\n");
1291 * ixgbe_atr_compute_hash_82599 - Compute the hashes for SW ATR
1292 * @stream: input bitstream to compute the hash on
1293 * @key: 32-bit hash key
1295 static u32
ixgbe_atr_compute_hash_82599(union ixgbe_atr_input
*atr_input
,
1299 * The algorithm is as follows:
1300 * Hash[15:0] = Sum { S[n] x K[n+16] }, n = 0...350
1301 * where Sum {A[n]}, n = 0...n is bitwise XOR of A[0], A[1]...A[n]
1302 * and A[n] x B[n] is bitwise AND between same length strings
1304 * K[n] is 16 bits, defined as:
1305 * for n modulo 32 >= 15, K[n] = K[n % 32 : (n % 32) - 15]
1306 * for n modulo 32 < 15, K[n] =
1307 * K[(n % 32:0) | (31:31 - (14 - (n % 32)))]
1309 * S[n] is 16 bits, defined as:
1310 * for n >= 15, S[n] = S[n:n - 15]
1311 * for n < 15, S[n] = S[(n:0) | (350:350 - (14 - n))]
1313 * To simplify for programming, the algorithm is implemented
1314 * in software this way:
1316 * key[31:0], hi_hash_dword[31:0], lo_hash_dword[31:0], hash[15:0]
1318 * for (i = 0; i < 352; i+=32)
1319 * hi_hash_dword[31:0] ^= Stream[(i+31):i];
1321 * lo_hash_dword[15:0] ^= Stream[15:0];
1322 * lo_hash_dword[15:0] ^= hi_hash_dword[31:16];
1323 * lo_hash_dword[31:16] ^= hi_hash_dword[15:0];
1325 * hi_hash_dword[31:0] ^= Stream[351:320];
1328 * hash[15:0] ^= Stream[15:0];
1330 * for (i = 0; i < 16; i++) {
1332 * hash[15:0] ^= lo_hash_dword[(i+15):i];
1334 * hash[15:0] ^= hi_hash_dword[(i+15):i];
1338 __be32 common_hash_dword
= 0;
1339 u32 hi_hash_dword
, lo_hash_dword
, flow_vm_vlan
;
1340 u32 hash_result
= 0;
1343 /* record the flow_vm_vlan bits as they are a key part to the hash */
1344 flow_vm_vlan
= ntohl(atr_input
->dword_stream
[0]);
1346 /* generate common hash dword */
1347 for (i
= 10; i
; i
-= 2)
1348 common_hash_dword
^= atr_input
->dword_stream
[i
] ^
1349 atr_input
->dword_stream
[i
- 1];
1351 hi_hash_dword
= ntohl(common_hash_dword
);
1353 /* low dword is word swapped version of common */
1354 lo_hash_dword
= (hi_hash_dword
>> 16) | (hi_hash_dword
<< 16);
1356 /* apply flow ID/VM pool/VLAN ID bits to hash words */
1357 hi_hash_dword
^= flow_vm_vlan
^ (flow_vm_vlan
>> 16);
1359 /* Process bits 0 and 16 */
1360 if (key
& 0x0001) hash_result
^= lo_hash_dword
;
1361 if (key
& 0x00010000) hash_result
^= hi_hash_dword
;
1364 * apply flow ID/VM pool/VLAN ID bits to lo hash dword, we had to
1365 * delay this because bit 0 of the stream should not be processed
1366 * so we do not add the vlan until after bit 0 was processed
1368 lo_hash_dword
^= flow_vm_vlan
^ (flow_vm_vlan
<< 16);
1371 /* process the remaining 30 bits in the key 2 bits at a time */
1372 for (i
= 15; i
; i
-- ) {
1373 if (key
& (0x0001 << i
)) hash_result
^= lo_hash_dword
>> i
;
1374 if (key
& (0x00010000 << i
)) hash_result
^= hi_hash_dword
>> i
;
1377 return hash_result
& IXGBE_ATR_HASH_MASK
;
1381 * These defines allow us to quickly generate all of the necessary instructions
1382 * in the function below by simply calling out IXGBE_COMPUTE_SIG_HASH_ITERATION
1383 * for values 0 through 15
1385 #define IXGBE_ATR_COMMON_HASH_KEY \
1386 (IXGBE_ATR_BUCKET_HASH_KEY & IXGBE_ATR_SIGNATURE_HASH_KEY)
1387 #define IXGBE_COMPUTE_SIG_HASH_ITERATION(_n) \
1390 if (IXGBE_ATR_COMMON_HASH_KEY & (0x01 << n)) \
1391 common_hash ^= lo_hash_dword >> n; \
1392 else if (IXGBE_ATR_BUCKET_HASH_KEY & (0x01 << n)) \
1393 bucket_hash ^= lo_hash_dword >> n; \
1394 else if (IXGBE_ATR_SIGNATURE_HASH_KEY & (0x01 << n)) \
1395 sig_hash ^= lo_hash_dword << (16 - n); \
1396 if (IXGBE_ATR_COMMON_HASH_KEY & (0x01 << (n + 16))) \
1397 common_hash ^= hi_hash_dword >> n; \
1398 else if (IXGBE_ATR_BUCKET_HASH_KEY & (0x01 << (n + 16))) \
1399 bucket_hash ^= hi_hash_dword >> n; \
1400 else if (IXGBE_ATR_SIGNATURE_HASH_KEY & (0x01 << (n + 16))) \
1401 sig_hash ^= hi_hash_dword << (16 - n); \
1405 * ixgbe_atr_compute_sig_hash_82599 - Compute the signature hash
1406 * @stream: input bitstream to compute the hash on
1408 * This function is almost identical to the function above but contains
1409 * several optomizations such as unwinding all of the loops, letting the
1410 * compiler work out all of the conditional ifs since the keys are static
1411 * defines, and computing two keys at once since the hashed dword stream
1412 * will be the same for both keys.
1414 static u32
ixgbe_atr_compute_sig_hash_82599(union ixgbe_atr_hash_dword input
,
1415 union ixgbe_atr_hash_dword common
)
1417 u32 hi_hash_dword
, lo_hash_dword
, flow_vm_vlan
;
1418 u32 sig_hash
= 0, bucket_hash
= 0, common_hash
= 0;
1420 /* record the flow_vm_vlan bits as they are a key part to the hash */
1421 flow_vm_vlan
= ntohl(input
.dword
);
1423 /* generate common hash dword */
1424 hi_hash_dword
= ntohl(common
.dword
);
1426 /* low dword is word swapped version of common */
1427 lo_hash_dword
= (hi_hash_dword
>> 16) | (hi_hash_dword
<< 16);
1429 /* apply flow ID/VM pool/VLAN ID bits to hash words */
1430 hi_hash_dword
^= flow_vm_vlan
^ (flow_vm_vlan
>> 16);
1432 /* Process bits 0 and 16 */
1433 IXGBE_COMPUTE_SIG_HASH_ITERATION(0);
1436 * apply flow ID/VM pool/VLAN ID bits to lo hash dword, we had to
1437 * delay this because bit 0 of the stream should not be processed
1438 * so we do not add the vlan until after bit 0 was processed
1440 lo_hash_dword
^= flow_vm_vlan
^ (flow_vm_vlan
<< 16);
1442 /* Process remaining 30 bit of the key */
1443 IXGBE_COMPUTE_SIG_HASH_ITERATION(1);
1444 IXGBE_COMPUTE_SIG_HASH_ITERATION(2);
1445 IXGBE_COMPUTE_SIG_HASH_ITERATION(3);
1446 IXGBE_COMPUTE_SIG_HASH_ITERATION(4);
1447 IXGBE_COMPUTE_SIG_HASH_ITERATION(5);
1448 IXGBE_COMPUTE_SIG_HASH_ITERATION(6);
1449 IXGBE_COMPUTE_SIG_HASH_ITERATION(7);
1450 IXGBE_COMPUTE_SIG_HASH_ITERATION(8);
1451 IXGBE_COMPUTE_SIG_HASH_ITERATION(9);
1452 IXGBE_COMPUTE_SIG_HASH_ITERATION(10);
1453 IXGBE_COMPUTE_SIG_HASH_ITERATION(11);
1454 IXGBE_COMPUTE_SIG_HASH_ITERATION(12);
1455 IXGBE_COMPUTE_SIG_HASH_ITERATION(13);
1456 IXGBE_COMPUTE_SIG_HASH_ITERATION(14);
1457 IXGBE_COMPUTE_SIG_HASH_ITERATION(15);
1459 /* combine common_hash result with signature and bucket hashes */
1460 bucket_hash
^= common_hash
;
1461 bucket_hash
&= IXGBE_ATR_HASH_MASK
;
1463 sig_hash
^= common_hash
<< 16;
1464 sig_hash
&= IXGBE_ATR_HASH_MASK
<< 16;
1466 /* return completed signature hash */
1467 return sig_hash
^ bucket_hash
;
1471 * ixgbe_atr_add_signature_filter_82599 - Adds a signature hash filter
1472 * @hw: pointer to hardware structure
1473 * @input: unique input dword
1474 * @common: compressed common input dword
1475 * @queue: queue index to direct traffic to
1477 s32
ixgbe_fdir_add_signature_filter_82599(struct ixgbe_hw
*hw
,
1478 union ixgbe_atr_hash_dword input
,
1479 union ixgbe_atr_hash_dword common
,
1486 * Get the flow_type in order to program FDIRCMD properly
1487 * lowest 2 bits are FDIRCMD.L4TYPE, third lowest bit is FDIRCMD.IPV6
1489 switch (input
.formatted
.flow_type
) {
1490 case IXGBE_ATR_FLOW_TYPE_TCPV4
:
1491 case IXGBE_ATR_FLOW_TYPE_UDPV4
:
1492 case IXGBE_ATR_FLOW_TYPE_SCTPV4
:
1493 case IXGBE_ATR_FLOW_TYPE_TCPV6
:
1494 case IXGBE_ATR_FLOW_TYPE_UDPV6
:
1495 case IXGBE_ATR_FLOW_TYPE_SCTPV6
:
1498 hw_dbg(hw
, " Error on flow type input\n");
1499 return IXGBE_ERR_CONFIG
;
1502 /* configure FDIRCMD register */
1503 fdircmd
= IXGBE_FDIRCMD_CMD_ADD_FLOW
| IXGBE_FDIRCMD_FILTER_UPDATE
|
1504 IXGBE_FDIRCMD_LAST
| IXGBE_FDIRCMD_QUEUE_EN
;
1505 fdircmd
|= input
.formatted
.flow_type
<< IXGBE_FDIRCMD_FLOW_TYPE_SHIFT
;
1506 fdircmd
|= (u32
)queue
<< IXGBE_FDIRCMD_RX_QUEUE_SHIFT
;
1509 * The lower 32-bits of fdirhashcmd is for FDIRHASH, the upper 32-bits
1510 * is for FDIRCMD. Then do a 64-bit register write from FDIRHASH.
1512 fdirhashcmd
= (u64
)fdircmd
<< 32;
1513 fdirhashcmd
|= ixgbe_atr_compute_sig_hash_82599(input
, common
);
1515 IXGBE_WRITE_REG64(hw
, IXGBE_FDIRHASH
, fdirhashcmd
);
1517 hw_dbg(hw
, "Tx Queue=%x hash=%x\n", queue
, (u32
)fdirhashcmd
);
1523 * ixgbe_get_fdirtcpm_82599 - generate a tcp port from atr_input_masks
1524 * @input_mask: mask to be bit swapped
1526 * The source and destination port masks for flow director are bit swapped
1527 * in that bit 15 effects bit 0, 14 effects 1, 13, 2 etc. In order to
1528 * generate a correctly swapped value we need to bit swap the mask and that
1529 * is what is accomplished by this function.
1531 static u32
ixgbe_get_fdirtcpm_82599(struct ixgbe_atr_input_masks
*input_masks
)
1533 u32 mask
= ntohs(input_masks
->dst_port_mask
);
1534 mask
<<= IXGBE_FDIRTCPM_DPORTM_SHIFT
;
1535 mask
|= ntohs(input_masks
->src_port_mask
);
1536 mask
= ((mask
& 0x55555555) << 1) | ((mask
& 0xAAAAAAAA) >> 1);
1537 mask
= ((mask
& 0x33333333) << 2) | ((mask
& 0xCCCCCCCC) >> 2);
1538 mask
= ((mask
& 0x0F0F0F0F) << 4) | ((mask
& 0xF0F0F0F0) >> 4);
1539 return ((mask
& 0x00FF00FF) << 8) | ((mask
& 0xFF00FF00) >> 8);
1543 * These two macros are meant to address the fact that we have registers
1544 * that are either all or in part big-endian. As a result on big-endian
1545 * systems we will end up byte swapping the value to little-endian before
1546 * it is byte swapped again and written to the hardware in the original
1547 * big-endian format.
1549 #define IXGBE_STORE_AS_BE32(_value) \
1550 (((u32)(_value) >> 24) | (((u32)(_value) & 0x00FF0000) >> 8) | \
1551 (((u32)(_value) & 0x0000FF00) << 8) | ((u32)(_value) << 24))
1553 #define IXGBE_WRITE_REG_BE32(a, reg, value) \
1554 IXGBE_WRITE_REG((a), (reg), IXGBE_STORE_AS_BE32(ntohl(value)))
1556 #define IXGBE_STORE_AS_BE16(_value) \
1557 (((u16)(_value) >> 8) | ((u16)(_value) << 8))
1560 * ixgbe_fdir_add_perfect_filter_82599 - Adds a perfect filter
1561 * @hw: pointer to hardware structure
1562 * @input: input bitstream
1563 * @input_masks: bitwise masks for relevant fields
1564 * @soft_id: software index into the silicon hash tables for filter storage
1565 * @queue: queue index to direct traffic to
1567 * Note that the caller to this function must lock before calling, since the
1568 * hardware writes must be protected from one another.
1570 s32
ixgbe_fdir_add_perfect_filter_82599(struct ixgbe_hw
*hw
,
1571 union ixgbe_atr_input
*input
,
1572 struct ixgbe_atr_input_masks
*input_masks
,
1573 u16 soft_id
, u8 queue
)
1577 u32 fdirport
, fdirtcpm
;
1579 /* start with VLAN, flex bytes, VM pool, and IPv6 destination masked */
1580 u32 fdirm
= IXGBE_FDIRM_VLANID
| IXGBE_FDIRM_VLANP
| IXGBE_FDIRM_FLEX
|
1581 IXGBE_FDIRM_POOL
| IXGBE_FDIRM_DIPv6
;
1584 * Check flow_type formatting, and bail out before we touch the hardware
1585 * if there's a configuration issue
1587 switch (input
->formatted
.flow_type
) {
1588 case IXGBE_ATR_FLOW_TYPE_IPV4
:
1589 /* use the L4 protocol mask for raw IPv4/IPv6 traffic */
1590 fdirm
|= IXGBE_FDIRM_L4P
;
1591 case IXGBE_ATR_FLOW_TYPE_SCTPV4
:
1592 if (input_masks
->dst_port_mask
|| input_masks
->src_port_mask
) {
1593 hw_dbg(hw
, " Error on src/dst port mask\n");
1594 return IXGBE_ERR_CONFIG
;
1596 case IXGBE_ATR_FLOW_TYPE_TCPV4
:
1597 case IXGBE_ATR_FLOW_TYPE_UDPV4
:
1600 hw_dbg(hw
, " Error on flow type input\n");
1601 return IXGBE_ERR_CONFIG
;
1605 * Program the relevant mask registers. If src/dst_port or src/dst_addr
1606 * are zero, then assume a full mask for that field. Also assume that
1607 * a VLAN of 0 is unspecified, so mask that out as well. L4type
1608 * cannot be masked out in this implementation.
1610 * This also assumes IPv4 only. IPv6 masking isn't supported at this
1615 switch (ntohs(input_masks
->vlan_id_mask
) & 0xEFFF) {
1617 /* Unmask VLAN ID - bit 0 and fall through to unmask prio */
1618 fdirm
&= ~IXGBE_FDIRM_VLANID
;
1620 /* Unmask VLAN prio - bit 1 */
1621 fdirm
&= ~IXGBE_FDIRM_VLANP
;
1624 /* Unmask VLAN ID - bit 0 */
1625 fdirm
&= ~IXGBE_FDIRM_VLANID
;
1628 /* do nothing, vlans already masked */
1631 hw_dbg(hw
, " Error on VLAN mask\n");
1632 return IXGBE_ERR_CONFIG
;
1635 if (input_masks
->flex_mask
& 0xFFFF) {
1636 if ((input_masks
->flex_mask
& 0xFFFF) != 0xFFFF) {
1637 hw_dbg(hw
, " Error on flexible byte mask\n");
1638 return IXGBE_ERR_CONFIG
;
1640 /* Unmask Flex Bytes - bit 4 */
1641 fdirm
&= ~IXGBE_FDIRM_FLEX
;
1644 /* Now mask VM pool and destination IPv6 - bits 5 and 2 */
1645 IXGBE_WRITE_REG(hw
, IXGBE_FDIRM
, fdirm
);
1647 /* store the TCP/UDP port masks, bit reversed from port layout */
1648 fdirtcpm
= ixgbe_get_fdirtcpm_82599(input_masks
);
1650 /* write both the same so that UDP and TCP use the same mask */
1651 IXGBE_WRITE_REG(hw
, IXGBE_FDIRTCPM
, ~fdirtcpm
);
1652 IXGBE_WRITE_REG(hw
, IXGBE_FDIRUDPM
, ~fdirtcpm
);
1654 /* store source and destination IP masks (big-enian) */
1655 IXGBE_WRITE_REG_BE32(hw
, IXGBE_FDIRSIP4M
,
1656 ~input_masks
->src_ip_mask
[0]);
1657 IXGBE_WRITE_REG_BE32(hw
, IXGBE_FDIRDIP4M
,
1658 ~input_masks
->dst_ip_mask
[0]);
1660 /* Apply masks to input data */
1661 input
->formatted
.vlan_id
&= input_masks
->vlan_id_mask
;
1662 input
->formatted
.flex_bytes
&= input_masks
->flex_mask
;
1663 input
->formatted
.src_port
&= input_masks
->src_port_mask
;
1664 input
->formatted
.dst_port
&= input_masks
->dst_port_mask
;
1665 input
->formatted
.src_ip
[0] &= input_masks
->src_ip_mask
[0];
1666 input
->formatted
.dst_ip
[0] &= input_masks
->dst_ip_mask
[0];
1668 /* record vlan (little-endian) and flex_bytes(big-endian) */
1670 IXGBE_STORE_AS_BE16(ntohs(input
->formatted
.flex_bytes
));
1671 fdirvlan
<<= IXGBE_FDIRVLAN_FLEX_SHIFT
;
1672 fdirvlan
|= ntohs(input
->formatted
.vlan_id
);
1673 IXGBE_WRITE_REG(hw
, IXGBE_FDIRVLAN
, fdirvlan
);
1675 /* record source and destination port (little-endian)*/
1676 fdirport
= ntohs(input
->formatted
.dst_port
);
1677 fdirport
<<= IXGBE_FDIRPORT_DESTINATION_SHIFT
;
1678 fdirport
|= ntohs(input
->formatted
.src_port
);
1679 IXGBE_WRITE_REG(hw
, IXGBE_FDIRPORT
, fdirport
);
1681 /* record the first 32 bits of the destination address (big-endian) */
1682 IXGBE_WRITE_REG_BE32(hw
, IXGBE_FDIRIPDA
, input
->formatted
.dst_ip
[0]);
1684 /* record the source address (big-endian) */
1685 IXGBE_WRITE_REG_BE32(hw
, IXGBE_FDIRIPSA
, input
->formatted
.src_ip
[0]);
1687 /* configure FDIRCMD register */
1688 fdircmd
= IXGBE_FDIRCMD_CMD_ADD_FLOW
| IXGBE_FDIRCMD_FILTER_UPDATE
|
1689 IXGBE_FDIRCMD_LAST
| IXGBE_FDIRCMD_QUEUE_EN
;
1690 fdircmd
|= input
->formatted
.flow_type
<< IXGBE_FDIRCMD_FLOW_TYPE_SHIFT
;
1691 fdircmd
|= (u32
)queue
<< IXGBE_FDIRCMD_RX_QUEUE_SHIFT
;
1693 /* we only want the bucket hash so drop the upper 16 bits */
1694 fdirhash
= ixgbe_atr_compute_hash_82599(input
,
1695 IXGBE_ATR_BUCKET_HASH_KEY
);
1696 fdirhash
|= soft_id
<< IXGBE_FDIRHASH_SIG_SW_INDEX_SHIFT
;
1698 IXGBE_WRITE_REG(hw
, IXGBE_FDIRHASH
, fdirhash
);
1699 IXGBE_WRITE_REG(hw
, IXGBE_FDIRCMD
, fdircmd
);
1705 * ixgbe_read_analog_reg8_82599 - Reads 8 bit Omer analog register
1706 * @hw: pointer to hardware structure
1707 * @reg: analog register to read
1710 * Performs read operation to Omer analog register specified.
1712 static s32
ixgbe_read_analog_reg8_82599(struct ixgbe_hw
*hw
, u32 reg
, u8
*val
)
1716 IXGBE_WRITE_REG(hw
, IXGBE_CORECTL
, IXGBE_CORECTL_WRITE_CMD
|
1718 IXGBE_WRITE_FLUSH(hw
);
1720 core_ctl
= IXGBE_READ_REG(hw
, IXGBE_CORECTL
);
1721 *val
= (u8
)core_ctl
;
1727 * ixgbe_write_analog_reg8_82599 - Writes 8 bit Omer analog register
1728 * @hw: pointer to hardware structure
1729 * @reg: atlas register to write
1730 * @val: value to write
1732 * Performs write operation to Omer analog register specified.
1734 static s32
ixgbe_write_analog_reg8_82599(struct ixgbe_hw
*hw
, u32 reg
, u8 val
)
1738 core_ctl
= (reg
<< 8) | val
;
1739 IXGBE_WRITE_REG(hw
, IXGBE_CORECTL
, core_ctl
);
1740 IXGBE_WRITE_FLUSH(hw
);
1747 * ixgbe_start_hw_82599 - Prepare hardware for Tx/Rx
1748 * @hw: pointer to hardware structure
1750 * Starts the hardware using the generic start_hw function
1751 * and the generation start_hw function.
1752 * Then performs revision-specific operations, if any.
1754 static s32
ixgbe_start_hw_82599(struct ixgbe_hw
*hw
)
1758 ret_val
= ixgbe_start_hw_generic(hw
);
1762 ret_val
= ixgbe_start_hw_gen2(hw
);
1766 /* We need to run link autotry after the driver loads */
1767 hw
->mac
.autotry_restart
= true;
1770 ret_val
= ixgbe_verify_fw_version_82599(hw
);
1776 * ixgbe_identify_phy_82599 - Get physical layer module
1777 * @hw: pointer to hardware structure
1779 * Determines the physical layer module found on the current adapter.
1780 * If PHY already detected, maintains current PHY type in hw struct,
1781 * otherwise executes the PHY detection routine.
1783 static s32
ixgbe_identify_phy_82599(struct ixgbe_hw
*hw
)
1785 s32 status
= IXGBE_ERR_PHY_ADDR_INVALID
;
1787 /* Detect PHY if not unknown - returns success if already detected. */
1788 status
= ixgbe_identify_phy_generic(hw
);
1790 /* 82599 10GBASE-T requires an external PHY */
1791 if (hw
->mac
.ops
.get_media_type(hw
) == ixgbe_media_type_copper
)
1794 status
= ixgbe_identify_sfp_module_generic(hw
);
1797 /* Set PHY type none if no PHY detected */
1798 if (hw
->phy
.type
== ixgbe_phy_unknown
) {
1799 hw
->phy
.type
= ixgbe_phy_none
;
1803 /* Return error if SFP module has been detected but is not supported */
1804 if (hw
->phy
.type
== ixgbe_phy_sfp_unsupported
)
1805 status
= IXGBE_ERR_SFP_NOT_SUPPORTED
;
1812 * ixgbe_get_supported_physical_layer_82599 - Returns physical layer type
1813 * @hw: pointer to hardware structure
1815 * Determines physical layer capabilities of the current configuration.
1817 static u32
ixgbe_get_supported_physical_layer_82599(struct ixgbe_hw
*hw
)
1819 u32 physical_layer
= IXGBE_PHYSICAL_LAYER_UNKNOWN
;
1820 u32 autoc
= IXGBE_READ_REG(hw
, IXGBE_AUTOC
);
1821 u32 autoc2
= IXGBE_READ_REG(hw
, IXGBE_AUTOC2
);
1822 u32 pma_pmd_10g_serial
= autoc2
& IXGBE_AUTOC2_10G_SERIAL_PMA_PMD_MASK
;
1823 u32 pma_pmd_10g_parallel
= autoc
& IXGBE_AUTOC_10G_PMA_PMD_MASK
;
1824 u32 pma_pmd_1g
= autoc
& IXGBE_AUTOC_1G_PMA_PMD_MASK
;
1825 u16 ext_ability
= 0;
1826 u8 comp_codes_10g
= 0;
1827 u8 comp_codes_1g
= 0;
1829 hw
->phy
.ops
.identify(hw
);
1831 switch (hw
->phy
.type
) {
1834 case ixgbe_phy_cu_unknown
:
1835 hw
->phy
.ops
.read_reg(hw
, MDIO_PMA_EXTABLE
, MDIO_MMD_PMAPMD
,
1837 if (ext_ability
& MDIO_PMA_EXTABLE_10GBT
)
1838 physical_layer
|= IXGBE_PHYSICAL_LAYER_10GBASE_T
;
1839 if (ext_ability
& MDIO_PMA_EXTABLE_1000BT
)
1840 physical_layer
|= IXGBE_PHYSICAL_LAYER_1000BASE_T
;
1841 if (ext_ability
& MDIO_PMA_EXTABLE_100BTX
)
1842 physical_layer
|= IXGBE_PHYSICAL_LAYER_100BASE_TX
;
1848 switch (autoc
& IXGBE_AUTOC_LMS_MASK
) {
1849 case IXGBE_AUTOC_LMS_1G_AN
:
1850 case IXGBE_AUTOC_LMS_1G_LINK_NO_AN
:
1851 if (pma_pmd_1g
== IXGBE_AUTOC_1G_KX_BX
) {
1852 physical_layer
= IXGBE_PHYSICAL_LAYER_1000BASE_KX
|
1853 IXGBE_PHYSICAL_LAYER_1000BASE_BX
;
1856 /* SFI mode so read SFP module */
1859 case IXGBE_AUTOC_LMS_10G_LINK_NO_AN
:
1860 if (pma_pmd_10g_parallel
== IXGBE_AUTOC_10G_CX4
)
1861 physical_layer
= IXGBE_PHYSICAL_LAYER_10GBASE_CX4
;
1862 else if (pma_pmd_10g_parallel
== IXGBE_AUTOC_10G_KX4
)
1863 physical_layer
= IXGBE_PHYSICAL_LAYER_10GBASE_KX4
;
1864 else if (pma_pmd_10g_parallel
== IXGBE_AUTOC_10G_XAUI
)
1865 physical_layer
= IXGBE_PHYSICAL_LAYER_10GBASE_XAUI
;
1868 case IXGBE_AUTOC_LMS_10G_SERIAL
:
1869 if (pma_pmd_10g_serial
== IXGBE_AUTOC2_10G_KR
) {
1870 physical_layer
= IXGBE_PHYSICAL_LAYER_10GBASE_KR
;
1872 } else if (pma_pmd_10g_serial
== IXGBE_AUTOC2_10G_SFI
)
1875 case IXGBE_AUTOC_LMS_KX4_KX_KR
:
1876 case IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN
:
1877 if (autoc
& IXGBE_AUTOC_KX_SUPP
)
1878 physical_layer
|= IXGBE_PHYSICAL_LAYER_1000BASE_KX
;
1879 if (autoc
& IXGBE_AUTOC_KX4_SUPP
)
1880 physical_layer
|= IXGBE_PHYSICAL_LAYER_10GBASE_KX4
;
1881 if (autoc
& IXGBE_AUTOC_KR_SUPP
)
1882 physical_layer
|= IXGBE_PHYSICAL_LAYER_10GBASE_KR
;
1891 /* SFP check must be done last since DA modules are sometimes used to
1892 * test KR mode - we need to id KR mode correctly before SFP module.
1893 * Call identify_sfp because the pluggable module may have changed */
1894 hw
->phy
.ops
.identify_sfp(hw
);
1895 if (hw
->phy
.sfp_type
== ixgbe_sfp_type_not_present
)
1898 switch (hw
->phy
.type
) {
1899 case ixgbe_phy_sfp_passive_tyco
:
1900 case ixgbe_phy_sfp_passive_unknown
:
1901 physical_layer
= IXGBE_PHYSICAL_LAYER_SFP_PLUS_CU
;
1903 case ixgbe_phy_sfp_ftl_active
:
1904 case ixgbe_phy_sfp_active_unknown
:
1905 physical_layer
= IXGBE_PHYSICAL_LAYER_SFP_ACTIVE_DA
;
1907 case ixgbe_phy_sfp_avago
:
1908 case ixgbe_phy_sfp_ftl
:
1909 case ixgbe_phy_sfp_intel
:
1910 case ixgbe_phy_sfp_unknown
:
1911 hw
->phy
.ops
.read_i2c_eeprom(hw
,
1912 IXGBE_SFF_1GBE_COMP_CODES
, &comp_codes_1g
);
1913 hw
->phy
.ops
.read_i2c_eeprom(hw
,
1914 IXGBE_SFF_10GBE_COMP_CODES
, &comp_codes_10g
);
1915 if (comp_codes_10g
& IXGBE_SFF_10GBASESR_CAPABLE
)
1916 physical_layer
= IXGBE_PHYSICAL_LAYER_10GBASE_SR
;
1917 else if (comp_codes_10g
& IXGBE_SFF_10GBASELR_CAPABLE
)
1918 physical_layer
= IXGBE_PHYSICAL_LAYER_10GBASE_LR
;
1919 else if (comp_codes_1g
& IXGBE_SFF_1GBASET_CAPABLE
)
1920 physical_layer
= IXGBE_PHYSICAL_LAYER_1000BASE_T
;
1927 return physical_layer
;
1931 * ixgbe_enable_rx_dma_82599 - Enable the Rx DMA unit on 82599
1932 * @hw: pointer to hardware structure
1933 * @regval: register value to write to RXCTRL
1935 * Enables the Rx DMA unit for 82599
1937 static s32
ixgbe_enable_rx_dma_82599(struct ixgbe_hw
*hw
, u32 regval
)
1939 #define IXGBE_MAX_SECRX_POLL 30
1944 * Workaround for 82599 silicon errata when enabling the Rx datapath.
1945 * If traffic is incoming before we enable the Rx unit, it could hang
1946 * the Rx DMA unit. Therefore, make sure the security engine is
1947 * completely disabled prior to enabling the Rx unit.
1949 secrxreg
= IXGBE_READ_REG(hw
, IXGBE_SECRXCTRL
);
1950 secrxreg
|= IXGBE_SECRXCTRL_RX_DIS
;
1951 IXGBE_WRITE_REG(hw
, IXGBE_SECRXCTRL
, secrxreg
);
1952 for (i
= 0; i
< IXGBE_MAX_SECRX_POLL
; i
++) {
1953 secrxreg
= IXGBE_READ_REG(hw
, IXGBE_SECRXSTAT
);
1954 if (secrxreg
& IXGBE_SECRXSTAT_SECRX_RDY
)
1957 /* Use interrupt-safe sleep just in case */
1961 /* For informational purposes only */
1962 if (i
>= IXGBE_MAX_SECRX_POLL
)
1963 hw_dbg(hw
, "Rx unit being enabled before security "
1964 "path fully disabled. Continuing with init.\n");
1966 IXGBE_WRITE_REG(hw
, IXGBE_RXCTRL
, regval
);
1967 secrxreg
= IXGBE_READ_REG(hw
, IXGBE_SECRXCTRL
);
1968 secrxreg
&= ~IXGBE_SECRXCTRL_RX_DIS
;
1969 IXGBE_WRITE_REG(hw
, IXGBE_SECRXCTRL
, secrxreg
);
1970 IXGBE_WRITE_FLUSH(hw
);
1976 * ixgbe_get_device_caps_82599 - Get additional device capabilities
1977 * @hw: pointer to hardware structure
1978 * @device_caps: the EEPROM word with the extra device capabilities
1980 * This function will read the EEPROM location for the device capabilities,
1981 * and return the word through device_caps.
1983 static s32
ixgbe_get_device_caps_82599(struct ixgbe_hw
*hw
, u16
*device_caps
)
1985 hw
->eeprom
.ops
.read(hw
, IXGBE_DEVICE_CAPS
, device_caps
);
1991 * ixgbe_verify_fw_version_82599 - verify fw version for 82599
1992 * @hw: pointer to hardware structure
1994 * Verifies that installed the firmware version is 0.6 or higher
1995 * for SFI devices. All 82599 SFI devices should have version 0.6 or higher.
1997 * Returns IXGBE_ERR_EEPROM_VERSION if the FW is not present or
1998 * if the FW version is not supported.
2000 static s32
ixgbe_verify_fw_version_82599(struct ixgbe_hw
*hw
)
2002 s32 status
= IXGBE_ERR_EEPROM_VERSION
;
2003 u16 fw_offset
, fw_ptp_cfg_offset
;
2006 /* firmware check is only necessary for SFI devices */
2007 if (hw
->phy
.media_type
!= ixgbe_media_type_fiber
) {
2009 goto fw_version_out
;
2012 /* get the offset to the Firmware Module block */
2013 hw
->eeprom
.ops
.read(hw
, IXGBE_FW_PTR
, &fw_offset
);
2015 if ((fw_offset
== 0) || (fw_offset
== 0xFFFF))
2016 goto fw_version_out
;
2018 /* get the offset to the Pass Through Patch Configuration block */
2019 hw
->eeprom
.ops
.read(hw
, (fw_offset
+
2020 IXGBE_FW_PASSTHROUGH_PATCH_CONFIG_PTR
),
2021 &fw_ptp_cfg_offset
);
2023 if ((fw_ptp_cfg_offset
== 0) || (fw_ptp_cfg_offset
== 0xFFFF))
2024 goto fw_version_out
;
2026 /* get the firmware version */
2027 hw
->eeprom
.ops
.read(hw
, (fw_ptp_cfg_offset
+
2028 IXGBE_FW_PATCH_VERSION_4
),
2031 if (fw_version
> 0x5)
2039 * ixgbe_verify_lesm_fw_enabled_82599 - Checks LESM FW module state.
2040 * @hw: pointer to hardware structure
2042 * Returns true if the LESM FW module is present and enabled. Otherwise
2043 * returns false. Smart Speed must be disabled if LESM FW module is enabled.
2045 static bool ixgbe_verify_lesm_fw_enabled_82599(struct ixgbe_hw
*hw
)
2047 bool lesm_enabled
= false;
2048 u16 fw_offset
, fw_lesm_param_offset
, fw_lesm_state
;
2051 /* get the offset to the Firmware Module block */
2052 status
= hw
->eeprom
.ops
.read(hw
, IXGBE_FW_PTR
, &fw_offset
);
2054 if ((status
!= 0) ||
2055 (fw_offset
== 0) || (fw_offset
== 0xFFFF))
2058 /* get the offset to the LESM Parameters block */
2059 status
= hw
->eeprom
.ops
.read(hw
, (fw_offset
+
2060 IXGBE_FW_LESM_PARAMETERS_PTR
),
2061 &fw_lesm_param_offset
);
2063 if ((status
!= 0) ||
2064 (fw_lesm_param_offset
== 0) || (fw_lesm_param_offset
== 0xFFFF))
2067 /* get the lesm state word */
2068 status
= hw
->eeprom
.ops
.read(hw
, (fw_lesm_param_offset
+
2069 IXGBE_FW_LESM_STATE_1
),
2072 if ((status
== 0) &&
2073 (fw_lesm_state
& IXGBE_FW_LESM_STATE_ENABLED
))
2074 lesm_enabled
= true;
2077 return lesm_enabled
;
2080 static struct ixgbe_mac_operations mac_ops_82599
= {
2081 .init_hw
= &ixgbe_init_hw_generic
,
2082 .reset_hw
= &ixgbe_reset_hw_82599
,
2083 .start_hw
= &ixgbe_start_hw_82599
,
2084 .clear_hw_cntrs
= &ixgbe_clear_hw_cntrs_generic
,
2085 .get_media_type
= &ixgbe_get_media_type_82599
,
2086 .get_supported_physical_layer
= &ixgbe_get_supported_physical_layer_82599
,
2087 .enable_rx_dma
= &ixgbe_enable_rx_dma_82599
,
2088 .get_mac_addr
= &ixgbe_get_mac_addr_generic
,
2089 .get_san_mac_addr
= &ixgbe_get_san_mac_addr_generic
,
2090 .get_device_caps
= &ixgbe_get_device_caps_82599
,
2091 .get_wwn_prefix
= &ixgbe_get_wwn_prefix_generic
,
2092 .stop_adapter
= &ixgbe_stop_adapter_generic
,
2093 .get_bus_info
= &ixgbe_get_bus_info_generic
,
2094 .set_lan_id
= &ixgbe_set_lan_id_multi_port_pcie
,
2095 .read_analog_reg8
= &ixgbe_read_analog_reg8_82599
,
2096 .write_analog_reg8
= &ixgbe_write_analog_reg8_82599
,
2097 .setup_link
= &ixgbe_setup_mac_link_82599
,
2098 .check_link
= &ixgbe_check_mac_link_generic
,
2099 .get_link_capabilities
= &ixgbe_get_link_capabilities_82599
,
2100 .led_on
= &ixgbe_led_on_generic
,
2101 .led_off
= &ixgbe_led_off_generic
,
2102 .blink_led_start
= &ixgbe_blink_led_start_generic
,
2103 .blink_led_stop
= &ixgbe_blink_led_stop_generic
,
2104 .set_rar
= &ixgbe_set_rar_generic
,
2105 .clear_rar
= &ixgbe_clear_rar_generic
,
2106 .set_vmdq
= &ixgbe_set_vmdq_generic
,
2107 .clear_vmdq
= &ixgbe_clear_vmdq_generic
,
2108 .init_rx_addrs
= &ixgbe_init_rx_addrs_generic
,
2109 .update_mc_addr_list
= &ixgbe_update_mc_addr_list_generic
,
2110 .enable_mc
= &ixgbe_enable_mc_generic
,
2111 .disable_mc
= &ixgbe_disable_mc_generic
,
2112 .clear_vfta
= &ixgbe_clear_vfta_generic
,
2113 .set_vfta
= &ixgbe_set_vfta_generic
,
2114 .fc_enable
= &ixgbe_fc_enable_generic
,
2115 .init_uta_tables
= &ixgbe_init_uta_tables_generic
,
2116 .setup_sfp
= &ixgbe_setup_sfp_modules_82599
,
2117 .set_mac_anti_spoofing
= &ixgbe_set_mac_anti_spoofing
,
2118 .set_vlan_anti_spoofing
= &ixgbe_set_vlan_anti_spoofing
,
2119 .acquire_swfw_sync
= &ixgbe_acquire_swfw_sync
,
2120 .release_swfw_sync
= &ixgbe_release_swfw_sync
,
2124 static struct ixgbe_eeprom_operations eeprom_ops_82599
= {
2125 .init_params
= &ixgbe_init_eeprom_params_generic
,
2126 .read
= &ixgbe_read_eerd_generic
,
2127 .write
= &ixgbe_write_eeprom_generic
,
2128 .calc_checksum
= &ixgbe_calc_eeprom_checksum_generic
,
2129 .validate_checksum
= &ixgbe_validate_eeprom_checksum_generic
,
2130 .update_checksum
= &ixgbe_update_eeprom_checksum_generic
,
2133 static struct ixgbe_phy_operations phy_ops_82599
= {
2134 .identify
= &ixgbe_identify_phy_82599
,
2135 .identify_sfp
= &ixgbe_identify_sfp_module_generic
,
2136 .init
= &ixgbe_init_phy_ops_82599
,
2137 .reset
= &ixgbe_reset_phy_generic
,
2138 .read_reg
= &ixgbe_read_phy_reg_generic
,
2139 .write_reg
= &ixgbe_write_phy_reg_generic
,
2140 .setup_link
= &ixgbe_setup_phy_link_generic
,
2141 .setup_link_speed
= &ixgbe_setup_phy_link_speed_generic
,
2142 .read_i2c_byte
= &ixgbe_read_i2c_byte_generic
,
2143 .write_i2c_byte
= &ixgbe_write_i2c_byte_generic
,
2144 .read_i2c_eeprom
= &ixgbe_read_i2c_eeprom_generic
,
2145 .write_i2c_eeprom
= &ixgbe_write_i2c_eeprom_generic
,
2146 .check_overtemp
= &ixgbe_tn_check_overtemp
,
2149 struct ixgbe_info ixgbe_82599_info
= {
2150 .mac
= ixgbe_mac_82599EB
,
2151 .get_invariants
= &ixgbe_get_invariants_82599
,
2152 .mac_ops
= &mac_ops_82599
,
2153 .eeprom_ops
= &eeprom_ops_82599
,
2154 .phy_ops
= &phy_ops_82599
,
2155 .mbx_ops
= &mbx_ops_generic
,