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igb: Add support for enabling VFs to PF driver.
[linux-2.6.git] / drivers / net / igb / igb_main.c
blobb9e7980e3f474aca17bce4967e8d2ad2e182dade
1 /*******************************************************************************
2
3 Intel(R) Gigabit Ethernet Linux driver
4 Copyright(c) 2007-2009 Intel Corporation.
5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
25
26 *******************************************************************************/
27
28 #include <linux/module.h>
29 #include <linux/types.h>
30 #include <linux/init.h>
31 #include <linux/vmalloc.h>
32 #include <linux/pagemap.h>
33 #include <linux/netdevice.h>
34 #include <linux/ipv6.h>
35 #include <net/checksum.h>
36 #include <net/ip6_checksum.h>
37 #include <linux/net_tstamp.h>
38 #include <linux/mii.h>
39 #include <linux/ethtool.h>
40 #include <linux/if_vlan.h>
41 #include <linux/pci.h>
42 #include <linux/pci-aspm.h>
43 #include <linux/delay.h>
44 #include <linux/interrupt.h>
45 #include <linux/if_ether.h>
46 #include <linux/aer.h>
47 #ifdef CONFIG_IGB_DCA
48 #include <linux/dca.h>
49 #endif
50 #include "igb.h"
51
52 #define DRV_VERSION "1.3.16-k2"
53 char igb_driver_name[] = "igb";
54 char igb_driver_version[] = DRV_VERSION;
55 static const char igb_driver_string[] =
56 "Intel(R) Gigabit Ethernet Network Driver";
57 static const char igb_copyright[] = "Copyright (c) 2007-2009 Intel Corporation.";
58
59 static const struct e1000_info *igb_info_tbl[] = {
60 [board_82575] = &e1000_82575_info,
61 };
62
63 static struct pci_device_id igb_pci_tbl[] = {
64 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576), board_82575 },
65 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_FIBER), board_82575 },
66 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_SERDES), board_82575 },
67 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575EB_COPPER), board_82575 },
68 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575EB_FIBER_SERDES), board_82575 },
69 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575GB_QUAD_COPPER), board_82575 },
70 /* required last entry */
71 {0, }
72 };
73
74 MODULE_DEVICE_TABLE(pci, igb_pci_tbl);
75
76 void igb_reset(struct igb_adapter *);
77 static int igb_setup_all_tx_resources(struct igb_adapter *);
78 static int igb_setup_all_rx_resources(struct igb_adapter *);
79 static void igb_free_all_tx_resources(struct igb_adapter *);
80 static void igb_free_all_rx_resources(struct igb_adapter *);
81 void igb_update_stats(struct igb_adapter *);
82 static int igb_probe(struct pci_dev *, const struct pci_device_id *);
83 static void __devexit igb_remove(struct pci_dev *pdev);
84 static int igb_sw_init(struct igb_adapter *);
85 static int igb_open(struct net_device *);
86 static int igb_close(struct net_device *);
87 static void igb_configure_tx(struct igb_adapter *);
88 static void igb_configure_rx(struct igb_adapter *);
89 static void igb_setup_rctl(struct igb_adapter *);
90 static void igb_clean_all_tx_rings(struct igb_adapter *);
91 static void igb_clean_all_rx_rings(struct igb_adapter *);
92 static void igb_clean_tx_ring(struct igb_ring *);
93 static void igb_clean_rx_ring(struct igb_ring *);
94 static void igb_set_multi(struct net_device *);
95 static void igb_update_phy_info(unsigned long);
96 static void igb_watchdog(unsigned long);
97 static void igb_watchdog_task(struct work_struct *);
98 static int igb_xmit_frame_ring_adv(struct sk_buff *, struct net_device *,
99 struct igb_ring *);
100 static int igb_xmit_frame_adv(struct sk_buff *skb, struct net_device *);
101 static struct net_device_stats *igb_get_stats(struct net_device *);
102 static int igb_change_mtu(struct net_device *, int);
103 static int igb_set_mac(struct net_device *, void *);
104 static irqreturn_t igb_intr(int irq, void *);
105 static irqreturn_t igb_intr_msi(int irq, void *);
106 static irqreturn_t igb_msix_other(int irq, void *);
107 static irqreturn_t igb_msix_rx(int irq, void *);
108 static irqreturn_t igb_msix_tx(int irq, void *);
109 #ifdef CONFIG_IGB_DCA
110 static void igb_update_rx_dca(struct igb_ring *);
111 static void igb_update_tx_dca(struct igb_ring *);
112 static void igb_setup_dca(struct igb_adapter *);
113 #endif /* CONFIG_IGB_DCA */
114 static bool igb_clean_tx_irq(struct igb_ring *);
115 static int igb_poll(struct napi_struct *, int);
116 static bool igb_clean_rx_irq_adv(struct igb_ring *, int *, int);
117 static void igb_alloc_rx_buffers_adv(struct igb_ring *, int);
118 static int igb_ioctl(struct net_device *, struct ifreq *, int cmd);
119 static void igb_tx_timeout(struct net_device *);
120 static void igb_reset_task(struct work_struct *);
121 static void igb_vlan_rx_register(struct net_device *, struct vlan_group *);
122 static void igb_vlan_rx_add_vid(struct net_device *, u16);
123 static void igb_vlan_rx_kill_vid(struct net_device *, u16);
124 static void igb_restore_vlan(struct igb_adapter *);
125 static void igb_ping_all_vfs(struct igb_adapter *);
126 static void igb_msg_task(struct igb_adapter *);
127 static int igb_rcv_msg_from_vf(struct igb_adapter *, u32);
128 static inline void igb_set_rah_pool(struct e1000_hw *, int , int);
129 static void igb_set_mc_list_pools(struct igb_adapter *, int, u16);
130 static void igb_vmm_control(struct igb_adapter *);
131 static inline void igb_set_vmolr(struct e1000_hw *, int);
132 static inline int igb_set_vf_rlpml(struct igb_adapter *, int, int);
133 static int igb_set_vf_mac(struct igb_adapter *adapter, int, unsigned char *);
134 static void igb_restore_vf_multicasts(struct igb_adapter *adapter);
135
136 static int igb_suspend(struct pci_dev *, pm_message_t);
137 #ifdef CONFIG_PM
138 static int igb_resume(struct pci_dev *);
139 #endif
140 static void igb_shutdown(struct pci_dev *);
141 #ifdef CONFIG_IGB_DCA
142 static int igb_notify_dca(struct notifier_block *, unsigned long, void *);
143 static struct notifier_block dca_notifier = {
144 .notifier_call = igb_notify_dca,
145 .next = NULL,
146 .priority = 0
147 };
148 #endif
149
150 #ifdef CONFIG_NET_POLL_CONTROLLER
151 /* for netdump / net console */
152 static void igb_netpoll(struct net_device *);
153 #endif
154
155 static pci_ers_result_t igb_io_error_detected(struct pci_dev *,
156 pci_channel_state_t);
157 static pci_ers_result_t igb_io_slot_reset(struct pci_dev *);
158 static void igb_io_resume(struct pci_dev *);
159
160 static struct pci_error_handlers igb_err_handler = {
161 .error_detected = igb_io_error_detected,
162 .slot_reset = igb_io_slot_reset,
163 .resume = igb_io_resume,
164 };
165
166
167 static struct pci_driver igb_driver = {
168 .name = igb_driver_name,
169 .id_table = igb_pci_tbl,
170 .probe = igb_probe,
171 .remove = __devexit_p(igb_remove),
172 #ifdef CONFIG_PM
173 /* Power Managment Hooks */
174 .suspend = igb_suspend,
175 .resume = igb_resume,
176 #endif
177 .shutdown = igb_shutdown,
178 .err_handler = &igb_err_handler
179 };
180
181 static int global_quad_port_a; /* global quad port a indication */
182
183 MODULE_AUTHOR("Intel Corporation, <e1000-devel@lists.sourceforge.net>");
184 MODULE_DESCRIPTION("Intel(R) Gigabit Ethernet Network Driver");
185 MODULE_LICENSE("GPL");
186 MODULE_VERSION(DRV_VERSION);
187
188 /**
189 * Scale the NIC clock cycle by a large factor so that
190 * relatively small clock corrections can be added or
191 * substracted at each clock tick. The drawbacks of a
192 * large factor are a) that the clock register overflows
193 * more quickly (not such a big deal) and b) that the
194 * increment per tick has to fit into 24 bits.
195 *
196 * Note that
197 * TIMINCA = IGB_TSYNC_CYCLE_TIME_IN_NANOSECONDS *
198 * IGB_TSYNC_SCALE
199 * TIMINCA += TIMINCA * adjustment [ppm] / 1e9
200 *
201 * The base scale factor is intentionally a power of two
202 * so that the division in %struct timecounter can be done with
203 * a shift.
204 */
205 #define IGB_TSYNC_SHIFT (19)
206 #define IGB_TSYNC_SCALE (1<<IGB_TSYNC_SHIFT)
207
208 /**
209 * The duration of one clock cycle of the NIC.
210 *
211 * @todo This hard-coded value is part of the specification and might change
212 * in future hardware revisions. Add revision check.
213 */
214 #define IGB_TSYNC_CYCLE_TIME_IN_NANOSECONDS 16
215
216 #if (IGB_TSYNC_SCALE * IGB_TSYNC_CYCLE_TIME_IN_NANOSECONDS) >= (1<<24)
217 # error IGB_TSYNC_SCALE and/or IGB_TSYNC_CYCLE_TIME_IN_NANOSECONDS are too large to fit into TIMINCA
218 #endif
219
220 /**
221 * igb_read_clock - read raw cycle counter (to be used by time counter)
222 */
223 static cycle_t igb_read_clock(const struct cyclecounter *tc)
224 {
225 struct igb_adapter *adapter =
226 container_of(tc, struct igb_adapter, cycles);
227 struct e1000_hw *hw = &adapter->hw;
228 u64 stamp;
229
230 stamp = rd32(E1000_SYSTIML);
231 stamp |= (u64)rd32(E1000_SYSTIMH) << 32ULL;
232
233 return stamp;
234 }
235
236 #ifdef DEBUG
237 /**
238 * igb_get_hw_dev_name - return device name string
239 * used by hardware layer to print debugging information
240 **/
241 char *igb_get_hw_dev_name(struct e1000_hw *hw)
242 {
243 struct igb_adapter *adapter = hw->back;
244 return adapter->netdev->name;
245 }
246
247 /**
248 * igb_get_time_str - format current NIC and system time as string
249 */
250 static char *igb_get_time_str(struct igb_adapter *adapter,
251 char buffer[160])
252 {
253 cycle_t hw = adapter->cycles.read(&adapter->cycles);
254 struct timespec nic = ns_to_timespec(timecounter_read(&adapter->clock));
255 struct timespec sys;
256 struct timespec delta;
257 getnstimeofday(&sys);
258
259 delta = timespec_sub(nic, sys);
260
261 sprintf(buffer,
262 "HW %llu, NIC %ld.%09lus, SYS %ld.%09lus, NIC-SYS %lds + %09luns",
263 hw,
264 (long)nic.tv_sec, nic.tv_nsec,
265 (long)sys.tv_sec, sys.tv_nsec,
266 (long)delta.tv_sec, delta.tv_nsec);
267
268 return buffer;
269 }
270 #endif
271
272 /**
273 * igb_init_module - Driver Registration Routine
274 *
275 * igb_init_module is the first routine called when the driver is
276 * loaded. All it does is register with the PCI subsystem.
277 **/
278 static int __init igb_init_module(void)
279 {
280 int ret;
281 printk(KERN_INFO "%s - version %s\n",
282 igb_driver_string, igb_driver_version);
283
284 printk(KERN_INFO "%s\n", igb_copyright);
285
286 global_quad_port_a = 0;
287
288 #ifdef CONFIG_IGB_DCA
289 dca_register_notify(&dca_notifier);
290 #endif
291
292 ret = pci_register_driver(&igb_driver);
293 return ret;
294 }
295
296 module_init(igb_init_module);
297
298 /**
299 * igb_exit_module - Driver Exit Cleanup Routine
300 *
301 * igb_exit_module is called just before the driver is removed
302 * from memory.
303 **/
304 static void __exit igb_exit_module(void)
305 {
306 #ifdef CONFIG_IGB_DCA
307 dca_unregister_notify(&dca_notifier);
308 #endif
309 pci_unregister_driver(&igb_driver);
310 }
311
312 module_exit(igb_exit_module);
313
314 #define Q_IDX_82576(i) (((i & 0x1) << 3) + (i >> 1))
315 /**
316 * igb_cache_ring_register - Descriptor ring to register mapping
317 * @adapter: board private structure to initialize
318 *
319 * Once we know the feature-set enabled for the device, we'll cache
320 * the register offset the descriptor ring is assigned to.
321 **/
322 static void igb_cache_ring_register(struct igb_adapter *adapter)
323 {
324 int i;
325 unsigned int rbase_offset = adapter->vfs_allocated_count;
326
327 switch (adapter->hw.mac.type) {
328 case e1000_82576:
329 /* The queues are allocated for virtualization such that VF 0
330 * is allocated queues 0 and 8, VF 1 queues 1 and 9, etc.
331 * In order to avoid collision we start at the first free queue
332 * and continue consuming queues in the same sequence
333 */
334 for (i = 0; i < adapter->num_rx_queues; i++)
335 adapter->rx_ring[i].reg_idx = rbase_offset +
336 Q_IDX_82576(i);
337 for (i = 0; i < adapter->num_tx_queues; i++)
338 adapter->tx_ring[i].reg_idx = rbase_offset +
339 Q_IDX_82576(i);
340 break;
341 case e1000_82575:
342 default:
343 for (i = 0; i < adapter->num_rx_queues; i++)
344 adapter->rx_ring[i].reg_idx = i;
345 for (i = 0; i < adapter->num_tx_queues; i++)
346 adapter->tx_ring[i].reg_idx = i;
347 break;
348 }
349 }
350
351 /**
352 * igb_alloc_queues - Allocate memory for all rings
353 * @adapter: board private structure to initialize
354 *
355 * We allocate one ring per queue at run-time since we don't know the
356 * number of queues at compile-time.
357 **/
358 static int igb_alloc_queues(struct igb_adapter *adapter)
359 {
360 int i;
361
362 adapter->tx_ring = kcalloc(adapter->num_tx_queues,
363 sizeof(struct igb_ring), GFP_KERNEL);
364 if (!adapter->tx_ring)
365 return -ENOMEM;
366
367 adapter->rx_ring = kcalloc(adapter->num_rx_queues,
368 sizeof(struct igb_ring), GFP_KERNEL);
369 if (!adapter->rx_ring) {
370 kfree(adapter->tx_ring);
371 return -ENOMEM;
372 }
373
374 adapter->rx_ring->buddy = adapter->tx_ring;
375
376 for (i = 0; i < adapter->num_tx_queues; i++) {
377 struct igb_ring *ring = &(adapter->tx_ring[i]);
378 ring->count = adapter->tx_ring_count;
379 ring->adapter = adapter;
380 ring->queue_index = i;
381 }
382 for (i = 0; i < adapter->num_rx_queues; i++) {
383 struct igb_ring *ring = &(adapter->rx_ring[i]);
384 ring->count = adapter->rx_ring_count;
385 ring->adapter = adapter;
386 ring->queue_index = i;
387 ring->itr_register = E1000_ITR;
388
389 /* set a default napi handler for each rx_ring */
390 netif_napi_add(adapter->netdev, &ring->napi, igb_poll, 64);
391 }
392
393 igb_cache_ring_register(adapter);
394 return 0;
395 }
396
397 static void igb_free_queues(struct igb_adapter *adapter)
398 {
399 int i;
400
401 for (i = 0; i < adapter->num_rx_queues; i++)
402 netif_napi_del(&adapter->rx_ring[i].napi);
403
404 kfree(adapter->tx_ring);
405 kfree(adapter->rx_ring);
406 }
407
408 #define IGB_N0_QUEUE -1
409 static void igb_assign_vector(struct igb_adapter *adapter, int rx_queue,
410 int tx_queue, int msix_vector)
411 {
412 u32 msixbm = 0;
413 struct e1000_hw *hw = &adapter->hw;
414 u32 ivar, index;
415
416 switch (hw->mac.type) {
417 case e1000_82575:
418 /* The 82575 assigns vectors using a bitmask, which matches the
419 bitmask for the EICR/EIMS/EIMC registers. To assign one
420 or more queues to a vector, we write the appropriate bits
421 into the MSIXBM register for that vector. */
422 if (rx_queue > IGB_N0_QUEUE) {
423 msixbm = E1000_EICR_RX_QUEUE0 << rx_queue;
424 adapter->rx_ring[rx_queue].eims_value = msixbm;
425 }
426 if (tx_queue > IGB_N0_QUEUE) {
427 msixbm |= E1000_EICR_TX_QUEUE0 << tx_queue;
428 adapter->tx_ring[tx_queue].eims_value =
429 E1000_EICR_TX_QUEUE0 << tx_queue;
430 }
431 array_wr32(E1000_MSIXBM(0), msix_vector, msixbm);
432 break;
433 case e1000_82576:
434 /* 82576 uses a table-based method for assigning vectors.
435 Each queue has a single entry in the table to which we write
436 a vector number along with a "valid" bit. Sadly, the layout
437 of the table is somewhat counterintuitive. */
438 if (rx_queue > IGB_N0_QUEUE) {
439 index = (rx_queue >> 1) + adapter->vfs_allocated_count;
440 ivar = array_rd32(E1000_IVAR0, index);
441 if (rx_queue & 0x1) {
442 /* vector goes into third byte of register */
443 ivar = ivar & 0xFF00FFFF;
444 ivar |= (msix_vector | E1000_IVAR_VALID) << 16;
445 } else {
446 /* vector goes into low byte of register */
447 ivar = ivar & 0xFFFFFF00;
448 ivar |= msix_vector | E1000_IVAR_VALID;
449 }
450 adapter->rx_ring[rx_queue].eims_value= 1 << msix_vector;
451 array_wr32(E1000_IVAR0, index, ivar);
452 }
453 if (tx_queue > IGB_N0_QUEUE) {
454 index = (tx_queue >> 1) + adapter->vfs_allocated_count;
455 ivar = array_rd32(E1000_IVAR0, index);
456 if (tx_queue & 0x1) {
457 /* vector goes into high byte of register */
458 ivar = ivar & 0x00FFFFFF;
459 ivar |= (msix_vector | E1000_IVAR_VALID) << 24;
460 } else {
461 /* vector goes into second byte of register */
462 ivar = ivar & 0xFFFF00FF;
463 ivar |= (msix_vector | E1000_IVAR_VALID) << 8;
464 }
465 adapter->tx_ring[tx_queue].eims_value= 1 << msix_vector;
466 array_wr32(E1000_IVAR0, index, ivar);
467 }
468 break;
469 default:
470 BUG();
471 break;
472 }
473 }
474
475 /**
476 * igb_configure_msix - Configure MSI-X hardware
477 *
478 * igb_configure_msix sets up the hardware to properly
479 * generate MSI-X interrupts.
480 **/
481 static void igb_configure_msix(struct igb_adapter *adapter)
482 {
483 u32 tmp;
484 int i, vector = 0;
485 struct e1000_hw *hw = &adapter->hw;
486
487 adapter->eims_enable_mask = 0;
488 if (hw->mac.type == e1000_82576)
489 /* Turn on MSI-X capability first, or our settings
490 * won't stick. And it will take days to debug. */
491 wr32(E1000_GPIE, E1000_GPIE_MSIX_MODE |
492 E1000_GPIE_PBA | E1000_GPIE_EIAME |
493 E1000_GPIE_NSICR);
494
495 for (i = 0; i < adapter->num_tx_queues; i++) {
496 struct igb_ring *tx_ring = &adapter->tx_ring[i];
497 igb_assign_vector(adapter, IGB_N0_QUEUE, i, vector++);
498 adapter->eims_enable_mask |= tx_ring->eims_value;
499 if (tx_ring->itr_val)
500 writel(tx_ring->itr_val,
501 hw->hw_addr + tx_ring->itr_register);
502 else
503 writel(1, hw->hw_addr + tx_ring->itr_register);
504 }
505
506 for (i = 0; i < adapter->num_rx_queues; i++) {
507 struct igb_ring *rx_ring = &adapter->rx_ring[i];
508 rx_ring->buddy = NULL;
509 igb_assign_vector(adapter, i, IGB_N0_QUEUE, vector++);
510 adapter->eims_enable_mask |= rx_ring->eims_value;
511 if (rx_ring->itr_val)
512 writel(rx_ring->itr_val,
513 hw->hw_addr + rx_ring->itr_register);
514 else
515 writel(1, hw->hw_addr + rx_ring->itr_register);
516 }
517
518
519 /* set vector for other causes, i.e. link changes */
520 switch (hw->mac.type) {
521 case e1000_82575:
522 array_wr32(E1000_MSIXBM(0), vector++,
523 E1000_EIMS_OTHER);
524
525 tmp = rd32(E1000_CTRL_EXT);
526 /* enable MSI-X PBA support*/
527 tmp |= E1000_CTRL_EXT_PBA_CLR;
528
529 /* Auto-Mask interrupts upon ICR read. */
530 tmp |= E1000_CTRL_EXT_EIAME;
531 tmp |= E1000_CTRL_EXT_IRCA;
532
533 wr32(E1000_CTRL_EXT, tmp);
534 adapter->eims_enable_mask |= E1000_EIMS_OTHER;
535 adapter->eims_other = E1000_EIMS_OTHER;
536
537 break;
538
539 case e1000_82576:
540 tmp = (vector++ | E1000_IVAR_VALID) << 8;
541 wr32(E1000_IVAR_MISC, tmp);
542
543 adapter->eims_enable_mask = (1 << (vector)) - 1;
544 adapter->eims_other = 1 << (vector - 1);
545 break;
546 default:
547 /* do nothing, since nothing else supports MSI-X */
548 break;
549 } /* switch (hw->mac.type) */
550 wrfl();
551 }
552
553 /**
554 * igb_request_msix - Initialize MSI-X interrupts
555 *
556 * igb_request_msix allocates MSI-X vectors and requests interrupts from the
557 * kernel.
558 **/
559 static int igb_request_msix(struct igb_adapter *adapter)
560 {
561 struct net_device *netdev = adapter->netdev;
562 int i, err = 0, vector = 0;
563
564 vector = 0;
565
566 for (i = 0; i < adapter->num_tx_queues; i++) {
567 struct igb_ring *ring = &(adapter->tx_ring[i]);
568 sprintf(ring->name, "%s-tx-%d", netdev->name, i);
569 err = request_irq(adapter->msix_entries[vector].vector,
570 &igb_msix_tx, 0, ring->name,
571 &(adapter->tx_ring[i]));
572 if (err)
573 goto out;
574 ring->itr_register = E1000_EITR(0) + (vector << 2);
575 ring->itr_val = 976; /* ~4000 ints/sec */
576 vector++;
577 }
578 for (i = 0; i < adapter->num_rx_queues; i++) {
579 struct igb_ring *ring = &(adapter->rx_ring[i]);
580 if (strlen(netdev->name) < (IFNAMSIZ - 5))
581 sprintf(ring->name, "%s-rx-%d", netdev->name, i);
582 else
583 memcpy(ring->name, netdev->name, IFNAMSIZ);
584 err = request_irq(adapter->msix_entries[vector].vector,
585 &igb_msix_rx, 0, ring->name,
586 &(adapter->rx_ring[i]));
587 if (err)
588 goto out;
589 ring->itr_register = E1000_EITR(0) + (vector << 2);
590 ring->itr_val = adapter->itr;
591 /* overwrite the poll routine for MSIX, we've already done
592 * netif_napi_add */
593 ring->napi.poll = &igb_clean_rx_ring_msix;
594 vector++;
595 }
596
597 err = request_irq(adapter->msix_entries[vector].vector,
598 &igb_msix_other, 0, netdev->name, netdev);
599 if (err)
600 goto out;
601
602 igb_configure_msix(adapter);
603 return 0;
604 out:
605 return err;
606 }
607
608 static void igb_reset_interrupt_capability(struct igb_adapter *adapter)
609 {
610 if (adapter->msix_entries) {
611 pci_disable_msix(adapter->pdev);
612 kfree(adapter->msix_entries);
613 adapter->msix_entries = NULL;
614 } else if (adapter->flags & IGB_FLAG_HAS_MSI)
615 pci_disable_msi(adapter->pdev);
616 return;
617 }
618
619
620 /**
621 * igb_set_interrupt_capability - set MSI or MSI-X if supported
622 *
623 * Attempt to configure interrupts using the best available
624 * capabilities of the hardware and kernel.
625 **/
626 static void igb_set_interrupt_capability(struct igb_adapter *adapter)
627 {
628 int err;
629 int numvecs, i;
630
631 /* Number of supported queues. */
632 /* Having more queues than CPUs doesn't make sense. */
633 adapter->num_rx_queues = min_t(u32, IGB_MAX_RX_QUEUES, num_online_cpus());
634 adapter->num_tx_queues = min_t(u32, IGB_MAX_TX_QUEUES, num_online_cpus());
635
636 numvecs = adapter->num_tx_queues + adapter->num_rx_queues + 1;
637 adapter->msix_entries = kcalloc(numvecs, sizeof(struct msix_entry),
638 GFP_KERNEL);
639 if (!adapter->msix_entries)
640 goto msi_only;
641
642 for (i = 0; i < numvecs; i++)
643 adapter->msix_entries[i].entry = i;
644
645 err = pci_enable_msix(adapter->pdev,
646 adapter->msix_entries,
647 numvecs);
648 if (err == 0)
649 goto out;
650
651 igb_reset_interrupt_capability(adapter);
652
653 /* If we can't do MSI-X, try MSI */
654 msi_only:
655 adapter->num_rx_queues = 1;
656 adapter->num_tx_queues = 1;
657 if (!pci_enable_msi(adapter->pdev))
658 adapter->flags |= IGB_FLAG_HAS_MSI;
659 out:
660 /* Notify the stack of the (possibly) reduced Tx Queue count. */
661 adapter->netdev->real_num_tx_queues = adapter->num_tx_queues;
662 return;
663 }
664
665 /**
666 * igb_request_irq - initialize interrupts
667 *
668 * Attempts to configure interrupts using the best available
669 * capabilities of the hardware and kernel.
670 **/
671 static int igb_request_irq(struct igb_adapter *adapter)
672 {
673 struct net_device *netdev = adapter->netdev;
674 struct e1000_hw *hw = &adapter->hw;
675 int err = 0;
676
677 if (adapter->msix_entries) {
678 err = igb_request_msix(adapter);
679 if (!err)
680 goto request_done;
681 /* fall back to MSI */
682 igb_reset_interrupt_capability(adapter);
683 if (!pci_enable_msi(adapter->pdev))
684 adapter->flags |= IGB_FLAG_HAS_MSI;
685 igb_free_all_tx_resources(adapter);
686 igb_free_all_rx_resources(adapter);
687 adapter->num_rx_queues = 1;
688 igb_alloc_queues(adapter);
689 } else {
690 switch (hw->mac.type) {
691 case e1000_82575:
692 wr32(E1000_MSIXBM(0),
693 (E1000_EICR_RX_QUEUE0 | E1000_EIMS_OTHER));
694 break;
695 case e1000_82576:
696 wr32(E1000_IVAR0, E1000_IVAR_VALID);
697 break;
698 default:
699 break;
700 }
701 }
702
703 if (adapter->flags & IGB_FLAG_HAS_MSI) {
704 err = request_irq(adapter->pdev->irq, &igb_intr_msi, 0,
705 netdev->name, netdev);
706 if (!err)
707 goto request_done;
708 /* fall back to legacy interrupts */
709 igb_reset_interrupt_capability(adapter);
710 adapter->flags &= ~IGB_FLAG_HAS_MSI;
711 }
712
713 err = request_irq(adapter->pdev->irq, &igb_intr, IRQF_SHARED,
714 netdev->name, netdev);
715
716 if (err)
717 dev_err(&adapter->pdev->dev, "Error %d getting interrupt\n",
718 err);
719
720 request_done:
721 return err;
722 }
723
724 static void igb_free_irq(struct igb_adapter *adapter)
725 {
726 struct net_device *netdev = adapter->netdev;
727
728 if (adapter->msix_entries) {
729 int vector = 0, i;
730
731 for (i = 0; i < adapter->num_tx_queues; i++)
732 free_irq(adapter->msix_entries[vector++].vector,
733 &(adapter->tx_ring[i]));
734 for (i = 0; i < adapter->num_rx_queues; i++)
735 free_irq(adapter->msix_entries[vector++].vector,
736 &(adapter->rx_ring[i]));
737
738 free_irq(adapter->msix_entries[vector++].vector, netdev);
739 return;
740 }
741
742 free_irq(adapter->pdev->irq, netdev);
743 }
744
745 /**
746 * igb_irq_disable - Mask off interrupt generation on the NIC
747 * @adapter: board private structure
748 **/
749 static void igb_irq_disable(struct igb_adapter *adapter)
750 {
751 struct e1000_hw *hw = &adapter->hw;
752
753 if (adapter->msix_entries) {
754 wr32(E1000_EIAM, 0);
755 wr32(E1000_EIMC, ~0);
756 wr32(E1000_EIAC, 0);
757 }
758
759 wr32(E1000_IAM, 0);
760 wr32(E1000_IMC, ~0);
761 wrfl();
762 synchronize_irq(adapter->pdev->irq);
763 }
764
765 /**
766 * igb_irq_enable - Enable default interrupt generation settings
767 * @adapter: board private structure
768 **/
769 static void igb_irq_enable(struct igb_adapter *adapter)
770 {
771 struct e1000_hw *hw = &adapter->hw;
772
773 if (adapter->msix_entries) {
774 wr32(E1000_EIAC, adapter->eims_enable_mask);
775 wr32(E1000_EIAM, adapter->eims_enable_mask);
776 wr32(E1000_EIMS, adapter->eims_enable_mask);
777 if (adapter->vfs_allocated_count)
778 wr32(E1000_MBVFIMR, 0xFF);
779 wr32(E1000_IMS, (E1000_IMS_LSC | E1000_IMS_VMMB |
780 E1000_IMS_DOUTSYNC));
781 } else {
782 wr32(E1000_IMS, IMS_ENABLE_MASK);
783 wr32(E1000_IAM, IMS_ENABLE_MASK);
784 }
785 }
786
787 static void igb_update_mng_vlan(struct igb_adapter *adapter)
788 {
789 struct net_device *netdev = adapter->netdev;
790 u16 vid = adapter->hw.mng_cookie.vlan_id;
791 u16 old_vid = adapter->mng_vlan_id;
792 if (adapter->vlgrp) {
793 if (!vlan_group_get_device(adapter->vlgrp, vid)) {
794 if (adapter->hw.mng_cookie.status &
795 E1000_MNG_DHCP_COOKIE_STATUS_VLAN) {
796 igb_vlan_rx_add_vid(netdev, vid);
797 adapter->mng_vlan_id = vid;
798 } else
799 adapter->mng_vlan_id = IGB_MNG_VLAN_NONE;
800
801 if ((old_vid != (u16)IGB_MNG_VLAN_NONE) &&
802 (vid != old_vid) &&
803 !vlan_group_get_device(adapter->vlgrp, old_vid))
804 igb_vlan_rx_kill_vid(netdev, old_vid);
805 } else
806 adapter->mng_vlan_id = vid;
807 }
808 }
809
810 /**
811 * igb_release_hw_control - release control of the h/w to f/w
812 * @adapter: address of board private structure
813 *
814 * igb_release_hw_control resets CTRL_EXT:DRV_LOAD bit.
815 * For ASF and Pass Through versions of f/w this means that the
816 * driver is no longer loaded.
817 *
818 **/
819 static void igb_release_hw_control(struct igb_adapter *adapter)
820 {
821 struct e1000_hw *hw = &adapter->hw;
822 u32 ctrl_ext;
823
824 /* Let firmware take over control of h/w */
825 ctrl_ext = rd32(E1000_CTRL_EXT);
826 wr32(E1000_CTRL_EXT,
827 ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD);
828 }
829
830
831 /**
832 * igb_get_hw_control - get control of the h/w from f/w
833 * @adapter: address of board private structure
834 *
835 * igb_get_hw_control sets CTRL_EXT:DRV_LOAD bit.
836 * For ASF and Pass Through versions of f/w this means that
837 * the driver is loaded.
838 *
839 **/
840 static void igb_get_hw_control(struct igb_adapter *adapter)
841 {
842 struct e1000_hw *hw = &adapter->hw;
843 u32 ctrl_ext;
844
845 /* Let firmware know the driver has taken over */
846 ctrl_ext = rd32(E1000_CTRL_EXT);
847 wr32(E1000_CTRL_EXT,
848 ctrl_ext | E1000_CTRL_EXT_DRV_LOAD);
849 }
850
851 /**
852 * igb_configure - configure the hardware for RX and TX
853 * @adapter: private board structure
854 **/
855 static void igb_configure(struct igb_adapter *adapter)
856 {
857 struct net_device *netdev = adapter->netdev;
858 int i;
859
860 igb_get_hw_control(adapter);
861 igb_set_multi(netdev);
862
863 igb_restore_vlan(adapter);
864
865 igb_configure_tx(adapter);
866 igb_setup_rctl(adapter);
867 igb_configure_rx(adapter);
868
869 igb_rx_fifo_flush_82575(&adapter->hw);
870
871 /* call IGB_DESC_UNUSED which always leaves
872 * at least 1 descriptor unused to make sure
873 * next_to_use != next_to_clean */
874 for (i = 0; i < adapter->num_rx_queues; i++) {
875 struct igb_ring *ring = &adapter->rx_ring[i];
876 igb_alloc_rx_buffers_adv(ring, IGB_DESC_UNUSED(ring));
877 }
878
879
880 adapter->tx_queue_len = netdev->tx_queue_len;
881 }
882
883
884 /**
885 * igb_up - Open the interface and prepare it to handle traffic
886 * @adapter: board private structure
887 **/
888
889 int igb_up(struct igb_adapter *adapter)
890 {
891 struct e1000_hw *hw = &adapter->hw;
892 int i;
893
894 /* hardware has been reset, we need to reload some things */
895 igb_configure(adapter);
896
897 clear_bit(__IGB_DOWN, &adapter->state);
898
899 for (i = 0; i < adapter->num_rx_queues; i++)
900 napi_enable(&adapter->rx_ring[i].napi);
901 if (adapter->msix_entries)
902 igb_configure_msix(adapter);
903
904 igb_vmm_control(adapter);
905 igb_set_rah_pool(hw, adapter->vfs_allocated_count, 0);
906 igb_set_vmolr(hw, adapter->vfs_allocated_count);
907
908 /* Clear any pending interrupts. */
909 rd32(E1000_ICR);
910 igb_irq_enable(adapter);
911
912 /* Fire a link change interrupt to start the watchdog. */
913 wr32(E1000_ICS, E1000_ICS_LSC);
914 return 0;
915 }
916
917 void igb_down(struct igb_adapter *adapter)
918 {
919 struct e1000_hw *hw = &adapter->hw;
920 struct net_device *netdev = adapter->netdev;
921 u32 tctl, rctl;
922 int i;
923
924 /* signal that we're down so the interrupt handler does not
925 * reschedule our watchdog timer */
926 set_bit(__IGB_DOWN, &adapter->state);
927
928 /* disable receives in the hardware */
929 rctl = rd32(E1000_RCTL);
930 wr32(E1000_RCTL, rctl & ~E1000_RCTL_EN);
931 /* flush and sleep below */
932
933 netif_tx_stop_all_queues(netdev);
934
935 /* disable transmits in the hardware */
936 tctl = rd32(E1000_TCTL);
937 tctl &= ~E1000_TCTL_EN;
938 wr32(E1000_TCTL, tctl);
939 /* flush both disables and wait for them to finish */
940 wrfl();
941 msleep(10);
942
943 for (i = 0; i < adapter->num_rx_queues; i++)
944 napi_disable(&adapter->rx_ring[i].napi);
945
946 igb_irq_disable(adapter);
947
948 del_timer_sync(&adapter->watchdog_timer);
949 del_timer_sync(&adapter->phy_info_timer);
950
951 netdev->tx_queue_len = adapter->tx_queue_len;
952 netif_carrier_off(netdev);
953
954 /* record the stats before reset*/
955 igb_update_stats(adapter);
956
957 adapter->link_speed = 0;
958 adapter->link_duplex = 0;
959
960 if (!pci_channel_offline(adapter->pdev))
961 igb_reset(adapter);
962 igb_clean_all_tx_rings(adapter);
963 igb_clean_all_rx_rings(adapter);
964 }
965
966 void igb_reinit_locked(struct igb_adapter *adapter)
967 {
968 WARN_ON(in_interrupt());
969 while (test_and_set_bit(__IGB_RESETTING, &adapter->state))
970 msleep(1);
971 igb_down(adapter);
972 igb_up(adapter);
973 clear_bit(__IGB_RESETTING, &adapter->state);
974 }
975
976 void igb_reset(struct igb_adapter *adapter)
977 {
978 struct e1000_hw *hw = &adapter->hw;
979 struct e1000_mac_info *mac = &hw->mac;
980 struct e1000_fc_info *fc = &hw->fc;
981 u32 pba = 0, tx_space, min_tx_space, min_rx_space;
982 u16 hwm;
983
984 /* Repartition Pba for greater than 9k mtu
985 * To take effect CTRL.RST is required.
986 */
987 switch (mac->type) {
988 case e1000_82576:
989 pba = E1000_PBA_64K;
990 break;
991 case e1000_82575:
992 default:
993 pba = E1000_PBA_34K;
994 break;
995 }
996
997 if ((adapter->max_frame_size > ETH_FRAME_LEN + ETH_FCS_LEN) &&
998 (mac->type < e1000_82576)) {
999 /* adjust PBA for jumbo frames */
1000 wr32(E1000_PBA, pba);
1001
1002 /* To maintain wire speed transmits, the Tx FIFO should be
1003 * large enough to accommodate two full transmit packets,
1004 * rounded up to the next 1KB and expressed in KB. Likewise,
1005 * the Rx FIFO should be large enough to accommodate at least
1006 * one full receive packet and is similarly rounded up and
1007 * expressed in KB. */
1008 pba = rd32(E1000_PBA);
1009 /* upper 16 bits has Tx packet buffer allocation size in KB */
1010 tx_space = pba >> 16;
1011 /* lower 16 bits has Rx packet buffer allocation size in KB */
1012 pba &= 0xffff;
1013 /* the tx fifo also stores 16 bytes of information about the tx
1014 * but don't include ethernet FCS because hardware appends it */
1015 min_tx_space = (adapter->max_frame_size +
1016 sizeof(union e1000_adv_tx_desc) -
1017 ETH_FCS_LEN) * 2;
1018 min_tx_space = ALIGN(min_tx_space, 1024);
1019 min_tx_space >>= 10;
1020 /* software strips receive CRC, so leave room for it */
1021 min_rx_space = adapter->max_frame_size;
1022 min_rx_space = ALIGN(min_rx_space, 1024);
1023 min_rx_space >>= 10;
1024
1025 /* If current Tx allocation is less than the min Tx FIFO size,
1026 * and the min Tx FIFO size is less than the current Rx FIFO
1027 * allocation, take space away from current Rx allocation */
1028 if (tx_space < min_tx_space &&
1029 ((min_tx_space - tx_space) < pba)) {
1030 pba = pba - (min_tx_space - tx_space);
1031
1032 /* if short on rx space, rx wins and must trump tx
1033 * adjustment */
1034 if (pba < min_rx_space)
1035 pba = min_rx_space;
1036 }
1037 wr32(E1000_PBA, pba);
1038 }
1039
1040 /* flow control settings */
1041 /* The high water mark must be low enough to fit one full frame
1042 * (or the size used for early receive) above it in the Rx FIFO.
1043 * Set it to the lower of:
1044 * - 90% of the Rx FIFO size, or
1045 * - the full Rx FIFO size minus one full frame */
1046 hwm = min(((pba << 10) * 9 / 10),
1047 ((pba << 10) - 2 * adapter->max_frame_size));
1048
1049 if (mac->type < e1000_82576) {
1050 fc->high_water = hwm & 0xFFF8; /* 8-byte granularity */
1051 fc->low_water = fc->high_water - 8;
1052 } else {
1053 fc->high_water = hwm & 0xFFF0; /* 16-byte granularity */
1054 fc->low_water = fc->high_water - 16;
1055 }
1056 fc->pause_time = 0xFFFF;
1057 fc->send_xon = 1;
1058 fc->type = fc->original_type;
1059
1060 /* disable receive for all VFs and wait one second */
1061 if (adapter->vfs_allocated_count) {
1062 int i;
1063 for (i = 0 ; i < adapter->vfs_allocated_count; i++)
1064 adapter->vf_data[i].clear_to_send = false;
1065
1066 /* ping all the active vfs to let them know we are going down */
1067 igb_ping_all_vfs(adapter);
1068
1069 /* disable transmits and receives */
1070 wr32(E1000_VFRE, 0);
1071 wr32(E1000_VFTE, 0);
1072 }
1073
1074 /* Allow time for pending master requests to run */
1075 adapter->hw.mac.ops.reset_hw(&adapter->hw);
1076 wr32(E1000_WUC, 0);
1077
1078 if (adapter->hw.mac.ops.init_hw(&adapter->hw))
1079 dev_err(&adapter->pdev->dev, "Hardware Error\n");
1080
1081 igb_update_mng_vlan(adapter);
1082
1083 /* Enable h/w to recognize an 802.1Q VLAN Ethernet packet */
1084 wr32(E1000_VET, ETHERNET_IEEE_VLAN_TYPE);
1085
1086 igb_reset_adaptive(&adapter->hw);
1087 igb_get_phy_info(&adapter->hw);
1088 }
1089
1090 static const struct net_device_ops igb_netdev_ops = {
1091 .ndo_open = igb_open,
1092 .ndo_stop = igb_close,
1093 .ndo_start_xmit = igb_xmit_frame_adv,
1094 .ndo_get_stats = igb_get_stats,
1095 .ndo_set_multicast_list = igb_set_multi,
1096 .ndo_set_mac_address = igb_set_mac,
1097 .ndo_change_mtu = igb_change_mtu,
1098 .ndo_do_ioctl = igb_ioctl,
1099 .ndo_tx_timeout = igb_tx_timeout,
1100 .ndo_validate_addr = eth_validate_addr,
1101 .ndo_vlan_rx_register = igb_vlan_rx_register,
1102 .ndo_vlan_rx_add_vid = igb_vlan_rx_add_vid,
1103 .ndo_vlan_rx_kill_vid = igb_vlan_rx_kill_vid,
1104 #ifdef CONFIG_NET_POLL_CONTROLLER
1105 .ndo_poll_controller = igb_netpoll,
1106 #endif
1107 };
1108
1109 /**
1110 * igb_probe - Device Initialization Routine
1111 * @pdev: PCI device information struct
1112 * @ent: entry in igb_pci_tbl
1113 *
1114 * Returns 0 on success, negative on failure
1115 *
1116 * igb_probe initializes an adapter identified by a pci_dev structure.
1117 * The OS initialization, configuring of the adapter private structure,
1118 * and a hardware reset occur.
1119 **/
1120 static int __devinit igb_probe(struct pci_dev *pdev,
1121 const struct pci_device_id *ent)
1122 {
1123 struct net_device *netdev;
1124 struct igb_adapter *adapter;
1125 struct e1000_hw *hw;
1126 struct pci_dev *us_dev;
1127 const struct e1000_info *ei = igb_info_tbl[ent->driver_data];
1128 unsigned long mmio_start, mmio_len;
1129 int err, pci_using_dac, pos;
1130 u16 eeprom_data = 0, state = 0;
1131 u16 eeprom_apme_mask = IGB_EEPROM_APME;
1132 u32 part_num;
1133
1134 err = pci_enable_device_mem(pdev);
1135 if (err)
1136 return err;
1137
1138 pci_using_dac = 0;
1139 err = pci_set_dma_mask(pdev, DMA_64BIT_MASK);
1140 if (!err) {
1141 err = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK);
1142 if (!err)
1143 pci_using_dac = 1;
1144 } else {
1145 err = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
1146 if (err) {
1147 err = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
1148 if (err) {
1149 dev_err(&pdev->dev, "No usable DMA "
1150 "configuration, aborting\n");
1151 goto err_dma;
1152 }
1153 }
1154 }
1155
1156 /* 82575 requires that the pci-e link partner disable the L0s state */
1157 switch (pdev->device) {
1158 case E1000_DEV_ID_82575EB_COPPER:
1159 case E1000_DEV_ID_82575EB_FIBER_SERDES:
1160 case E1000_DEV_ID_82575GB_QUAD_COPPER:
1161 us_dev = pdev->bus->self;
1162 pos = pci_find_capability(us_dev, PCI_CAP_ID_EXP);
1163 if (pos) {
1164 pci_read_config_word(us_dev, pos + PCI_EXP_LNKCTL,
1165 &state);
1166 state &= ~PCIE_LINK_STATE_L0S;
1167 pci_write_config_word(us_dev, pos + PCI_EXP_LNKCTL,
1168 state);
1169 dev_info(&pdev->dev,
1170 "Disabling ASPM L0s upstream switch port %s\n",
1171 pci_name(us_dev));
1172 }
1173 default:
1174 break;
1175 }
1176
1177 err = pci_request_selected_regions(pdev, pci_select_bars(pdev,
1178 IORESOURCE_MEM),
1179 igb_driver_name);
1180 if (err)
1181 goto err_pci_reg;
1182
1183 err = pci_enable_pcie_error_reporting(pdev);
1184 if (err) {
1185 dev_err(&pdev->dev, "pci_enable_pcie_error_reporting failed "
1186 "0x%x\n", err);
1187 /* non-fatal, continue */
1188 }
1189
1190 pci_set_master(pdev);
1191 pci_save_state(pdev);
1192
1193 err = -ENOMEM;
1194 netdev = alloc_etherdev_mq(sizeof(struct igb_adapter),
1195 IGB_ABS_MAX_TX_QUEUES);
1196 if (!netdev)
1197 goto err_alloc_etherdev;
1198
1199 SET_NETDEV_DEV(netdev, &pdev->dev);
1200
1201 pci_set_drvdata(pdev, netdev);
1202 adapter = netdev_priv(netdev);
1203 adapter->netdev = netdev;
1204 adapter->pdev = pdev;
1205 hw = &adapter->hw;
1206 hw->back = adapter;
1207 adapter->msg_enable = NETIF_MSG_DRV | NETIF_MSG_PROBE;
1208
1209 mmio_start = pci_resource_start(pdev, 0);
1210 mmio_len = pci_resource_len(pdev, 0);
1211
1212 err = -EIO;
1213 hw->hw_addr = ioremap(mmio_start, mmio_len);
1214 if (!hw->hw_addr)
1215 goto err_ioremap;
1216
1217 netdev->netdev_ops = &igb_netdev_ops;
1218 igb_set_ethtool_ops(netdev);
1219 netdev->watchdog_timeo = 5 * HZ;
1220
1221 strncpy(netdev->name, pci_name(pdev), sizeof(netdev->name) - 1);
1222
1223 netdev->mem_start = mmio_start;
1224 netdev->mem_end = mmio_start + mmio_len;
1225
1226 /* PCI config space info */
1227 hw->vendor_id = pdev->vendor;
1228 hw->device_id = pdev->device;
1229 hw->revision_id = pdev->revision;
1230 hw->subsystem_vendor_id = pdev->subsystem_vendor;
1231 hw->subsystem_device_id = pdev->subsystem_device;
1232
1233 /* setup the private structure */
1234 hw->back = adapter;
1235 /* Copy the default MAC, PHY and NVM function pointers */
1236 memcpy(&hw->mac.ops, ei->mac_ops, sizeof(hw->mac.ops));
1237 memcpy(&hw->phy.ops, ei->phy_ops, sizeof(hw->phy.ops));
1238 memcpy(&hw->nvm.ops, ei->nvm_ops, sizeof(hw->nvm.ops));
1239 /* Initialize skew-specific constants */
1240 err = ei->get_invariants(hw);
1241 if (err)
1242 goto err_sw_init;
1243
1244 /* setup the private structure */
1245 err = igb_sw_init(adapter);
1246 if (err)
1247 goto err_sw_init;
1248
1249 igb_get_bus_info_pcie(hw);
1250
1251 /* set flags */
1252 switch (hw->mac.type) {
1253 case e1000_82575:
1254 adapter->flags |= IGB_FLAG_NEED_CTX_IDX;
1255 break;
1256 case e1000_82576:
1257 default:
1258 break;
1259 }
1260
1261 hw->phy.autoneg_wait_to_complete = false;
1262 hw->mac.adaptive_ifs = true;
1263
1264 /* Copper options */
1265 if (hw->phy.media_type == e1000_media_type_copper) {
1266 hw->phy.mdix = AUTO_ALL_MODES;
1267 hw->phy.disable_polarity_correction = false;
1268 hw->phy.ms_type = e1000_ms_hw_default;
1269 }
1270
1271 if (igb_check_reset_block(hw))
1272 dev_info(&pdev->dev,
1273 "PHY reset is blocked due to SOL/IDER session.\n");
1274
1275 netdev->features = NETIF_F_SG |
1276 NETIF_F_IP_CSUM |
1277 NETIF_F_HW_VLAN_TX |
1278 NETIF_F_HW_VLAN_RX |
1279 NETIF_F_HW_VLAN_FILTER;
1280
1281 netdev->features |= NETIF_F_IPV6_CSUM;
1282 netdev->features |= NETIF_F_TSO;
1283 netdev->features |= NETIF_F_TSO6;
1284
1285 netdev->features |= NETIF_F_GRO;
1286
1287 netdev->vlan_features |= NETIF_F_TSO;
1288 netdev->vlan_features |= NETIF_F_TSO6;
1289 netdev->vlan_features |= NETIF_F_IP_CSUM;
1290 netdev->vlan_features |= NETIF_F_SG;
1291
1292 if (pci_using_dac)
1293 netdev->features |= NETIF_F_HIGHDMA;
1294
1295 adapter->en_mng_pt = igb_enable_mng_pass_thru(&adapter->hw);
1296
1297 /* before reading the NVM, reset the controller to put the device in a
1298 * known good starting state */
1299 hw->mac.ops.reset_hw(hw);
1300
1301 /* make sure the NVM is good */
1302 if (igb_validate_nvm_checksum(hw) < 0) {
1303 dev_err(&pdev->dev, "The NVM Checksum Is Not Valid\n");
1304 err = -EIO;
1305 goto err_eeprom;
1306 }
1307
1308 /* copy the MAC address out of the NVM */
1309 if (hw->mac.ops.read_mac_addr(hw))
1310 dev_err(&pdev->dev, "NVM Read Error\n");
1311
1312 memcpy(netdev->dev_addr, hw->mac.addr, netdev->addr_len);
1313 memcpy(netdev->perm_addr, hw->mac.addr, netdev->addr_len);
1314
1315 if (!is_valid_ether_addr(netdev->perm_addr)) {
1316 dev_err(&pdev->dev, "Invalid MAC Address\n");
1317 err = -EIO;
1318 goto err_eeprom;
1319 }
1320
1321 init_timer(&adapter->watchdog_timer);
1322 adapter->watchdog_timer.function = &igb_watchdog;
1323 adapter->watchdog_timer.data = (unsigned long) adapter;
1324
1325 init_timer(&adapter->phy_info_timer);
1326 adapter->phy_info_timer.function = &igb_update_phy_info;
1327 adapter->phy_info_timer.data = (unsigned long) adapter;
1328
1329 INIT_WORK(&adapter->reset_task, igb_reset_task);
1330 INIT_WORK(&adapter->watchdog_task, igb_watchdog_task);
1331
1332 /* Initialize link properties that are user-changeable */
1333 adapter->fc_autoneg = true;
1334 hw->mac.autoneg = true;
1335 hw->phy.autoneg_advertised = 0x2f;
1336
1337 hw->fc.original_type = e1000_fc_default;
1338 hw->fc.type = e1000_fc_default;
1339
1340 adapter->itr_setting = IGB_DEFAULT_ITR;
1341 adapter->itr = IGB_START_ITR;
1342
1343 igb_validate_mdi_setting(hw);
1344
1345 adapter->rx_csum = 1;
1346
1347 /* Initial Wake on LAN setting If APM wake is enabled in the EEPROM,
1348 * enable the ACPI Magic Packet filter
1349 */
1350
1351 if (hw->bus.func == 0 ||
1352 hw->device_id == E1000_DEV_ID_82575EB_COPPER)
1353 hw->nvm.ops.read(hw, NVM_INIT_CONTROL3_PORT_A, 1, &eeprom_data);
1354
1355 if (eeprom_data & eeprom_apme_mask)
1356 adapter->eeprom_wol |= E1000_WUFC_MAG;
1357
1358 /* now that we have the eeprom settings, apply the special cases where
1359 * the eeprom may be wrong or the board simply won't support wake on
1360 * lan on a particular port */
1361 switch (pdev->device) {
1362 case E1000_DEV_ID_82575GB_QUAD_COPPER:
1363 adapter->eeprom_wol = 0;
1364 break;
1365 case E1000_DEV_ID_82575EB_FIBER_SERDES:
1366 case E1000_DEV_ID_82576_FIBER:
1367 case E1000_DEV_ID_82576_SERDES:
1368 /* Wake events only supported on port A for dual fiber
1369 * regardless of eeprom setting */
1370 if (rd32(E1000_STATUS) & E1000_STATUS_FUNC_1)
1371 adapter->eeprom_wol = 0;
1372 break;
1373 }
1374
1375 /* initialize the wol settings based on the eeprom settings */
1376 adapter->wol = adapter->eeprom_wol;
1377 device_set_wakeup_enable(&adapter->pdev->dev, adapter->wol);
1378
1379 /* reset the hardware with the new settings */
1380 igb_reset(adapter);
1381
1382 /* let the f/w know that the h/w is now under the control of the
1383 * driver. */
1384 igb_get_hw_control(adapter);
1385
1386 /* tell the stack to leave us alone until igb_open() is called */
1387 netif_carrier_off(netdev);
1388 netif_tx_stop_all_queues(netdev);
1389
1390 strcpy(netdev->name, "eth%d");
1391 err = register_netdev(netdev);
1392 if (err)
1393 goto err_register;
1394
1395 #ifdef CONFIG_IGB_DCA
1396 if (dca_add_requester(&pdev->dev) == 0) {
1397 adapter->flags |= IGB_FLAG_DCA_ENABLED;
1398 dev_info(&pdev->dev, "DCA enabled\n");
1399 /* Always use CB2 mode, difference is masked
1400 * in the CB driver. */
1401 wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_CB2);
1402 igb_setup_dca(adapter);
1403 }
1404 #endif
1405
1406 /*
1407 * Initialize hardware timer: we keep it running just in case
1408 * that some program needs it later on.
1409 */
1410 memset(&adapter->cycles, 0, sizeof(adapter->cycles));
1411 adapter->cycles.read = igb_read_clock;
1412 adapter->cycles.mask = CLOCKSOURCE_MASK(64);
1413 adapter->cycles.mult = 1;
1414 adapter->cycles.shift = IGB_TSYNC_SHIFT;
1415 wr32(E1000_TIMINCA,
1416 (1<<24) |
1417 IGB_TSYNC_CYCLE_TIME_IN_NANOSECONDS * IGB_TSYNC_SCALE);
1418 #if 0
1419 /*
1420 * Avoid rollover while we initialize by resetting the time counter.
1421 */
1422 wr32(E1000_SYSTIML, 0x00000000);
1423 wr32(E1000_SYSTIMH, 0x00000000);
1424 #else
1425 /*
1426 * Set registers so that rollover occurs soon to test this.
1427 */
1428 wr32(E1000_SYSTIML, 0x00000000);
1429 wr32(E1000_SYSTIMH, 0xFF800000);
1430 #endif
1431 wrfl();
1432 timecounter_init(&adapter->clock,
1433 &adapter->cycles,
1434 ktime_to_ns(ktime_get_real()));
1435
1436 /*
1437 * Synchronize our NIC clock against system wall clock. NIC
1438 * time stamp reading requires ~3us per sample, each sample
1439 * was pretty stable even under load => only require 10
1440 * samples for each offset comparison.
1441 */
1442 memset(&adapter->compare, 0, sizeof(adapter->compare));
1443 adapter->compare.source = &adapter->clock;
1444 adapter->compare.target = ktime_get_real;
1445 adapter->compare.num_samples = 10;
1446 timecompare_update(&adapter->compare, 0);
1447
1448 #ifdef DEBUG
1449 {
1450 char buffer[160];
1451 printk(KERN_DEBUG
1452 "igb: %s: hw %p initialized timer\n",
1453 igb_get_time_str(adapter, buffer),
1454 &adapter->hw);
1455 }
1456 #endif
1457
1458 dev_info(&pdev->dev, "Intel(R) Gigabit Ethernet Network Connection\n");
1459 /* print bus type/speed/width info */
1460 dev_info(&pdev->dev, "%s: (PCIe:%s:%s) %pM\n",
1461 netdev->name,
1462 ((hw->bus.speed == e1000_bus_speed_2500)
1463 ? "2.5Gb/s" : "unknown"),
1464 ((hw->bus.width == e1000_bus_width_pcie_x4)
1465 ? "Width x4" : (hw->bus.width == e1000_bus_width_pcie_x1)
1466 ? "Width x1" : "unknown"),
1467 netdev->dev_addr);
1468
1469 igb_read_part_num(hw, &part_num);
1470 dev_info(&pdev->dev, "%s: PBA No: %06x-%03x\n", netdev->name,
1471 (part_num >> 8), (part_num & 0xff));
1472
1473 dev_info(&pdev->dev,
1474 "Using %s interrupts. %d rx queue(s), %d tx queue(s)\n",
1475 adapter->msix_entries ? "MSI-X" :
1476 (adapter->flags & IGB_FLAG_HAS_MSI) ? "MSI" : "legacy",
1477 adapter->num_rx_queues, adapter->num_tx_queues);
1478
1479 return 0;
1480
1481 err_register:
1482 igb_release_hw_control(adapter);
1483 err_eeprom:
1484 if (!igb_check_reset_block(hw))
1485 igb_reset_phy(hw);
1486
1487 if (hw->flash_address)
1488 iounmap(hw->flash_address);
1489
1490 igb_free_queues(adapter);
1491 err_sw_init:
1492 iounmap(hw->hw_addr);
1493 err_ioremap:
1494 free_netdev(netdev);
1495 err_alloc_etherdev:
1496 pci_release_selected_regions(pdev, pci_select_bars(pdev,
1497 IORESOURCE_MEM));
1498 err_pci_reg:
1499 err_dma:
1500 pci_disable_device(pdev);
1501 return err;
1502 }
1503
1504 /**
1505 * igb_remove - Device Removal Routine
1506 * @pdev: PCI device information struct
1507 *
1508 * igb_remove is called by the PCI subsystem to alert the driver
1509 * that it should release a PCI device. The could be caused by a
1510 * Hot-Plug event, or because the driver is going to be removed from
1511 * memory.
1512 **/
1513 static void __devexit igb_remove(struct pci_dev *pdev)
1514 {
1515 struct net_device *netdev = pci_get_drvdata(pdev);
1516 struct igb_adapter *adapter = netdev_priv(netdev);
1517 struct e1000_hw *hw = &adapter->hw;
1518 int err;
1519
1520 /* flush_scheduled work may reschedule our watchdog task, so
1521 * explicitly disable watchdog tasks from being rescheduled */
1522 set_bit(__IGB_DOWN, &adapter->state);
1523 del_timer_sync(&adapter->watchdog_timer);
1524 del_timer_sync(&adapter->phy_info_timer);
1525
1526 flush_scheduled_work();
1527
1528 #ifdef CONFIG_IGB_DCA
1529 if (adapter->flags & IGB_FLAG_DCA_ENABLED) {
1530 dev_info(&pdev->dev, "DCA disabled\n");
1531 dca_remove_requester(&pdev->dev);
1532 adapter->flags &= ~IGB_FLAG_DCA_ENABLED;
1533 wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_DISABLE);
1534 }
1535 #endif
1536
1537 /* Release control of h/w to f/w. If f/w is AMT enabled, this
1538 * would have already happened in close and is redundant. */
1539 igb_release_hw_control(adapter);
1540
1541 unregister_netdev(netdev);
1542
1543 if (!igb_check_reset_block(&adapter->hw))
1544 igb_reset_phy(&adapter->hw);
1545
1546 igb_reset_interrupt_capability(adapter);
1547
1548 igb_free_queues(adapter);
1549
1550 iounmap(hw->hw_addr);
1551 if (hw->flash_address)
1552 iounmap(hw->flash_address);
1553 pci_release_selected_regions(pdev, pci_select_bars(pdev,
1554 IORESOURCE_MEM));
1555
1556 free_netdev(netdev);
1557
1558 err = pci_disable_pcie_error_reporting(pdev);
1559 if (err)
1560 dev_err(&pdev->dev,
1561 "pci_disable_pcie_error_reporting failed 0x%x\n", err);
1562
1563 pci_disable_device(pdev);
1564 }
1565
1566 /**
1567 * igb_sw_init - Initialize general software structures (struct igb_adapter)
1568 * @adapter: board private structure to initialize
1569 *
1570 * igb_sw_init initializes the Adapter private data structure.
1571 * Fields are initialized based on PCI device information and
1572 * OS network device settings (MTU size).
1573 **/
1574 static int __devinit igb_sw_init(struct igb_adapter *adapter)
1575 {
1576 struct e1000_hw *hw = &adapter->hw;
1577 struct net_device *netdev = adapter->netdev;
1578 struct pci_dev *pdev = adapter->pdev;
1579
1580 pci_read_config_word(pdev, PCI_COMMAND, &hw->bus.pci_cmd_word);
1581
1582 adapter->tx_ring_count = IGB_DEFAULT_TXD;
1583 adapter->rx_ring_count = IGB_DEFAULT_RXD;
1584 adapter->rx_buffer_len = MAXIMUM_ETHERNET_VLAN_SIZE;
1585 adapter->rx_ps_hdr_size = 0; /* disable packet split */
1586 adapter->max_frame_size = netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
1587 adapter->min_frame_size = ETH_ZLEN + ETH_FCS_LEN;
1588
1589 /* This call may decrease the number of queues depending on
1590 * interrupt mode. */
1591 igb_set_interrupt_capability(adapter);
1592
1593 if (igb_alloc_queues(adapter)) {
1594 dev_err(&pdev->dev, "Unable to allocate memory for queues\n");
1595 return -ENOMEM;
1596 }
1597
1598 /* Explicitly disable IRQ since the NIC can be in any state. */
1599 igb_irq_disable(adapter);
1600
1601 set_bit(__IGB_DOWN, &adapter->state);
1602 return 0;
1603 }
1604
1605 /**
1606 * igb_open - Called when a network interface is made active
1607 * @netdev: network interface device structure
1608 *
1609 * Returns 0 on success, negative value on failure
1610 *
1611 * The open entry point is called when a network interface is made
1612 * active by the system (IFF_UP). At this point all resources needed
1613 * for transmit and receive operations are allocated, the interrupt
1614 * handler is registered with the OS, the watchdog timer is started,
1615 * and the stack is notified that the interface is ready.
1616 **/
1617 static int igb_open(struct net_device *netdev)
1618 {
1619 struct igb_adapter *adapter = netdev_priv(netdev);
1620 struct e1000_hw *hw = &adapter->hw;
1621 int err;
1622 int i;
1623
1624 /* disallow open during test */
1625 if (test_bit(__IGB_TESTING, &adapter->state))
1626 return -EBUSY;
1627
1628 /* allocate transmit descriptors */
1629 err = igb_setup_all_tx_resources(adapter);
1630 if (err)
1631 goto err_setup_tx;
1632
1633 /* allocate receive descriptors */
1634 err = igb_setup_all_rx_resources(adapter);
1635 if (err)
1636 goto err_setup_rx;
1637
1638 /* e1000_power_up_phy(adapter); */
1639
1640 adapter->mng_vlan_id = IGB_MNG_VLAN_NONE;
1641 if ((adapter->hw.mng_cookie.status &
1642 E1000_MNG_DHCP_COOKIE_STATUS_VLAN))
1643 igb_update_mng_vlan(adapter);
1644
1645 /* before we allocate an interrupt, we must be ready to handle it.
1646 * Setting DEBUG_SHIRQ in the kernel makes it fire an interrupt
1647 * as soon as we call pci_request_irq, so we have to setup our
1648 * clean_rx handler before we do so. */
1649 igb_configure(adapter);
1650
1651 igb_vmm_control(adapter);
1652 igb_set_rah_pool(hw, adapter->vfs_allocated_count, 0);
1653 igb_set_vmolr(hw, adapter->vfs_allocated_count);
1654
1655 err = igb_request_irq(adapter);
1656 if (err)
1657 goto err_req_irq;
1658
1659 /* From here on the code is the same as igb_up() */
1660 clear_bit(__IGB_DOWN, &adapter->state);
1661
1662 for (i = 0; i < adapter->num_rx_queues; i++)
1663 napi_enable(&adapter->rx_ring[i].napi);
1664
1665 /* Clear any pending interrupts. */
1666 rd32(E1000_ICR);
1667
1668 igb_irq_enable(adapter);
1669
1670 netif_tx_start_all_queues(netdev);
1671
1672 /* Fire a link status change interrupt to start the watchdog. */
1673 wr32(E1000_ICS, E1000_ICS_LSC);
1674
1675 return 0;
1676
1677 err_req_irq:
1678 igb_release_hw_control(adapter);
1679 /* e1000_power_down_phy(adapter); */
1680 igb_free_all_rx_resources(adapter);
1681 err_setup_rx:
1682 igb_free_all_tx_resources(adapter);
1683 err_setup_tx:
1684 igb_reset(adapter);
1685
1686 return err;
1687 }
1688
1689 /**
1690 * igb_close - Disables a network interface
1691 * @netdev: network interface device structure
1692 *
1693 * Returns 0, this is not allowed to fail
1694 *
1695 * The close entry point is called when an interface is de-activated
1696 * by the OS. The hardware is still under the driver's control, but
1697 * needs to be disabled. A global MAC reset is issued to stop the
1698 * hardware, and all transmit and receive resources are freed.
1699 **/
1700 static int igb_close(struct net_device *netdev)
1701 {
1702 struct igb_adapter *adapter = netdev_priv(netdev);
1703
1704 WARN_ON(test_bit(__IGB_RESETTING, &adapter->state));
1705 igb_down(adapter);
1706
1707 igb_free_irq(adapter);
1708
1709 igb_free_all_tx_resources(adapter);
1710 igb_free_all_rx_resources(adapter);
1711
1712 /* kill manageability vlan ID if supported, but not if a vlan with
1713 * the same ID is registered on the host OS (let 8021q kill it) */
1714 if ((adapter->hw.mng_cookie.status &
1715 E1000_MNG_DHCP_COOKIE_STATUS_VLAN) &&
1716 !(adapter->vlgrp &&
1717 vlan_group_get_device(adapter->vlgrp, adapter->mng_vlan_id)))
1718 igb_vlan_rx_kill_vid(netdev, adapter->mng_vlan_id);
1719
1720 return 0;
1721 }
1722
1723 /**
1724 * igb_setup_tx_resources - allocate Tx resources (Descriptors)
1725 * @adapter: board private structure
1726 * @tx_ring: tx descriptor ring (for a specific queue) to setup
1727 *
1728 * Return 0 on success, negative on failure
1729 **/
1730 int igb_setup_tx_resources(struct igb_adapter *adapter,
1731 struct igb_ring *tx_ring)
1732 {
1733 struct pci_dev *pdev = adapter->pdev;
1734 int size;
1735
1736 size = sizeof(struct igb_buffer) * tx_ring->count;
1737 tx_ring->buffer_info = vmalloc(size);
1738 if (!tx_ring->buffer_info)
1739 goto err;
1740 memset(tx_ring->buffer_info, 0, size);
1741
1742 /* round up to nearest 4K */
1743 tx_ring->size = tx_ring->count * sizeof(union e1000_adv_tx_desc);
1744 tx_ring->size = ALIGN(tx_ring->size, 4096);
1745
1746 tx_ring->desc = pci_alloc_consistent(pdev, tx_ring->size,
1747 &tx_ring->dma);
1748
1749 if (!tx_ring->desc)
1750 goto err;
1751
1752 tx_ring->adapter = adapter;
1753 tx_ring->next_to_use = 0;
1754 tx_ring->next_to_clean = 0;
1755 return 0;
1756
1757 err:
1758 vfree(tx_ring->buffer_info);
1759 dev_err(&adapter->pdev->dev,
1760 "Unable to allocate memory for the transmit descriptor ring\n");
1761 return -ENOMEM;
1762 }
1763
1764 /**
1765 * igb_setup_all_tx_resources - wrapper to allocate Tx resources
1766 * (Descriptors) for all queues
1767 * @adapter: board private structure
1768 *
1769 * Return 0 on success, negative on failure
1770 **/
1771 static int igb_setup_all_tx_resources(struct igb_adapter *adapter)
1772 {
1773 int i, err = 0;
1774 int r_idx;
1775
1776 for (i = 0; i < adapter->num_tx_queues; i++) {
1777 err = igb_setup_tx_resources(adapter, &adapter->tx_ring[i]);
1778 if (err) {
1779 dev_err(&adapter->pdev->dev,
1780 "Allocation for Tx Queue %u failed\n", i);
1781 for (i--; i >= 0; i--)
1782 igb_free_tx_resources(&adapter->tx_ring[i]);
1783 break;
1784 }
1785 }
1786
1787 for (i = 0; i < IGB_MAX_TX_QUEUES; i++) {
1788 r_idx = i % adapter->num_tx_queues;
1789 adapter->multi_tx_table[i] = &adapter->tx_ring[r_idx];
1790 }
1791 return err;
1792 }
1793
1794 /**
1795 * igb_configure_tx - Configure transmit Unit after Reset
1796 * @adapter: board private structure
1797 *
1798 * Configure the Tx unit of the MAC after a reset.
1799 **/
1800 static void igb_configure_tx(struct igb_adapter *adapter)
1801 {
1802 u64 tdba;
1803 struct e1000_hw *hw = &adapter->hw;
1804 u32 tctl;
1805 u32 txdctl, txctrl;
1806 int i, j;
1807
1808 for (i = 0; i < adapter->num_tx_queues; i++) {
1809 struct igb_ring *ring = &adapter->tx_ring[i];
1810 j = ring->reg_idx;
1811 wr32(E1000_TDLEN(j),
1812 ring->count * sizeof(union e1000_adv_tx_desc));
1813 tdba = ring->dma;
1814 wr32(E1000_TDBAL(j),
1815 tdba & 0x00000000ffffffffULL);
1816 wr32(E1000_TDBAH(j), tdba >> 32);
1817
1818 ring->head = E1000_TDH(j);
1819 ring->tail = E1000_TDT(j);
1820 writel(0, hw->hw_addr + ring->tail);
1821 writel(0, hw->hw_addr + ring->head);
1822 txdctl = rd32(E1000_TXDCTL(j));
1823 txdctl |= E1000_TXDCTL_QUEUE_ENABLE;
1824 wr32(E1000_TXDCTL(j), txdctl);
1825
1826 /* Turn off Relaxed Ordering on head write-backs. The
1827 * writebacks MUST be delivered in order or it will
1828 * completely screw up our bookeeping.
1829 */
1830 txctrl = rd32(E1000_DCA_TXCTRL(j));
1831 txctrl &= ~E1000_DCA_TXCTRL_TX_WB_RO_EN;
1832 wr32(E1000_DCA_TXCTRL(j), txctrl);
1833 }
1834
1835 /* disable queue 0 to prevent tail bump w/o re-configuration */
1836 if (adapter->vfs_allocated_count)
1837 wr32(E1000_TXDCTL(0), 0);
1838
1839 /* Program the Transmit Control Register */
1840 tctl = rd32(E1000_TCTL);
1841 tctl &= ~E1000_TCTL_CT;
1842 tctl |= E1000_TCTL_PSP | E1000_TCTL_RTLC |
1843 (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT);
1844
1845 igb_config_collision_dist(hw);
1846
1847 /* Setup Transmit Descriptor Settings for eop descriptor */
1848 adapter->txd_cmd = E1000_TXD_CMD_EOP | E1000_TXD_CMD_RS;
1849
1850 /* Enable transmits */
1851 tctl |= E1000_TCTL_EN;
1852
1853 wr32(E1000_TCTL, tctl);
1854 }
1855
1856 /**
1857 * igb_setup_rx_resources - allocate Rx resources (Descriptors)
1858 * @adapter: board private structure
1859 * @rx_ring: rx descriptor ring (for a specific queue) to setup
1860 *
1861 * Returns 0 on success, negative on failure
1862 **/
1863 int igb_setup_rx_resources(struct igb_adapter *adapter,
1864 struct igb_ring *rx_ring)
1865 {
1866 struct pci_dev *pdev = adapter->pdev;
1867 int size, desc_len;
1868
1869 size = sizeof(struct igb_buffer) * rx_ring->count;
1870 rx_ring->buffer_info = vmalloc(size);
1871 if (!rx_ring->buffer_info)
1872 goto err;
1873 memset(rx_ring->buffer_info, 0, size);
1874
1875 desc_len = sizeof(union e1000_adv_rx_desc);
1876
1877 /* Round up to nearest 4K */
1878 rx_ring->size = rx_ring->count * desc_len;
1879 rx_ring->size = ALIGN(rx_ring->size, 4096);
1880
1881 rx_ring->desc = pci_alloc_consistent(pdev, rx_ring->size,
1882 &rx_ring->dma);
1883
1884 if (!rx_ring->desc)
1885 goto err;
1886
1887 rx_ring->next_to_clean = 0;
1888 rx_ring->next_to_use = 0;
1889
1890 rx_ring->adapter = adapter;
1891
1892 return 0;
1893
1894 err:
1895 vfree(rx_ring->buffer_info);
1896 dev_err(&adapter->pdev->dev, "Unable to allocate memory for "
1897 "the receive descriptor ring\n");
1898 return -ENOMEM;
1899 }
1900
1901 /**
1902 * igb_setup_all_rx_resources - wrapper to allocate Rx resources
1903 * (Descriptors) for all queues
1904 * @adapter: board private structure
1905 *
1906 * Return 0 on success, negative on failure
1907 **/
1908 static int igb_setup_all_rx_resources(struct igb_adapter *adapter)
1909 {
1910 int i, err = 0;
1911
1912 for (i = 0; i < adapter->num_rx_queues; i++) {
1913 err = igb_setup_rx_resources(adapter, &adapter->rx_ring[i]);
1914 if (err) {
1915 dev_err(&adapter->pdev->dev,
1916 "Allocation for Rx Queue %u failed\n", i);
1917 for (i--; i >= 0; i--)
1918 igb_free_rx_resources(&adapter->rx_ring[i]);
1919 break;
1920 }
1921 }
1922
1923 return err;
1924 }
1925
1926 /**
1927 * igb_setup_rctl - configure the receive control registers
1928 * @adapter: Board private structure
1929 **/
1930 static void igb_setup_rctl(struct igb_adapter *adapter)
1931 {
1932 struct e1000_hw *hw = &adapter->hw;
1933 u32 rctl;
1934 u32 srrctl = 0;
1935 int i, j;
1936
1937 rctl = rd32(E1000_RCTL);
1938
1939 rctl &= ~(3 << E1000_RCTL_MO_SHIFT);
1940 rctl &= ~(E1000_RCTL_LBM_TCVR | E1000_RCTL_LBM_MAC);
1941
1942 rctl |= E1000_RCTL_EN | E1000_RCTL_BAM | E1000_RCTL_RDMTS_HALF |
1943 (hw->mac.mc_filter_type << E1000_RCTL_MO_SHIFT);
1944
1945 /*
1946 * enable stripping of CRC. It's unlikely this will break BMC
1947 * redirection as it did with e1000. Newer features require
1948 * that the HW strips the CRC.
1949 */
1950 rctl |= E1000_RCTL_SECRC;
1951
1952 /*
1953 * disable store bad packets and clear size bits.
1954 */
1955 rctl &= ~(E1000_RCTL_SBP | E1000_RCTL_SZ_256);
1956
1957 /* enable LPE when to prevent packets larger than max_frame_size */
1958 rctl |= E1000_RCTL_LPE;
1959
1960 /* Setup buffer sizes */
1961 switch (adapter->rx_buffer_len) {
1962 case IGB_RXBUFFER_256:
1963 rctl |= E1000_RCTL_SZ_256;
1964 break;
1965 case IGB_RXBUFFER_512:
1966 rctl |= E1000_RCTL_SZ_512;
1967 break;
1968 default:
1969 srrctl = ALIGN(adapter->rx_buffer_len, 1024)
1970 >> E1000_SRRCTL_BSIZEPKT_SHIFT;
1971 break;
1972 }
1973
1974 /* 82575 and greater support packet-split where the protocol
1975 * header is placed in skb->data and the packet data is
1976 * placed in pages hanging off of skb_shinfo(skb)->nr_frags.
1977 * In the case of a non-split, skb->data is linearly filled,
1978 * followed by the page buffers. Therefore, skb->data is
1979 * sized to hold the largest protocol header.
1980 */
1981 /* allocations using alloc_page take too long for regular MTU
1982 * so only enable packet split for jumbo frames */
1983 if (adapter->netdev->mtu > ETH_DATA_LEN) {
1984 adapter->rx_ps_hdr_size = IGB_RXBUFFER_128;
1985 srrctl |= adapter->rx_ps_hdr_size <<
1986 E1000_SRRCTL_BSIZEHDRSIZE_SHIFT;
1987 srrctl |= E1000_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS;
1988 } else {
1989 adapter->rx_ps_hdr_size = 0;
1990 srrctl |= E1000_SRRCTL_DESCTYPE_ADV_ONEBUF;
1991 }
1992
1993 /* Attention!!! For SR-IOV PF driver operations you must enable
1994 * queue drop for all VF and PF queues to prevent head of line blocking
1995 * if an un-trusted VF does not provide descriptors to hardware.
1996 */
1997 if (adapter->vfs_allocated_count) {
1998 u32 vmolr;
1999
2000 j = adapter->rx_ring[0].reg_idx;
2001
2002 /* set all queue drop enable bits */
2003 wr32(E1000_QDE, ALL_QUEUES);
2004 srrctl |= E1000_SRRCTL_DROP_EN;
2005
2006 /* disable queue 0 to prevent tail write w/o re-config */
2007 wr32(E1000_RXDCTL(0), 0);
2008
2009 vmolr = rd32(E1000_VMOLR(j));
2010 if (rctl & E1000_RCTL_LPE)
2011 vmolr |= E1000_VMOLR_LPE;
2012 if (adapter->num_rx_queues > 0)
2013 vmolr |= E1000_VMOLR_RSSE;
2014 wr32(E1000_VMOLR(j), vmolr);
2015 }
2016
2017 for (i = 0; i < adapter->num_rx_queues; i++) {
2018 j = adapter->rx_ring[i].reg_idx;
2019 wr32(E1000_SRRCTL(j), srrctl);
2020 }
2021
2022 wr32(E1000_RCTL, rctl);
2023 }
2024
2025 /**
2026 * igb_rlpml_set - set maximum receive packet size
2027 * @adapter: board private structure
2028 *
2029 * Configure maximum receivable packet size.
2030 **/
2031 static void igb_rlpml_set(struct igb_adapter *adapter)
2032 {
2033 u32 max_frame_size = adapter->max_frame_size;
2034 struct e1000_hw *hw = &adapter->hw;
2035 u16 pf_id = adapter->vfs_allocated_count;
2036
2037 if (adapter->vlgrp)
2038 max_frame_size += VLAN_TAG_SIZE;
2039
2040 /* if vfs are enabled we set RLPML to the largest possible request
2041 * size and set the VMOLR RLPML to the size we need */
2042 if (pf_id) {
2043 igb_set_vf_rlpml(adapter, max_frame_size, pf_id);
2044 max_frame_size = MAX_STD_JUMBO_FRAME_SIZE + VLAN_TAG_SIZE;
2045 }
2046
2047 wr32(E1000_RLPML, max_frame_size);
2048 }
2049
2050 /**
2051 * igb_configure_vt_default_pool - Configure VT default pool
2052 * @adapter: board private structure
2053 *
2054 * Configure the default pool
2055 **/
2056 static void igb_configure_vt_default_pool(struct igb_adapter *adapter)
2057 {
2058 struct e1000_hw *hw = &adapter->hw;
2059 u16 pf_id = adapter->vfs_allocated_count;
2060 u32 vtctl;
2061
2062 /* not in sr-iov mode - do nothing */
2063 if (!pf_id)
2064 return;
2065
2066 vtctl = rd32(E1000_VT_CTL);
2067 vtctl &= ~(E1000_VT_CTL_DEFAULT_POOL_MASK |
2068 E1000_VT_CTL_DISABLE_DEF_POOL);
2069 vtctl |= pf_id << E1000_VT_CTL_DEFAULT_POOL_SHIFT;
2070 wr32(E1000_VT_CTL, vtctl);
2071 }
2072
2073 /**
2074 * igb_configure_rx - Configure receive Unit after Reset
2075 * @adapter: board private structure
2076 *
2077 * Configure the Rx unit of the MAC after a reset.
2078 **/
2079 static void igb_configure_rx(struct igb_adapter *adapter)
2080 {
2081 u64 rdba;
2082 struct e1000_hw *hw = &adapter->hw;
2083 u32 rctl, rxcsum;
2084 u32 rxdctl;
2085 int i;
2086
2087 /* disable receives while setting up the descriptors */
2088 rctl = rd32(E1000_RCTL);
2089 wr32(E1000_RCTL, rctl & ~E1000_RCTL_EN);
2090 wrfl();
2091 mdelay(10);
2092
2093 if (adapter->itr_setting > 3)
2094 wr32(E1000_ITR, adapter->itr);
2095
2096 /* Setup the HW Rx Head and Tail Descriptor Pointers and
2097 * the Base and Length of the Rx Descriptor Ring */
2098 for (i = 0; i < adapter->num_rx_queues; i++) {
2099 struct igb_ring *ring = &adapter->rx_ring[i];
2100 int j = ring->reg_idx;
2101 rdba = ring->dma;
2102 wr32(E1000_RDBAL(j),
2103 rdba & 0x00000000ffffffffULL);
2104 wr32(E1000_RDBAH(j), rdba >> 32);
2105 wr32(E1000_RDLEN(j),
2106 ring->count * sizeof(union e1000_adv_rx_desc));
2107
2108 ring->head = E1000_RDH(j);
2109 ring->tail = E1000_RDT(j);
2110 writel(0, hw->hw_addr + ring->tail);
2111 writel(0, hw->hw_addr + ring->head);
2112
2113 rxdctl = rd32(E1000_RXDCTL(j));
2114 rxdctl |= E1000_RXDCTL_QUEUE_ENABLE;
2115 rxdctl &= 0xFFF00000;
2116 rxdctl |= IGB_RX_PTHRESH;
2117 rxdctl |= IGB_RX_HTHRESH << 8;
2118 rxdctl |= IGB_RX_WTHRESH << 16;
2119 wr32(E1000_RXDCTL(j), rxdctl);
2120 }
2121
2122 if (adapter->num_rx_queues > 1) {
2123 u32 random[10];
2124 u32 mrqc;
2125 u32 j, shift;
2126 union e1000_reta {
2127 u32 dword;
2128 u8 bytes[4];
2129 } reta;
2130
2131 get_random_bytes(&random[0], 40);
2132
2133 if (hw->mac.type >= e1000_82576)
2134 shift = 0;
2135 else
2136 shift = 6;
2137 for (j = 0; j < (32 * 4); j++) {
2138 reta.bytes[j & 3] =
2139 adapter->rx_ring[(j % adapter->num_rx_queues)].reg_idx << shift;
2140 if ((j & 3) == 3)
2141 writel(reta.dword,
2142 hw->hw_addr + E1000_RETA(0) + (j & ~3));
2143 }
2144 if (adapter->vfs_allocated_count)
2145 mrqc = E1000_MRQC_ENABLE_VMDQ_RSS_2Q;
2146 else
2147 mrqc = E1000_MRQC_ENABLE_RSS_4Q;
2148
2149 /* Fill out hash function seeds */
2150 for (j = 0; j < 10; j++)
2151 array_wr32(E1000_RSSRK(0), j, random[j]);
2152
2153 mrqc |= (E1000_MRQC_RSS_FIELD_IPV4 |
2154 E1000_MRQC_RSS_FIELD_IPV4_TCP);
2155 mrqc |= (E1000_MRQC_RSS_FIELD_IPV6 |
2156 E1000_MRQC_RSS_FIELD_IPV6_TCP);
2157 mrqc |= (E1000_MRQC_RSS_FIELD_IPV4_UDP |
2158 E1000_MRQC_RSS_FIELD_IPV6_UDP);
2159 mrqc |= (E1000_MRQC_RSS_FIELD_IPV6_UDP_EX |
2160 E1000_MRQC_RSS_FIELD_IPV6_TCP_EX);
2161
2162
2163 wr32(E1000_MRQC, mrqc);
2164
2165 /* Multiqueue and raw packet checksumming are mutually
2166 * exclusive. Note that this not the same as TCP/IP
2167 * checksumming, which works fine. */
2168 rxcsum = rd32(E1000_RXCSUM);
2169 rxcsum |= E1000_RXCSUM_PCSD;
2170 wr32(E1000_RXCSUM, rxcsum);
2171 } else {
2172 /* Enable multi-queue for sr-iov */
2173 if (adapter->vfs_allocated_count)
2174 wr32(E1000_MRQC, E1000_MRQC_ENABLE_VMDQ);
2175 /* Enable Receive Checksum Offload for TCP and UDP */
2176 rxcsum = rd32(E1000_RXCSUM);
2177 if (adapter->rx_csum)
2178 rxcsum |= E1000_RXCSUM_TUOFL | E1000_RXCSUM_IPPCSE;
2179 else
2180 rxcsum &= ~(E1000_RXCSUM_TUOFL | E1000_RXCSUM_IPPCSE);
2181
2182 wr32(E1000_RXCSUM, rxcsum);
2183 }
2184
2185 /* Set the default pool for the PF's first queue */
2186 igb_configure_vt_default_pool(adapter);
2187
2188 igb_rlpml_set(adapter);
2189
2190 /* Enable Receives */
2191 wr32(E1000_RCTL, rctl);
2192 }
2193
2194 /**
2195 * igb_free_tx_resources - Free Tx Resources per Queue
2196 * @tx_ring: Tx descriptor ring for a specific queue
2197 *
2198 * Free all transmit software resources
2199 **/
2200 void igb_free_tx_resources(struct igb_ring *tx_ring)
2201 {
2202 struct pci_dev *pdev = tx_ring->adapter->pdev;
2203
2204 igb_clean_tx_ring(tx_ring);
2205
2206 vfree(tx_ring->buffer_info);
2207 tx_ring->buffer_info = NULL;
2208
2209 pci_free_consistent(pdev, tx_ring->size, tx_ring->desc, tx_ring->dma);
2210
2211 tx_ring->desc = NULL;
2212 }
2213
2214 /**
2215 * igb_free_all_tx_resources - Free Tx Resources for All Queues
2216 * @adapter: board private structure
2217 *
2218 * Free all transmit software resources
2219 **/
2220 static void igb_free_all_tx_resources(struct igb_adapter *adapter)
2221 {
2222 int i;
2223
2224 for (i = 0; i < adapter->num_tx_queues; i++)
2225 igb_free_tx_resources(&adapter->tx_ring[i]);
2226 }
2227
2228 static void igb_unmap_and_free_tx_resource(struct igb_adapter *adapter,
2229 struct igb_buffer *buffer_info)
2230 {
2231 if (buffer_info->dma) {
2232 pci_unmap_page(adapter->pdev,
2233 buffer_info->dma,
2234 buffer_info->length,
2235 PCI_DMA_TODEVICE);
2236 buffer_info->dma = 0;
2237 }
2238 if (buffer_info->skb) {
2239 dev_kfree_skb_any(buffer_info->skb);
2240 buffer_info->skb = NULL;
2241 }
2242 buffer_info->time_stamp = 0;
2243 buffer_info->next_to_watch = 0;
2244 /* buffer_info must be completely set up in the transmit path */
2245 }
2246
2247 /**
2248 * igb_clean_tx_ring - Free Tx Buffers
2249 * @tx_ring: ring to be cleaned
2250 **/
2251 static void igb_clean_tx_ring(struct igb_ring *tx_ring)
2252 {
2253 struct igb_adapter *adapter = tx_ring->adapter;
2254 struct igb_buffer *buffer_info;
2255 unsigned long size;
2256 unsigned int i;
2257
2258 if (!tx_ring->buffer_info)
2259 return;
2260 /* Free all the Tx ring sk_buffs */
2261
2262 for (i = 0; i < tx_ring->count; i++) {
2263 buffer_info = &tx_ring->buffer_info[i];
2264 igb_unmap_and_free_tx_resource(adapter, buffer_info);
2265 }
2266
2267 size = sizeof(struct igb_buffer) * tx_ring->count;
2268 memset(tx_ring->buffer_info, 0, size);
2269
2270 /* Zero out the descriptor ring */
2271
2272 memset(tx_ring->desc, 0, tx_ring->size);
2273
2274 tx_ring->next_to_use = 0;
2275 tx_ring->next_to_clean = 0;
2276
2277 writel(0, adapter->hw.hw_addr + tx_ring->head);
2278 writel(0, adapter->hw.hw_addr + tx_ring->tail);
2279 }
2280
2281 /**
2282 * igb_clean_all_tx_rings - Free Tx Buffers for all queues
2283 * @adapter: board private structure
2284 **/
2285 static void igb_clean_all_tx_rings(struct igb_adapter *adapter)
2286 {
2287 int i;
2288
2289 for (i = 0; i < adapter->num_tx_queues; i++)
2290 igb_clean_tx_ring(&adapter->tx_ring[i]);
2291 }
2292
2293 /**
2294 * igb_free_rx_resources - Free Rx Resources
2295 * @rx_ring: ring to clean the resources from
2296 *
2297 * Free all receive software resources
2298 **/
2299 void igb_free_rx_resources(struct igb_ring *rx_ring)
2300 {
2301 struct pci_dev *pdev = rx_ring->adapter->pdev;
2302
2303 igb_clean_rx_ring(rx_ring);
2304
2305 vfree(rx_ring->buffer_info);
2306 rx_ring->buffer_info = NULL;
2307
2308 pci_free_consistent(pdev, rx_ring->size, rx_ring->desc, rx_ring->dma);
2309
2310 rx_ring->desc = NULL;
2311 }
2312
2313 /**
2314 * igb_free_all_rx_resources - Free Rx Resources for All Queues
2315 * @adapter: board private structure
2316 *
2317 * Free all receive software resources
2318 **/
2319 static void igb_free_all_rx_resources(struct igb_adapter *adapter)
2320 {
2321 int i;
2322
2323 for (i = 0; i < adapter->num_rx_queues; i++)
2324 igb_free_rx_resources(&adapter->rx_ring[i]);
2325 }
2326
2327 /**
2328 * igb_clean_rx_ring - Free Rx Buffers per Queue
2329 * @rx_ring: ring to free buffers from
2330 **/
2331 static void igb_clean_rx_ring(struct igb_ring *rx_ring)
2332 {
2333 struct igb_adapter *adapter = rx_ring->adapter;
2334 struct igb_buffer *buffer_info;
2335 struct pci_dev *pdev = adapter->pdev;
2336 unsigned long size;
2337 unsigned int i;
2338
2339 if (!rx_ring->buffer_info)
2340 return;
2341 /* Free all the Rx ring sk_buffs */
2342 for (i = 0; i < rx_ring->count; i++) {
2343 buffer_info = &rx_ring->buffer_info[i];
2344 if (buffer_info->dma) {
2345 if (adapter->rx_ps_hdr_size)
2346 pci_unmap_single(pdev, buffer_info->dma,
2347 adapter->rx_ps_hdr_size,
2348 PCI_DMA_FROMDEVICE);
2349 else
2350 pci_unmap_single(pdev, buffer_info->dma,
2351 adapter->rx_buffer_len,
2352 PCI_DMA_FROMDEVICE);
2353 buffer_info->dma = 0;
2354 }
2355
2356 if (buffer_info->skb) {
2357 dev_kfree_skb(buffer_info->skb);
2358 buffer_info->skb = NULL;
2359 }
2360 if (buffer_info->page) {
2361 if (buffer_info->page_dma)
2362 pci_unmap_page(pdev, buffer_info->page_dma,
2363 PAGE_SIZE / 2,
2364 PCI_DMA_FROMDEVICE);
2365 put_page(buffer_info->page);
2366 buffer_info->page = NULL;
2367 buffer_info->page_dma = 0;
2368 buffer_info->page_offset = 0;
2369 }
2370 }
2371
2372 size = sizeof(struct igb_buffer) * rx_ring->count;
2373 memset(rx_ring->buffer_info, 0, size);
2374
2375 /* Zero out the descriptor ring */
2376 memset(rx_ring->desc, 0, rx_ring->size);
2377
2378 rx_ring->next_to_clean = 0;
2379 rx_ring->next_to_use = 0;
2380
2381 writel(0, adapter->hw.hw_addr + rx_ring->head);
2382 writel(0, adapter->hw.hw_addr + rx_ring->tail);
2383 }
2384
2385 /**
2386 * igb_clean_all_rx_rings - Free Rx Buffers for all queues
2387 * @adapter: board private structure
2388 **/
2389 static void igb_clean_all_rx_rings(struct igb_adapter *adapter)
2390 {
2391 int i;
2392
2393 for (i = 0; i < adapter->num_rx_queues; i++)
2394 igb_clean_rx_ring(&adapter->rx_ring[i]);
2395 }
2396
2397 /**
2398 * igb_set_mac - Change the Ethernet Address of the NIC
2399 * @netdev: network interface device structure
2400 * @p: pointer to an address structure
2401 *
2402 * Returns 0 on success, negative on failure
2403 **/
2404 static int igb_set_mac(struct net_device *netdev, void *p)
2405 {
2406 struct igb_adapter *adapter = netdev_priv(netdev);
2407 struct e1000_hw *hw = &adapter->hw;
2408 struct sockaddr *addr = p;
2409
2410 if (!is_valid_ether_addr(addr->sa_data))
2411 return -EADDRNOTAVAIL;
2412
2413 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
2414 memcpy(hw->mac.addr, addr->sa_data, netdev->addr_len);
2415
2416 hw->mac.ops.rar_set(hw, hw->mac.addr, 0);
2417
2418 igb_set_rah_pool(hw, adapter->vfs_allocated_count, 0);
2419
2420 return 0;
2421 }
2422
2423 /**
2424 * igb_set_multi - Multicast and Promiscuous mode set
2425 * @netdev: network interface device structure
2426 *
2427 * The set_multi entry point is called whenever the multicast address
2428 * list or the network interface flags are updated. This routine is
2429 * responsible for configuring the hardware for proper multicast,
2430 * promiscuous mode, and all-multi behavior.
2431 **/
2432 static void igb_set_multi(struct net_device *netdev)
2433 {
2434 struct igb_adapter *adapter = netdev_priv(netdev);
2435 struct e1000_hw *hw = &adapter->hw;
2436 struct e1000_mac_info *mac = &hw->mac;
2437 struct dev_mc_list *mc_ptr;
2438 u8 *mta_list;
2439 u32 rctl;
2440 int i;
2441
2442 /* Check for Promiscuous and All Multicast modes */
2443
2444 rctl = rd32(E1000_RCTL);
2445
2446 if (netdev->flags & IFF_PROMISC) {
2447 rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE);
2448 rctl &= ~E1000_RCTL_VFE;
2449 } else {
2450 if (netdev->flags & IFF_ALLMULTI) {
2451 rctl |= E1000_RCTL_MPE;
2452 rctl &= ~E1000_RCTL_UPE;
2453 } else
2454 rctl &= ~(E1000_RCTL_UPE | E1000_RCTL_MPE);
2455 rctl |= E1000_RCTL_VFE;
2456 }
2457 wr32(E1000_RCTL, rctl);
2458
2459 if (!netdev->mc_count) {
2460 /* nothing to program, so clear mc list */
2461 igb_update_mc_addr_list(hw, NULL, 0, 1,
2462 mac->rar_entry_count);
2463 return;
2464 }
2465
2466 mta_list = kzalloc(netdev->mc_count * 6, GFP_ATOMIC);
2467 if (!mta_list)
2468 return;
2469
2470 /* The shared function expects a packed array of only addresses. */
2471 mc_ptr = netdev->mc_list;
2472
2473 for (i = 0; i < netdev->mc_count; i++) {
2474 if (!mc_ptr)
2475 break;
2476 memcpy(mta_list + (i*ETH_ALEN), mc_ptr->dmi_addr, ETH_ALEN);
2477 mc_ptr = mc_ptr->next;
2478 }
2479 igb_update_mc_addr_list(hw, mta_list, i,
2480 adapter->vfs_allocated_count + 1,
2481 mac->rar_entry_count);
2482
2483 igb_set_mc_list_pools(adapter, i, mac->rar_entry_count);
2484 igb_restore_vf_multicasts(adapter);
2485
2486 kfree(mta_list);
2487 }
2488
2489 /* Need to wait a few seconds after link up to get diagnostic information from
2490 * the phy */
2491 static void igb_update_phy_info(unsigned long data)
2492 {
2493 struct igb_adapter *adapter = (struct igb_adapter *) data;
2494 igb_get_phy_info(&adapter->hw);
2495 }
2496
2497 /**
2498 * igb_has_link - check shared code for link and determine up/down
2499 * @adapter: pointer to driver private info
2500 **/
2501 static bool igb_has_link(struct igb_adapter *adapter)
2502 {
2503 struct e1000_hw *hw = &adapter->hw;
2504 bool link_active = false;
2505 s32 ret_val = 0;
2506
2507 /* get_link_status is set on LSC (link status) interrupt or
2508 * rx sequence error interrupt. get_link_status will stay
2509 * false until the e1000_check_for_link establishes link
2510 * for copper adapters ONLY
2511 */
2512 switch (hw->phy.media_type) {
2513 case e1000_media_type_copper:
2514 if (hw->mac.get_link_status) {
2515 ret_val = hw->mac.ops.check_for_link(hw);
2516 link_active = !hw->mac.get_link_status;
2517 } else {
2518 link_active = true;
2519 }
2520 break;
2521 case e1000_media_type_fiber:
2522 ret_val = hw->mac.ops.check_for_link(hw);
2523 link_active = !!(rd32(E1000_STATUS) & E1000_STATUS_LU);
2524 break;
2525 case e1000_media_type_internal_serdes:
2526 ret_val = hw->mac.ops.check_for_link(hw);
2527 link_active = hw->mac.serdes_has_link;
2528 break;
2529 default:
2530 case e1000_media_type_unknown:
2531 break;
2532 }
2533
2534 return link_active;
2535 }
2536
2537 /**
2538 * igb_watchdog - Timer Call-back
2539 * @data: pointer to adapter cast into an unsigned long
2540 **/
2541 static void igb_watchdog(unsigned long data)
2542 {
2543 struct igb_adapter *adapter = (struct igb_adapter *)data;
2544 /* Do the rest outside of interrupt context */
2545 schedule_work(&adapter->watchdog_task);
2546 }
2547
2548 static void igb_watchdog_task(struct work_struct *work)
2549 {
2550 struct igb_adapter *adapter = container_of(work,
2551 struct igb_adapter, watchdog_task);
2552 struct e1000_hw *hw = &adapter->hw;
2553 struct net_device *netdev = adapter->netdev;
2554 struct igb_ring *tx_ring = adapter->tx_ring;
2555 u32 link;
2556 u32 eics = 0;
2557 int i;
2558
2559 link = igb_has_link(adapter);
2560 if ((netif_carrier_ok(netdev)) && link)
2561 goto link_up;
2562
2563 if (link) {
2564 if (!netif_carrier_ok(netdev)) {
2565 u32 ctrl;
2566 hw->mac.ops.get_speed_and_duplex(&adapter->hw,
2567 &adapter->link_speed,
2568 &adapter->link_duplex);
2569
2570 ctrl = rd32(E1000_CTRL);
2571 /* Links status message must follow this format */
2572 printk(KERN_INFO "igb: %s NIC Link is Up %d Mbps %s, "
2573 "Flow Control: %s\n",
2574 netdev->name,
2575 adapter->link_speed,
2576 adapter->link_duplex == FULL_DUPLEX ?
2577 "Full Duplex" : "Half Duplex",
2578 ((ctrl & E1000_CTRL_TFCE) && (ctrl &
2579 E1000_CTRL_RFCE)) ? "RX/TX" : ((ctrl &
2580 E1000_CTRL_RFCE) ? "RX" : ((ctrl &
2581 E1000_CTRL_TFCE) ? "TX" : "None")));
2582
2583 /* tweak tx_queue_len according to speed/duplex and
2584 * adjust the timeout factor */
2585 netdev->tx_queue_len = adapter->tx_queue_len;
2586 adapter->tx_timeout_factor = 1;
2587 switch (adapter->link_speed) {
2588 case SPEED_10:
2589 netdev->tx_queue_len = 10;
2590 adapter->tx_timeout_factor = 14;
2591 break;
2592 case SPEED_100:
2593 netdev->tx_queue_len = 100;
2594 /* maybe add some timeout factor ? */
2595 break;
2596 }
2597
2598 netif_carrier_on(netdev);
2599 netif_tx_wake_all_queues(netdev);
2600
2601 igb_ping_all_vfs(adapter);
2602
2603 /* link state has changed, schedule phy info update */
2604 if (!test_bit(__IGB_DOWN, &adapter->state))
2605 mod_timer(&adapter->phy_info_timer,
2606 round_jiffies(jiffies + 2 * HZ));
2607 }
2608 } else {
2609 if (netif_carrier_ok(netdev)) {
2610 adapter->link_speed = 0;
2611 adapter->link_duplex = 0;
2612 /* Links status message must follow this format */
2613 printk(KERN_INFO "igb: %s NIC Link is Down\n",
2614 netdev->name);
2615 netif_carrier_off(netdev);
2616 netif_tx_stop_all_queues(netdev);
2617
2618 igb_ping_all_vfs(adapter);
2619
2620 /* link state has changed, schedule phy info update */
2621 if (!test_bit(__IGB_DOWN, &adapter->state))
2622 mod_timer(&adapter->phy_info_timer,
2623 round_jiffies(jiffies + 2 * HZ));
2624 }
2625 }
2626
2627 link_up:
2628 igb_update_stats(adapter);
2629
2630 hw->mac.tx_packet_delta = adapter->stats.tpt - adapter->tpt_old;
2631 adapter->tpt_old = adapter->stats.tpt;
2632 hw->mac.collision_delta = adapter->stats.colc - adapter->colc_old;
2633 adapter->colc_old = adapter->stats.colc;
2634
2635 adapter->gorc = adapter->stats.gorc - adapter->gorc_old;
2636 adapter->gorc_old = adapter->stats.gorc;
2637 adapter->gotc = adapter->stats.gotc - adapter->gotc_old;
2638 adapter->gotc_old = adapter->stats.gotc;
2639
2640 igb_update_adaptive(&adapter->hw);
2641
2642 if (!netif_carrier_ok(netdev)) {
2643 if (IGB_DESC_UNUSED(tx_ring) + 1 < tx_ring->count) {
2644 /* We've lost link, so the controller stops DMA,
2645 * but we've got queued Tx work that's never going
2646 * to get done, so reset controller to flush Tx.
2647 * (Do the reset outside of interrupt context). */
2648 adapter->tx_timeout_count++;
2649 schedule_work(&adapter->reset_task);
2650 }
2651 }
2652
2653 /* Cause software interrupt to ensure rx ring is cleaned */
2654 if (adapter->msix_entries) {
2655 for (i = 0; i < adapter->num_rx_queues; i++)
2656 eics |= adapter->rx_ring[i].eims_value;
2657 wr32(E1000_EICS, eics);
2658 } else {
2659 wr32(E1000_ICS, E1000_ICS_RXDMT0);
2660 }
2661
2662 /* Force detection of hung controller every watchdog period */
2663 tx_ring->detect_tx_hung = true;
2664
2665 /* Reset the timer */
2666 if (!test_bit(__IGB_DOWN, &adapter->state))
2667 mod_timer(&adapter->watchdog_timer,
2668 round_jiffies(jiffies + 2 * HZ));
2669 }
2670
2671 enum latency_range {
2672 lowest_latency = 0,
2673 low_latency = 1,
2674 bulk_latency = 2,
2675 latency_invalid = 255
2676 };
2677
2678
2679 /**
2680 * igb_update_ring_itr - update the dynamic ITR value based on packet size
2681 *
2682 * Stores a new ITR value based on strictly on packet size. This
2683 * algorithm is less sophisticated than that used in igb_update_itr,
2684 * due to the difficulty of synchronizing statistics across multiple
2685 * receive rings. The divisors and thresholds used by this fuction
2686 * were determined based on theoretical maximum wire speed and testing
2687 * data, in order to minimize response time while increasing bulk
2688 * throughput.
2689 * This functionality is controlled by the InterruptThrottleRate module
2690 * parameter (see igb_param.c)
2691 * NOTE: This function is called only when operating in a multiqueue
2692 * receive environment.
2693 * @rx_ring: pointer to ring
2694 **/
2695 static void igb_update_ring_itr(struct igb_ring *rx_ring)
2696 {
2697 int new_val = rx_ring->itr_val;
2698 int avg_wire_size = 0;
2699 struct igb_adapter *adapter = rx_ring->adapter;
2700
2701 if (!rx_ring->total_packets)
2702 goto clear_counts; /* no packets, so don't do anything */
2703
2704 /* For non-gigabit speeds, just fix the interrupt rate at 4000
2705 * ints/sec - ITR timer value of 120 ticks.
2706 */
2707 if (adapter->link_speed != SPEED_1000) {
2708 new_val = 120;
2709 goto set_itr_val;
2710 }
2711 avg_wire_size = rx_ring->total_bytes / rx_ring->total_packets;
2712
2713 /* Add 24 bytes to size to account for CRC, preamble, and gap */
2714 avg_wire_size += 24;
2715
2716 /* Don't starve jumbo frames */
2717 avg_wire_size = min(avg_wire_size, 3000);
2718
2719 /* Give a little boost to mid-size frames */
2720 if ((avg_wire_size > 300) && (avg_wire_size < 1200))
2721 new_val = avg_wire_size / 3;
2722 else
2723 new_val = avg_wire_size / 2;
2724
2725 set_itr_val:
2726 if (new_val != rx_ring->itr_val) {
2727 rx_ring->itr_val = new_val;
2728 rx_ring->set_itr = 1;
2729 }
2730 clear_counts:
2731 rx_ring->total_bytes = 0;
2732 rx_ring->total_packets = 0;
2733 }
2734
2735 /**
2736 * igb_update_itr - update the dynamic ITR value based on statistics
2737 * Stores a new ITR value based on packets and byte
2738 * counts during the last interrupt. The advantage of per interrupt
2739 * computation is faster updates and more accurate ITR for the current
2740 * traffic pattern. Constants in this function were computed
2741 * based on theoretical maximum wire speed and thresholds were set based
2742 * on testing data as well as attempting to minimize response time
2743 * while increasing bulk throughput.
2744 * this functionality is controlled by the InterruptThrottleRate module
2745 * parameter (see igb_param.c)
2746 * NOTE: These calculations are only valid when operating in a single-
2747 * queue environment.
2748 * @adapter: pointer to adapter
2749 * @itr_setting: current adapter->itr
2750 * @packets: the number of packets during this measurement interval
2751 * @bytes: the number of bytes during this measurement interval
2752 **/
2753 static unsigned int igb_update_itr(struct igb_adapter *adapter, u16 itr_setting,
2754 int packets, int bytes)
2755 {
2756 unsigned int retval = itr_setting;
2757
2758 if (packets == 0)
2759 goto update_itr_done;
2760
2761 switch (itr_setting) {
2762 case lowest_latency:
2763 /* handle TSO and jumbo frames */
2764 if (bytes/packets > 8000)
2765 retval = bulk_latency;
2766 else if ((packets < 5) && (bytes > 512))
2767 retval = low_latency;
2768 break;
2769 case low_latency: /* 50 usec aka 20000 ints/s */
2770 if (bytes > 10000) {
2771 /* this if handles the TSO accounting */
2772 if (bytes/packets > 8000) {
2773 retval = bulk_latency;
2774 } else if ((packets < 10) || ((bytes/packets) > 1200)) {
2775 retval = bulk_latency;
2776 } else if ((packets > 35)) {
2777 retval = lowest_latency;
2778 }
2779 } else if (bytes/packets > 2000) {
2780 retval = bulk_latency;
2781 } else if (packets <= 2 && bytes < 512) {
2782 retval = lowest_latency;
2783 }
2784 break;
2785 case bulk_latency: /* 250 usec aka 4000 ints/s */
2786 if (bytes > 25000) {
2787 if (packets > 35)
2788 retval = low_latency;
2789 } else if (bytes < 1500) {
2790 retval = low_latency;
2791 }
2792 break;
2793 }
2794
2795 update_itr_done:
2796 return retval;
2797 }
2798
2799 static void igb_set_itr(struct igb_adapter *adapter)
2800 {
2801 u16 current_itr;
2802 u32 new_itr = adapter->itr;
2803
2804 /* for non-gigabit speeds, just fix the interrupt rate at 4000 */
2805 if (adapter->link_speed != SPEED_1000) {
2806 current_itr = 0;
2807 new_itr = 4000;
2808 goto set_itr_now;
2809 }
2810
2811 adapter->rx_itr = igb_update_itr(adapter,
2812 adapter->rx_itr,
2813 adapter->rx_ring->total_packets,
2814 adapter->rx_ring->total_bytes);
2815
2816 if (adapter->rx_ring->buddy) {
2817 adapter->tx_itr = igb_update_itr(adapter,
2818 adapter->tx_itr,
2819 adapter->tx_ring->total_packets,
2820 adapter->tx_ring->total_bytes);
2821 current_itr = max(adapter->rx_itr, adapter->tx_itr);
2822 } else {
2823 current_itr = adapter->rx_itr;
2824 }
2825
2826 /* conservative mode (itr 3) eliminates the lowest_latency setting */
2827 if (adapter->itr_setting == 3 && current_itr == lowest_latency)
2828 current_itr = low_latency;
2829
2830 switch (current_itr) {
2831 /* counts and packets in update_itr are dependent on these numbers */
2832 case lowest_latency:
2833 new_itr = 70000;
2834 break;
2835 case low_latency:
2836 new_itr = 20000; /* aka hwitr = ~200 */
2837 break;
2838 case bulk_latency:
2839 new_itr = 4000;
2840 break;
2841 default:
2842 break;
2843 }
2844
2845 set_itr_now:
2846 adapter->rx_ring->total_bytes = 0;
2847 adapter->rx_ring->total_packets = 0;
2848 if (adapter->rx_ring->buddy) {
2849 adapter->rx_ring->buddy->total_bytes = 0;
2850 adapter->rx_ring->buddy->total_packets = 0;
2851 }
2852
2853 if (new_itr != adapter->itr) {
2854 /* this attempts to bias the interrupt rate towards Bulk
2855 * by adding intermediate steps when interrupt rate is
2856 * increasing */
2857 new_itr = new_itr > adapter->itr ?
2858 min(adapter->itr + (new_itr >> 2), new_itr) :
2859 new_itr;
2860 /* Don't write the value here; it resets the adapter's
2861 * internal timer, and causes us to delay far longer than
2862 * we should between interrupts. Instead, we write the ITR
2863 * value at the beginning of the next interrupt so the timing
2864 * ends up being correct.
2865 */
2866 adapter->itr = new_itr;
2867 adapter->rx_ring->itr_val = 1000000000 / (new_itr * 256);
2868 adapter->rx_ring->set_itr = 1;
2869 }
2870
2871 return;
2872 }
2873
2874
2875 #define IGB_TX_FLAGS_CSUM 0x00000001
2876 #define IGB_TX_FLAGS_VLAN 0x00000002
2877 #define IGB_TX_FLAGS_TSO 0x00000004
2878 #define IGB_TX_FLAGS_IPV4 0x00000008
2879 #define IGB_TX_FLAGS_TSTAMP 0x00000010
2880 #define IGB_TX_FLAGS_VLAN_MASK 0xffff0000
2881 #define IGB_TX_FLAGS_VLAN_SHIFT 16
2882
2883 static inline int igb_tso_adv(struct igb_adapter *adapter,
2884 struct igb_ring *tx_ring,
2885 struct sk_buff *skb, u32 tx_flags, u8 *hdr_len)
2886 {
2887 struct e1000_adv_tx_context_desc *context_desc;
2888 unsigned int i;
2889 int err;
2890 struct igb_buffer *buffer_info;
2891 u32 info = 0, tu_cmd = 0;
2892 u32 mss_l4len_idx, l4len;
2893 *hdr_len = 0;
2894
2895 if (skb_header_cloned(skb)) {
2896 err = pskb_expand_head(skb, 0, 0, GFP_ATOMIC);
2897 if (err)
2898 return err;
2899 }
2900
2901 l4len = tcp_hdrlen(skb);
2902 *hdr_len += l4len;
2903
2904 if (skb->protocol == htons(ETH_P_IP)) {
2905 struct iphdr *iph = ip_hdr(skb);
2906 iph->tot_len = 0;
2907 iph->check = 0;
2908 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
2909 iph->daddr, 0,
2910 IPPROTO_TCP,
2911 0);
2912 } else if (skb_shinfo(skb)->gso_type == SKB_GSO_TCPV6) {
2913 ipv6_hdr(skb)->payload_len = 0;
2914 tcp_hdr(skb)->check = ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr,
2915 &ipv6_hdr(skb)->daddr,
2916 0, IPPROTO_TCP, 0);
2917 }
2918
2919 i = tx_ring->next_to_use;
2920
2921 buffer_info = &tx_ring->buffer_info[i];
2922 context_desc = E1000_TX_CTXTDESC_ADV(*tx_ring, i);
2923 /* VLAN MACLEN IPLEN */
2924 if (tx_flags & IGB_TX_FLAGS_VLAN)
2925 info |= (tx_flags & IGB_TX_FLAGS_VLAN_MASK);
2926 info |= (skb_network_offset(skb) << E1000_ADVTXD_MACLEN_SHIFT);
2927 *hdr_len += skb_network_offset(skb);
2928 info |= skb_network_header_len(skb);
2929 *hdr_len += skb_network_header_len(skb);
2930 context_desc->vlan_macip_lens = cpu_to_le32(info);
2931
2932 /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */
2933 tu_cmd |= (E1000_TXD_CMD_DEXT | E1000_ADVTXD_DTYP_CTXT);
2934
2935 if (skb->protocol == htons(ETH_P_IP))
2936 tu_cmd |= E1000_ADVTXD_TUCMD_IPV4;
2937 tu_cmd |= E1000_ADVTXD_TUCMD_L4T_TCP;
2938
2939 context_desc->type_tucmd_mlhl = cpu_to_le32(tu_cmd);
2940
2941 /* MSS L4LEN IDX */
2942 mss_l4len_idx = (skb_shinfo(skb)->gso_size << E1000_ADVTXD_MSS_SHIFT);
2943 mss_l4len_idx |= (l4len << E1000_ADVTXD_L4LEN_SHIFT);
2944
2945 /* For 82575, context index must be unique per ring. */
2946 if (adapter->flags & IGB_FLAG_NEED_CTX_IDX)
2947 mss_l4len_idx |= tx_ring->queue_index << 4;
2948
2949 context_desc->mss_l4len_idx = cpu_to_le32(mss_l4len_idx);
2950 context_desc->seqnum_seed = 0;
2951
2952 buffer_info->time_stamp = jiffies;
2953 buffer_info->next_to_watch = i;
2954 buffer_info->dma = 0;
2955 i++;
2956 if (i == tx_ring->count)
2957 i = 0;
2958
2959 tx_ring->next_to_use = i;
2960
2961 return true;
2962 }
2963
2964 static inline bool igb_tx_csum_adv(struct igb_adapter *adapter,
2965 struct igb_ring *tx_ring,
2966 struct sk_buff *skb, u32 tx_flags)
2967 {
2968 struct e1000_adv_tx_context_desc *context_desc;
2969 unsigned int i;
2970 struct igb_buffer *buffer_info;
2971 u32 info = 0, tu_cmd = 0;
2972
2973 if ((skb->ip_summed == CHECKSUM_PARTIAL) ||
2974 (tx_flags & IGB_TX_FLAGS_VLAN)) {
2975 i = tx_ring->next_to_use;
2976 buffer_info = &tx_ring->buffer_info[i];
2977 context_desc = E1000_TX_CTXTDESC_ADV(*tx_ring, i);
2978
2979 if (tx_flags & IGB_TX_FLAGS_VLAN)
2980 info |= (tx_flags & IGB_TX_FLAGS_VLAN_MASK);
2981 info |= (skb_network_offset(skb) << E1000_ADVTXD_MACLEN_SHIFT);
2982 if (skb->ip_summed == CHECKSUM_PARTIAL)
2983 info |= skb_network_header_len(skb);
2984
2985 context_desc->vlan_macip_lens = cpu_to_le32(info);
2986
2987 tu_cmd |= (E1000_TXD_CMD_DEXT | E1000_ADVTXD_DTYP_CTXT);
2988
2989 if (skb->ip_summed == CHECKSUM_PARTIAL) {
2990 switch (skb->protocol) {
2991 case cpu_to_be16(ETH_P_IP):
2992 tu_cmd |= E1000_ADVTXD_TUCMD_IPV4;
2993 if (ip_hdr(skb)->protocol == IPPROTO_TCP)
2994 tu_cmd |= E1000_ADVTXD_TUCMD_L4T_TCP;
2995 break;
2996 case cpu_to_be16(ETH_P_IPV6):
2997 /* XXX what about other V6 headers?? */
2998 if (ipv6_hdr(skb)->nexthdr == IPPROTO_TCP)
2999 tu_cmd |= E1000_ADVTXD_TUCMD_L4T_TCP;
3000 break;
3001 default:
3002 if (unlikely(net_ratelimit()))
3003 dev_warn(&adapter->pdev->dev,
3004 "partial checksum but proto=%x!\n",
3005 skb->protocol);
3006 break;
3007 }
3008 }
3009
3010 context_desc->type_tucmd_mlhl = cpu_to_le32(tu_cmd);
3011 context_desc->seqnum_seed = 0;
3012 if (adapter->flags & IGB_FLAG_NEED_CTX_IDX)
3013 context_desc->mss_l4len_idx =
3014 cpu_to_le32(tx_ring->queue_index << 4);
3015 else
3016 context_desc->mss_l4len_idx = 0;
3017
3018 buffer_info->time_stamp = jiffies;
3019 buffer_info->next_to_watch = i;
3020 buffer_info->dma = 0;
3021
3022 i++;
3023 if (i == tx_ring->count)
3024 i = 0;
3025 tx_ring->next_to_use = i;
3026
3027 return true;
3028 }
3029 return false;
3030 }
3031
3032 #define IGB_MAX_TXD_PWR 16
3033 #define IGB_MAX_DATA_PER_TXD (1<<IGB_MAX_TXD_PWR)
3034
3035 static inline int igb_tx_map_adv(struct igb_adapter *adapter,
3036 struct igb_ring *tx_ring, struct sk_buff *skb,
3037 unsigned int first)
3038 {
3039 struct igb_buffer *buffer_info;
3040 unsigned int len = skb_headlen(skb);
3041 unsigned int count = 0, i;
3042 unsigned int f;
3043
3044 i = tx_ring->next_to_use;
3045
3046 buffer_info = &tx_ring->buffer_info[i];
3047 BUG_ON(len >= IGB_MAX_DATA_PER_TXD);
3048 buffer_info->length = len;
3049 /* set time_stamp *before* dma to help avoid a possible race */
3050 buffer_info->time_stamp = jiffies;
3051 buffer_info->next_to_watch = i;
3052 buffer_info->dma = pci_map_single(adapter->pdev, skb->data, len,
3053 PCI_DMA_TODEVICE);
3054 count++;
3055 i++;
3056 if (i == tx_ring->count)
3057 i = 0;
3058
3059 for (f = 0; f < skb_shinfo(skb)->nr_frags; f++) {
3060 struct skb_frag_struct *frag;
3061
3062 frag = &skb_shinfo(skb)->frags[f];
3063 len = frag->size;
3064
3065 buffer_info = &tx_ring->buffer_info[i];
3066 BUG_ON(len >= IGB_MAX_DATA_PER_TXD);
3067 buffer_info->length = len;
3068 buffer_info->time_stamp = jiffies;
3069 buffer_info->next_to_watch = i;
3070 buffer_info->dma = pci_map_page(adapter->pdev,
3071 frag->page,
3072 frag->page_offset,
3073 len,
3074 PCI_DMA_TODEVICE);
3075
3076 count++;
3077 i++;
3078 if (i == tx_ring->count)
3079 i = 0;
3080 }
3081
3082 i = ((i == 0) ? tx_ring->count - 1 : i - 1);
3083 tx_ring->buffer_info[i].skb = skb;
3084 tx_ring->buffer_info[first].next_to_watch = i;
3085
3086 return count;
3087 }
3088
3089 static inline void igb_tx_queue_adv(struct igb_adapter *adapter,
3090 struct igb_ring *tx_ring,
3091 int tx_flags, int count, u32 paylen,
3092 u8 hdr_len)
3093 {
3094 union e1000_adv_tx_desc *tx_desc = NULL;
3095 struct igb_buffer *buffer_info;
3096 u32 olinfo_status = 0, cmd_type_len;
3097 unsigned int i;
3098
3099 cmd_type_len = (E1000_ADVTXD_DTYP_DATA | E1000_ADVTXD_DCMD_IFCS |
3100 E1000_ADVTXD_DCMD_DEXT);
3101
3102 if (tx_flags & IGB_TX_FLAGS_VLAN)
3103 cmd_type_len |= E1000_ADVTXD_DCMD_VLE;
3104
3105 if (tx_flags & IGB_TX_FLAGS_TSTAMP)
3106 cmd_type_len |= E1000_ADVTXD_MAC_TSTAMP;
3107
3108 if (tx_flags & IGB_TX_FLAGS_TSO) {
3109 cmd_type_len |= E1000_ADVTXD_DCMD_TSE;
3110
3111 /* insert tcp checksum */
3112 olinfo_status |= E1000_TXD_POPTS_TXSM << 8;
3113
3114 /* insert ip checksum */
3115 if (tx_flags & IGB_TX_FLAGS_IPV4)
3116 olinfo_status |= E1000_TXD_POPTS_IXSM << 8;
3117
3118 } else if (tx_flags & IGB_TX_FLAGS_CSUM) {
3119 olinfo_status |= E1000_TXD_POPTS_TXSM << 8;
3120 }
3121
3122 if ((adapter->flags & IGB_FLAG_NEED_CTX_IDX) &&
3123 (tx_flags & (IGB_TX_FLAGS_CSUM | IGB_TX_FLAGS_TSO |
3124 IGB_TX_FLAGS_VLAN)))
3125 olinfo_status |= tx_ring->queue_index << 4;
3126
3127 olinfo_status |= ((paylen - hdr_len) << E1000_ADVTXD_PAYLEN_SHIFT);
3128
3129 i = tx_ring->next_to_use;
3130 while (count--) {
3131 buffer_info = &tx_ring->buffer_info[i];
3132 tx_desc = E1000_TX_DESC_ADV(*tx_ring, i);
3133 tx_desc->read.buffer_addr = cpu_to_le64(buffer_info->dma);
3134 tx_desc->read.cmd_type_len =
3135 cpu_to_le32(cmd_type_len | buffer_info->length);
3136 tx_desc->read.olinfo_status = cpu_to_le32(olinfo_status);
3137 i++;
3138 if (i == tx_ring->count)
3139 i = 0;
3140 }
3141
3142 tx_desc->read.cmd_type_len |= cpu_to_le32(adapter->txd_cmd);
3143 /* Force memory writes to complete before letting h/w
3144 * know there are new descriptors to fetch. (Only
3145 * applicable for weak-ordered memory model archs,
3146 * such as IA-64). */
3147 wmb();
3148
3149 tx_ring->next_to_use = i;
3150 writel(i, adapter->hw.hw_addr + tx_ring->tail);
3151 /* we need this if more than one processor can write to our tail
3152 * at a time, it syncronizes IO on IA64/Altix systems */
3153 mmiowb();
3154 }
3155
3156 static int __igb_maybe_stop_tx(struct net_device *netdev,
3157 struct igb_ring *tx_ring, int size)
3158 {
3159 struct igb_adapter *adapter = netdev_priv(netdev);
3160
3161 netif_stop_subqueue(netdev, tx_ring->queue_index);
3162
3163 /* Herbert's original patch had:
3164 * smp_mb__after_netif_stop_queue();
3165 * but since that doesn't exist yet, just open code it. */
3166 smp_mb();
3167
3168 /* We need to check again in a case another CPU has just
3169 * made room available. */
3170 if (IGB_DESC_UNUSED(tx_ring) < size)
3171 return -EBUSY;
3172
3173 /* A reprieve! */
3174 netif_wake_subqueue(netdev, tx_ring->queue_index);
3175 ++adapter->restart_queue;
3176 return 0;
3177 }
3178
3179 static int igb_maybe_stop_tx(struct net_device *netdev,
3180 struct igb_ring *tx_ring, int size)
3181 {
3182 if (IGB_DESC_UNUSED(tx_ring) >= size)
3183 return 0;
3184 return __igb_maybe_stop_tx(netdev, tx_ring, size);
3185 }
3186
3187 static int igb_xmit_frame_ring_adv(struct sk_buff *skb,
3188 struct net_device *netdev,
3189 struct igb_ring *tx_ring)
3190 {
3191 struct igb_adapter *adapter = netdev_priv(netdev);
3192 unsigned int first;
3193 unsigned int tx_flags = 0;
3194 u8 hdr_len = 0;
3195 int tso = 0;
3196 union skb_shared_tx *shtx;
3197
3198 if (test_bit(__IGB_DOWN, &adapter->state)) {
3199 dev_kfree_skb_any(skb);
3200 return NETDEV_TX_OK;
3201 }
3202
3203 if (skb->len <= 0) {
3204 dev_kfree_skb_any(skb);
3205 return NETDEV_TX_OK;
3206 }
3207
3208 /* need: 1 descriptor per page,
3209 * + 2 desc gap to keep tail from touching head,
3210 * + 1 desc for skb->data,
3211 * + 1 desc for context descriptor,
3212 * otherwise try next time */
3213 if (igb_maybe_stop_tx(netdev, tx_ring, skb_shinfo(skb)->nr_frags + 4)) {
3214 /* this is a hard error */
3215 return NETDEV_TX_BUSY;
3216 }
3217
3218 /*
3219 * TODO: check that there currently is no other packet with
3220 * time stamping in the queue
3221 *
3222 * When doing time stamping, keep the connection to the socket
3223 * a while longer: it is still needed by skb_hwtstamp_tx(),
3224 * called either in igb_tx_hwtstamp() or by our caller when
3225 * doing software time stamping.
3226 */
3227 shtx = skb_tx(skb);
3228 if (unlikely(shtx->hardware)) {
3229 shtx->in_progress = 1;
3230 tx_flags |= IGB_TX_FLAGS_TSTAMP;
3231 } else if (likely(!shtx->software)) {
3232 /*
3233 * TODO: can this be solved in dev.c:dev_hard_start_xmit()?
3234 * There are probably unmodified driver which do something
3235 * like this and thus don't work in combination with
3236 * SOF_TIMESTAMPING_TX_SOFTWARE.
3237 */
3238 skb_orphan(skb);
3239 }
3240
3241 if (adapter->vlgrp && vlan_tx_tag_present(skb)) {
3242 tx_flags |= IGB_TX_FLAGS_VLAN;
3243 tx_flags |= (vlan_tx_tag_get(skb) << IGB_TX_FLAGS_VLAN_SHIFT);
3244 }
3245
3246 if (skb->protocol == htons(ETH_P_IP))
3247 tx_flags |= IGB_TX_FLAGS_IPV4;
3248
3249 first = tx_ring->next_to_use;
3250 tso = skb_is_gso(skb) ? igb_tso_adv(adapter, tx_ring, skb, tx_flags,
3251 &hdr_len) : 0;
3252
3253 if (tso < 0) {
3254 dev_kfree_skb_any(skb);
3255 return NETDEV_TX_OK;
3256 }
3257
3258 if (tso)
3259 tx_flags |= IGB_TX_FLAGS_TSO;
3260 else if (igb_tx_csum_adv(adapter, tx_ring, skb, tx_flags) &&
3261 (skb->ip_summed == CHECKSUM_PARTIAL))
3262 tx_flags |= IGB_TX_FLAGS_CSUM;
3263
3264 igb_tx_queue_adv(adapter, tx_ring, tx_flags,
3265 igb_tx_map_adv(adapter, tx_ring, skb, first),
3266 skb->len, hdr_len);
3267
3268 netdev->trans_start = jiffies;
3269
3270 /* Make sure there is space in the ring for the next send. */
3271 igb_maybe_stop_tx(netdev, tx_ring, MAX_SKB_FRAGS + 4);
3272
3273 return NETDEV_TX_OK;
3274 }
3275
3276 static int igb_xmit_frame_adv(struct sk_buff *skb, struct net_device *netdev)
3277 {
3278 struct igb_adapter *adapter = netdev_priv(netdev);
3279 struct igb_ring *tx_ring;
3280
3281 int r_idx = 0;
3282 r_idx = skb->queue_mapping & (IGB_ABS_MAX_TX_QUEUES - 1);
3283 tx_ring = adapter->multi_tx_table[r_idx];
3284
3285 /* This goes back to the question of how to logically map a tx queue
3286 * to a flow. Right now, performance is impacted slightly negatively
3287 * if using multiple tx queues. If the stack breaks away from a
3288 * single qdisc implementation, we can look at this again. */
3289 return (igb_xmit_frame_ring_adv(skb, netdev, tx_ring));
3290 }
3291
3292 /**
3293 * igb_tx_timeout - Respond to a Tx Hang
3294 * @netdev: network interface device structure
3295 **/
3296 static void igb_tx_timeout(struct net_device *netdev)
3297 {
3298 struct igb_adapter *adapter = netdev_priv(netdev);
3299 struct e1000_hw *hw = &adapter->hw;
3300
3301 /* Do the reset outside of interrupt context */
3302 adapter->tx_timeout_count++;
3303 schedule_work(&adapter->reset_task);
3304 wr32(E1000_EICS,
3305 (adapter->eims_enable_mask & ~adapter->eims_other));
3306 }
3307
3308 static void igb_reset_task(struct work_struct *work)
3309 {
3310 struct igb_adapter *adapter;
3311 adapter = container_of(work, struct igb_adapter, reset_task);
3312
3313 igb_reinit_locked(adapter);
3314 }
3315
3316 /**
3317 * igb_get_stats - Get System Network Statistics
3318 * @netdev: network interface device structure
3319 *
3320 * Returns the address of the device statistics structure.
3321 * The statistics are actually updated from the timer callback.
3322 **/
3323 static struct net_device_stats *igb_get_stats(struct net_device *netdev)
3324 {
3325 struct igb_adapter *adapter = netdev_priv(netdev);
3326
3327 /* only return the current stats */
3328 return &adapter->net_stats;
3329 }
3330
3331 /**
3332 * igb_change_mtu - Change the Maximum Transfer Unit
3333 * @netdev: network interface device structure
3334 * @new_mtu: new value for maximum frame size
3335 *
3336 * Returns 0 on success, negative on failure
3337 **/
3338 static int igb_change_mtu(struct net_device *netdev, int new_mtu)
3339 {
3340 struct igb_adapter *adapter = netdev_priv(netdev);
3341 int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN;
3342
3343 if ((max_frame < ETH_ZLEN + ETH_FCS_LEN) ||
3344 (max_frame > MAX_JUMBO_FRAME_SIZE)) {
3345 dev_err(&adapter->pdev->dev, "Invalid MTU setting\n");
3346 return -EINVAL;
3347 }
3348
3349 if (max_frame > MAX_STD_JUMBO_FRAME_SIZE) {
3350 dev_err(&adapter->pdev->dev, "MTU > 9216 not supported.\n");
3351 return -EINVAL;
3352 }
3353
3354 while (test_and_set_bit(__IGB_RESETTING, &adapter->state))
3355 msleep(1);
3356
3357 /* igb_down has a dependency on max_frame_size */
3358 adapter->max_frame_size = max_frame;
3359 if (netif_running(netdev))
3360 igb_down(adapter);
3361
3362 /* NOTE: netdev_alloc_skb reserves 16 bytes, and typically NET_IP_ALIGN
3363 * means we reserve 2 more, this pushes us to allocate from the next
3364 * larger slab size.
3365 * i.e. RXBUFFER_2048 --> size-4096 slab
3366 */
3367
3368 if (max_frame <= IGB_RXBUFFER_256)
3369 adapter->rx_buffer_len = IGB_RXBUFFER_256;
3370 else if (max_frame <= IGB_RXBUFFER_512)
3371 adapter->rx_buffer_len = IGB_RXBUFFER_512;
3372 else if (max_frame <= IGB_RXBUFFER_1024)
3373 adapter->rx_buffer_len = IGB_RXBUFFER_1024;
3374 else if (max_frame <= IGB_RXBUFFER_2048)
3375 adapter->rx_buffer_len = IGB_RXBUFFER_2048;
3376 else
3377 #if (PAGE_SIZE / 2) > IGB_RXBUFFER_16384
3378 adapter->rx_buffer_len = IGB_RXBUFFER_16384;
3379 #else
3380 adapter->rx_buffer_len = PAGE_SIZE / 2;
3381 #endif
3382
3383 /* if sr-iov is enabled we need to force buffer size to 1K or larger */
3384 if (adapter->vfs_allocated_count &&
3385 (adapter->rx_buffer_len < IGB_RXBUFFER_1024))
3386 adapter->rx_buffer_len = IGB_RXBUFFER_1024;
3387
3388 /* adjust allocation if LPE protects us, and we aren't using SBP */
3389 if ((max_frame == ETH_FRAME_LEN + ETH_FCS_LEN) ||
3390 (max_frame == MAXIMUM_ETHERNET_VLAN_SIZE))
3391 adapter->rx_buffer_len = MAXIMUM_ETHERNET_VLAN_SIZE;
3392
3393 dev_info(&adapter->pdev->dev, "changing MTU from %d to %d\n",
3394 netdev->mtu, new_mtu);
3395 netdev->mtu = new_mtu;
3396
3397 if (netif_running(netdev))
3398 igb_up(adapter);
3399 else
3400 igb_reset(adapter);
3401
3402 clear_bit(__IGB_RESETTING, &adapter->state);
3403
3404 return 0;
3405 }
3406
3407 /**
3408 * igb_update_stats - Update the board statistics counters
3409 * @adapter: board private structure
3410 **/
3411
3412 void igb_update_stats(struct igb_adapter *adapter)
3413 {
3414 struct e1000_hw *hw = &adapter->hw;
3415 struct pci_dev *pdev = adapter->pdev;
3416 u16 phy_tmp;
3417
3418 #define PHY_IDLE_ERROR_COUNT_MASK 0x00FF
3419
3420 /*
3421 * Prevent stats update while adapter is being reset, or if the pci
3422 * connection is down.
3423 */
3424 if (adapter->link_speed == 0)
3425 return;
3426 if (pci_channel_offline(pdev))
3427 return;
3428
3429 adapter->stats.crcerrs += rd32(E1000_CRCERRS);
3430 adapter->stats.gprc += rd32(E1000_GPRC);
3431 adapter->stats.gorc += rd32(E1000_GORCL);
3432 rd32(E1000_GORCH); /* clear GORCL */
3433 adapter->stats.bprc += rd32(E1000_BPRC);
3434 adapter->stats.mprc += rd32(E1000_MPRC);
3435 adapter->stats.roc += rd32(E1000_ROC);
3436
3437 adapter->stats.prc64 += rd32(E1000_PRC64);
3438 adapter->stats.prc127 += rd32(E1000_PRC127);
3439 adapter->stats.prc255 += rd32(E1000_PRC255);
3440 adapter->stats.prc511 += rd32(E1000_PRC511);
3441 adapter->stats.prc1023 += rd32(E1000_PRC1023);
3442 adapter->stats.prc1522 += rd32(E1000_PRC1522);
3443 adapter->stats.symerrs += rd32(E1000_SYMERRS);
3444 adapter->stats.sec += rd32(E1000_SEC);
3445
3446 adapter->stats.mpc += rd32(E1000_MPC);
3447 adapter->stats.scc += rd32(E1000_SCC);
3448 adapter->stats.ecol += rd32(E1000_ECOL);
3449 adapter->stats.mcc += rd32(E1000_MCC);
3450 adapter->stats.latecol += rd32(E1000_LATECOL);
3451 adapter->stats.dc += rd32(E1000_DC);
3452 adapter->stats.rlec += rd32(E1000_RLEC);
3453 adapter->stats.xonrxc += rd32(E1000_XONRXC);
3454 adapter->stats.xontxc += rd32(E1000_XONTXC);
3455 adapter->stats.xoffrxc += rd32(E1000_XOFFRXC);
3456 adapter->stats.xofftxc += rd32(E1000_XOFFTXC);
3457 adapter->stats.fcruc += rd32(E1000_FCRUC);
3458 adapter->stats.gptc += rd32(E1000_GPTC);
3459 adapter->stats.gotc += rd32(E1000_GOTCL);
3460 rd32(E1000_GOTCH); /* clear GOTCL */
3461 adapter->stats.rnbc += rd32(E1000_RNBC);
3462 adapter->stats.ruc += rd32(E1000_RUC);
3463 adapter->stats.rfc += rd32(E1000_RFC);
3464 adapter->stats.rjc += rd32(E1000_RJC);
3465 adapter->stats.tor += rd32(E1000_TORH);
3466 adapter->stats.tot += rd32(E1000_TOTH);
3467 adapter->stats.tpr += rd32(E1000_TPR);
3468
3469 adapter->stats.ptc64 += rd32(E1000_PTC64);
3470 adapter->stats.ptc127 += rd32(E1000_PTC127);
3471 adapter->stats.ptc255 += rd32(E1000_PTC255);
3472 adapter->stats.ptc511 += rd32(E1000_PTC511);
3473 adapter->stats.ptc1023 += rd32(E1000_PTC1023);
3474 adapter->stats.ptc1522 += rd32(E1000_PTC1522);
3475
3476 adapter->stats.mptc += rd32(E1000_MPTC);
3477 adapter->stats.bptc += rd32(E1000_BPTC);
3478
3479 /* used for adaptive IFS */
3480
3481 hw->mac.tx_packet_delta = rd32(E1000_TPT);
3482 adapter->stats.tpt += hw->mac.tx_packet_delta;
3483 hw->mac.collision_delta = rd32(E1000_COLC);
3484 adapter->stats.colc += hw->mac.collision_delta;
3485
3486 adapter->stats.algnerrc += rd32(E1000_ALGNERRC);
3487 adapter->stats.rxerrc += rd32(E1000_RXERRC);
3488 adapter->stats.tncrs += rd32(E1000_TNCRS);
3489 adapter->stats.tsctc += rd32(E1000_TSCTC);
3490 adapter->stats.tsctfc += rd32(E1000_TSCTFC);
3491
3492 adapter->stats.iac += rd32(E1000_IAC);
3493 adapter->stats.icrxoc += rd32(E1000_ICRXOC);
3494 adapter->stats.icrxptc += rd32(E1000_ICRXPTC);
3495 adapter->stats.icrxatc += rd32(E1000_ICRXATC);
3496 adapter->stats.ictxptc += rd32(E1000_ICTXPTC);
3497 adapter->stats.ictxatc += rd32(E1000_ICTXATC);
3498 adapter->stats.ictxqec += rd32(E1000_ICTXQEC);
3499 adapter->stats.ictxqmtc += rd32(E1000_ICTXQMTC);
3500 adapter->stats.icrxdmtc += rd32(E1000_ICRXDMTC);
3501
3502 /* Fill out the OS statistics structure */
3503 adapter->net_stats.multicast = adapter->stats.mprc;
3504 adapter->net_stats.collisions = adapter->stats.colc;
3505
3506 /* Rx Errors */
3507
3508 /* RLEC on some newer hardware can be incorrect so build
3509 * our own version based on RUC and ROC */
3510 adapter->net_stats.rx_errors = adapter->stats.rxerrc +
3511 adapter->stats.crcerrs + adapter->stats.algnerrc +
3512 adapter->stats.ruc + adapter->stats.roc +
3513 adapter->stats.cexterr;
3514 adapter->net_stats.rx_length_errors = adapter->stats.ruc +
3515 adapter->stats.roc;
3516 adapter->net_stats.rx_crc_errors = adapter->stats.crcerrs;
3517 adapter->net_stats.rx_frame_errors = adapter->stats.algnerrc;
3518 adapter->net_stats.rx_missed_errors = adapter->stats.mpc;
3519
3520 /* Tx Errors */
3521 adapter->net_stats.tx_errors = adapter->stats.ecol +
3522 adapter->stats.latecol;
3523 adapter->net_stats.tx_aborted_errors = adapter->stats.ecol;
3524 adapter->net_stats.tx_window_errors = adapter->stats.latecol;
3525 adapter->net_stats.tx_carrier_errors = adapter->stats.tncrs;
3526
3527 /* Tx Dropped needs to be maintained elsewhere */
3528
3529 /* Phy Stats */
3530 if (hw->phy.media_type == e1000_media_type_copper) {
3531 if ((adapter->link_speed == SPEED_1000) &&
3532 (!igb_read_phy_reg(hw, PHY_1000T_STATUS, &phy_tmp))) {
3533 phy_tmp &= PHY_IDLE_ERROR_COUNT_MASK;
3534 adapter->phy_stats.idle_errors += phy_tmp;
3535 }
3536 }
3537
3538 /* Management Stats */
3539 adapter->stats.mgptc += rd32(E1000_MGTPTC);
3540 adapter->stats.mgprc += rd32(E1000_MGTPRC);
3541 adapter->stats.mgpdc += rd32(E1000_MGTPDC);
3542 }
3543
3544 static irqreturn_t igb_msix_other(int irq, void *data)
3545 {
3546 struct net_device *netdev = data;
3547 struct igb_adapter *adapter = netdev_priv(netdev);
3548 struct e1000_hw *hw = &adapter->hw;
3549 u32 icr = rd32(E1000_ICR);
3550
3551 /* reading ICR causes bit 31 of EICR to be cleared */
3552
3553 if(icr & E1000_ICR_DOUTSYNC) {
3554 /* HW is reporting DMA is out of sync */
3555 adapter->stats.doosync++;
3556 }
3557
3558 /* Check for a mailbox event */
3559 if (icr & E1000_ICR_VMMB)
3560 igb_msg_task(adapter);
3561
3562 if (icr & E1000_ICR_LSC) {
3563 hw->mac.get_link_status = 1;
3564 /* guard against interrupt when we're going down */
3565 if (!test_bit(__IGB_DOWN, &adapter->state))
3566 mod_timer(&adapter->watchdog_timer, jiffies + 1);
3567 }
3568
3569 wr32(E1000_IMS, E1000_IMS_LSC | E1000_IMS_DOUTSYNC | E1000_IMS_VMMB);
3570 wr32(E1000_EIMS, adapter->eims_other);
3571
3572 return IRQ_HANDLED;
3573 }
3574
3575 static irqreturn_t igb_msix_tx(int irq, void *data)
3576 {
3577 struct igb_ring *tx_ring = data;
3578 struct igb_adapter *adapter = tx_ring->adapter;
3579 struct e1000_hw *hw = &adapter->hw;
3580
3581 #ifdef CONFIG_IGB_DCA
3582 if (adapter->flags & IGB_FLAG_DCA_ENABLED)
3583 igb_update_tx_dca(tx_ring);
3584 #endif
3585
3586 tx_ring->total_bytes = 0;
3587 tx_ring->total_packets = 0;
3588
3589 /* auto mask will automatically reenable the interrupt when we write
3590 * EICS */
3591 if (!igb_clean_tx_irq(tx_ring))
3592 /* Ring was not completely cleaned, so fire another interrupt */
3593 wr32(E1000_EICS, tx_ring->eims_value);
3594 else
3595 wr32(E1000_EIMS, tx_ring->eims_value);
3596
3597 return IRQ_HANDLED;
3598 }
3599
3600 static void igb_write_itr(struct igb_ring *ring)
3601 {
3602 struct e1000_hw *hw = &ring->adapter->hw;
3603 if ((ring->adapter->itr_setting & 3) && ring->set_itr) {
3604 switch (hw->mac.type) {
3605 case e1000_82576:
3606 wr32(ring->itr_register, ring->itr_val |
3607 0x80000000);
3608 break;
3609 default:
3610 wr32(ring->itr_register, ring->itr_val |
3611 (ring->itr_val << 16));
3612 break;
3613 }
3614 ring->set_itr = 0;
3615 }
3616 }
3617
3618 static irqreturn_t igb_msix_rx(int irq, void *data)
3619 {
3620 struct igb_ring *rx_ring = data;
3621
3622 /* Write the ITR value calculated at the end of the
3623 * previous interrupt.
3624 */
3625
3626 igb_write_itr(rx_ring);
3627
3628 if (napi_schedule_prep(&rx_ring->napi))
3629 __napi_schedule(&rx_ring->napi);
3630
3631 #ifdef CONFIG_IGB_DCA
3632 if (rx_ring->adapter->flags & IGB_FLAG_DCA_ENABLED)
3633 igb_update_rx_dca(rx_ring);
3634 #endif
3635 return IRQ_HANDLED;
3636 }
3637
3638 #ifdef CONFIG_IGB_DCA
3639 static void igb_update_rx_dca(struct igb_ring *rx_ring)
3640 {
3641 u32 dca_rxctrl;
3642 struct igb_adapter *adapter = rx_ring->adapter;
3643 struct e1000_hw *hw = &adapter->hw;
3644 int cpu = get_cpu();
3645 int q = rx_ring->reg_idx;
3646
3647 if (rx_ring->cpu != cpu) {
3648 dca_rxctrl = rd32(E1000_DCA_RXCTRL(q));
3649 if (hw->mac.type == e1000_82576) {
3650 dca_rxctrl &= ~E1000_DCA_RXCTRL_CPUID_MASK_82576;
3651 dca_rxctrl |= dca_get_tag(cpu) <<
3652 E1000_DCA_RXCTRL_CPUID_SHIFT;
3653 } else {
3654 dca_rxctrl &= ~E1000_DCA_RXCTRL_CPUID_MASK;
3655 dca_rxctrl |= dca_get_tag(cpu);
3656 }
3657 dca_rxctrl |= E1000_DCA_RXCTRL_DESC_DCA_EN;
3658 dca_rxctrl |= E1000_DCA_RXCTRL_HEAD_DCA_EN;
3659 dca_rxctrl |= E1000_DCA_RXCTRL_DATA_DCA_EN;
3660 wr32(E1000_DCA_RXCTRL(q), dca_rxctrl);
3661 rx_ring->cpu = cpu;
3662 }
3663 put_cpu();
3664 }
3665
3666 static void igb_update_tx_dca(struct igb_ring *tx_ring)
3667 {
3668 u32 dca_txctrl;
3669 struct igb_adapter *adapter = tx_ring->adapter;
3670 struct e1000_hw *hw = &adapter->hw;
3671 int cpu = get_cpu();
3672 int q = tx_ring->reg_idx;
3673
3674 if (tx_ring->cpu != cpu) {
3675 dca_txctrl = rd32(E1000_DCA_TXCTRL(q));
3676 if (hw->mac.type == e1000_82576) {
3677 dca_txctrl &= ~E1000_DCA_TXCTRL_CPUID_MASK_82576;
3678 dca_txctrl |= dca_get_tag(cpu) <<
3679 E1000_DCA_TXCTRL_CPUID_SHIFT;
3680 } else {
3681 dca_txctrl &= ~E1000_DCA_TXCTRL_CPUID_MASK;
3682 dca_txctrl |= dca_get_tag(cpu);
3683 }
3684 dca_txctrl |= E1000_DCA_TXCTRL_DESC_DCA_EN;
3685 wr32(E1000_DCA_TXCTRL(q), dca_txctrl);
3686 tx_ring->cpu = cpu;
3687 }
3688 put_cpu();
3689 }
3690
3691 static void igb_setup_dca(struct igb_adapter *adapter)
3692 {
3693 int i;
3694
3695 if (!(adapter->flags & IGB_FLAG_DCA_ENABLED))
3696 return;
3697
3698 for (i = 0; i < adapter->num_tx_queues; i++) {
3699 adapter->tx_ring[i].cpu = -1;
3700 igb_update_tx_dca(&adapter->tx_ring[i]);
3701 }
3702 for (i = 0; i < adapter->num_rx_queues; i++) {
3703 adapter->rx_ring[i].cpu = -1;
3704 igb_update_rx_dca(&adapter->rx_ring[i]);
3705 }
3706 }
3707
3708 static int __igb_notify_dca(struct device *dev, void *data)
3709 {
3710 struct net_device *netdev = dev_get_drvdata(dev);
3711 struct igb_adapter *adapter = netdev_priv(netdev);
3712 struct e1000_hw *hw = &adapter->hw;
3713 unsigned long event = *(unsigned long *)data;
3714
3715 switch (event) {
3716 case DCA_PROVIDER_ADD:
3717 /* if already enabled, don't do it again */
3718 if (adapter->flags & IGB_FLAG_DCA_ENABLED)
3719 break;
3720 /* Always use CB2 mode, difference is masked
3721 * in the CB driver. */
3722 wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_CB2);
3723 if (dca_add_requester(dev) == 0) {
3724 adapter->flags |= IGB_FLAG_DCA_ENABLED;
3725 dev_info(&adapter->pdev->dev, "DCA enabled\n");
3726 igb_setup_dca(adapter);
3727 break;
3728 }
3729 /* Fall Through since DCA is disabled. */
3730 case DCA_PROVIDER_REMOVE:
3731 if (adapter->flags & IGB_FLAG_DCA_ENABLED) {
3732 /* without this a class_device is left
3733 * hanging around in the sysfs model */
3734 dca_remove_requester(dev);
3735 dev_info(&adapter->pdev->dev, "DCA disabled\n");
3736 adapter->flags &= ~IGB_FLAG_DCA_ENABLED;
3737 wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_DISABLE);
3738 }
3739 break;
3740 }
3741
3742 return 0;
3743 }
3744
3745 static int igb_notify_dca(struct notifier_block *nb, unsigned long event,
3746 void *p)
3747 {
3748 int ret_val;
3749
3750 ret_val = driver_for_each_device(&igb_driver.driver, NULL, &event,
3751 __igb_notify_dca);
3752
3753 return ret_val ? NOTIFY_BAD : NOTIFY_DONE;
3754 }
3755 #endif /* CONFIG_IGB_DCA */
3756
3757 static void igb_ping_all_vfs(struct igb_adapter *adapter)
3758 {
3759 struct e1000_hw *hw = &adapter->hw;
3760 u32 ping;
3761 int i;
3762
3763 for (i = 0 ; i < adapter->vfs_allocated_count; i++) {
3764 ping = E1000_PF_CONTROL_MSG;
3765 if (adapter->vf_data[i].clear_to_send)
3766 ping |= E1000_VT_MSGTYPE_CTS;
3767 igb_write_mbx(hw, &ping, 1, i);
3768 }
3769 }
3770
3771 static int igb_set_vf_multicasts(struct igb_adapter *adapter,
3772 u32 *msgbuf, u32 vf)
3773 {
3774 int n = (msgbuf[0] & E1000_VT_MSGINFO_MASK) >> E1000_VT_MSGINFO_SHIFT;
3775 u16 *hash_list = (u16 *)&msgbuf[1];
3776 struct vf_data_storage *vf_data = &adapter->vf_data[vf];
3777 int i;
3778
3779 /* only up to 30 hash values supported */
3780 if (n > 30)
3781 n = 30;
3782
3783 /* salt away the number of multi cast addresses assigned
3784 * to this VF for later use to restore when the PF multi cast
3785 * list changes
3786 */
3787 vf_data->num_vf_mc_hashes = n;
3788
3789 /* VFs are limited to using the MTA hash table for their multicast
3790 * addresses */
3791 for (i = 0; i < n; i++)
3792 vf_data->vf_mc_hashes[i] = hash_list[i];;
3793
3794 /* Flush and reset the mta with the new values */
3795 igb_set_multi(adapter->netdev);
3796
3797 return 0;
3798 }
3799
3800 static void igb_restore_vf_multicasts(struct igb_adapter *adapter)
3801 {
3802 struct e1000_hw *hw = &adapter->hw;
3803 struct vf_data_storage *vf_data;
3804 int i, j;
3805
3806 for (i = 0; i < adapter->vfs_allocated_count; i++) {
3807 vf_data = &adapter->vf_data[i];
3808 for (j = 0; j < vf_data[i].num_vf_mc_hashes; j++)
3809 igb_mta_set(hw, vf_data->vf_mc_hashes[j]);
3810 }
3811 }
3812
3813 static void igb_clear_vf_vfta(struct igb_adapter *adapter, u32 vf)
3814 {
3815 struct e1000_hw *hw = &adapter->hw;
3816 u32 pool_mask, reg, vid;
3817 int i;
3818
3819 pool_mask = 1 << (E1000_VLVF_POOLSEL_SHIFT + vf);
3820
3821 /* Find the vlan filter for this id */
3822 for (i = 0; i < E1000_VLVF_ARRAY_SIZE; i++) {
3823 reg = rd32(E1000_VLVF(i));
3824
3825 /* remove the vf from the pool */
3826 reg &= ~pool_mask;
3827
3828 /* if pool is empty then remove entry from vfta */
3829 if (!(reg & E1000_VLVF_POOLSEL_MASK) &&
3830 (reg & E1000_VLVF_VLANID_ENABLE)) {
3831 reg = 0;
3832 vid = reg & E1000_VLVF_VLANID_MASK;
3833 igb_vfta_set(hw, vid, false);
3834 }
3835
3836 wr32(E1000_VLVF(i), reg);
3837 }
3838 }
3839
3840 static s32 igb_vlvf_set(struct igb_adapter *adapter, u32 vid, bool add, u32 vf)
3841 {
3842 struct e1000_hw *hw = &adapter->hw;
3843 u32 reg, i;
3844
3845 /* It is an error to call this function when VFs are not enabled */
3846 if (!adapter->vfs_allocated_count)
3847 return -1;
3848
3849 /* Find the vlan filter for this id */
3850 for (i = 0; i < E1000_VLVF_ARRAY_SIZE; i++) {
3851 reg = rd32(E1000_VLVF(i));
3852 if ((reg & E1000_VLVF_VLANID_ENABLE) &&
3853 vid == (reg & E1000_VLVF_VLANID_MASK))
3854 break;
3855 }
3856
3857 if (add) {
3858 if (i == E1000_VLVF_ARRAY_SIZE) {
3859 /* Did not find a matching VLAN ID entry that was
3860 * enabled. Search for a free filter entry, i.e.
3861 * one without the enable bit set
3862 */
3863 for (i = 0; i < E1000_VLVF_ARRAY_SIZE; i++) {
3864 reg = rd32(E1000_VLVF(i));
3865 if (!(reg & E1000_VLVF_VLANID_ENABLE))
3866 break;
3867 }
3868 }
3869 if (i < E1000_VLVF_ARRAY_SIZE) {
3870 /* Found an enabled/available entry */
3871 reg |= 1 << (E1000_VLVF_POOLSEL_SHIFT + vf);
3872
3873 /* if !enabled we need to set this up in vfta */
3874 if (!(reg & E1000_VLVF_VLANID_ENABLE)) {
3875 /* add VID to filter table */
3876 igb_vfta_set(hw, vid, true);
3877 reg |= E1000_VLVF_VLANID_ENABLE;
3878 }
3879
3880 wr32(E1000_VLVF(i), reg);
3881 return 0;
3882 }
3883 } else {
3884 if (i < E1000_VLVF_ARRAY_SIZE) {
3885 /* remove vf from the pool */
3886 reg &= ~(1 << (E1000_VLVF_POOLSEL_SHIFT + vf));
3887 /* if pool is empty then remove entry from vfta */
3888 if (!(reg & E1000_VLVF_POOLSEL_MASK)) {
3889 reg = 0;
3890 igb_vfta_set(hw, vid, false);
3891 }
3892 wr32(E1000_VLVF(i), reg);
3893 return 0;
3894 }
3895 }
3896 return -1;
3897 }
3898
3899 static int igb_set_vf_vlan(struct igb_adapter *adapter, u32 *msgbuf, u32 vf)
3900 {
3901 int add = (msgbuf[0] & E1000_VT_MSGINFO_MASK) >> E1000_VT_MSGINFO_SHIFT;
3902 int vid = (msgbuf[1] & E1000_VLVF_VLANID_MASK);
3903
3904 return igb_vlvf_set(adapter, vid, add, vf);
3905 }
3906
3907 static inline void igb_vf_reset_event(struct igb_adapter *adapter, u32 vf)
3908 {
3909 struct e1000_hw *hw = &adapter->hw;
3910
3911 /* disable mailbox functionality for vf */
3912 adapter->vf_data[vf].clear_to_send = false;
3913
3914 /* reset offloads to defaults */
3915 igb_set_vmolr(hw, vf);
3916
3917 /* reset vlans for device */
3918 igb_clear_vf_vfta(adapter, vf);
3919
3920 /* reset multicast table array for vf */
3921 adapter->vf_data[vf].num_vf_mc_hashes = 0;
3922
3923 /* Flush and reset the mta with the new values */
3924 igb_set_multi(adapter->netdev);
3925 }
3926
3927 static inline void igb_vf_reset_msg(struct igb_adapter *adapter, u32 vf)
3928 {
3929 struct e1000_hw *hw = &adapter->hw;
3930 unsigned char *vf_mac = adapter->vf_data[vf].vf_mac_addresses;
3931 u32 reg, msgbuf[3];
3932 u8 *addr = (u8 *)(&msgbuf[1]);
3933
3934 /* process all the same items cleared in a function level reset */
3935 igb_vf_reset_event(adapter, vf);
3936
3937 /* set vf mac address */
3938 igb_rar_set(hw, vf_mac, vf + 1);
3939 igb_set_rah_pool(hw, vf, vf + 1);
3940
3941 /* enable transmit and receive for vf */
3942 reg = rd32(E1000_VFTE);
3943 wr32(E1000_VFTE, reg | (1 << vf));
3944 reg = rd32(E1000_VFRE);
3945 wr32(E1000_VFRE, reg | (1 << vf));
3946
3947 /* enable mailbox functionality for vf */
3948 adapter->vf_data[vf].clear_to_send = true;
3949
3950 /* reply to reset with ack and vf mac address */
3951 msgbuf[0] = E1000_VF_RESET | E1000_VT_MSGTYPE_ACK;
3952 memcpy(addr, vf_mac, 6);
3953 igb_write_mbx(hw, msgbuf, 3, vf);
3954 }
3955
3956 static int igb_set_vf_mac_addr(struct igb_adapter *adapter, u32 *msg, int vf)
3957 {
3958 unsigned char *addr = (char *)&msg[1];
3959 int err = -1;
3960
3961 if (is_valid_ether_addr(addr))
3962 err = igb_set_vf_mac(adapter, vf, addr);
3963
3964 return err;
3965
3966 }
3967
3968 static void igb_rcv_ack_from_vf(struct igb_adapter *adapter, u32 vf)
3969 {
3970 struct e1000_hw *hw = &adapter->hw;
3971 u32 msg = E1000_VT_MSGTYPE_NACK;
3972
3973 /* if device isn't clear to send it shouldn't be reading either */
3974 if (!adapter->vf_data[vf].clear_to_send)
3975 igb_write_mbx(hw, &msg, 1, vf);
3976 }
3977
3978
3979 static void igb_msg_task(struct igb_adapter *adapter)
3980 {
3981 struct e1000_hw *hw = &adapter->hw;
3982 u32 vf;
3983
3984 for (vf = 0; vf < adapter->vfs_allocated_count; vf++) {
3985 /* process any reset requests */
3986 if (!igb_check_for_rst(hw, vf)) {
3987 adapter->vf_data[vf].clear_to_send = false;
3988 igb_vf_reset_event(adapter, vf);
3989 }
3990
3991 /* process any messages pending */
3992 if (!igb_check_for_msg(hw, vf))
3993 igb_rcv_msg_from_vf(adapter, vf);
3994
3995 /* process any acks */
3996 if (!igb_check_for_ack(hw, vf))
3997 igb_rcv_ack_from_vf(adapter, vf);
3998
3999 }
4000 }
4001
4002 static int igb_rcv_msg_from_vf(struct igb_adapter *adapter, u32 vf)
4003 {
4004 u32 mbx_size = E1000_VFMAILBOX_SIZE;
4005 u32 msgbuf[mbx_size];
4006 struct e1000_hw *hw = &adapter->hw;
4007 s32 retval;
4008
4009 retval = igb_read_mbx(hw, msgbuf, mbx_size, vf);
4010
4011 if (retval)
4012 dev_err(&adapter->pdev->dev,
4013 "Error receiving message from VF\n");
4014
4015 /* this is a message we already processed, do nothing */
4016 if (msgbuf[0] & (E1000_VT_MSGTYPE_ACK | E1000_VT_MSGTYPE_NACK))
4017 return retval;
4018
4019 /*
4020 * until the vf completes a reset it should not be
4021 * allowed to start any configuration.
4022 */
4023
4024 if (msgbuf[0] == E1000_VF_RESET) {
4025 igb_vf_reset_msg(adapter, vf);
4026
4027 return retval;
4028 }
4029
4030 if (!adapter->vf_data[vf].clear_to_send) {
4031 msgbuf[0] |= E1000_VT_MSGTYPE_NACK;
4032 igb_write_mbx(hw, msgbuf, 1, vf);
4033 return retval;
4034 }
4035
4036 switch ((msgbuf[0] & 0xFFFF)) {
4037 case E1000_VF_SET_MAC_ADDR:
4038 retval = igb_set_vf_mac_addr(adapter, msgbuf, vf);
4039 break;
4040 case E1000_VF_SET_MULTICAST:
4041 retval = igb_set_vf_multicasts(adapter, msgbuf, vf);
4042 break;
4043 case E1000_VF_SET_LPE:
4044 retval = igb_set_vf_rlpml(adapter, msgbuf[1], vf);
4045 break;
4046 case E1000_VF_SET_VLAN:
4047 retval = igb_set_vf_vlan(adapter, msgbuf, vf);
4048 break;
4049 default:
4050 dev_err(&adapter->pdev->dev, "Unhandled Msg %08x\n", msgbuf[0]);
4051 retval = -1;
4052 break;
4053 }
4054
4055 /* notify the VF of the results of what it sent us */
4056 if (retval)
4057 msgbuf[0] |= E1000_VT_MSGTYPE_NACK;
4058 else
4059 msgbuf[0] |= E1000_VT_MSGTYPE_ACK;
4060
4061 msgbuf[0] |= E1000_VT_MSGTYPE_CTS;
4062
4063 igb_write_mbx(hw, msgbuf, 1, vf);
4064
4065 return retval;
4066 }
4067
4068 /**
4069 * igb_intr_msi - Interrupt Handler
4070 * @irq: interrupt number
4071 * @data: pointer to a network interface device structure
4072 **/
4073 static irqreturn_t igb_intr_msi(int irq, void *data)
4074 {
4075 struct net_device *netdev = data;
4076 struct igb_adapter *adapter = netdev_priv(netdev);
4077 struct e1000_hw *hw = &adapter->hw;
4078 /* read ICR disables interrupts using IAM */
4079 u32 icr = rd32(E1000_ICR);
4080
4081 igb_write_itr(adapter->rx_ring);
4082
4083 if(icr & E1000_ICR_DOUTSYNC) {
4084 /* HW is reporting DMA is out of sync */
4085 adapter->stats.doosync++;
4086 }
4087
4088 if (icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) {
4089 hw->mac.get_link_status = 1;
4090 if (!test_bit(__IGB_DOWN, &adapter->state))
4091 mod_timer(&adapter->watchdog_timer, jiffies + 1);
4092 }
4093
4094 napi_schedule(&adapter->rx_ring[0].napi);
4095
4096 return IRQ_HANDLED;
4097 }
4098
4099 /**
4100 * igb_intr - Legacy Interrupt Handler
4101 * @irq: interrupt number
4102 * @data: pointer to a network interface device structure
4103 **/
4104 static irqreturn_t igb_intr(int irq, void *data)
4105 {
4106 struct net_device *netdev = data;
4107 struct igb_adapter *adapter = netdev_priv(netdev);
4108 struct e1000_hw *hw = &adapter->hw;
4109 /* Interrupt Auto-Mask...upon reading ICR, interrupts are masked. No
4110 * need for the IMC write */
4111 u32 icr = rd32(E1000_ICR);
4112 if (!icr)
4113 return IRQ_NONE; /* Not our interrupt */
4114
4115 igb_write_itr(adapter->rx_ring);
4116
4117 /* IMS will not auto-mask if INT_ASSERTED is not set, and if it is
4118 * not set, then the adapter didn't send an interrupt */
4119 if (!(icr & E1000_ICR_INT_ASSERTED))
4120 return IRQ_NONE;
4121
4122 if(icr & E1000_ICR_DOUTSYNC) {
4123 /* HW is reporting DMA is out of sync */
4124 adapter->stats.doosync++;
4125 }
4126
4127 if (icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) {
4128 hw->mac.get_link_status = 1;
4129 /* guard against interrupt when we're going down */
4130 if (!test_bit(__IGB_DOWN, &adapter->state))
4131 mod_timer(&adapter->watchdog_timer, jiffies + 1);
4132 }
4133
4134 napi_schedule(&adapter->rx_ring[0].napi);
4135
4136 return IRQ_HANDLED;
4137 }
4138
4139 static inline void igb_rx_irq_enable(struct igb_ring *rx_ring)
4140 {
4141 struct igb_adapter *adapter = rx_ring->adapter;
4142 struct e1000_hw *hw = &adapter->hw;
4143
4144 if (adapter->itr_setting & 3) {
4145 if (adapter->num_rx_queues == 1)
4146 igb_set_itr(adapter);
4147 else
4148 igb_update_ring_itr(rx_ring);
4149 }
4150
4151 if (!test_bit(__IGB_DOWN, &adapter->state)) {
4152 if (adapter->msix_entries)
4153 wr32(E1000_EIMS, rx_ring->eims_value);
4154 else
4155 igb_irq_enable(adapter);
4156 }
4157 }
4158
4159 /**
4160 * igb_poll - NAPI Rx polling callback
4161 * @napi: napi polling structure
4162 * @budget: count of how many packets we should handle
4163 **/
4164 static int igb_poll(struct napi_struct *napi, int budget)
4165 {
4166 struct igb_ring *rx_ring = container_of(napi, struct igb_ring, napi);
4167 struct igb_adapter *adapter = rx_ring->adapter;
4168 struct net_device *netdev = adapter->netdev;
4169 int work_done = 0;
4170
4171 #ifdef CONFIG_IGB_DCA
4172 if (adapter->flags & IGB_FLAG_DCA_ENABLED)
4173 igb_update_rx_dca(rx_ring);
4174 #endif
4175 igb_clean_rx_irq_adv(rx_ring, &work_done, budget);
4176
4177 if (rx_ring->buddy) {
4178 #ifdef CONFIG_IGB_DCA
4179 if (adapter->flags & IGB_FLAG_DCA_ENABLED)
4180 igb_update_tx_dca(rx_ring->buddy);
4181 #endif
4182 if (!igb_clean_tx_irq(rx_ring->buddy))
4183 work_done = budget;
4184 }
4185
4186 /* If not enough Rx work done, exit the polling mode */
4187 if ((work_done < budget) || !netif_running(netdev)) {
4188 napi_complete(napi);
4189 igb_rx_irq_enable(rx_ring);
4190 }
4191
4192 return work_done;
4193 }
4194
4195 /**
4196 * igb_hwtstamp - utility function which checks for TX time stamp
4197 * @adapter: board private structure
4198 * @skb: packet that was just sent
4199 *
4200 * If we were asked to do hardware stamping and such a time stamp is
4201 * available, then it must have been for this skb here because we only
4202 * allow only one such packet into the queue.
4203 */
4204 static void igb_tx_hwtstamp(struct igb_adapter *adapter, struct sk_buff *skb)
4205 {
4206 union skb_shared_tx *shtx = skb_tx(skb);
4207 struct e1000_hw *hw = &adapter->hw;
4208
4209 if (unlikely(shtx->hardware)) {
4210 u32 valid = rd32(E1000_TSYNCTXCTL) & E1000_TSYNCTXCTL_VALID;
4211 if (valid) {
4212 u64 regval = rd32(E1000_TXSTMPL);
4213 u64 ns;
4214 struct skb_shared_hwtstamps shhwtstamps;
4215
4216 memset(&shhwtstamps, 0, sizeof(shhwtstamps));
4217 regval |= (u64)rd32(E1000_TXSTMPH) << 32;
4218 ns = timecounter_cyc2time(&adapter->clock,
4219 regval);
4220 timecompare_update(&adapter->compare, ns);
4221 shhwtstamps.hwtstamp = ns_to_ktime(ns);
4222 shhwtstamps.syststamp =
4223 timecompare_transform(&adapter->compare, ns);
4224 skb_tstamp_tx(skb, &shhwtstamps);
4225 }
4226
4227 /* delayed orphaning: skb_tstamp_tx() needs the socket */
4228 skb_orphan(skb);
4229 }
4230 }
4231
4232 /**
4233 * igb_clean_tx_irq - Reclaim resources after transmit completes
4234 * @adapter: board private structure
4235 * returns true if ring is completely cleaned
4236 **/
4237 static bool igb_clean_tx_irq(struct igb_ring *tx_ring)
4238 {
4239 struct igb_adapter *adapter = tx_ring->adapter;
4240 struct net_device *netdev = adapter->netdev;
4241 struct e1000_hw *hw = &adapter->hw;
4242 struct igb_buffer *buffer_info;
4243 struct sk_buff *skb;
4244 union e1000_adv_tx_desc *tx_desc, *eop_desc;
4245 unsigned int total_bytes = 0, total_packets = 0;
4246 unsigned int i, eop, count = 0;
4247 bool cleaned = false;
4248
4249 i = tx_ring->next_to_clean;
4250 eop = tx_ring->buffer_info[i].next_to_watch;
4251 eop_desc = E1000_TX_DESC_ADV(*tx_ring, eop);
4252
4253 while ((eop_desc->wb.status & cpu_to_le32(E1000_TXD_STAT_DD)) &&
4254 (count < tx_ring->count)) {
4255 for (cleaned = false; !cleaned; count++) {
4256 tx_desc = E1000_TX_DESC_ADV(*tx_ring, i);
4257 buffer_info = &tx_ring->buffer_info[i];
4258 cleaned = (i == eop);
4259 skb = buffer_info->skb;
4260
4261 if (skb) {
4262 unsigned int segs, bytecount;
4263 /* gso_segs is currently only valid for tcp */
4264 segs = skb_shinfo(skb)->gso_segs ?: 1;
4265 /* multiply data chunks by size of headers */
4266 bytecount = ((segs - 1) * skb_headlen(skb)) +
4267 skb->len;
4268 total_packets += segs;
4269 total_bytes += bytecount;
4270
4271 igb_tx_hwtstamp(adapter, skb);
4272 }
4273
4274 igb_unmap_and_free_tx_resource(adapter, buffer_info);
4275 tx_desc->wb.status = 0;
4276
4277 i++;
4278 if (i == tx_ring->count)
4279 i = 0;
4280 }
4281 eop = tx_ring->buffer_info[i].next_to_watch;
4282 eop_desc = E1000_TX_DESC_ADV(*tx_ring, eop);
4283 }
4284
4285 tx_ring->next_to_clean = i;
4286
4287 if (unlikely(count &&
4288 netif_carrier_ok(netdev) &&
4289 IGB_DESC_UNUSED(tx_ring) >= IGB_TX_QUEUE_WAKE)) {
4290 /* Make sure that anybody stopping the queue after this
4291 * sees the new next_to_clean.
4292 */
4293 smp_mb();
4294 if (__netif_subqueue_stopped(netdev, tx_ring->queue_index) &&
4295 !(test_bit(__IGB_DOWN, &adapter->state))) {
4296 netif_wake_subqueue(netdev, tx_ring->queue_index);
4297 ++adapter->restart_queue;
4298 }
4299 }
4300
4301 if (tx_ring->detect_tx_hung) {
4302 /* Detect a transmit hang in hardware, this serializes the
4303 * check with the clearing of time_stamp and movement of i */
4304 tx_ring->detect_tx_hung = false;
4305 if (tx_ring->buffer_info[i].time_stamp &&
4306 time_after(jiffies, tx_ring->buffer_info[i].time_stamp +
4307 (adapter->tx_timeout_factor * HZ))
4308 && !(rd32(E1000_STATUS) &
4309 E1000_STATUS_TXOFF)) {
4310
4311 /* detected Tx unit hang */
4312 dev_err(&adapter->pdev->dev,
4313 "Detected Tx Unit Hang\n"
4314 " Tx Queue <%d>\n"
4315 " TDH <%x>\n"
4316 " TDT <%x>\n"
4317 " next_to_use <%x>\n"
4318 " next_to_clean <%x>\n"
4319 "buffer_info[next_to_clean]\n"
4320 " time_stamp <%lx>\n"
4321 " next_to_watch <%x>\n"
4322 " jiffies <%lx>\n"
4323 " desc.status <%x>\n",
4324 tx_ring->queue_index,
4325 readl(adapter->hw.hw_addr + tx_ring->head),
4326 readl(adapter->hw.hw_addr + tx_ring->tail),
4327 tx_ring->next_to_use,
4328 tx_ring->next_to_clean,
4329 tx_ring->buffer_info[i].time_stamp,
4330 eop,
4331 jiffies,
4332 eop_desc->wb.status);
4333 netif_stop_subqueue(netdev, tx_ring->queue_index);
4334 }
4335 }
4336 tx_ring->total_bytes += total_bytes;
4337 tx_ring->total_packets += total_packets;
4338 tx_ring->tx_stats.bytes += total_bytes;
4339 tx_ring->tx_stats.packets += total_packets;
4340 adapter->net_stats.tx_bytes += total_bytes;
4341 adapter->net_stats.tx_packets += total_packets;
4342 return (count < tx_ring->count);
4343 }
4344
4345 /**
4346 * igb_receive_skb - helper function to handle rx indications
4347 * @ring: pointer to receive ring receving this packet
4348 * @status: descriptor status field as written by hardware
4349 * @rx_desc: receive descriptor containing vlan and type information.
4350 * @skb: pointer to sk_buff to be indicated to stack
4351 **/
4352 static void igb_receive_skb(struct igb_ring *ring, u8 status,
4353 union e1000_adv_rx_desc * rx_desc,
4354 struct sk_buff *skb)
4355 {
4356 struct igb_adapter * adapter = ring->adapter;
4357 bool vlan_extracted = (adapter->vlgrp && (status & E1000_RXD_STAT_VP));
4358
4359 skb_record_rx_queue(skb, ring->queue_index);
4360 if (skb->ip_summed == CHECKSUM_UNNECESSARY) {
4361 if (vlan_extracted)
4362 vlan_gro_receive(&ring->napi, adapter->vlgrp,
4363 le16_to_cpu(rx_desc->wb.upper.vlan),
4364 skb);
4365 else
4366 napi_gro_receive(&ring->napi, skb);
4367 } else {
4368 if (vlan_extracted)
4369 vlan_hwaccel_receive_skb(skb, adapter->vlgrp,
4370 le16_to_cpu(rx_desc->wb.upper.vlan));
4371 else
4372 netif_receive_skb(skb);
4373 }
4374 }
4375
4376 static inline void igb_rx_checksum_adv(struct igb_adapter *adapter,
4377 u32 status_err, struct sk_buff *skb)
4378 {
4379 skb->ip_summed = CHECKSUM_NONE;
4380
4381 /* Ignore Checksum bit is set or checksum is disabled through ethtool */
4382 if ((status_err & E1000_RXD_STAT_IXSM) || !adapter->rx_csum)
4383 return;
4384 /* TCP/UDP checksum error bit is set */
4385 if (status_err &
4386 (E1000_RXDEXT_STATERR_TCPE | E1000_RXDEXT_STATERR_IPE)) {
4387 /* let the stack verify checksum errors */
4388 adapter->hw_csum_err++;
4389 return;
4390 }
4391 /* It must be a TCP or UDP packet with a valid checksum */
4392 if (status_err & (E1000_RXD_STAT_TCPCS | E1000_RXD_STAT_UDPCS))
4393 skb->ip_summed = CHECKSUM_UNNECESSARY;
4394
4395 adapter->hw_csum_good++;
4396 }
4397
4398 static bool igb_clean_rx_irq_adv(struct igb_ring *rx_ring,
4399 int *work_done, int budget)
4400 {
4401 struct igb_adapter *adapter = rx_ring->adapter;
4402 struct net_device *netdev = adapter->netdev;
4403 struct e1000_hw *hw = &adapter->hw;
4404 struct pci_dev *pdev = adapter->pdev;
4405 union e1000_adv_rx_desc *rx_desc , *next_rxd;
4406 struct igb_buffer *buffer_info , *next_buffer;
4407 struct sk_buff *skb;
4408 bool cleaned = false;
4409 int cleaned_count = 0;
4410 unsigned int total_bytes = 0, total_packets = 0;
4411 unsigned int i;
4412 u32 length, hlen, staterr;
4413
4414 i = rx_ring->next_to_clean;
4415 buffer_info = &rx_ring->buffer_info[i];
4416 rx_desc = E1000_RX_DESC_ADV(*rx_ring, i);
4417 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
4418
4419 while (staterr & E1000_RXD_STAT_DD) {
4420 if (*work_done >= budget)
4421 break;
4422 (*work_done)++;
4423
4424 skb = buffer_info->skb;
4425 prefetch(skb->data - NET_IP_ALIGN);
4426 buffer_info->skb = NULL;
4427
4428 i++;
4429 if (i == rx_ring->count)
4430 i = 0;
4431 next_rxd = E1000_RX_DESC_ADV(*rx_ring, i);
4432 prefetch(next_rxd);
4433 next_buffer = &rx_ring->buffer_info[i];
4434
4435 length = le16_to_cpu(rx_desc->wb.upper.length);
4436 cleaned = true;
4437 cleaned_count++;
4438
4439 if (!adapter->rx_ps_hdr_size) {
4440 pci_unmap_single(pdev, buffer_info->dma,
4441 adapter->rx_buffer_len +
4442 NET_IP_ALIGN,
4443 PCI_DMA_FROMDEVICE);
4444 skb_put(skb, length);
4445 goto send_up;
4446 }
4447
4448 /* HW will not DMA in data larger than the given buffer, even
4449 * if it parses the (NFS, of course) header to be larger. In
4450 * that case, it fills the header buffer and spills the rest
4451 * into the page.
4452 */
4453 hlen = (le16_to_cpu(rx_desc->wb.lower.lo_dword.hdr_info) &
4454 E1000_RXDADV_HDRBUFLEN_MASK) >> E1000_RXDADV_HDRBUFLEN_SHIFT;
4455 if (hlen > adapter->rx_ps_hdr_size)
4456 hlen = adapter->rx_ps_hdr_size;
4457
4458 if (!skb_shinfo(skb)->nr_frags) {
4459 pci_unmap_single(pdev, buffer_info->dma,
4460 adapter->rx_ps_hdr_size + NET_IP_ALIGN,
4461 PCI_DMA_FROMDEVICE);
4462 skb_put(skb, hlen);
4463 }
4464
4465 if (length) {
4466 pci_unmap_page(pdev, buffer_info->page_dma,
4467 PAGE_SIZE / 2, PCI_DMA_FROMDEVICE);
4468 buffer_info->page_dma = 0;
4469
4470 skb_fill_page_desc(skb, skb_shinfo(skb)->nr_frags++,
4471 buffer_info->page,
4472 buffer_info->page_offset,
4473 length);
4474
4475 if ((adapter->rx_buffer_len > (PAGE_SIZE / 2)) ||
4476 (page_count(buffer_info->page) != 1))
4477 buffer_info->page = NULL;
4478 else
4479 get_page(buffer_info->page);
4480
4481 skb->len += length;
4482 skb->data_len += length;
4483
4484 skb->truesize += length;
4485 }
4486
4487 if (!(staterr & E1000_RXD_STAT_EOP)) {
4488 buffer_info->skb = next_buffer->skb;
4489 buffer_info->dma = next_buffer->dma;
4490 next_buffer->skb = skb;
4491 next_buffer->dma = 0;
4492 goto next_desc;
4493 }
4494 send_up:
4495 /*
4496 * If this bit is set, then the RX registers contain
4497 * the time stamp. No other packet will be time
4498 * stamped until we read these registers, so read the
4499 * registers to make them available again. Because
4500 * only one packet can be time stamped at a time, we
4501 * know that the register values must belong to this
4502 * one here and therefore we don't need to compare
4503 * any of the additional attributes stored for it.
4504 *
4505 * If nothing went wrong, then it should have a
4506 * skb_shared_tx that we can turn into a
4507 * skb_shared_hwtstamps.
4508 *
4509 * TODO: can time stamping be triggered (thus locking
4510 * the registers) without the packet reaching this point
4511 * here? In that case RX time stamping would get stuck.
4512 *
4513 * TODO: in "time stamp all packets" mode this bit is
4514 * not set. Need a global flag for this mode and then
4515 * always read the registers. Cannot be done without
4516 * a race condition.
4517 */
4518 if (unlikely(staterr & E1000_RXD_STAT_TS)) {
4519 u64 regval;
4520 u64 ns;
4521 struct skb_shared_hwtstamps *shhwtstamps =
4522 skb_hwtstamps(skb);
4523
4524 WARN(!(rd32(E1000_TSYNCRXCTL) & E1000_TSYNCRXCTL_VALID),
4525 "igb: no RX time stamp available for time stamped packet");
4526 regval = rd32(E1000_RXSTMPL);
4527 regval |= (u64)rd32(E1000_RXSTMPH) << 32;
4528 ns = timecounter_cyc2time(&adapter->clock, regval);
4529 timecompare_update(&adapter->compare, ns);
4530 memset(shhwtstamps, 0, sizeof(*shhwtstamps));
4531 shhwtstamps->hwtstamp = ns_to_ktime(ns);
4532 shhwtstamps->syststamp =
4533 timecompare_transform(&adapter->compare, ns);
4534 }
4535
4536 if (staterr & E1000_RXDEXT_ERR_FRAME_ERR_MASK) {
4537 dev_kfree_skb_irq(skb);
4538 goto next_desc;
4539 }
4540
4541 total_bytes += skb->len;
4542 total_packets++;
4543
4544 igb_rx_checksum_adv(adapter, staterr, skb);
4545
4546 skb->protocol = eth_type_trans(skb, netdev);
4547
4548 igb_receive_skb(rx_ring, staterr, rx_desc, skb);
4549
4550 next_desc:
4551 rx_desc->wb.upper.status_error = 0;
4552
4553 /* return some buffers to hardware, one at a time is too slow */
4554 if (cleaned_count >= IGB_RX_BUFFER_WRITE) {
4555 igb_alloc_rx_buffers_adv(rx_ring, cleaned_count);
4556 cleaned_count = 0;
4557 }
4558
4559 /* use prefetched values */
4560 rx_desc = next_rxd;
4561 buffer_info = next_buffer;
4562 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
4563 }
4564
4565 rx_ring->next_to_clean = i;
4566 cleaned_count = IGB_DESC_UNUSED(rx_ring);
4567
4568 if (cleaned_count)
4569 igb_alloc_rx_buffers_adv(rx_ring, cleaned_count);
4570
4571 rx_ring->total_packets += total_packets;
4572 rx_ring->total_bytes += total_bytes;
4573 rx_ring->rx_stats.packets += total_packets;
4574 rx_ring->rx_stats.bytes += total_bytes;
4575 adapter->net_stats.rx_bytes += total_bytes;
4576 adapter->net_stats.rx_packets += total_packets;
4577 return cleaned;
4578 }
4579
4580 /**
4581 * igb_alloc_rx_buffers_adv - Replace used receive buffers; packet split
4582 * @adapter: address of board private structure
4583 **/
4584 static void igb_alloc_rx_buffers_adv(struct igb_ring *rx_ring,
4585 int cleaned_count)
4586 {
4587 struct igb_adapter *adapter = rx_ring->adapter;
4588 struct net_device *netdev = adapter->netdev;
4589 struct pci_dev *pdev = adapter->pdev;
4590 union e1000_adv_rx_desc *rx_desc;
4591 struct igb_buffer *buffer_info;
4592 struct sk_buff *skb;
4593 unsigned int i;
4594 int bufsz;
4595
4596 i = rx_ring->next_to_use;
4597 buffer_info = &rx_ring->buffer_info[i];
4598
4599 if (adapter->rx_ps_hdr_size)
4600 bufsz = adapter->rx_ps_hdr_size;
4601 else
4602 bufsz = adapter->rx_buffer_len;
4603 bufsz += NET_IP_ALIGN;
4604
4605 while (cleaned_count--) {
4606 rx_desc = E1000_RX_DESC_ADV(*rx_ring, i);
4607
4608 if (adapter->rx_ps_hdr_size && !buffer_info->page_dma) {
4609 if (!buffer_info->page) {
4610 buffer_info->page = alloc_page(GFP_ATOMIC);
4611 if (!buffer_info->page) {
4612 adapter->alloc_rx_buff_failed++;
4613 goto no_buffers;
4614 }
4615 buffer_info->page_offset = 0;
4616 } else {
4617 buffer_info->page_offset ^= PAGE_SIZE / 2;
4618 }
4619 buffer_info->page_dma =
4620 pci_map_page(pdev, buffer_info->page,
4621 buffer_info->page_offset,
4622 PAGE_SIZE / 2,
4623 PCI_DMA_FROMDEVICE);
4624 }
4625
4626 if (!buffer_info->skb) {
4627 skb = netdev_alloc_skb(netdev, bufsz);
4628 if (!skb) {
4629 adapter->alloc_rx_buff_failed++;
4630 goto no_buffers;
4631 }
4632
4633 /* Make buffer alignment 2 beyond a 16 byte boundary
4634 * this will result in a 16 byte aligned IP header after
4635 * the 14 byte MAC header is removed
4636 */
4637 skb_reserve(skb, NET_IP_ALIGN);
4638
4639 buffer_info->skb = skb;
4640 buffer_info->dma = pci_map_single(pdev, skb->data,
4641 bufsz,
4642 PCI_DMA_FROMDEVICE);
4643 }
4644 /* Refresh the desc even if buffer_addrs didn't change because
4645 * each write-back erases this info. */
4646 if (adapter->rx_ps_hdr_size) {
4647 rx_desc->read.pkt_addr =
4648 cpu_to_le64(buffer_info->page_dma);
4649 rx_desc->read.hdr_addr = cpu_to_le64(buffer_info->dma);
4650 } else {
4651 rx_desc->read.pkt_addr =
4652 cpu_to_le64(buffer_info->dma);
4653 rx_desc->read.hdr_addr = 0;
4654 }
4655
4656 i++;
4657 if (i == rx_ring->count)
4658 i = 0;
4659 buffer_info = &rx_ring->buffer_info[i];
4660 }
4661
4662 no_buffers:
4663 if (rx_ring->next_to_use != i) {
4664 rx_ring->next_to_use = i;
4665 if (i == 0)
4666 i = (rx_ring->count - 1);
4667 else
4668 i--;
4669
4670 /* Force memory writes to complete before letting h/w
4671 * know there are new descriptors to fetch. (Only
4672 * applicable for weak-ordered memory model archs,
4673 * such as IA-64). */
4674 wmb();
4675 writel(i, adapter->hw.hw_addr + rx_ring->tail);
4676 }
4677 }
4678
4679 /**
4680 * igb_mii_ioctl -
4681 * @netdev:
4682 * @ifreq:
4683 * @cmd:
4684 **/
4685 static int igb_mii_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
4686 {
4687 struct igb_adapter *adapter = netdev_priv(netdev);
4688 struct mii_ioctl_data *data = if_mii(ifr);
4689
4690 if (adapter->hw.phy.media_type != e1000_media_type_copper)
4691 return -EOPNOTSUPP;
4692
4693 switch (cmd) {
4694 case SIOCGMIIPHY:
4695 data->phy_id = adapter->hw.phy.addr;
4696 break;
4697 case SIOCGMIIREG:
4698 if (!capable(CAP_NET_ADMIN))
4699 return -EPERM;
4700 if (igb_read_phy_reg(&adapter->hw, data->reg_num & 0x1F,
4701 &data->val_out))
4702 return -EIO;
4703 break;
4704 case SIOCSMIIREG:
4705 default:
4706 return -EOPNOTSUPP;
4707 }
4708 return 0;
4709 }
4710
4711 /**
4712 * igb_hwtstamp_ioctl - control hardware time stamping
4713 * @netdev:
4714 * @ifreq:
4715 * @cmd:
4716 *
4717 * Outgoing time stamping can be enabled and disabled. Play nice and
4718 * disable it when requested, although it shouldn't case any overhead
4719 * when no packet needs it. At most one packet in the queue may be
4720 * marked for time stamping, otherwise it would be impossible to tell
4721 * for sure to which packet the hardware time stamp belongs.
4722 *
4723 * Incoming time stamping has to be configured via the hardware
4724 * filters. Not all combinations are supported, in particular event
4725 * type has to be specified. Matching the kind of event packet is
4726 * not supported, with the exception of "all V2 events regardless of
4727 * level 2 or 4".
4728 *
4729 **/
4730 static int igb_hwtstamp_ioctl(struct net_device *netdev,
4731 struct ifreq *ifr, int cmd)
4732 {
4733 struct igb_adapter *adapter = netdev_priv(netdev);
4734 struct e1000_hw *hw = &adapter->hw;
4735 struct hwtstamp_config config;
4736 u32 tsync_tx_ctl_bit = E1000_TSYNCTXCTL_ENABLED;
4737 u32 tsync_rx_ctl_bit = E1000_TSYNCRXCTL_ENABLED;
4738 u32 tsync_rx_ctl_type = 0;
4739 u32 tsync_rx_cfg = 0;
4740 int is_l4 = 0;
4741 int is_l2 = 0;
4742 short port = 319; /* PTP */
4743 u32 regval;
4744
4745 if (copy_from_user(&config, ifr->ifr_data, sizeof(config)))
4746 return -EFAULT;
4747
4748 /* reserved for future extensions */
4749 if (config.flags)
4750 return -EINVAL;
4751
4752 switch (config.tx_type) {
4753 case HWTSTAMP_TX_OFF:
4754 tsync_tx_ctl_bit = 0;
4755 break;
4756 case HWTSTAMP_TX_ON:
4757 tsync_tx_ctl_bit = E1000_TSYNCTXCTL_ENABLED;
4758 break;
4759 default:
4760 return -ERANGE;
4761 }
4762
4763 switch (config.rx_filter) {
4764 case HWTSTAMP_FILTER_NONE:
4765 tsync_rx_ctl_bit = 0;
4766 break;
4767 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
4768 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
4769 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
4770 case HWTSTAMP_FILTER_ALL:
4771 /*
4772 * register TSYNCRXCFG must be set, therefore it is not
4773 * possible to time stamp both Sync and Delay_Req messages
4774 * => fall back to time stamping all packets
4775 */
4776 tsync_rx_ctl_type = E1000_TSYNCRXCTL_TYPE_ALL;
4777 config.rx_filter = HWTSTAMP_FILTER_ALL;
4778 break;
4779 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
4780 tsync_rx_ctl_type = E1000_TSYNCRXCTL_TYPE_L4_V1;
4781 tsync_rx_cfg = E1000_TSYNCRXCFG_PTP_V1_SYNC_MESSAGE;
4782 is_l4 = 1;
4783 break;
4784 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
4785 tsync_rx_ctl_type = E1000_TSYNCRXCTL_TYPE_L4_V1;
4786 tsync_rx_cfg = E1000_TSYNCRXCFG_PTP_V1_DELAY_REQ_MESSAGE;
4787 is_l4 = 1;
4788 break;
4789 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
4790 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
4791 tsync_rx_ctl_type = E1000_TSYNCRXCTL_TYPE_L2_L4_V2;
4792 tsync_rx_cfg = E1000_TSYNCRXCFG_PTP_V2_SYNC_MESSAGE;
4793 is_l2 = 1;
4794 is_l4 = 1;
4795 config.rx_filter = HWTSTAMP_FILTER_SOME;
4796 break;
4797 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
4798 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
4799 tsync_rx_ctl_type = E1000_TSYNCRXCTL_TYPE_L2_L4_V2;
4800 tsync_rx_cfg = E1000_TSYNCRXCFG_PTP_V2_DELAY_REQ_MESSAGE;
4801 is_l2 = 1;
4802 is_l4 = 1;
4803 config.rx_filter = HWTSTAMP_FILTER_SOME;
4804 break;
4805 case HWTSTAMP_FILTER_PTP_V2_EVENT:
4806 case HWTSTAMP_FILTER_PTP_V2_SYNC:
4807 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
4808 tsync_rx_ctl_type = E1000_TSYNCRXCTL_TYPE_EVENT_V2;
4809 config.rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT;
4810 is_l2 = 1;
4811 break;
4812 default:
4813 return -ERANGE;
4814 }
4815
4816 /* enable/disable TX */
4817 regval = rd32(E1000_TSYNCTXCTL);
4818 regval = (regval & ~E1000_TSYNCTXCTL_ENABLED) | tsync_tx_ctl_bit;
4819 wr32(E1000_TSYNCTXCTL, regval);
4820
4821 /* enable/disable RX, define which PTP packets are time stamped */
4822 regval = rd32(E1000_TSYNCRXCTL);
4823 regval = (regval & ~E1000_TSYNCRXCTL_ENABLED) | tsync_rx_ctl_bit;
4824 regval = (regval & ~0xE) | tsync_rx_ctl_type;
4825 wr32(E1000_TSYNCRXCTL, regval);
4826 wr32(E1000_TSYNCRXCFG, tsync_rx_cfg);
4827
4828 /*
4829 * Ethertype Filter Queue Filter[0][15:0] = 0x88F7
4830 * (Ethertype to filter on)
4831 * Ethertype Filter Queue Filter[0][26] = 0x1 (Enable filter)
4832 * Ethertype Filter Queue Filter[0][30] = 0x1 (Enable Timestamping)
4833 */
4834 wr32(E1000_ETQF0, is_l2 ? 0x440088f7 : 0);
4835
4836 /* L4 Queue Filter[0]: only filter by source and destination port */
4837 wr32(E1000_SPQF0, htons(port));
4838 wr32(E1000_IMIREXT(0), is_l4 ?
4839 ((1<<12) | (1<<19) /* bypass size and control flags */) : 0);
4840 wr32(E1000_IMIR(0), is_l4 ?
4841 (htons(port)
4842 | (0<<16) /* immediate interrupt disabled */
4843 | 0 /* (1<<17) bit cleared: do not bypass
4844 destination port check */)
4845 : 0);
4846 wr32(E1000_FTQF0, is_l4 ?
4847 (0x11 /* UDP */
4848 | (1<<15) /* VF not compared */
4849 | (1<<27) /* Enable Timestamping */
4850 | (7<<28) /* only source port filter enabled,
4851 source/target address and protocol
4852 masked */)
4853 : ((1<<15) | (15<<28) /* all mask bits set = filter not
4854 enabled */));
4855
4856 wrfl();
4857
4858 adapter->hwtstamp_config = config;
4859
4860 /* clear TX/RX time stamp registers, just to be sure */
4861 regval = rd32(E1000_TXSTMPH);
4862 regval = rd32(E1000_RXSTMPH);
4863
4864 return copy_to_user(ifr->ifr_data, &config, sizeof(config)) ?
4865 -EFAULT : 0;
4866 }
4867
4868 /**
4869 * igb_ioctl -
4870 * @netdev:
4871 * @ifreq:
4872 * @cmd:
4873 **/
4874 static int igb_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
4875 {
4876 switch (cmd) {
4877 case SIOCGMIIPHY:
4878 case SIOCGMIIREG:
4879 case SIOCSMIIREG:
4880 return igb_mii_ioctl(netdev, ifr, cmd);
4881 case SIOCSHWTSTAMP:
4882 return igb_hwtstamp_ioctl(netdev, ifr, cmd);
4883 default:
4884 return -EOPNOTSUPP;
4885 }
4886 }
4887
4888 static void igb_vlan_rx_register(struct net_device *netdev,
4889 struct vlan_group *grp)
4890 {
4891 struct igb_adapter *adapter = netdev_priv(netdev);
4892 struct e1000_hw *hw = &adapter->hw;
4893 u32 ctrl, rctl;
4894
4895 igb_irq_disable(adapter);
4896 adapter->vlgrp = grp;
4897
4898 if (grp) {
4899 /* enable VLAN tag insert/strip */
4900 ctrl = rd32(E1000_CTRL);
4901 ctrl |= E1000_CTRL_VME;
4902 wr32(E1000_CTRL, ctrl);
4903
4904 /* enable VLAN receive filtering */
4905 rctl = rd32(E1000_RCTL);
4906 rctl &= ~E1000_RCTL_CFIEN;
4907 wr32(E1000_RCTL, rctl);
4908 igb_update_mng_vlan(adapter);
4909 } else {
4910 /* disable VLAN tag insert/strip */
4911 ctrl = rd32(E1000_CTRL);
4912 ctrl &= ~E1000_CTRL_VME;
4913 wr32(E1000_CTRL, ctrl);
4914
4915 if (adapter->mng_vlan_id != (u16)IGB_MNG_VLAN_NONE) {
4916 igb_vlan_rx_kill_vid(netdev, adapter->mng_vlan_id);
4917 adapter->mng_vlan_id = IGB_MNG_VLAN_NONE;
4918 }
4919 }
4920
4921 igb_rlpml_set(adapter);
4922
4923 if (!test_bit(__IGB_DOWN, &adapter->state))
4924 igb_irq_enable(adapter);
4925 }
4926
4927 static void igb_vlan_rx_add_vid(struct net_device *netdev, u16 vid)
4928 {
4929 struct igb_adapter *adapter = netdev_priv(netdev);
4930 struct e1000_hw *hw = &adapter->hw;
4931 int pf_id = adapter->vfs_allocated_count;
4932
4933 if ((hw->mng_cookie.status &
4934 E1000_MNG_DHCP_COOKIE_STATUS_VLAN) &&
4935 (vid == adapter->mng_vlan_id))
4936 return;
4937
4938 /* add vid to vlvf if sr-iov is enabled,
4939 * if that fails add directly to filter table */
4940 if (igb_vlvf_set(adapter, vid, true, pf_id))
4941 igb_vfta_set(hw, vid, true);
4942
4943 }
4944
4945 static void igb_vlan_rx_kill_vid(struct net_device *netdev, u16 vid)
4946 {
4947 struct igb_adapter *adapter = netdev_priv(netdev);
4948 struct e1000_hw *hw = &adapter->hw;
4949 int pf_id = adapter->vfs_allocated_count;
4950
4951 igb_irq_disable(adapter);
4952 vlan_group_set_device(adapter->vlgrp, vid, NULL);
4953
4954 if (!test_bit(__IGB_DOWN, &adapter->state))
4955 igb_irq_enable(adapter);
4956
4957 if ((adapter->hw.mng_cookie.status &
4958 E1000_MNG_DHCP_COOKIE_STATUS_VLAN) &&
4959 (vid == adapter->mng_vlan_id)) {
4960 /* release control to f/w */
4961 igb_release_hw_control(adapter);
4962 return;
4963 }
4964
4965 /* remove vid from vlvf if sr-iov is enabled,
4966 * if not in vlvf remove from vfta */
4967 if (igb_vlvf_set(adapter, vid, false, pf_id))
4968 igb_vfta_set(hw, vid, false);
4969 }
4970
4971 static void igb_restore_vlan(struct igb_adapter *adapter)
4972 {
4973 igb_vlan_rx_register(adapter->netdev, adapter->vlgrp);
4974
4975 if (adapter->vlgrp) {
4976 u16 vid;
4977 for (vid = 0; vid < VLAN_GROUP_ARRAY_LEN; vid++) {
4978 if (!vlan_group_get_device(adapter->vlgrp, vid))
4979 continue;
4980 igb_vlan_rx_add_vid(adapter->netdev, vid);
4981 }
4982 }
4983 }
4984
4985 int igb_set_spd_dplx(struct igb_adapter *adapter, u16 spddplx)
4986 {
4987 struct e1000_mac_info *mac = &adapter->hw.mac;
4988
4989 mac->autoneg = 0;
4990
4991 /* Fiber NICs only allow 1000 gbps Full duplex */
4992 if ((adapter->hw.phy.media_type == e1000_media_type_fiber) &&
4993 spddplx != (SPEED_1000 + DUPLEX_FULL)) {
4994 dev_err(&adapter->pdev->dev,
4995 "Unsupported Speed/Duplex configuration\n");
4996 return -EINVAL;
4997 }
4998
4999 switch (spddplx) {
5000 case SPEED_10 + DUPLEX_HALF:
5001 mac->forced_speed_duplex = ADVERTISE_10_HALF;
5002 break;
5003 case SPEED_10 + DUPLEX_FULL:
5004 mac->forced_speed_duplex = ADVERTISE_10_FULL;
5005 break;
5006 case SPEED_100 + DUPLEX_HALF:
5007 mac->forced_speed_duplex = ADVERTISE_100_HALF;
5008 break;
5009 case SPEED_100 + DUPLEX_FULL:
5010 mac->forced_speed_duplex = ADVERTISE_100_FULL;
5011 break;
5012 case SPEED_1000 + DUPLEX_FULL:
5013 mac->autoneg = 1;
5014 adapter->hw.phy.autoneg_advertised = ADVERTISE_1000_FULL;
5015 break;
5016 case SPEED_1000 + DUPLEX_HALF: /* not supported */
5017 default:
5018 dev_err(&adapter->pdev->dev,
5019 "Unsupported Speed/Duplex configuration\n");
5020 return -EINVAL;
5021 }
5022 return 0;
5023 }
5024
5025 static int igb_suspend(struct pci_dev *pdev, pm_message_t state)
5026 {
5027 struct net_device *netdev = pci_get_drvdata(pdev);
5028 struct igb_adapter *adapter = netdev_priv(netdev);
5029 struct e1000_hw *hw = &adapter->hw;
5030 u32 ctrl, rctl, status;
5031 u32 wufc = adapter->wol;
5032 #ifdef CONFIG_PM
5033 int retval = 0;
5034 #endif
5035
5036 netif_device_detach(netdev);
5037
5038 if (netif_running(netdev))
5039 igb_close(netdev);
5040
5041 igb_reset_interrupt_capability(adapter);
5042
5043 igb_free_queues(adapter);
5044
5045 #ifdef CONFIG_PM
5046 retval = pci_save_state(pdev);
5047 if (retval)
5048 return retval;
5049 #endif
5050
5051 status = rd32(E1000_STATUS);
5052 if (status & E1000_STATUS_LU)
5053 wufc &= ~E1000_WUFC_LNKC;
5054
5055 if (wufc) {
5056 igb_setup_rctl(adapter);
5057 igb_set_multi(netdev);
5058
5059 /* turn on all-multi mode if wake on multicast is enabled */
5060 if (wufc & E1000_WUFC_MC) {
5061 rctl = rd32(E1000_RCTL);
5062 rctl |= E1000_RCTL_MPE;
5063 wr32(E1000_RCTL, rctl);
5064 }
5065
5066 ctrl = rd32(E1000_CTRL);
5067 /* advertise wake from D3Cold */
5068 #define E1000_CTRL_ADVD3WUC 0x00100000
5069 /* phy power management enable */
5070 #define E1000_CTRL_EN_PHY_PWR_MGMT 0x00200000
5071 ctrl |= E1000_CTRL_ADVD3WUC;
5072 wr32(E1000_CTRL, ctrl);
5073
5074 /* Allow time for pending master requests to run */
5075 igb_disable_pcie_master(&adapter->hw);
5076
5077 wr32(E1000_WUC, E1000_WUC_PME_EN);
5078 wr32(E1000_WUFC, wufc);
5079 } else {
5080 wr32(E1000_WUC, 0);
5081 wr32(E1000_WUFC, 0);
5082 }
5083
5084 /* make sure adapter isn't asleep if manageability/wol is enabled */
5085 if (wufc || adapter->en_mng_pt) {
5086 pci_enable_wake(pdev, PCI_D3hot, 1);
5087 pci_enable_wake(pdev, PCI_D3cold, 1);
5088 } else {
5089 igb_shutdown_fiber_serdes_link_82575(hw);
5090 pci_enable_wake(pdev, PCI_D3hot, 0);
5091 pci_enable_wake(pdev, PCI_D3cold, 0);
5092 }
5093
5094 /* Release control of h/w to f/w. If f/w is AMT enabled, this
5095 * would have already happened in close and is redundant. */
5096 igb_release_hw_control(adapter);
5097
5098 pci_disable_device(pdev);
5099
5100 pci_set_power_state(pdev, pci_choose_state(pdev, state));
5101
5102 return 0;
5103 }
5104
5105 #ifdef CONFIG_PM
5106 static int igb_resume(struct pci_dev *pdev)
5107 {
5108 struct net_device *netdev = pci_get_drvdata(pdev);
5109 struct igb_adapter *adapter = netdev_priv(netdev);
5110 struct e1000_hw *hw = &adapter->hw;
5111 u32 err;
5112
5113 pci_set_power_state(pdev, PCI_D0);
5114 pci_restore_state(pdev);
5115
5116 err = pci_enable_device_mem(pdev);
5117 if (err) {
5118 dev_err(&pdev->dev,
5119 "igb: Cannot enable PCI device from suspend\n");
5120 return err;
5121 }
5122 pci_set_master(pdev);
5123
5124 pci_enable_wake(pdev, PCI_D3hot, 0);
5125 pci_enable_wake(pdev, PCI_D3cold, 0);
5126
5127 igb_set_interrupt_capability(adapter);
5128
5129 if (igb_alloc_queues(adapter)) {
5130 dev_err(&pdev->dev, "Unable to allocate memory for queues\n");
5131 return -ENOMEM;
5132 }
5133
5134 /* e1000_power_up_phy(adapter); */
5135
5136 igb_reset(adapter);
5137
5138 /* let the f/w know that the h/w is now under the control of the
5139 * driver. */
5140 igb_get_hw_control(adapter);
5141
5142 wr32(E1000_WUS, ~0);
5143
5144 if (netif_running(netdev)) {
5145 err = igb_open(netdev);
5146 if (err)
5147 return err;
5148 }
5149
5150 netif_device_attach(netdev);
5151
5152 return 0;
5153 }
5154 #endif
5155
5156 static void igb_shutdown(struct pci_dev *pdev)
5157 {
5158 igb_suspend(pdev, PMSG_SUSPEND);
5159 }
5160
5161 #ifdef CONFIG_NET_POLL_CONTROLLER
5162 /*
5163 * Polling 'interrupt' - used by things like netconsole to send skbs
5164 * without having to re-enable interrupts. It's not called while
5165 * the interrupt routine is executing.
5166 */
5167 static void igb_netpoll(struct net_device *netdev)
5168 {
5169 struct igb_adapter *adapter = netdev_priv(netdev);
5170 struct e1000_hw *hw = &adapter->hw;
5171 int i;
5172
5173 if (!adapter->msix_entries) {
5174 igb_irq_disable(adapter);
5175 napi_schedule(&adapter->rx_ring[0].napi);
5176 return;
5177 }
5178
5179 for (i = 0; i < adapter->num_tx_queues; i++) {
5180 struct igb_ring *tx_ring = &adapter->tx_ring[i];
5181 wr32(E1000_EIMC, tx_ring->eims_value);
5182 igb_clean_tx_irq(tx_ring);
5183 wr32(E1000_EIMS, tx_ring->eims_value);
5184 }
5185
5186 for (i = 0; i < adapter->num_rx_queues; i++) {
5187 struct igb_ring *rx_ring = &adapter->rx_ring[i];
5188 wr32(E1000_EIMC, rx_ring->eims_value);
5189 napi_schedule(&rx_ring->napi);
5190 }
5191 }
5192 #endif /* CONFIG_NET_POLL_CONTROLLER */
5193
5194 /**
5195 * igb_io_error_detected - called when PCI error is detected
5196 * @pdev: Pointer to PCI device
5197 * @state: The current pci connection state
5198 *
5199 * This function is called after a PCI bus error affecting
5200 * this device has been detected.
5201 */
5202 static pci_ers_result_t igb_io_error_detected(struct pci_dev *pdev,
5203 pci_channel_state_t state)
5204 {
5205 struct net_device *netdev = pci_get_drvdata(pdev);
5206 struct igb_adapter *adapter = netdev_priv(netdev);
5207
5208 netif_device_detach(netdev);
5209
5210 if (netif_running(netdev))
5211 igb_down(adapter);
5212 pci_disable_device(pdev);
5213
5214 /* Request a slot slot reset. */
5215 return PCI_ERS_RESULT_NEED_RESET;
5216 }
5217
5218 /**
5219 * igb_io_slot_reset - called after the pci bus has been reset.
5220 * @pdev: Pointer to PCI device
5221 *
5222 * Restart the card from scratch, as if from a cold-boot. Implementation
5223 * resembles the first-half of the igb_resume routine.
5224 */
5225 static pci_ers_result_t igb_io_slot_reset(struct pci_dev *pdev)
5226 {
5227 struct net_device *netdev = pci_get_drvdata(pdev);
5228 struct igb_adapter *adapter = netdev_priv(netdev);
5229 struct e1000_hw *hw = &adapter->hw;
5230 pci_ers_result_t result;
5231 int err;
5232
5233 if (pci_enable_device_mem(pdev)) {
5234 dev_err(&pdev->dev,
5235 "Cannot re-enable PCI device after reset.\n");
5236 result = PCI_ERS_RESULT_DISCONNECT;
5237 } else {
5238 pci_set_master(pdev);
5239 pci_restore_state(pdev);
5240
5241 pci_enable_wake(pdev, PCI_D3hot, 0);
5242 pci_enable_wake(pdev, PCI_D3cold, 0);
5243
5244 igb_reset(adapter);
5245 wr32(E1000_WUS, ~0);
5246 result = PCI_ERS_RESULT_RECOVERED;
5247 }
5248
5249 err = pci_cleanup_aer_uncorrect_error_status(pdev);
5250 if (err) {
5251 dev_err(&pdev->dev, "pci_cleanup_aer_uncorrect_error_status "
5252 "failed 0x%0x\n", err);
5253 /* non-fatal, continue */
5254 }
5255
5256 return result;
5257 }
5258
5259 /**
5260 * igb_io_resume - called when traffic can start flowing again.
5261 * @pdev: Pointer to PCI device
5262 *
5263 * This callback is called when the error recovery driver tells us that
5264 * its OK to resume normal operation. Implementation resembles the
5265 * second-half of the igb_resume routine.
5266 */
5267 static void igb_io_resume(struct pci_dev *pdev)
5268 {
5269 struct net_device *netdev = pci_get_drvdata(pdev);
5270 struct igb_adapter *adapter = netdev_priv(netdev);
5271
5272 if (netif_running(netdev)) {
5273 if (igb_up(adapter)) {
5274 dev_err(&pdev->dev, "igb_up failed after reset\n");
5275 return;
5276 }
5277 }
5278
5279 netif_device_attach(netdev);
5280
5281 /* let the f/w know that the h/w is now under the control of the
5282 * driver. */
5283 igb_get_hw_control(adapter);
5284 }
5285
5286 static inline void igb_set_vmolr(struct e1000_hw *hw, int vfn)
5287 {
5288 u32 reg_data;
5289
5290 reg_data = rd32(E1000_VMOLR(vfn));
5291 reg_data |= E1000_VMOLR_BAM | /* Accept broadcast */
5292 E1000_VMOLR_ROPE | /* Accept packets matched in UTA */
5293 E1000_VMOLR_ROMPE | /* Accept packets matched in MTA */
5294 E1000_VMOLR_AUPE | /* Accept untagged packets */
5295 E1000_VMOLR_STRVLAN; /* Strip vlan tags */
5296 wr32(E1000_VMOLR(vfn), reg_data);
5297 }
5298
5299 static inline int igb_set_vf_rlpml(struct igb_adapter *adapter, int size,
5300 int vfn)
5301 {
5302 struct e1000_hw *hw = &adapter->hw;
5303 u32 vmolr;
5304
5305 vmolr = rd32(E1000_VMOLR(vfn));
5306 vmolr &= ~E1000_VMOLR_RLPML_MASK;
5307 vmolr |= size | E1000_VMOLR_LPE;
5308 wr32(E1000_VMOLR(vfn), vmolr);
5309
5310 return 0;
5311 }
5312
5313 static inline void igb_set_rah_pool(struct e1000_hw *hw, int pool, int entry)
5314 {
5315 u32 reg_data;
5316
5317 reg_data = rd32(E1000_RAH(entry));
5318 reg_data &= ~E1000_RAH_POOL_MASK;
5319 reg_data |= E1000_RAH_POOL_1 << pool;;
5320 wr32(E1000_RAH(entry), reg_data);
5321 }
5322
5323 static void igb_set_mc_list_pools(struct igb_adapter *adapter,
5324 int entry_count, u16 total_rar_filters)
5325 {
5326 struct e1000_hw *hw = &adapter->hw;
5327 int i = adapter->vfs_allocated_count + 1;
5328
5329 if ((i + entry_count) < total_rar_filters)
5330 total_rar_filters = i + entry_count;
5331
5332 for (; i < total_rar_filters; i++)
5333 igb_set_rah_pool(hw, adapter->vfs_allocated_count, i);
5334 }
5335
5336 static int igb_set_vf_mac(struct igb_adapter *adapter,
5337 int vf, unsigned char *mac_addr)
5338 {
5339 struct e1000_hw *hw = &adapter->hw;
5340 int rar_entry = vf + 1; /* VF MAC addresses start at entry 1 */
5341
5342 igb_rar_set(hw, mac_addr, rar_entry);
5343
5344 memcpy(adapter->vf_data[vf].vf_mac_addresses, mac_addr, 6);
5345
5346 igb_set_rah_pool(hw, vf, rar_entry);
5347
5348 return 0;
5349 }
5350
5351 static void igb_vmm_control(struct igb_adapter *adapter)
5352 {
5353 struct e1000_hw *hw = &adapter->hw;
5354 u32 reg_data;
5355
5356 if (!adapter->vfs_allocated_count)
5357 return;
5358
5359 /* VF's need PF reset indication before they
5360 * can send/receive mail */
5361 reg_data = rd32(E1000_CTRL_EXT);
5362 reg_data |= E1000_CTRL_EXT_PFRSTD;
5363 wr32(E1000_CTRL_EXT, reg_data);
5364
5365 igb_vmdq_set_loopback_pf(hw, true);
5366 igb_vmdq_set_replication_pf(hw, true);
5367 }
5368
5369 /* igb_main.c */
Linus' kernel tree