include/asm-mips/mips-boards/maltaint.h

   1 /*
   2  * Carsten Langgaard, carstenl@mips.com
   3  * Copyright (C) 2000 MIPS Technologies, Inc.  All rights reserved.
   4  *
   5  * ########################################################################
   6  *
   7  *  This program is free software; you can distribute it and/or modify it
   8  *  under the terms of the GNU General Public License (Version 2) as
   9  *  published by the Free Software Foundation.
  10  *
  11  *  This program is distributed in the hope it will be useful, but WITHOUT
  12  *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  13  *  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  14  *  for more details.
  15  *
  16  *  You should have received a copy of the GNU General Public License along
  17  *  with this program; if not, write to the Free Software Foundation, Inc.,
  18  *  59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
  19  *
  20  * ########################################################################
  21  *
  22  * Defines for the Malta interrupt controller.
  23  *
  24  */
  25 #ifndef _MIPS_MALTAINT_H
  26 #define _MIPS_MALTAINT_H
  27
  28 /*
  29  * Interrupts 0..15 are used for Malta ISA compatible interrupts
  30  */
  31 #define MALTA_INT_BASE          0
  32
  33 /*
  34  * Interrupts 16..23 are used for Malta CPU interrupts (nonEIC mode)
  35  */
  36 #define MIPSCPU_INT_BASE        16
  37
  38 /* CPU interrupt offsets */
  39 #define MIPSCPU_INT_SW0         0
  40 #define MIPSCPU_INT_SW1         1
  41 #define MIPSCPU_INT_MB0         2
  42 #define MIPSCPU_INT_I8259A      MIPSCPU_INT_MB0
  43 #define MIPSCPU_INT_MB1         3
  44 #define MIPSCPU_INT_SMI         MIPSCPU_INT_MB1
  45 #define MIPSCPU_INT_MB2         4
  46 #define MIPSCPU_INT_MB3         5
  47 #define MIPSCPU_INT_COREHI      MIPSCPU_INT_MB3
  48 #define MIPSCPU_INT_MB4         6
  49 #define MIPSCPU_INT_CORELO      MIPSCPU_INT_MB4
  50 #define MIPSCPU_INT_CPUCTR      7
  51
  52 /*
  53  * Interrupts 64..127 are used for Soc-it Classic interrupts
  54  */
  55 #define MSC01C_INT_BASE         64
  56
  57 /* SOC-it Classic interrupt offsets */
  58 #define MSC01C_INT_TMR          0
  59 #define MSC01C_INT_PCI          1
  60
  61 /*
  62  * Interrupts 64..127 are used for Soc-it EIC interrupts
  63  */
  64 #define MSC01E_INT_BASE         64
  65
  66 /* SOC-it EIC interrupt offsets */
  67 #define MSC01E_INT_SW0          1
  68 #define MSC01E_INT_SW1          2
  69 #define MSC01E_INT_MB0          3
  70 #define MSC01E_INT_I8259A       MSC01E_INT_MB0
  71 #define MSC01E_INT_MB1          4
  72 #define MSC01E_INT_SMI          MSC01E_INT_MB1
  73 #define MSC01E_INT_MB2          5
  74 #define MSC01E_INT_MB3          6
  75 #define MSC01E_INT_COREHI       MSC01E_INT_MB3
  76 #define MSC01E_INT_MB4          7
  77 #define MSC01E_INT_CORELO       MSC01E_INT_MB4
  78 #define MSC01E_INT_TMR          8
  79 #define MSC01E_INT_PCI          9
  80 #define MSC01E_INT_PERFCTR      10
  81 #define MSC01E_INT_CPUCTR       11
  82
  83 #ifndef __ASSEMBLY__
  84 extern void maltaint_init(void);
  85 #endif
  86
  87 #endif /* !(_MIPS_MALTAINT_H) */