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[MIPS] SNI: Fix mc146818_decode_year
[linux-2.6.git] / drivers / serial / sunzilog.c
blobda73205e54cded364297a9df504316229e7f7c6c
1 /* sunzilog.c: Zilog serial driver for Sparc systems.
2 *
3 * Driver for Zilog serial chips found on Sun workstations and
4 * servers. This driver could actually be made more generic.
5 *
6 * This is based on the old drivers/sbus/char/zs.c code. A lot
7 * of code has been simply moved over directly from there but
8 * much has been rewritten. Credits therefore go out to Eddie
9 * C. Dost, Pete Zaitcev, Ted Ts'o and Alex Buell for their
10 * work there.
11 *
12 * Copyright (C) 2002, 2006 David S. Miller (davem@davemloft.net)
13 */
14
15 #include <linux/module.h>
16 #include <linux/kernel.h>
17 #include <linux/errno.h>
18 #include <linux/delay.h>
19 #include <linux/tty.h>
20 #include <linux/tty_flip.h>
21 #include <linux/major.h>
22 #include <linux/string.h>
23 #include <linux/ptrace.h>
24 #include <linux/ioport.h>
25 #include <linux/slab.h>
26 #include <linux/circ_buf.h>
27 #include <linux/serial.h>
28 #include <linux/sysrq.h>
29 #include <linux/console.h>
30 #include <linux/spinlock.h>
31 #ifdef CONFIG_SERIO
32 #include <linux/serio.h>
33 #endif
34 #include <linux/init.h>
35
36 #include <asm/io.h>
37 #include <asm/irq.h>
38 #include <asm/prom.h>
39 #include <asm/of_device.h>
40
41 #if defined(CONFIG_SERIAL_SUNZILOG_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
42 #define SUPPORT_SYSRQ
43 #endif
44
45 #include <linux/serial_core.h>
46
47 #include "suncore.h"
48 #include "sunzilog.h"
49
50 /* On 32-bit sparcs we need to delay after register accesses
51 * to accommodate sun4 systems, but we do not need to flush writes.
52 * On 64-bit sparc we only need to flush single writes to ensure
53 * completion.
54 */
55 #ifndef CONFIG_SPARC64
56 #define ZSDELAY() udelay(5)
57 #define ZSDELAY_LONG() udelay(20)
58 #define ZS_WSYNC(channel) do { } while (0)
59 #else
60 #define ZSDELAY()
61 #define ZSDELAY_LONG()
62 #define ZS_WSYNC(__channel) \
63 readb(&((__channel)->control))
64 #endif
65
66 static int num_sunzilog;
67 #define NUM_SUNZILOG num_sunzilog
68 #define NUM_CHANNELS (NUM_SUNZILOG * 2)
69
70 #define ZS_CLOCK 4915200 /* Zilog input clock rate. */
71 #define ZS_CLOCK_DIVISOR 16 /* Divisor this driver uses. */
72
73 /*
74 * We wrap our port structure around the generic uart_port.
75 */
76 struct uart_sunzilog_port {
77 struct uart_port port;
78
79 /* IRQ servicing chain. */
80 struct uart_sunzilog_port *next;
81
82 /* Current values of Zilog write registers. */
83 unsigned char curregs[NUM_ZSREGS];
84
85 unsigned int flags;
86 #define SUNZILOG_FLAG_CONS_KEYB 0x00000001
87 #define SUNZILOG_FLAG_CONS_MOUSE 0x00000002
88 #define SUNZILOG_FLAG_IS_CONS 0x00000004
89 #define SUNZILOG_FLAG_IS_KGDB 0x00000008
90 #define SUNZILOG_FLAG_MODEM_STATUS 0x00000010
91 #define SUNZILOG_FLAG_IS_CHANNEL_A 0x00000020
92 #define SUNZILOG_FLAG_REGS_HELD 0x00000040
93 #define SUNZILOG_FLAG_TX_STOPPED 0x00000080
94 #define SUNZILOG_FLAG_TX_ACTIVE 0x00000100
95
96 unsigned int cflag;
97
98 unsigned char parity_mask;
99 unsigned char prev_status;
100
101 #ifdef CONFIG_SERIO
102 struct serio serio;
103 int serio_open;
104 #endif
105 };
106
107 #define ZILOG_CHANNEL_FROM_PORT(PORT) ((struct zilog_channel __iomem *)((PORT)->membase))
108 #define UART_ZILOG(PORT) ((struct uart_sunzilog_port *)(PORT))
109
110 #define ZS_IS_KEYB(UP) ((UP)->flags & SUNZILOG_FLAG_CONS_KEYB)
111 #define ZS_IS_MOUSE(UP) ((UP)->flags & SUNZILOG_FLAG_CONS_MOUSE)
112 #define ZS_IS_CONS(UP) ((UP)->flags & SUNZILOG_FLAG_IS_CONS)
113 #define ZS_IS_KGDB(UP) ((UP)->flags & SUNZILOG_FLAG_IS_KGDB)
114 #define ZS_WANTS_MODEM_STATUS(UP) ((UP)->flags & SUNZILOG_FLAG_MODEM_STATUS)
115 #define ZS_IS_CHANNEL_A(UP) ((UP)->flags & SUNZILOG_FLAG_IS_CHANNEL_A)
116 #define ZS_REGS_HELD(UP) ((UP)->flags & SUNZILOG_FLAG_REGS_HELD)
117 #define ZS_TX_STOPPED(UP) ((UP)->flags & SUNZILOG_FLAG_TX_STOPPED)
118 #define ZS_TX_ACTIVE(UP) ((UP)->flags & SUNZILOG_FLAG_TX_ACTIVE)
119
120 /* Reading and writing Zilog8530 registers. The delays are to make this
121 * driver work on the Sun4 which needs a settling delay after each chip
122 * register access, other machines handle this in hardware via auxiliary
123 * flip-flops which implement the settle time we do in software.
124 *
125 * The port lock must be held and local IRQs must be disabled
126 * when {read,write}_zsreg is invoked.
127 */
128 static unsigned char read_zsreg(struct zilog_channel __iomem *channel,
129 unsigned char reg)
130 {
131 unsigned char retval;
132
133 writeb(reg, &channel->control);
134 ZSDELAY();
135 retval = readb(&channel->control);
136 ZSDELAY();
137
138 return retval;
139 }
140
141 static void write_zsreg(struct zilog_channel __iomem *channel,
142 unsigned char reg, unsigned char value)
143 {
144 writeb(reg, &channel->control);
145 ZSDELAY();
146 writeb(value, &channel->control);
147 ZSDELAY();
148 }
149
150 static void sunzilog_clear_fifo(struct zilog_channel __iomem *channel)
151 {
152 int i;
153
154 for (i = 0; i < 32; i++) {
155 unsigned char regval;
156
157 regval = readb(&channel->control);
158 ZSDELAY();
159 if (regval & Rx_CH_AV)
160 break;
161
162 regval = read_zsreg(channel, R1);
163 readb(&channel->data);
164 ZSDELAY();
165
166 if (regval & (PAR_ERR | Rx_OVR | CRC_ERR)) {
167 writeb(ERR_RES, &channel->control);
168 ZSDELAY();
169 ZS_WSYNC(channel);
170 }
171 }
172 }
173
174 /* This function must only be called when the TX is not busy. The UART
175 * port lock must be held and local interrupts disabled.
176 */
177 static void __load_zsregs(struct zilog_channel __iomem *channel, unsigned char *regs)
178 {
179 int i;
180
181 /* Let pending transmits finish. */
182 for (i = 0; i < 1000; i++) {
183 unsigned char stat = read_zsreg(channel, R1);
184 if (stat & ALL_SNT)
185 break;
186 udelay(100);
187 }
188
189 writeb(ERR_RES, &channel->control);
190 ZSDELAY();
191 ZS_WSYNC(channel);
192
193 sunzilog_clear_fifo(channel);
194
195 /* Disable all interrupts. */
196 write_zsreg(channel, R1,
197 regs[R1] & ~(RxINT_MASK | TxINT_ENAB | EXT_INT_ENAB));
198
199 /* Set parity, sync config, stop bits, and clock divisor. */
200 write_zsreg(channel, R4, regs[R4]);
201
202 /* Set misc. TX/RX control bits. */
203 write_zsreg(channel, R10, regs[R10]);
204
205 /* Set TX/RX controls sans the enable bits. */
206 write_zsreg(channel, R3, regs[R3] & ~RxENAB);
207 write_zsreg(channel, R5, regs[R5] & ~TxENAB);
208
209 /* Synchronous mode config. */
210 write_zsreg(channel, R6, regs[R6]);
211 write_zsreg(channel, R7, regs[R7]);
212
213 /* Don't mess with the interrupt vector (R2, unused by us) and
214 * master interrupt control (R9). We make sure this is setup
215 * properly at probe time then never touch it again.
216 */
217
218 /* Disable baud generator. */
219 write_zsreg(channel, R14, regs[R14] & ~BRENAB);
220
221 /* Clock mode control. */
222 write_zsreg(channel, R11, regs[R11]);
223
224 /* Lower and upper byte of baud rate generator divisor. */
225 write_zsreg(channel, R12, regs[R12]);
226 write_zsreg(channel, R13, regs[R13]);
227
228 /* Now rewrite R14, with BRENAB (if set). */
229 write_zsreg(channel, R14, regs[R14]);
230
231 /* External status interrupt control. */
232 write_zsreg(channel, R15, regs[R15]);
233
234 /* Reset external status interrupts. */
235 write_zsreg(channel, R0, RES_EXT_INT);
236 write_zsreg(channel, R0, RES_EXT_INT);
237
238 /* Rewrite R3/R5, this time without enables masked. */
239 write_zsreg(channel, R3, regs[R3]);
240 write_zsreg(channel, R5, regs[R5]);
241
242 /* Rewrite R1, this time without IRQ enabled masked. */
243 write_zsreg(channel, R1, regs[R1]);
244 }
245
246 /* Reprogram the Zilog channel HW registers with the copies found in the
247 * software state struct. If the transmitter is busy, we defer this update
248 * until the next TX complete interrupt. Else, we do it right now.
249 *
250 * The UART port lock must be held and local interrupts disabled.
251 */
252 static void sunzilog_maybe_update_regs(struct uart_sunzilog_port *up,
253 struct zilog_channel __iomem *channel)
254 {
255 if (!ZS_REGS_HELD(up)) {
256 if (ZS_TX_ACTIVE(up)) {
257 up->flags |= SUNZILOG_FLAG_REGS_HELD;
258 } else {
259 __load_zsregs(channel, up->curregs);
260 }
261 }
262 }
263
264 static void sunzilog_change_mouse_baud(struct uart_sunzilog_port *up)
265 {
266 unsigned int cur_cflag = up->cflag;
267 int brg, new_baud;
268
269 up->cflag &= ~CBAUD;
270 up->cflag |= suncore_mouse_baud_cflag_next(cur_cflag, &new_baud);
271
272 brg = BPS_TO_BRG(new_baud, ZS_CLOCK / ZS_CLOCK_DIVISOR);
273 up->curregs[R12] = (brg & 0xff);
274 up->curregs[R13] = (brg >> 8) & 0xff;
275 sunzilog_maybe_update_regs(up, ZILOG_CHANNEL_FROM_PORT(&up->port));
276 }
277
278 static void sunzilog_kbdms_receive_chars(struct uart_sunzilog_port *up,
279 unsigned char ch, int is_break)
280 {
281 if (ZS_IS_KEYB(up)) {
282 /* Stop-A is handled by drivers/char/keyboard.c now. */
283 #ifdef CONFIG_SERIO
284 if (up->serio_open)
285 serio_interrupt(&up->serio, ch, 0);
286 #endif
287 } else if (ZS_IS_MOUSE(up)) {
288 int ret = suncore_mouse_baud_detection(ch, is_break);
289
290 switch (ret) {
291 case 2:
292 sunzilog_change_mouse_baud(up);
293 /* fallthru */
294 case 1:
295 break;
296
297 case 0:
298 #ifdef CONFIG_SERIO
299 if (up->serio_open)
300 serio_interrupt(&up->serio, ch, 0);
301 #endif
302 break;
303 };
304 }
305 }
306
307 static struct tty_struct *
308 sunzilog_receive_chars(struct uart_sunzilog_port *up,
309 struct zilog_channel __iomem *channel)
310 {
311 struct tty_struct *tty;
312 unsigned char ch, r1, flag;
313
314 tty = NULL;
315 if (up->port.info != NULL && /* Unopened serial console */
316 up->port.info->tty != NULL) /* Keyboard || mouse */
317 tty = up->port.info->tty;
318
319 for (;;) {
320
321 r1 = read_zsreg(channel, R1);
322 if (r1 & (PAR_ERR | Rx_OVR | CRC_ERR)) {
323 writeb(ERR_RES, &channel->control);
324 ZSDELAY();
325 ZS_WSYNC(channel);
326 }
327
328 ch = readb(&channel->control);
329 ZSDELAY();
330
331 /* This funny hack depends upon BRK_ABRT not interfering
332 * with the other bits we care about in R1.
333 */
334 if (ch & BRK_ABRT)
335 r1 |= BRK_ABRT;
336
337 if (!(ch & Rx_CH_AV))
338 break;
339
340 ch = readb(&channel->data);
341 ZSDELAY();
342
343 ch &= up->parity_mask;
344
345 if (unlikely(ZS_IS_KEYB(up)) || unlikely(ZS_IS_MOUSE(up))) {
346 sunzilog_kbdms_receive_chars(up, ch, 0);
347 continue;
348 }
349
350 if (tty == NULL) {
351 uart_handle_sysrq_char(&up->port, ch);
352 continue;
353 }
354
355 /* A real serial line, record the character and status. */
356 flag = TTY_NORMAL;
357 up->port.icount.rx++;
358 if (r1 & (BRK_ABRT | PAR_ERR | Rx_OVR | CRC_ERR)) {
359 if (r1 & BRK_ABRT) {
360 r1 &= ~(PAR_ERR | CRC_ERR);
361 up->port.icount.brk++;
362 if (uart_handle_break(&up->port))
363 continue;
364 }
365 else if (r1 & PAR_ERR)
366 up->port.icount.parity++;
367 else if (r1 & CRC_ERR)
368 up->port.icount.frame++;
369 if (r1 & Rx_OVR)
370 up->port.icount.overrun++;
371 r1 &= up->port.read_status_mask;
372 if (r1 & BRK_ABRT)
373 flag = TTY_BREAK;
374 else if (r1 & PAR_ERR)
375 flag = TTY_PARITY;
376 else if (r1 & CRC_ERR)
377 flag = TTY_FRAME;
378 }
379 if (uart_handle_sysrq_char(&up->port, ch))
380 continue;
381
382 if (up->port.ignore_status_mask == 0xff ||
383 (r1 & up->port.ignore_status_mask) == 0) {
384 tty_insert_flip_char(tty, ch, flag);
385 }
386 if (r1 & Rx_OVR)
387 tty_insert_flip_char(tty, 0, TTY_OVERRUN);
388 }
389
390 return tty;
391 }
392
393 static void sunzilog_status_handle(struct uart_sunzilog_port *up,
394 struct zilog_channel __iomem *channel)
395 {
396 unsigned char status;
397
398 status = readb(&channel->control);
399 ZSDELAY();
400
401 writeb(RES_EXT_INT, &channel->control);
402 ZSDELAY();
403 ZS_WSYNC(channel);
404
405 if (status & BRK_ABRT) {
406 if (ZS_IS_MOUSE(up))
407 sunzilog_kbdms_receive_chars(up, 0, 1);
408 if (ZS_IS_CONS(up)) {
409 /* Wait for BREAK to deassert to avoid potentially
410 * confusing the PROM.
411 */
412 while (1) {
413 status = readb(&channel->control);
414 ZSDELAY();
415 if (!(status & BRK_ABRT))
416 break;
417 }
418 sun_do_break();
419 return;
420 }
421 }
422
423 if (ZS_WANTS_MODEM_STATUS(up)) {
424 if (status & SYNC)
425 up->port.icount.dsr++;
426
427 /* The Zilog just gives us an interrupt when DCD/CTS/etc. change.
428 * But it does not tell us which bit has changed, we have to keep
429 * track of this ourselves.
430 */
431 if ((status ^ up->prev_status) ^ DCD)
432 uart_handle_dcd_change(&up->port,
433 (status & DCD));
434 if ((status ^ up->prev_status) ^ CTS)
435 uart_handle_cts_change(&up->port,
436 (status & CTS));
437
438 wake_up_interruptible(&up->port.info->delta_msr_wait);
439 }
440
441 up->prev_status = status;
442 }
443
444 static void sunzilog_transmit_chars(struct uart_sunzilog_port *up,
445 struct zilog_channel __iomem *channel)
446 {
447 struct circ_buf *xmit;
448
449 if (ZS_IS_CONS(up)) {
450 unsigned char status = readb(&channel->control);
451 ZSDELAY();
452
453 /* TX still busy? Just wait for the next TX done interrupt.
454 *
455 * It can occur because of how we do serial console writes. It would
456 * be nice to transmit console writes just like we normally would for
457 * a TTY line. (ie. buffered and TX interrupt driven). That is not
458 * easy because console writes cannot sleep. One solution might be
459 * to poll on enough port->xmit space becomming free. -DaveM
460 */
461 if (!(status & Tx_BUF_EMP))
462 return;
463 }
464
465 up->flags &= ~SUNZILOG_FLAG_TX_ACTIVE;
466
467 if (ZS_REGS_HELD(up)) {
468 __load_zsregs(channel, up->curregs);
469 up->flags &= ~SUNZILOG_FLAG_REGS_HELD;
470 }
471
472 if (ZS_TX_STOPPED(up)) {
473 up->flags &= ~SUNZILOG_FLAG_TX_STOPPED;
474 goto ack_tx_int;
475 }
476
477 if (up->port.x_char) {
478 up->flags |= SUNZILOG_FLAG_TX_ACTIVE;
479 writeb(up->port.x_char, &channel->data);
480 ZSDELAY();
481 ZS_WSYNC(channel);
482
483 up->port.icount.tx++;
484 up->port.x_char = 0;
485 return;
486 }
487
488 if (up->port.info == NULL)
489 goto ack_tx_int;
490 xmit = &up->port.info->xmit;
491 if (uart_circ_empty(xmit))
492 goto ack_tx_int;
493
494 if (uart_tx_stopped(&up->port))
495 goto ack_tx_int;
496
497 up->flags |= SUNZILOG_FLAG_TX_ACTIVE;
498 writeb(xmit->buf[xmit->tail], &channel->data);
499 ZSDELAY();
500 ZS_WSYNC(channel);
501
502 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
503 up->port.icount.tx++;
504
505 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
506 uart_write_wakeup(&up->port);
507
508 return;
509
510 ack_tx_int:
511 writeb(RES_Tx_P, &channel->control);
512 ZSDELAY();
513 ZS_WSYNC(channel);
514 }
515
516 static irqreturn_t sunzilog_interrupt(int irq, void *dev_id)
517 {
518 struct uart_sunzilog_port *up = dev_id;
519
520 while (up) {
521 struct zilog_channel __iomem *channel
522 = ZILOG_CHANNEL_FROM_PORT(&up->port);
523 struct tty_struct *tty;
524 unsigned char r3;
525
526 spin_lock(&up->port.lock);
527 r3 = read_zsreg(channel, R3);
528
529 /* Channel A */
530 tty = NULL;
531 if (r3 & (CHAEXT | CHATxIP | CHARxIP)) {
532 writeb(RES_H_IUS, &channel->control);
533 ZSDELAY();
534 ZS_WSYNC(channel);
535
536 if (r3 & CHARxIP)
537 tty = sunzilog_receive_chars(up, channel);
538 if (r3 & CHAEXT)
539 sunzilog_status_handle(up, channel);
540 if (r3 & CHATxIP)
541 sunzilog_transmit_chars(up, channel);
542 }
543 spin_unlock(&up->port.lock);
544
545 if (tty)
546 tty_flip_buffer_push(tty);
547
548 /* Channel B */
549 up = up->next;
550 channel = ZILOG_CHANNEL_FROM_PORT(&up->port);
551
552 spin_lock(&up->port.lock);
553 tty = NULL;
554 if (r3 & (CHBEXT | CHBTxIP | CHBRxIP)) {
555 writeb(RES_H_IUS, &channel->control);
556 ZSDELAY();
557 ZS_WSYNC(channel);
558
559 if (r3 & CHBRxIP)
560 tty = sunzilog_receive_chars(up, channel);
561 if (r3 & CHBEXT)
562 sunzilog_status_handle(up, channel);
563 if (r3 & CHBTxIP)
564 sunzilog_transmit_chars(up, channel);
565 }
566 spin_unlock(&up->port.lock);
567
568 if (tty)
569 tty_flip_buffer_push(tty);
570
571 up = up->next;
572 }
573
574 return IRQ_HANDLED;
575 }
576
577 /* A convenient way to quickly get R0 status. The caller must _not_ hold the
578 * port lock, it is acquired here.
579 */
580 static __inline__ unsigned char sunzilog_read_channel_status(struct uart_port *port)
581 {
582 struct zilog_channel __iomem *channel;
583 unsigned char status;
584
585 channel = ZILOG_CHANNEL_FROM_PORT(port);
586 status = readb(&channel->control);
587 ZSDELAY();
588
589 return status;
590 }
591
592 /* The port lock is not held. */
593 static unsigned int sunzilog_tx_empty(struct uart_port *port)
594 {
595 unsigned long flags;
596 unsigned char status;
597 unsigned int ret;
598
599 spin_lock_irqsave(&port->lock, flags);
600
601 status = sunzilog_read_channel_status(port);
602
603 spin_unlock_irqrestore(&port->lock, flags);
604
605 if (status & Tx_BUF_EMP)
606 ret = TIOCSER_TEMT;
607 else
608 ret = 0;
609
610 return ret;
611 }
612
613 /* The port lock is held and interrupts are disabled. */
614 static unsigned int sunzilog_get_mctrl(struct uart_port *port)
615 {
616 unsigned char status;
617 unsigned int ret;
618
619 status = sunzilog_read_channel_status(port);
620
621 ret = 0;
622 if (status & DCD)
623 ret |= TIOCM_CAR;
624 if (status & SYNC)
625 ret |= TIOCM_DSR;
626 if (status & CTS)
627 ret |= TIOCM_CTS;
628
629 return ret;
630 }
631
632 /* The port lock is held and interrupts are disabled. */
633 static void sunzilog_set_mctrl(struct uart_port *port, unsigned int mctrl)
634 {
635 struct uart_sunzilog_port *up = (struct uart_sunzilog_port *) port;
636 struct zilog_channel __iomem *channel = ZILOG_CHANNEL_FROM_PORT(port);
637 unsigned char set_bits, clear_bits;
638
639 set_bits = clear_bits = 0;
640
641 if (mctrl & TIOCM_RTS)
642 set_bits |= RTS;
643 else
644 clear_bits |= RTS;
645 if (mctrl & TIOCM_DTR)
646 set_bits |= DTR;
647 else
648 clear_bits |= DTR;
649
650 /* NOTE: Not subject to 'transmitter active' rule. */
651 up->curregs[R5] |= set_bits;
652 up->curregs[R5] &= ~clear_bits;
653 write_zsreg(channel, R5, up->curregs[R5]);
654 }
655
656 /* The port lock is held and interrupts are disabled. */
657 static void sunzilog_stop_tx(struct uart_port *port)
658 {
659 struct uart_sunzilog_port *up = (struct uart_sunzilog_port *) port;
660
661 up->flags |= SUNZILOG_FLAG_TX_STOPPED;
662 }
663
664 /* The port lock is held and interrupts are disabled. */
665 static void sunzilog_start_tx(struct uart_port *port)
666 {
667 struct uart_sunzilog_port *up = (struct uart_sunzilog_port *) port;
668 struct zilog_channel __iomem *channel = ZILOG_CHANNEL_FROM_PORT(port);
669 unsigned char status;
670
671 up->flags |= SUNZILOG_FLAG_TX_ACTIVE;
672 up->flags &= ~SUNZILOG_FLAG_TX_STOPPED;
673
674 status = readb(&channel->control);
675 ZSDELAY();
676
677 /* TX busy? Just wait for the TX done interrupt. */
678 if (!(status & Tx_BUF_EMP))
679 return;
680
681 /* Send the first character to jump-start the TX done
682 * IRQ sending engine.
683 */
684 if (port->x_char) {
685 writeb(port->x_char, &channel->data);
686 ZSDELAY();
687 ZS_WSYNC(channel);
688
689 port->icount.tx++;
690 port->x_char = 0;
691 } else {
692 struct circ_buf *xmit = &port->info->xmit;
693
694 writeb(xmit->buf[xmit->tail], &channel->data);
695 ZSDELAY();
696 ZS_WSYNC(channel);
697
698 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
699 port->icount.tx++;
700
701 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
702 uart_write_wakeup(&up->port);
703 }
704 }
705
706 /* The port lock is held. */
707 static void sunzilog_stop_rx(struct uart_port *port)
708 {
709 struct uart_sunzilog_port *up = UART_ZILOG(port);
710 struct zilog_channel __iomem *channel;
711
712 if (ZS_IS_CONS(up))
713 return;
714
715 channel = ZILOG_CHANNEL_FROM_PORT(port);
716
717 /* Disable all RX interrupts. */
718 up->curregs[R1] &= ~RxINT_MASK;
719 sunzilog_maybe_update_regs(up, channel);
720 }
721
722 /* The port lock is held. */
723 static void sunzilog_enable_ms(struct uart_port *port)
724 {
725 struct uart_sunzilog_port *up = (struct uart_sunzilog_port *) port;
726 struct zilog_channel __iomem *channel = ZILOG_CHANNEL_FROM_PORT(port);
727 unsigned char new_reg;
728
729 new_reg = up->curregs[R15] | (DCDIE | SYNCIE | CTSIE);
730 if (new_reg != up->curregs[R15]) {
731 up->curregs[R15] = new_reg;
732
733 /* NOTE: Not subject to 'transmitter active' rule. */
734 write_zsreg(channel, R15, up->curregs[R15]);
735 }
736 }
737
738 /* The port lock is not held. */
739 static void sunzilog_break_ctl(struct uart_port *port, int break_state)
740 {
741 struct uart_sunzilog_port *up = (struct uart_sunzilog_port *) port;
742 struct zilog_channel __iomem *channel = ZILOG_CHANNEL_FROM_PORT(port);
743 unsigned char set_bits, clear_bits, new_reg;
744 unsigned long flags;
745
746 set_bits = clear_bits = 0;
747
748 if (break_state)
749 set_bits |= SND_BRK;
750 else
751 clear_bits |= SND_BRK;
752
753 spin_lock_irqsave(&port->lock, flags);
754
755 new_reg = (up->curregs[R5] | set_bits) & ~clear_bits;
756 if (new_reg != up->curregs[R5]) {
757 up->curregs[R5] = new_reg;
758
759 /* NOTE: Not subject to 'transmitter active' rule. */
760 write_zsreg(channel, R5, up->curregs[R5]);
761 }
762
763 spin_unlock_irqrestore(&port->lock, flags);
764 }
765
766 static void __sunzilog_startup(struct uart_sunzilog_port *up)
767 {
768 struct zilog_channel __iomem *channel;
769
770 channel = ZILOG_CHANNEL_FROM_PORT(&up->port);
771 up->prev_status = readb(&channel->control);
772
773 /* Enable receiver and transmitter. */
774 up->curregs[R3] |= RxENAB;
775 up->curregs[R5] |= TxENAB;
776
777 up->curregs[R1] |= EXT_INT_ENAB | INT_ALL_Rx | TxINT_ENAB;
778 sunzilog_maybe_update_regs(up, channel);
779 }
780
781 static int sunzilog_startup(struct uart_port *port)
782 {
783 struct uart_sunzilog_port *up = UART_ZILOG(port);
784 unsigned long flags;
785
786 if (ZS_IS_CONS(up))
787 return 0;
788
789 spin_lock_irqsave(&port->lock, flags);
790 __sunzilog_startup(up);
791 spin_unlock_irqrestore(&port->lock, flags);
792 return 0;
793 }
794
795 /*
796 * The test for ZS_IS_CONS is explained by the following e-mail:
797 *****
798 * From: Russell King <rmk@arm.linux.org.uk>
799 * Date: Sun, 8 Dec 2002 10:18:38 +0000
800 *
801 * On Sun, Dec 08, 2002 at 02:43:36AM -0500, Pete Zaitcev wrote:
802 * > I boot my 2.5 boxes using "console=ttyS0,9600" argument,
803 * > and I noticed that something is not right with reference
804 * > counting in this case. It seems that when the console
805 * > is open by kernel initially, this is not accounted
806 * > as an open, and uart_startup is not called.
807 *
808 * That is correct. We are unable to call uart_startup when the serial
809 * console is initialised because it may need to allocate memory (as
810 * request_irq does) and the memory allocators may not have been
811 * initialised.
812 *
813 * 1. initialise the port into a state where it can send characters in the
814 * console write method.
815 *
816 * 2. don't do the actual hardware shutdown in your shutdown() method (but
817 * do the normal software shutdown - ie, free irqs etc)
818 *****
819 */
820 static void sunzilog_shutdown(struct uart_port *port)
821 {
822 struct uart_sunzilog_port *up = UART_ZILOG(port);
823 struct zilog_channel __iomem *channel;
824 unsigned long flags;
825
826 if (ZS_IS_CONS(up))
827 return;
828
829 spin_lock_irqsave(&port->lock, flags);
830
831 channel = ZILOG_CHANNEL_FROM_PORT(port);
832
833 /* Disable receiver and transmitter. */
834 up->curregs[R3] &= ~RxENAB;
835 up->curregs[R5] &= ~TxENAB;
836
837 /* Disable all interrupts and BRK assertion. */
838 up->curregs[R1] &= ~(EXT_INT_ENAB | TxINT_ENAB | RxINT_MASK);
839 up->curregs[R5] &= ~SND_BRK;
840 sunzilog_maybe_update_regs(up, channel);
841
842 spin_unlock_irqrestore(&port->lock, flags);
843 }
844
845 /* Shared by TTY driver and serial console setup. The port lock is held
846 * and local interrupts are disabled.
847 */
848 static void
849 sunzilog_convert_to_zs(struct uart_sunzilog_port *up, unsigned int cflag,
850 unsigned int iflag, int brg)
851 {
852
853 up->curregs[R10] = NRZ;
854 up->curregs[R11] = TCBR | RCBR;
855
856 /* Program BAUD and clock source. */
857 up->curregs[R4] &= ~XCLK_MASK;
858 up->curregs[R4] |= X16CLK;
859 up->curregs[R12] = brg & 0xff;
860 up->curregs[R13] = (brg >> 8) & 0xff;
861 up->curregs[R14] = BRSRC | BRENAB;
862
863 /* Character size, stop bits, and parity. */
864 up->curregs[3] &= ~RxN_MASK;
865 up->curregs[5] &= ~TxN_MASK;
866 switch (cflag & CSIZE) {
867 case CS5:
868 up->curregs[3] |= Rx5;
869 up->curregs[5] |= Tx5;
870 up->parity_mask = 0x1f;
871 break;
872 case CS6:
873 up->curregs[3] |= Rx6;
874 up->curregs[5] |= Tx6;
875 up->parity_mask = 0x3f;
876 break;
877 case CS7:
878 up->curregs[3] |= Rx7;
879 up->curregs[5] |= Tx7;
880 up->parity_mask = 0x7f;
881 break;
882 case CS8:
883 default:
884 up->curregs[3] |= Rx8;
885 up->curregs[5] |= Tx8;
886 up->parity_mask = 0xff;
887 break;
888 };
889 up->curregs[4] &= ~0x0c;
890 if (cflag & CSTOPB)
891 up->curregs[4] |= SB2;
892 else
893 up->curregs[4] |= SB1;
894 if (cflag & PARENB)
895 up->curregs[4] |= PAR_ENAB;
896 else
897 up->curregs[4] &= ~PAR_ENAB;
898 if (!(cflag & PARODD))
899 up->curregs[4] |= PAR_EVEN;
900 else
901 up->curregs[4] &= ~PAR_EVEN;
902
903 up->port.read_status_mask = Rx_OVR;
904 if (iflag & INPCK)
905 up->port.read_status_mask |= CRC_ERR | PAR_ERR;
906 if (iflag & (BRKINT | PARMRK))
907 up->port.read_status_mask |= BRK_ABRT;
908
909 up->port.ignore_status_mask = 0;
910 if (iflag & IGNPAR)
911 up->port.ignore_status_mask |= CRC_ERR | PAR_ERR;
912 if (iflag & IGNBRK) {
913 up->port.ignore_status_mask |= BRK_ABRT;
914 if (iflag & IGNPAR)
915 up->port.ignore_status_mask |= Rx_OVR;
916 }
917
918 if ((cflag & CREAD) == 0)
919 up->port.ignore_status_mask = 0xff;
920 }
921
922 /* The port lock is not held. */
923 static void
924 sunzilog_set_termios(struct uart_port *port, struct ktermios *termios,
925 struct ktermios *old)
926 {
927 struct uart_sunzilog_port *up = (struct uart_sunzilog_port *) port;
928 unsigned long flags;
929 int baud, brg;
930
931 baud = uart_get_baud_rate(port, termios, old, 1200, 76800);
932
933 spin_lock_irqsave(&up->port.lock, flags);
934
935 brg = BPS_TO_BRG(baud, ZS_CLOCK / ZS_CLOCK_DIVISOR);
936
937 sunzilog_convert_to_zs(up, termios->c_cflag, termios->c_iflag, brg);
938
939 if (UART_ENABLE_MS(&up->port, termios->c_cflag))
940 up->flags |= SUNZILOG_FLAG_MODEM_STATUS;
941 else
942 up->flags &= ~SUNZILOG_FLAG_MODEM_STATUS;
943
944 up->cflag = termios->c_cflag;
945
946 sunzilog_maybe_update_regs(up, ZILOG_CHANNEL_FROM_PORT(port));
947
948 uart_update_timeout(port, termios->c_cflag, baud);
949
950 spin_unlock_irqrestore(&up->port.lock, flags);
951 }
952
953 static const char *sunzilog_type(struct uart_port *port)
954 {
955 return "zs";
956 }
957
958 /* We do not request/release mappings of the registers here, this
959 * happens at early serial probe time.
960 */
961 static void sunzilog_release_port(struct uart_port *port)
962 {
963 }
964
965 static int sunzilog_request_port(struct uart_port *port)
966 {
967 return 0;
968 }
969
970 /* These do not need to do anything interesting either. */
971 static void sunzilog_config_port(struct uart_port *port, int flags)
972 {
973 }
974
975 /* We do not support letting the user mess with the divisor, IRQ, etc. */
976 static int sunzilog_verify_port(struct uart_port *port, struct serial_struct *ser)
977 {
978 return -EINVAL;
979 }
980
981 static struct uart_ops sunzilog_pops = {
982 .tx_empty = sunzilog_tx_empty,
983 .set_mctrl = sunzilog_set_mctrl,
984 .get_mctrl = sunzilog_get_mctrl,
985 .stop_tx = sunzilog_stop_tx,
986 .start_tx = sunzilog_start_tx,
987 .stop_rx = sunzilog_stop_rx,
988 .enable_ms = sunzilog_enable_ms,
989 .break_ctl = sunzilog_break_ctl,
990 .startup = sunzilog_startup,
991 .shutdown = sunzilog_shutdown,
992 .set_termios = sunzilog_set_termios,
993 .type = sunzilog_type,
994 .release_port = sunzilog_release_port,
995 .request_port = sunzilog_request_port,
996 .config_port = sunzilog_config_port,
997 .verify_port = sunzilog_verify_port,
998 };
999
1000 static struct uart_sunzilog_port *sunzilog_port_table;
1001 static struct zilog_layout __iomem **sunzilog_chip_regs;
1002
1003 static struct uart_sunzilog_port *sunzilog_irq_chain;
1004
1005 static struct uart_driver sunzilog_reg = {
1006 .owner = THIS_MODULE,
1007 .driver_name = "ttyS",
1008 .dev_name = "ttyS",
1009 .major = TTY_MAJOR,
1010 };
1011
1012 static int __init sunzilog_alloc_tables(void)
1013 {
1014 struct uart_sunzilog_port *up;
1015 unsigned long size;
1016 int i;
1017
1018 size = NUM_CHANNELS * sizeof(struct uart_sunzilog_port);
1019 sunzilog_port_table = kzalloc(size, GFP_KERNEL);
1020 if (!sunzilog_port_table)
1021 return -ENOMEM;
1022
1023 for (i = 0; i < NUM_CHANNELS; i++) {
1024 up = &sunzilog_port_table[i];
1025
1026 spin_lock_init(&up->port.lock);
1027
1028 if (i == 0)
1029 sunzilog_irq_chain = up;
1030
1031 if (i < NUM_CHANNELS - 1)
1032 up->next = up + 1;
1033 else
1034 up->next = NULL;
1035 }
1036
1037 size = NUM_SUNZILOG * sizeof(struct zilog_layout __iomem *);
1038 sunzilog_chip_regs = kzalloc(size, GFP_KERNEL);
1039 if (!sunzilog_chip_regs) {
1040 kfree(sunzilog_port_table);
1041 sunzilog_irq_chain = NULL;
1042 return -ENOMEM;
1043 }
1044
1045 return 0;
1046 }
1047
1048 static void sunzilog_free_tables(void)
1049 {
1050 kfree(sunzilog_port_table);
1051 sunzilog_irq_chain = NULL;
1052 kfree(sunzilog_chip_regs);
1053 }
1054
1055 #define ZS_PUT_CHAR_MAX_DELAY 2000 /* 10 ms */
1056
1057 static void sunzilog_putchar(struct uart_port *port, int ch)
1058 {
1059 struct zilog_channel __iomem *channel = ZILOG_CHANNEL_FROM_PORT(port);
1060 int loops = ZS_PUT_CHAR_MAX_DELAY;
1061
1062 /* This is a timed polling loop so do not switch the explicit
1063 * udelay with ZSDELAY as that is a NOP on some platforms. -DaveM
1064 */
1065 do {
1066 unsigned char val = readb(&channel->control);
1067 if (val & Tx_BUF_EMP) {
1068 ZSDELAY();
1069 break;
1070 }
1071 udelay(5);
1072 } while (--loops);
1073
1074 writeb(ch, &channel->data);
1075 ZSDELAY();
1076 ZS_WSYNC(channel);
1077 }
1078
1079 #ifdef CONFIG_SERIO
1080
1081 static DEFINE_SPINLOCK(sunzilog_serio_lock);
1082
1083 static int sunzilog_serio_write(struct serio *serio, unsigned char ch)
1084 {
1085 struct uart_sunzilog_port *up = serio->port_data;
1086 unsigned long flags;
1087
1088 spin_lock_irqsave(&sunzilog_serio_lock, flags);
1089
1090 sunzilog_putchar(&up->port, ch);
1091
1092 spin_unlock_irqrestore(&sunzilog_serio_lock, flags);
1093
1094 return 0;
1095 }
1096
1097 static int sunzilog_serio_open(struct serio *serio)
1098 {
1099 struct uart_sunzilog_port *up = serio->port_data;
1100 unsigned long flags;
1101 int ret;
1102
1103 spin_lock_irqsave(&sunzilog_serio_lock, flags);
1104 if (!up->serio_open) {
1105 up->serio_open = 1;
1106 ret = 0;
1107 } else
1108 ret = -EBUSY;
1109 spin_unlock_irqrestore(&sunzilog_serio_lock, flags);
1110
1111 return ret;
1112 }
1113
1114 static void sunzilog_serio_close(struct serio *serio)
1115 {
1116 struct uart_sunzilog_port *up = serio->port_data;
1117 unsigned long flags;
1118
1119 spin_lock_irqsave(&sunzilog_serio_lock, flags);
1120 up->serio_open = 0;
1121 spin_unlock_irqrestore(&sunzilog_serio_lock, flags);
1122 }
1123
1124 #endif /* CONFIG_SERIO */
1125
1126 #ifdef CONFIG_SERIAL_SUNZILOG_CONSOLE
1127 static void
1128 sunzilog_console_write(struct console *con, const char *s, unsigned int count)
1129 {
1130 struct uart_sunzilog_port *up = &sunzilog_port_table[con->index];
1131 unsigned long flags;
1132
1133 spin_lock_irqsave(&up->port.lock, flags);
1134 uart_console_write(&up->port, s, count, sunzilog_putchar);
1135 udelay(2);
1136 spin_unlock_irqrestore(&up->port.lock, flags);
1137 }
1138
1139 static int __init sunzilog_console_setup(struct console *con, char *options)
1140 {
1141 struct uart_sunzilog_port *up = &sunzilog_port_table[con->index];
1142 unsigned long flags;
1143 int baud, brg;
1144
1145 if (up->port.type != PORT_SUNZILOG)
1146 return -1;
1147
1148 printk(KERN_INFO "Console: ttyS%d (SunZilog zs%d)\n",
1149 (sunzilog_reg.minor - 64) + con->index, con->index);
1150
1151 /* Get firmware console settings. */
1152 sunserial_console_termios(con);
1153
1154 /* Firmware console speed is limited to 150-->38400 baud so
1155 * this hackish cflag thing is OK.
1156 */
1157 switch (con->cflag & CBAUD) {
1158 case B150: baud = 150; break;
1159 case B300: baud = 300; break;
1160 case B600: baud = 600; break;
1161 case B1200: baud = 1200; break;
1162 case B2400: baud = 2400; break;
1163 case B4800: baud = 4800; break;
1164 default: case B9600: baud = 9600; break;
1165 case B19200: baud = 19200; break;
1166 case B38400: baud = 38400; break;
1167 };
1168
1169 brg = BPS_TO_BRG(baud, ZS_CLOCK / ZS_CLOCK_DIVISOR);
1170
1171 spin_lock_irqsave(&up->port.lock, flags);
1172
1173 up->curregs[R15] = BRKIE;
1174 sunzilog_convert_to_zs(up, con->cflag, 0, brg);
1175
1176 sunzilog_set_mctrl(&up->port, TIOCM_DTR | TIOCM_RTS);
1177 __sunzilog_startup(up);
1178
1179 spin_unlock_irqrestore(&up->port.lock, flags);
1180
1181 return 0;
1182 }
1183
1184 static struct console sunzilog_console_ops = {
1185 .name = "ttyS",
1186 .write = sunzilog_console_write,
1187 .device = uart_console_device,
1188 .setup = sunzilog_console_setup,
1189 .flags = CON_PRINTBUFFER,
1190 .index = -1,
1191 .data = &sunzilog_reg,
1192 };
1193
1194 static inline struct console *SUNZILOG_CONSOLE(void)
1195 {
1196 int i;
1197
1198 if (con_is_present())
1199 return NULL;
1200
1201 for (i = 0; i < NUM_CHANNELS; i++) {
1202 int this_minor = sunzilog_reg.minor + i;
1203
1204 if ((this_minor - 64) == (serial_console - 1))
1205 break;
1206 }
1207 if (i == NUM_CHANNELS)
1208 return NULL;
1209
1210 sunzilog_console_ops.index = i;
1211 sunzilog_port_table[i].flags |= SUNZILOG_FLAG_IS_CONS;
1212
1213 return &sunzilog_console_ops;
1214 }
1215
1216 #else
1217 #define SUNZILOG_CONSOLE() (NULL)
1218 #endif
1219
1220 static void __init sunzilog_init_kbdms(struct uart_sunzilog_port *up, int channel)
1221 {
1222 int baud, brg;
1223
1224 if (up->flags & SUNZILOG_FLAG_CONS_KEYB) {
1225 up->cflag = B1200 | CS8 | CLOCAL | CREAD;
1226 baud = 1200;
1227 } else {
1228 up->cflag = B4800 | CS8 | CLOCAL | CREAD;
1229 baud = 4800;
1230 }
1231
1232 up->curregs[R15] = BRKIE;
1233 brg = BPS_TO_BRG(baud, ZS_CLOCK / ZS_CLOCK_DIVISOR);
1234 sunzilog_convert_to_zs(up, up->cflag, 0, brg);
1235 sunzilog_set_mctrl(&up->port, TIOCM_DTR | TIOCM_RTS);
1236 __sunzilog_startup(up);
1237 }
1238
1239 #ifdef CONFIG_SERIO
1240 static void __init sunzilog_register_serio(struct uart_sunzilog_port *up)
1241 {
1242 struct serio *serio = &up->serio;
1243
1244 serio->port_data = up;
1245
1246 serio->id.type = SERIO_RS232;
1247 if (up->flags & SUNZILOG_FLAG_CONS_KEYB) {
1248 serio->id.proto = SERIO_SUNKBD;
1249 strlcpy(serio->name, "zskbd", sizeof(serio->name));
1250 } else {
1251 serio->id.proto = SERIO_SUN;
1252 serio->id.extra = 1;
1253 strlcpy(serio->name, "zsms", sizeof(serio->name));
1254 }
1255 strlcpy(serio->phys,
1256 ((up->flags & SUNZILOG_FLAG_CONS_KEYB) ?
1257 "zs/serio0" : "zs/serio1"),
1258 sizeof(serio->phys));
1259
1260 serio->write = sunzilog_serio_write;
1261 serio->open = sunzilog_serio_open;
1262 serio->close = sunzilog_serio_close;
1263 serio->dev.parent = up->port.dev;
1264
1265 serio_register_port(serio);
1266 }
1267 #endif
1268
1269 static void __devinit sunzilog_init_hw(struct uart_sunzilog_port *up)
1270 {
1271 struct zilog_channel __iomem *channel;
1272 unsigned long flags;
1273 int baud, brg;
1274
1275 channel = ZILOG_CHANNEL_FROM_PORT(&up->port);
1276
1277 spin_lock_irqsave(&up->port.lock, flags);
1278 if (ZS_IS_CHANNEL_A(up)) {
1279 write_zsreg(channel, R9, FHWRES);
1280 ZSDELAY_LONG();
1281 (void) read_zsreg(channel, R0);
1282 }
1283
1284 if (up->flags & (SUNZILOG_FLAG_CONS_KEYB |
1285 SUNZILOG_FLAG_CONS_MOUSE)) {
1286 sunzilog_init_kbdms(up, up->port.line);
1287 up->curregs[R9] |= (NV | MIE);
1288 write_zsreg(channel, R9, up->curregs[R9]);
1289 } else {
1290 /* Normal serial TTY. */
1291 up->parity_mask = 0xff;
1292 up->curregs[R1] = EXT_INT_ENAB | INT_ALL_Rx | TxINT_ENAB;
1293 up->curregs[R4] = PAR_EVEN | X16CLK | SB1;
1294 up->curregs[R3] = RxENAB | Rx8;
1295 up->curregs[R5] = TxENAB | Tx8;
1296 up->curregs[R9] = NV | MIE;
1297 up->curregs[R10] = NRZ;
1298 up->curregs[R11] = TCBR | RCBR;
1299 baud = 9600;
1300 brg = BPS_TO_BRG(baud, ZS_CLOCK / ZS_CLOCK_DIVISOR);
1301 up->curregs[R12] = (brg & 0xff);
1302 up->curregs[R13] = (brg >> 8) & 0xff;
1303 up->curregs[R14] = BRSRC | BRENAB;
1304 __load_zsregs(channel, up->curregs);
1305 write_zsreg(channel, R9, up->curregs[R9]);
1306 }
1307
1308 spin_unlock_irqrestore(&up->port.lock, flags);
1309
1310 #ifdef CONFIG_SERIO
1311 if (up->flags & (SUNZILOG_FLAG_CONS_KEYB |
1312 SUNZILOG_FLAG_CONS_MOUSE))
1313 sunzilog_register_serio(up);
1314 #endif
1315 }
1316
1317 static int zilog_irq = -1;
1318
1319 static int __devinit zs_probe(struct of_device *op, const struct of_device_id *match)
1320 {
1321 static int inst;
1322 struct uart_sunzilog_port *up;
1323 struct zilog_layout __iomem *rp;
1324 int keyboard_mouse;
1325 int err;
1326
1327 keyboard_mouse = 0;
1328 if (of_find_property(op->node, "keyboard", NULL))
1329 keyboard_mouse = 1;
1330
1331 sunzilog_chip_regs[inst] = of_ioremap(&op->resource[0], 0,
1332 sizeof(struct zilog_layout),
1333 "zs");
1334 if (!sunzilog_chip_regs[inst])
1335 return -ENOMEM;
1336
1337 rp = sunzilog_chip_regs[inst];
1338
1339 if (zilog_irq == -1)
1340 zilog_irq = op->irqs[0];
1341
1342 up = &sunzilog_port_table[inst * 2];
1343
1344 /* Channel A */
1345 up[0].port.mapbase = op->resource[0].start + 0x00;
1346 up[0].port.membase = (void __iomem *) &rp->channelA;
1347 up[0].port.iotype = UPIO_MEM;
1348 up[0].port.irq = op->irqs[0];
1349 up[0].port.uartclk = ZS_CLOCK;
1350 up[0].port.fifosize = 1;
1351 up[0].port.ops = &sunzilog_pops;
1352 up[0].port.type = PORT_SUNZILOG;
1353 up[0].port.flags = 0;
1354 up[0].port.line = (inst * 2) + 0;
1355 up[0].port.dev = &op->dev;
1356 up[0].flags |= SUNZILOG_FLAG_IS_CHANNEL_A;
1357 if (keyboard_mouse)
1358 up[0].flags |= SUNZILOG_FLAG_CONS_KEYB;
1359 sunzilog_init_hw(&up[0]);
1360
1361 /* Channel B */
1362 up[1].port.mapbase = op->resource[0].start + 0x04;
1363 up[1].port.membase = (void __iomem *) &rp->channelB;
1364 up[1].port.iotype = UPIO_MEM;
1365 up[1].port.irq = op->irqs[0];
1366 up[1].port.uartclk = ZS_CLOCK;
1367 up[1].port.fifosize = 1;
1368 up[1].port.ops = &sunzilog_pops;
1369 up[1].port.type = PORT_SUNZILOG;
1370 up[1].port.flags = 0;
1371 up[1].port.line = (inst * 2) + 1;
1372 up[1].port.dev = &op->dev;
1373 up[1].flags |= 0;
1374 if (keyboard_mouse)
1375 up[1].flags |= SUNZILOG_FLAG_CONS_MOUSE;
1376 sunzilog_init_hw(&up[1]);
1377
1378 if (!keyboard_mouse) {
1379 err = uart_add_one_port(&sunzilog_reg, &up[0].port);
1380 if (err) {
1381 of_iounmap(&op->resource[0],
1382 rp, sizeof(struct zilog_layout));
1383 return err;
1384 }
1385 err = uart_add_one_port(&sunzilog_reg, &up[1].port);
1386 if (err) {
1387 uart_remove_one_port(&sunzilog_reg, &up[0].port);
1388 of_iounmap(&op->resource[0],
1389 rp, sizeof(struct zilog_layout));
1390 return err;
1391 }
1392 } else {
1393 printk(KERN_INFO "%s: Keyboard at MMIO %lx (irq = %d) "
1394 "is a zs\n",
1395 op->dev.bus_id, up[0].port.mapbase, op->irqs[0]);
1396 printk(KERN_INFO "%s: Mouse at MMIO %lx (irq = %d) "
1397 "is a zs\n",
1398 op->dev.bus_id, up[1].port.mapbase, op->irqs[0]);
1399 }
1400
1401 dev_set_drvdata(&op->dev, &up[0]);
1402
1403 inst++;
1404
1405 return 0;
1406 }
1407
1408 static void __devexit zs_remove_one(struct uart_sunzilog_port *up)
1409 {
1410 if (ZS_IS_KEYB(up) || ZS_IS_MOUSE(up)) {
1411 #ifdef CONFIG_SERIO
1412 serio_unregister_port(&up->serio);
1413 #endif
1414 } else
1415 uart_remove_one_port(&sunzilog_reg, &up->port);
1416 }
1417
1418 static int __devexit zs_remove(struct of_device *op)
1419 {
1420 struct uart_sunzilog_port *up = dev_get_drvdata(&op->dev);
1421 struct zilog_layout __iomem *regs;
1422
1423 zs_remove_one(&up[0]);
1424 zs_remove_one(&up[1]);
1425
1426 regs = sunzilog_chip_regs[up[0].port.line / 2];
1427 of_iounmap(&op->resource[0], regs, sizeof(struct zilog_layout));
1428
1429 dev_set_drvdata(&op->dev, NULL);
1430
1431 return 0;
1432 }
1433
1434 static struct of_device_id zs_match[] = {
1435 {
1436 .name = "zs",
1437 },
1438 {},
1439 };
1440 MODULE_DEVICE_TABLE(of, zs_match);
1441
1442 static struct of_platform_driver zs_driver = {
1443 .name = "zs",
1444 .match_table = zs_match,
1445 .probe = zs_probe,
1446 .remove = __devexit_p(zs_remove),
1447 };
1448
1449 static int __init sunzilog_init(void)
1450 {
1451 struct device_node *dp;
1452 int err, uart_count;
1453 int num_keybms;
1454
1455 NUM_SUNZILOG = 0;
1456 num_keybms = 0;
1457 for_each_node_by_name(dp, "zs") {
1458 NUM_SUNZILOG++;
1459 if (of_find_property(dp, "keyboard", NULL))
1460 num_keybms++;
1461 }
1462
1463 uart_count = 0;
1464 if (NUM_SUNZILOG) {
1465 int uart_count;
1466
1467 err = sunzilog_alloc_tables();
1468 if (err)
1469 goto out;
1470
1471 uart_count = (NUM_SUNZILOG * 2) - (2 * num_keybms);
1472
1473 sunzilog_reg.nr = uart_count;
1474 sunzilog_reg.minor = sunserial_current_minor;
1475 err = uart_register_driver(&sunzilog_reg);
1476 if (err)
1477 goto out_free_tables;
1478
1479 sunzilog_reg.tty_driver->name_base = sunzilog_reg.minor - 64;
1480 sunzilog_reg.cons = SUNZILOG_CONSOLE();
1481
1482 sunserial_current_minor += uart_count;
1483 }
1484
1485 err = of_register_driver(&zs_driver, &of_bus_type);
1486 if (err)
1487 goto out_unregister_uart;
1488
1489 if (zilog_irq != -1) {
1490 err = request_irq(zilog_irq, sunzilog_interrupt, IRQF_SHARED,
1491 "zs", sunzilog_irq_chain);
1492 if (err)
1493 goto out_unregister_driver;
1494 }
1495
1496 out:
1497 return err;
1498
1499 out_unregister_driver:
1500 of_unregister_driver(&zs_driver);
1501
1502 out_unregister_uart:
1503 if (NUM_SUNZILOG) {
1504 uart_unregister_driver(&sunzilog_reg);
1505 sunzilog_reg.cons = NULL;
1506 }
1507
1508 out_free_tables:
1509 sunzilog_free_tables();
1510 goto out;
1511 }
1512
1513 static void __exit sunzilog_exit(void)
1514 {
1515 of_unregister_driver(&zs_driver);
1516
1517 if (zilog_irq != -1) {
1518 free_irq(zilog_irq, sunzilog_irq_chain);
1519 zilog_irq = -1;
1520 }
1521
1522 if (NUM_SUNZILOG) {
1523 uart_unregister_driver(&sunzilog_reg);
1524 sunzilog_free_tables();
1525 }
1526 }
1527
1528 module_init(sunzilog_init);
1529 module_exit(sunzilog_exit);
1530
1531 MODULE_AUTHOR("David S. Miller");
1532 MODULE_DESCRIPTION("Sun Zilog serial port driver");
1533 MODULE_VERSION("2.0");
1534 MODULE_LICENSE("GPL");
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