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mm: vmscan: immediately reclaim end-of-LRU dirty pages when writeback completes
[linux-2.6.git] / drivers / gpio / gpio-u300.c
blob4035778852b0d7a1cfbc97d16ab1f8637c1bba59
1 /*
2 * U300 GPIO module.
3 *
4 * Copyright (C) 2007-2011 ST-Ericsson AB
5 * License terms: GNU General Public License (GPL) version 2
6 * This can driver either of the two basic GPIO cores
7 * available in the U300 platforms:
8 * COH 901 335 - Used in DB3150 (U300 1.0) and DB3200 (U330 1.0)
9 * COH 901 571/3 - Used in DB3210 (U365 2.0) and DB3350 (U335 1.0)
10 * Author: Linus Walleij <linus.walleij@linaro.org>
11 * Author: Jonas Aaberg <jonas.aberg@stericsson.com>
12 */
13 #include <linux/module.h>
14 #include <linux/irq.h>
15 #include <linux/interrupt.h>
16 #include <linux/delay.h>
17 #include <linux/errno.h>
18 #include <linux/io.h>
19 #include <linux/clk.h>
20 #include <linux/err.h>
21 #include <linux/platform_device.h>
22 #include <linux/gpio.h>
23 #include <linux/list.h>
24 #include <linux/slab.h>
25 #include <mach/gpio-u300.h>
26
27 /*
28 * Bias modes for U300 GPIOs
29 *
30 * GPIO_U300_CONFIG_BIAS_UNKNOWN: this bias mode is not known to us
31 * GPIO_U300_CONFIG_BIAS_FLOAT: no specific bias, the GPIO will float or state
32 * is not controlled by software
33 * GPIO_U300_CONFIG_BIAS_PULL_UP: the GPIO will be pulled up (usually with high
34 * impedance to VDD)
35 */
36 #define GPIO_U300_CONFIG_BIAS_UNKNOWN 0x1000
37 #define GPIO_U300_CONFIG_BIAS_FLOAT 0x1001
38 #define GPIO_U300_CONFIG_BIAS_PULL_UP 0x1002
39
40 /*
41 * Drive modes for U300 GPIOs (output)
42 *
43 * GPIO_U300_CONFIG_DRIVE_PUSH_PULL: the GPIO will be driven actively high and
44 * low, this is the most typical case and is typically achieved with two
45 * active transistors on the output
46 * GPIO_U300_CONFIG_DRIVE_OPEN_DRAIN: the GPIO will be driven with open drain
47 * (open collector) which means it is usually wired with other output
48 * ports which are then pulled up with an external resistor
49 * GPIO_U300_CONFIG_DRIVE_OPEN_SOURCE: the GPIO will be driven with open drain
50 * (open emitter) which is the same as open drain mutatis mutandis but
51 * pulled to ground
52 */
53 #define GPIO_U300_CONFIG_DRIVE_PUSH_PULL 0x2000
54 #define GPIO_U300_CONFIG_DRIVE_OPEN_DRAIN 0x2001
55 #define GPIO_U300_CONFIG_DRIVE_OPEN_SOURCE 0x2002
56
57 /*
58 * Register definitions for COH 901 335 variant
59 */
60 #define U300_335_PORT_STRIDE (0x1C)
61 /* Port X Pin Data Register 32bit, this is both input and output (R/W) */
62 #define U300_335_PXPDIR (0x00)
63 #define U300_335_PXPDOR (0x00)
64 /* Port X Pin Config Register 32bit (R/W) */
65 #define U300_335_PXPCR (0x04)
66 /* This register layout is the same in both blocks */
67 #define U300_GPIO_PXPCR_ALL_PINS_MODE_MASK (0x0000FFFFUL)
68 #define U300_GPIO_PXPCR_PIN_MODE_MASK (0x00000003UL)
69 #define U300_GPIO_PXPCR_PIN_MODE_SHIFT (0x00000002UL)
70 #define U300_GPIO_PXPCR_PIN_MODE_INPUT (0x00000000UL)
71 #define U300_GPIO_PXPCR_PIN_MODE_OUTPUT_PUSH_PULL (0x00000001UL)
72 #define U300_GPIO_PXPCR_PIN_MODE_OUTPUT_OPEN_DRAIN (0x00000002UL)
73 #define U300_GPIO_PXPCR_PIN_MODE_OUTPUT_OPEN_SOURCE (0x00000003UL)
74 /* Port X Interrupt Event Register 32bit (R/W) */
75 #define U300_335_PXIEV (0x08)
76 /* Port X Interrupt Enable Register 32bit (R/W) */
77 #define U300_335_PXIEN (0x0C)
78 /* Port X Interrupt Force Register 32bit (R/W) */
79 #define U300_335_PXIFR (0x10)
80 /* Port X Interrupt Config Register 32bit (R/W) */
81 #define U300_335_PXICR (0x14)
82 /* This register layout is the same in both blocks */
83 #define U300_GPIO_PXICR_ALL_IRQ_CONFIG_MASK (0x000000FFUL)
84 #define U300_GPIO_PXICR_IRQ_CONFIG_MASK (0x00000001UL)
85 #define U300_GPIO_PXICR_IRQ_CONFIG_FALLING_EDGE (0x00000000UL)
86 #define U300_GPIO_PXICR_IRQ_CONFIG_RISING_EDGE (0x00000001UL)
87 /* Port X Pull-up Enable Register 32bit (R/W) */
88 #define U300_335_PXPER (0x18)
89 /* This register layout is the same in both blocks */
90 #define U300_GPIO_PXPER_ALL_PULL_UP_DISABLE_MASK (0x000000FFUL)
91 #define U300_GPIO_PXPER_PULL_UP_DISABLE (0x00000001UL)
92 /* Control Register 32bit (R/W) */
93 #define U300_335_CR (0x54)
94 #define U300_335_CR_BLOCK_CLOCK_ENABLE (0x00000001UL)
95
96 /*
97 * Register definitions for COH 901 571 / 3 variant
98 */
99 #define U300_571_PORT_STRIDE (0x30)
100 /*
101 * Control Register 32bit (R/W)
102 * bit 15-9 (mask 0x0000FE00) contains the number of cores. 8*cores
103 * gives the number of GPIO pins.
104 * bit 8-2 (mask 0x000001FC) contains the core version ID.
105 */
106 #define U300_571_CR (0x00)
107 #define U300_571_CR_SYNC_SEL_ENABLE (0x00000002UL)
108 #define U300_571_CR_BLOCK_CLKRQ_ENABLE (0x00000001UL)
109 /*
110 * These registers have the same layout and function as the corresponding
111 * COH 901 335 registers, just at different offset.
112 */
113 #define U300_571_PXPDIR (0x04)
114 #define U300_571_PXPDOR (0x08)
115 #define U300_571_PXPCR (0x0C)
116 #define U300_571_PXPER (0x10)
117 #define U300_571_PXIEV (0x14)
118 #define U300_571_PXIEN (0x18)
119 #define U300_571_PXIFR (0x1C)
120 #define U300_571_PXICR (0x20)
121
122 /* 8 bits per port, no version has more than 7 ports */
123 #define U300_GPIO_PINS_PER_PORT 8
124 #define U300_GPIO_MAX (U300_GPIO_PINS_PER_PORT * 7)
125
126 struct u300_gpio {
127 struct gpio_chip chip;
128 struct list_head port_list;
129 struct clk *clk;
130 struct resource *memres;
131 void __iomem *base;
132 struct device *dev;
133 int irq_base;
134 u32 stride;
135 /* Register offsets */
136 u32 pcr;
137 u32 dor;
138 u32 dir;
139 u32 per;
140 u32 icr;
141 u32 ien;
142 u32 iev;
143 };
144
145 struct u300_gpio_port {
146 struct list_head node;
147 struct u300_gpio *gpio;
148 char name[8];
149 int irq;
150 int number;
151 u8 toggle_edge_mode;
152 };
153
154 /*
155 * Macro to expand to read a specific register found in the "gpio"
156 * struct. It requires the struct u300_gpio *gpio variable to exist in
157 * its context. It calculates the port offset from the given pin
158 * offset, muliplies by the port stride and adds the register offset
159 * so it provides a pointer to the desired register.
160 */
161 #define U300_PIN_REG(pin, reg) \
162 (gpio->base + (pin >> 3) * gpio->stride + gpio->reg)
163
164 /*
165 * Provides a bitmask for a specific gpio pin inside an 8-bit GPIO
166 * register.
167 */
168 #define U300_PIN_BIT(pin) \
169 (1 << (pin & 0x07))
170
171 struct u300_gpio_confdata {
172 u16 bias_mode;
173 bool output;
174 int outval;
175 };
176
177 /* BS335 has seven ports of 8 bits each = GPIO pins 0..55 */
178 #define BS335_GPIO_NUM_PORTS 7
179 /* BS365 has five ports of 8 bits each = GPIO pins 0..39 */
180 #define BS365_GPIO_NUM_PORTS 5
181
182 #define U300_FLOATING_INPUT { \
183 .bias_mode = GPIO_U300_CONFIG_BIAS_FLOAT, \
184 .output = false, \
185 }
186
187 #define U300_PULL_UP_INPUT { \
188 .bias_mode = GPIO_U300_CONFIG_BIAS_PULL_UP, \
189 .output = false, \
190 }
191
192 #define U300_OUTPUT_LOW { \
193 .output = true, \
194 .outval = 0, \
195 }
196
197 #define U300_OUTPUT_HIGH { \
198 .output = true, \
199 .outval = 1, \
200 }
201
202
203 /* Initial configuration */
204 static const struct __initdata u300_gpio_confdata
205 bs335_gpio_config[BS335_GPIO_NUM_PORTS][U300_GPIO_PINS_PER_PORT] = {
206 /* Port 0, pins 0-7 */
207 {
208 U300_FLOATING_INPUT,
209 U300_OUTPUT_HIGH,
210 U300_FLOATING_INPUT,
211 U300_OUTPUT_LOW,
212 U300_OUTPUT_LOW,
213 U300_OUTPUT_LOW,
214 U300_OUTPUT_LOW,
215 U300_OUTPUT_LOW,
216 },
217 /* Port 1, pins 0-7 */
218 {
219 U300_OUTPUT_LOW,
220 U300_OUTPUT_LOW,
221 U300_OUTPUT_LOW,
222 U300_PULL_UP_INPUT,
223 U300_FLOATING_INPUT,
224 U300_OUTPUT_HIGH,
225 U300_OUTPUT_LOW,
226 U300_OUTPUT_LOW,
227 },
228 /* Port 2, pins 0-7 */
229 {
230 U300_FLOATING_INPUT,
231 U300_FLOATING_INPUT,
232 U300_FLOATING_INPUT,
233 U300_FLOATING_INPUT,
234 U300_OUTPUT_LOW,
235 U300_PULL_UP_INPUT,
236 U300_OUTPUT_LOW,
237 U300_PULL_UP_INPUT,
238 },
239 /* Port 3, pins 0-7 */
240 {
241 U300_PULL_UP_INPUT,
242 U300_OUTPUT_LOW,
243 U300_FLOATING_INPUT,
244 U300_FLOATING_INPUT,
245 U300_FLOATING_INPUT,
246 U300_FLOATING_INPUT,
247 U300_FLOATING_INPUT,
248 U300_FLOATING_INPUT,
249 },
250 /* Port 4, pins 0-7 */
251 {
252 U300_FLOATING_INPUT,
253 U300_FLOATING_INPUT,
254 U300_FLOATING_INPUT,
255 U300_FLOATING_INPUT,
256 U300_FLOATING_INPUT,
257 U300_FLOATING_INPUT,
258 U300_FLOATING_INPUT,
259 U300_FLOATING_INPUT,
260 },
261 /* Port 5, pins 0-7 */
262 {
263 U300_FLOATING_INPUT,
264 U300_FLOATING_INPUT,
265 U300_FLOATING_INPUT,
266 U300_FLOATING_INPUT,
267 U300_FLOATING_INPUT,
268 U300_FLOATING_INPUT,
269 U300_FLOATING_INPUT,
270 U300_FLOATING_INPUT,
271 },
272 /* Port 6, pind 0-7 */
273 {
274 U300_FLOATING_INPUT,
275 U300_FLOATING_INPUT,
276 U300_FLOATING_INPUT,
277 U300_FLOATING_INPUT,
278 U300_FLOATING_INPUT,
279 U300_FLOATING_INPUT,
280 U300_FLOATING_INPUT,
281 U300_FLOATING_INPUT,
282 }
283 };
284
285 static const struct __initdata u300_gpio_confdata
286 bs365_gpio_config[BS365_GPIO_NUM_PORTS][U300_GPIO_PINS_PER_PORT] = {
287 /* Port 0, pins 0-7 */
288 {
289 U300_FLOATING_INPUT,
290 U300_OUTPUT_LOW,
291 U300_FLOATING_INPUT,
292 U300_OUTPUT_LOW,
293 U300_OUTPUT_LOW,
294 U300_OUTPUT_LOW,
295 U300_PULL_UP_INPUT,
296 U300_FLOATING_INPUT,
297 },
298 /* Port 1, pins 0-7 */
299 {
300 U300_OUTPUT_LOW,
301 U300_FLOATING_INPUT,
302 U300_OUTPUT_LOW,
303 U300_FLOATING_INPUT,
304 U300_FLOATING_INPUT,
305 U300_OUTPUT_HIGH,
306 U300_OUTPUT_LOW,
307 U300_OUTPUT_LOW,
308 },
309 /* Port 2, pins 0-7 */
310 {
311 U300_FLOATING_INPUT,
312 U300_PULL_UP_INPUT,
313 U300_OUTPUT_LOW,
314 U300_OUTPUT_LOW,
315 U300_PULL_UP_INPUT,
316 U300_PULL_UP_INPUT,
317 U300_PULL_UP_INPUT,
318 U300_PULL_UP_INPUT,
319 },
320 /* Port 3, pins 0-7 */
321 {
322 U300_PULL_UP_INPUT,
323 U300_PULL_UP_INPUT,
324 U300_PULL_UP_INPUT,
325 U300_PULL_UP_INPUT,
326 U300_PULL_UP_INPUT,
327 U300_PULL_UP_INPUT,
328 U300_PULL_UP_INPUT,
329 U300_PULL_UP_INPUT,
330 },
331 /* Port 4, pins 0-7 */
332 {
333 U300_PULL_UP_INPUT,
334 U300_PULL_UP_INPUT,
335 U300_PULL_UP_INPUT,
336 U300_PULL_UP_INPUT,
337 /* These 4 pins doesn't exist on DB3210 */
338 U300_OUTPUT_LOW,
339 U300_OUTPUT_LOW,
340 U300_OUTPUT_LOW,
341 U300_OUTPUT_LOW,
342 }
343 };
344
345 /**
346 * to_u300_gpio() - get the pointer to u300_gpio
347 * @chip: the gpio chip member of the structure u300_gpio
348 */
349 static inline struct u300_gpio *to_u300_gpio(struct gpio_chip *chip)
350 {
351 return container_of(chip, struct u300_gpio, chip);
352 }
353
354 static int u300_gpio_get(struct gpio_chip *chip, unsigned offset)
355 {
356 struct u300_gpio *gpio = to_u300_gpio(chip);
357
358 return readl(U300_PIN_REG(offset, dir)) & U300_PIN_BIT(offset);
359 }
360
361 static void u300_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
362 {
363 struct u300_gpio *gpio = to_u300_gpio(chip);
364 unsigned long flags;
365 u32 val;
366
367 local_irq_save(flags);
368
369 val = readl(U300_PIN_REG(offset, dor));
370 if (value)
371 writel(val | U300_PIN_BIT(offset), U300_PIN_REG(offset, dor));
372 else
373 writel(val & ~U300_PIN_BIT(offset), U300_PIN_REG(offset, dor));
374
375 local_irq_restore(flags);
376 }
377
378 static int u300_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
379 {
380 struct u300_gpio *gpio = to_u300_gpio(chip);
381 unsigned long flags;
382 u32 val;
383
384 local_irq_save(flags);
385 val = readl(U300_PIN_REG(offset, pcr));
386 /* Mask out this pin, note 2 bits per setting */
387 val &= ~(U300_GPIO_PXPCR_PIN_MODE_MASK << ((offset & 0x07) << 1));
388 writel(val, U300_PIN_REG(offset, pcr));
389 local_irq_restore(flags);
390 return 0;
391 }
392
393 static int u300_gpio_direction_output(struct gpio_chip *chip, unsigned offset,
394 int value)
395 {
396 struct u300_gpio *gpio = to_u300_gpio(chip);
397 unsigned long flags;
398 u32 oldmode;
399 u32 val;
400
401 local_irq_save(flags);
402 val = readl(U300_PIN_REG(offset, pcr));
403 /*
404 * Drive mode must be set by the special mode set function, set
405 * push/pull mode by default if no mode has been selected.
406 */
407 oldmode = val & (U300_GPIO_PXPCR_PIN_MODE_MASK <<
408 ((offset & 0x07) << 1));
409 /* mode = 0 means input, else some mode is already set */
410 if (oldmode == 0) {
411 val &= ~(U300_GPIO_PXPCR_PIN_MODE_MASK <<
412 ((offset & 0x07) << 1));
413 val |= (U300_GPIO_PXPCR_PIN_MODE_OUTPUT_PUSH_PULL
414 << ((offset & 0x07) << 1));
415 writel(val, U300_PIN_REG(offset, pcr));
416 }
417 u300_gpio_set(chip, offset, value);
418 local_irq_restore(flags);
419 return 0;
420 }
421
422 static int u300_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
423 {
424 struct u300_gpio *gpio = to_u300_gpio(chip);
425 int retirq = gpio->irq_base + offset;
426
427 dev_dbg(gpio->dev, "request IRQ for GPIO %d, return %d\n", offset,
428 retirq);
429 return retirq;
430 }
431
432 static int u300_gpio_config(struct gpio_chip *chip, unsigned offset,
433 u16 param, unsigned long *data)
434 {
435 struct u300_gpio *gpio = to_u300_gpio(chip);
436 unsigned long flags;
437 u32 val;
438
439 local_irq_save(flags);
440 switch (param) {
441 case GPIO_U300_CONFIG_BIAS_UNKNOWN:
442 case GPIO_U300_CONFIG_BIAS_FLOAT:
443 val = readl(U300_PIN_REG(offset, per));
444 writel(val | U300_PIN_BIT(offset), U300_PIN_REG(offset, per));
445 break;
446 case GPIO_U300_CONFIG_BIAS_PULL_UP:
447 val = readl(U300_PIN_REG(offset, per));
448 writel(val & ~U300_PIN_BIT(offset), U300_PIN_REG(offset, per));
449 break;
450 case GPIO_U300_CONFIG_DRIVE_PUSH_PULL:
451 val = readl(U300_PIN_REG(offset, pcr));
452 val &= ~(U300_GPIO_PXPCR_PIN_MODE_MASK
453 << ((offset & 0x07) << 1));
454 val |= (U300_GPIO_PXPCR_PIN_MODE_OUTPUT_PUSH_PULL
455 << ((offset & 0x07) << 1));
456 writel(val, U300_PIN_REG(offset, pcr));
457 break;
458 case GPIO_U300_CONFIG_DRIVE_OPEN_DRAIN:
459 val = readl(U300_PIN_REG(offset, pcr));
460 val &= ~(U300_GPIO_PXPCR_PIN_MODE_MASK
461 << ((offset & 0x07) << 1));
462 val |= (U300_GPIO_PXPCR_PIN_MODE_OUTPUT_OPEN_DRAIN
463 << ((offset & 0x07) << 1));
464 writel(val, U300_PIN_REG(offset, pcr));
465 break;
466 case GPIO_U300_CONFIG_DRIVE_OPEN_SOURCE:
467 val = readl(U300_PIN_REG(offset, pcr));
468 val &= ~(U300_GPIO_PXPCR_PIN_MODE_MASK
469 << ((offset & 0x07) << 1));
470 val |= (U300_GPIO_PXPCR_PIN_MODE_OUTPUT_OPEN_SOURCE
471 << ((offset & 0x07) << 1));
472 writel(val, U300_PIN_REG(offset, pcr));
473 break;
474 default:
475 local_irq_restore(flags);
476 dev_err(gpio->dev, "illegal configuration requested\n");
477 return -EINVAL;
478 }
479 local_irq_restore(flags);
480 return 0;
481 }
482
483 static struct gpio_chip u300_gpio_chip = {
484 .label = "u300-gpio-chip",
485 .owner = THIS_MODULE,
486 .get = u300_gpio_get,
487 .set = u300_gpio_set,
488 .direction_input = u300_gpio_direction_input,
489 .direction_output = u300_gpio_direction_output,
490 .to_irq = u300_gpio_to_irq,
491 };
492
493 static void u300_toggle_trigger(struct u300_gpio *gpio, unsigned offset)
494 {
495 u32 val;
496
497 val = readl(U300_PIN_REG(offset, icr));
498 /* Set mode depending on state */
499 if (u300_gpio_get(&gpio->chip, offset)) {
500 /* High now, let's trigger on falling edge next then */
501 writel(val & ~U300_PIN_BIT(offset), U300_PIN_REG(offset, icr));
502 dev_dbg(gpio->dev, "next IRQ on falling edge on pin %d\n",
503 offset);
504 } else {
505 /* Low now, let's trigger on rising edge next then */
506 writel(val | U300_PIN_BIT(offset), U300_PIN_REG(offset, icr));
507 dev_dbg(gpio->dev, "next IRQ on rising edge on pin %d\n",
508 offset);
509 }
510 }
511
512 static int u300_gpio_irq_type(struct irq_data *d, unsigned trigger)
513 {
514 struct u300_gpio_port *port = irq_data_get_irq_chip_data(d);
515 struct u300_gpio *gpio = port->gpio;
516 int offset = d->irq - gpio->irq_base;
517 u32 val;
518
519 if ((trigger & IRQF_TRIGGER_RISING) &&
520 (trigger & IRQF_TRIGGER_FALLING)) {
521 /*
522 * The GPIO block can only trigger on falling OR rising edges,
523 * not both. So we need to toggle the mode whenever the pin
524 * goes from one state to the other with a special state flag
525 */
526 dev_dbg(gpio->dev,
527 "trigger on both rising and falling edge on pin %d\n",
528 offset);
529 port->toggle_edge_mode |= U300_PIN_BIT(offset);
530 u300_toggle_trigger(gpio, offset);
531 } else if (trigger & IRQF_TRIGGER_RISING) {
532 dev_dbg(gpio->dev, "trigger on rising edge on pin %d\n",
533 offset);
534 val = readl(U300_PIN_REG(offset, icr));
535 writel(val | U300_PIN_BIT(offset), U300_PIN_REG(offset, icr));
536 port->toggle_edge_mode &= ~U300_PIN_BIT(offset);
537 } else if (trigger & IRQF_TRIGGER_FALLING) {
538 dev_dbg(gpio->dev, "trigger on falling edge on pin %d\n",
539 offset);
540 val = readl(U300_PIN_REG(offset, icr));
541 writel(val & ~U300_PIN_BIT(offset), U300_PIN_REG(offset, icr));
542 port->toggle_edge_mode &= ~U300_PIN_BIT(offset);
543 }
544
545 return 0;
546 }
547
548 static void u300_gpio_irq_enable(struct irq_data *d)
549 {
550 struct u300_gpio_port *port = irq_data_get_irq_chip_data(d);
551 struct u300_gpio *gpio = port->gpio;
552 int offset = d->irq - gpio->irq_base;
553 u32 val;
554 unsigned long flags;
555
556 local_irq_save(flags);
557 val = readl(U300_PIN_REG(offset, ien));
558 writel(val | U300_PIN_BIT(offset), U300_PIN_REG(offset, ien));
559 local_irq_restore(flags);
560 }
561
562 static void u300_gpio_irq_disable(struct irq_data *d)
563 {
564 struct u300_gpio_port *port = irq_data_get_irq_chip_data(d);
565 struct u300_gpio *gpio = port->gpio;
566 int offset = d->irq - gpio->irq_base;
567 u32 val;
568 unsigned long flags;
569
570 local_irq_save(flags);
571 val = readl(U300_PIN_REG(offset, ien));
572 writel(val & ~U300_PIN_BIT(offset), U300_PIN_REG(offset, ien));
573 local_irq_restore(flags);
574 }
575
576 static struct irq_chip u300_gpio_irqchip = {
577 .name = "u300-gpio-irqchip",
578 .irq_enable = u300_gpio_irq_enable,
579 .irq_disable = u300_gpio_irq_disable,
580 .irq_set_type = u300_gpio_irq_type,
581
582 };
583
584 static void u300_gpio_irq_handler(unsigned irq, struct irq_desc *desc)
585 {
586 struct u300_gpio_port *port = irq_get_handler_data(irq);
587 struct u300_gpio *gpio = port->gpio;
588 int pinoffset = port->number << 3; /* get the right stride */
589 unsigned long val;
590
591 desc->irq_data.chip->irq_ack(&desc->irq_data);
592 /* Read event register */
593 val = readl(U300_PIN_REG(pinoffset, iev));
594 /* Mask relevant bits */
595 val &= 0xFFU; /* 8 bits per port */
596 /* ACK IRQ (clear event) */
597 writel(val, U300_PIN_REG(pinoffset, iev));
598
599 /* Call IRQ handler */
600 if (val != 0) {
601 int irqoffset;
602
603 for_each_set_bit(irqoffset, &val, U300_GPIO_PINS_PER_PORT) {
604 int pin_irq = gpio->irq_base + (port->number << 3)
605 + irqoffset;
606 int offset = pinoffset + irqoffset;
607
608 dev_dbg(gpio->dev, "GPIO IRQ %d on pin %d\n",
609 pin_irq, offset);
610 generic_handle_irq(pin_irq);
611 /*
612 * Triggering IRQ on both rising and falling edge
613 * needs mockery
614 */
615 if (port->toggle_edge_mode & U300_PIN_BIT(offset))
616 u300_toggle_trigger(gpio, offset);
617 }
618 }
619
620 desc->irq_data.chip->irq_unmask(&desc->irq_data);
621 }
622
623 static void __init u300_gpio_init_pin(struct u300_gpio *gpio,
624 int offset,
625 const struct u300_gpio_confdata *conf)
626 {
627 /* Set mode: input or output */
628 if (conf->output) {
629 u300_gpio_direction_output(&gpio->chip, offset, conf->outval);
630
631 /* Deactivate bias mode for output */
632 u300_gpio_config(&gpio->chip, offset,
633 GPIO_U300_CONFIG_BIAS_FLOAT,
634 NULL);
635
636 /* Set drive mode for output */
637 u300_gpio_config(&gpio->chip, offset,
638 GPIO_U300_CONFIG_DRIVE_PUSH_PULL, NULL);
639
640 dev_dbg(gpio->dev, "set up pin %d as output, value: %d\n",
641 offset, conf->outval);
642 } else {
643 u300_gpio_direction_input(&gpio->chip, offset);
644
645 /* Always set output low on input pins */
646 u300_gpio_set(&gpio->chip, offset, 0);
647
648 /* Set bias mode for input */
649 u300_gpio_config(&gpio->chip, offset, conf->bias_mode, NULL);
650
651 dev_dbg(gpio->dev, "set up pin %d as input, bias: %04x\n",
652 offset, conf->bias_mode);
653 }
654 }
655
656 static void __init u300_gpio_init_coh901571(struct u300_gpio *gpio,
657 struct u300_gpio_platform *plat)
658 {
659 int i, j;
660
661 /* Write default config and values to all pins */
662 for (i = 0; i < plat->ports; i++) {
663 for (j = 0; j < 8; j++) {
664 const struct u300_gpio_confdata *conf;
665 int offset = (i*8) + j;
666
667 if (plat->variant == U300_GPIO_COH901571_3_BS335)
668 conf = &bs335_gpio_config[i][j];
669 else if (plat->variant == U300_GPIO_COH901571_3_BS365)
670 conf = &bs365_gpio_config[i][j];
671 else
672 break;
673
674 u300_gpio_init_pin(gpio, offset, conf);
675 }
676 }
677 }
678
679 static inline void u300_gpio_free_ports(struct u300_gpio *gpio)
680 {
681 struct u300_gpio_port *port;
682 struct list_head *p, *n;
683
684 list_for_each_safe(p, n, &gpio->port_list) {
685 port = list_entry(p, struct u300_gpio_port, node);
686 list_del(&port->node);
687 free_irq(port->irq, port);
688 kfree(port);
689 }
690 }
691
692 static int __init u300_gpio_probe(struct platform_device *pdev)
693 {
694 struct u300_gpio_platform *plat = dev_get_platdata(&pdev->dev);
695 struct u300_gpio *gpio;
696 int err = 0;
697 int portno;
698 u32 val;
699 u32 ifr;
700 int i;
701
702 gpio = kzalloc(sizeof(struct u300_gpio), GFP_KERNEL);
703 if (gpio == NULL) {
704 dev_err(&pdev->dev, "failed to allocate memory\n");
705 return -ENOMEM;
706 }
707
708 gpio->chip = u300_gpio_chip;
709 gpio->chip.ngpio = plat->ports * U300_GPIO_PINS_PER_PORT;
710 gpio->irq_base = plat->gpio_irq_base;
711 gpio->chip.dev = &pdev->dev;
712 gpio->chip.base = plat->gpio_base;
713 gpio->dev = &pdev->dev;
714
715 /* Get GPIO clock */
716 gpio->clk = clk_get(gpio->dev, NULL);
717 if (IS_ERR(gpio->clk)) {
718 err = PTR_ERR(gpio->clk);
719 dev_err(gpio->dev, "could not get GPIO clock\n");
720 goto err_no_clk;
721 }
722 err = clk_enable(gpio->clk);
723 if (err) {
724 dev_err(gpio->dev, "could not enable GPIO clock\n");
725 goto err_no_clk_enable;
726 }
727
728 gpio->memres = platform_get_resource(pdev, IORESOURCE_MEM, 0);
729 if (!gpio->memres) {
730 dev_err(gpio->dev, "could not get GPIO memory resource\n");
731 err = -ENODEV;
732 goto err_no_resource;
733 }
734
735 if (!request_mem_region(gpio->memres->start,
736 resource_size(gpio->memres),
737 "GPIO Controller")) {
738 err = -ENODEV;
739 goto err_no_ioregion;
740 }
741
742 gpio->base = ioremap(gpio->memres->start, resource_size(gpio->memres));
743 if (!gpio->base) {
744 err = -ENOMEM;
745 goto err_no_ioremap;
746 }
747
748 if (plat->variant == U300_GPIO_COH901335) {
749 dev_info(gpio->dev,
750 "initializing GPIO Controller COH 901 335\n");
751 gpio->stride = U300_335_PORT_STRIDE;
752 gpio->pcr = U300_335_PXPCR;
753 gpio->dor = U300_335_PXPDOR;
754 gpio->dir = U300_335_PXPDIR;
755 gpio->per = U300_335_PXPER;
756 gpio->icr = U300_335_PXICR;
757 gpio->ien = U300_335_PXIEN;
758 gpio->iev = U300_335_PXIEV;
759 ifr = U300_335_PXIFR;
760
761 /* Turn on the GPIO block */
762 writel(U300_335_CR_BLOCK_CLOCK_ENABLE,
763 gpio->base + U300_335_CR);
764 } else if (plat->variant == U300_GPIO_COH901571_3_BS335 ||
765 plat->variant == U300_GPIO_COH901571_3_BS365) {
766 dev_info(gpio->dev,
767 "initializing GPIO Controller COH 901 571/3\n");
768 gpio->stride = U300_571_PORT_STRIDE;
769 gpio->pcr = U300_571_PXPCR;
770 gpio->dor = U300_571_PXPDOR;
771 gpio->dir = U300_571_PXPDIR;
772 gpio->per = U300_571_PXPER;
773 gpio->icr = U300_571_PXICR;
774 gpio->ien = U300_571_PXIEN;
775 gpio->iev = U300_571_PXIEV;
776 ifr = U300_571_PXIFR;
777
778 val = readl(gpio->base + U300_571_CR);
779 dev_info(gpio->dev, "COH901571/3 block version: %d, " \
780 "number of cores: %d totalling %d pins\n",
781 ((val & 0x000001FC) >> 2),
782 ((val & 0x0000FE00) >> 9),
783 ((val & 0x0000FE00) >> 9) * 8);
784 writel(U300_571_CR_BLOCK_CLKRQ_ENABLE,
785 gpio->base + U300_571_CR);
786 u300_gpio_init_coh901571(gpio, plat);
787 } else {
788 dev_err(gpio->dev, "unknown block variant\n");
789 err = -ENODEV;
790 goto err_unknown_variant;
791 }
792
793 /* Add each port with its IRQ separately */
794 INIT_LIST_HEAD(&gpio->port_list);
795 for (portno = 0 ; portno < plat->ports; portno++) {
796 struct u300_gpio_port *port =
797 kmalloc(sizeof(struct u300_gpio_port), GFP_KERNEL);
798
799 if (!port) {
800 dev_err(gpio->dev, "out of memory\n");
801 err = -ENOMEM;
802 goto err_no_port;
803 }
804
805 snprintf(port->name, 8, "gpio%d", portno);
806 port->number = portno;
807 port->gpio = gpio;
808
809 port->irq = platform_get_irq_byname(pdev,
810 port->name);
811
812 dev_dbg(gpio->dev, "register IRQ %d for %s\n", port->irq,
813 port->name);
814
815 irq_set_chained_handler(port->irq, u300_gpio_irq_handler);
816 irq_set_handler_data(port->irq, port);
817
818 /* For each GPIO pin set the unique IRQ handler */
819 for (i = 0; i < U300_GPIO_PINS_PER_PORT; i++) {
820 int irqno = gpio->irq_base + (portno << 3) + i;
821
822 dev_dbg(gpio->dev, "handler for IRQ %d on %s\n",
823 irqno, port->name);
824 irq_set_chip_and_handler(irqno, &u300_gpio_irqchip,
825 handle_simple_irq);
826 set_irq_flags(irqno, IRQF_VALID);
827 irq_set_chip_data(irqno, port);
828 }
829
830 /* Turns off irq force (test register) for this port */
831 writel(0x0, gpio->base + portno * gpio->stride + ifr);
832
833 list_add_tail(&port->node, &gpio->port_list);
834 }
835 dev_dbg(gpio->dev, "initialized %d GPIO ports\n", portno);
836
837 err = gpiochip_add(&gpio->chip);
838 if (err) {
839 dev_err(gpio->dev, "unable to add gpiochip: %d\n", err);
840 goto err_no_chip;
841 }
842
843 platform_set_drvdata(pdev, gpio);
844
845 return 0;
846
847 err_no_chip:
848 err_no_port:
849 u300_gpio_free_ports(gpio);
850 err_unknown_variant:
851 iounmap(gpio->base);
852 err_no_ioremap:
853 release_mem_region(gpio->memres->start, resource_size(gpio->memres));
854 err_no_ioregion:
855 err_no_resource:
856 clk_disable(gpio->clk);
857 err_no_clk_enable:
858 clk_put(gpio->clk);
859 err_no_clk:
860 kfree(gpio);
861 dev_info(&pdev->dev, "module ERROR:%d\n", err);
862 return err;
863 }
864
865 static int __exit u300_gpio_remove(struct platform_device *pdev)
866 {
867 struct u300_gpio_platform *plat = dev_get_platdata(&pdev->dev);
868 struct u300_gpio *gpio = platform_get_drvdata(pdev);
869 int err;
870
871 /* Turn off the GPIO block */
872 if (plat->variant == U300_GPIO_COH901335)
873 writel(0x00000000U, gpio->base + U300_335_CR);
874 if (plat->variant == U300_GPIO_COH901571_3_BS335 ||
875 plat->variant == U300_GPIO_COH901571_3_BS365)
876 writel(0x00000000U, gpio->base + U300_571_CR);
877
878 err = gpiochip_remove(&gpio->chip);
879 if (err < 0) {
880 dev_err(gpio->dev, "unable to remove gpiochip: %d\n", err);
881 return err;
882 }
883 u300_gpio_free_ports(gpio);
884 iounmap(gpio->base);
885 release_mem_region(gpio->memres->start,
886 resource_size(gpio->memres));
887 clk_disable(gpio->clk);
888 clk_put(gpio->clk);
889 platform_set_drvdata(pdev, NULL);
890 kfree(gpio);
891 return 0;
892 }
893
894 static struct platform_driver u300_gpio_driver = {
895 .driver = {
896 .name = "u300-gpio",
897 },
898 .remove = __exit_p(u300_gpio_remove),
899 };
900
901
902 static int __init u300_gpio_init(void)
903 {
904 return platform_driver_probe(&u300_gpio_driver, u300_gpio_probe);
905 }
906
907 static void __exit u300_gpio_exit(void)
908 {
909 platform_driver_unregister(&u300_gpio_driver);
910 }
911
912 arch_initcall(u300_gpio_init);
913 module_exit(u300_gpio_exit);
914
915 MODULE_AUTHOR("Linus Walleij <linus.walleij@stericsson.com>");
916 MODULE_DESCRIPTION("ST-Ericsson AB COH 901 335/COH 901 571/3 GPIO driver");
917 MODULE_LICENSE("GPL");
Linus' kernel tree