2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
6 * Copyright (C) 1994 Waldorf GMBH
7 * Copyright (C) 1995, 1996, 1997, 1998, 1999, 2001, 2002, 2003 Ralf Baechle
8 * Copyright (C) 1996 Paul M. Antoine
9 * Copyright (C) 1999, 2000 Silicon Graphics, Inc.
11 #ifndef _ASM_PROCESSOR_H
12 #define _ASM_PROCESSOR_H
14 #include <linux/cpumask.h>
15 #include <linux/threads.h>
17 #include <asm/cachectl.h>
19 #include <asm/cpu-info.h>
20 #include <asm/mipsregs.h>
21 #include <asm/prefetch.h>
24 * Return current * instruction pointer ("program counter").
26 #define current_text_addr() ({ __label__ _l; _l: &&_l;})
29 * System setup and hardware flags..
31 extern void (*cpu_wait
)(void);
33 extern unsigned int vced_count
, vcei_count
;
36 * MIPS does have an arch_pick_mmap_layout()
38 #define HAVE_ARCH_PICK_MMAP_LAYOUT 1
41 * A special page (the vdso) is mapped into all processes at the very
42 * top of the virtual memory space.
44 #define SPECIAL_PAGES_SIZE PAGE_SIZE
48 * User space process size: 2GB. This is hardcoded into a few places,
49 * so don't change it unless you know what you are doing.
51 #define TASK_SIZE 0x7fff8000UL
54 #define STACK_TOP_MAX TASK_SIZE
57 #define TASK_IS_32BIT_ADDR 1
63 * User space process size: 1TB. This is hardcoded into a few places,
64 * so don't change it unless you know what you are doing. TASK_SIZE
65 * is limited to 1TB by the R4000 architecture; R10000 and better can
66 * support 16TB; the architectural reserve for future expansion is
69 #define TASK_SIZE32 0x7fff8000UL
70 #define TASK_SIZE64 0x10000000000UL
71 #define TASK_SIZE (test_thread_flag(TIF_32BIT_ADDR) ? TASK_SIZE32 : TASK_SIZE64)
74 #define STACK_TOP_MAX TASK_SIZE64
78 #define TASK_SIZE_OF(tsk) \
79 (test_tsk_thread_flag(tsk, TIF_32BIT_ADDR) ? TASK_SIZE32 : TASK_SIZE64)
81 #define TASK_IS_32BIT_ADDR test_thread_flag(TIF_32BIT_ADDR)
85 #define STACK_TOP ((TASK_SIZE & PAGE_MASK) - SPECIAL_PAGES_SIZE)
88 * This decides where the kernel will search for a free chunk of vm
89 * space during mmap's.
91 #define TASK_UNMAPPED_BASE PAGE_ALIGN(TASK_SIZE / 3)
94 #define NUM_FPU_REGS 32
96 typedef __u64 fpureg_t
;
99 * It would be nice to add some more fields for emulator statistics, but there
100 * are a number of fixed offsets in offset.h and elsewhere that would have to
101 * be recalculated by hand. So the additional information will be private to
102 * the FPU emulator for now. See asm-mips/fpu_emulator.h.
105 struct mips_fpu_struct
{
106 fpureg_t fpr
[NUM_FPU_REGS
];
110 #define NUM_DSP_REGS 6
112 typedef __u32 dspreg_t
;
114 struct mips_dsp_state
{
115 dspreg_t dspr
[NUM_DSP_REGS
];
116 unsigned int dspcontrol
;
119 #define INIT_CPUMASK { \
123 struct mips3264_watch_reg_state
{
124 /* The width of watchlo is 32 in a 32 bit kernel and 64 in a
125 64 bit kernel. We use unsigned long as it has the same
127 unsigned long watchlo
[NUM_WATCH_REGS
];
128 /* Only the mask and IRW bits from watchhi. */
129 u16 watchhi
[NUM_WATCH_REGS
];
132 union mips_watch_reg_state
{
133 struct mips3264_watch_reg_state mips3264
;
136 #ifdef CONFIG_CPU_CAVIUM_OCTEON
138 struct octeon_cop2_state
{
139 /* DMFC2 rt, 0x0201 */
140 unsigned long cop2_crc_iv
;
141 /* DMFC2 rt, 0x0202 (Set with DMTC2 rt, 0x1202) */
142 unsigned long cop2_crc_length
;
143 /* DMFC2 rt, 0x0200 (set with DMTC2 rt, 0x4200) */
144 unsigned long cop2_crc_poly
;
145 /* DMFC2 rt, 0x0402; DMFC2 rt, 0x040A */
146 unsigned long cop2_llm_dat
[2];
147 /* DMFC2 rt, 0x0084 */
148 unsigned long cop2_3des_iv
;
149 /* DMFC2 rt, 0x0080; DMFC2 rt, 0x0081; DMFC2 rt, 0x0082 */
150 unsigned long cop2_3des_key
[3];
151 /* DMFC2 rt, 0x0088 (Set with DMTC2 rt, 0x0098) */
152 unsigned long cop2_3des_result
;
153 /* DMFC2 rt, 0x0111 (FIXME: Read Pass1 Errata) */
154 unsigned long cop2_aes_inp0
;
155 /* DMFC2 rt, 0x0102; DMFC2 rt, 0x0103 */
156 unsigned long cop2_aes_iv
[2];
157 /* DMFC2 rt, 0x0104; DMFC2 rt, 0x0105; DMFC2 rt, 0x0106; DMFC2
159 unsigned long cop2_aes_key
[4];
160 /* DMFC2 rt, 0x0110 */
161 unsigned long cop2_aes_keylen
;
162 /* DMFC2 rt, 0x0100; DMFC2 rt, 0x0101 */
163 unsigned long cop2_aes_result
[2];
164 /* DMFC2 rt, 0x0240; DMFC2 rt, 0x0241; DMFC2 rt, 0x0242; DMFC2
165 * rt, 0x0243; DMFC2 rt, 0x0244; DMFC2 rt, 0x0245; DMFC2 rt,
166 * 0x0246; DMFC2 rt, 0x0247; DMFC2 rt, 0x0248; DMFC2 rt,
167 * 0x0249; DMFC2 rt, 0x024A; DMFC2 rt, 0x024B; DMFC2 rt,
168 * 0x024C; DMFC2 rt, 0x024D; DMFC2 rt, 0x024E - Pass2 */
169 unsigned long cop2_hsh_datw
[15];
170 /* DMFC2 rt, 0x0250; DMFC2 rt, 0x0251; DMFC2 rt, 0x0252; DMFC2
171 * rt, 0x0253; DMFC2 rt, 0x0254; DMFC2 rt, 0x0255; DMFC2 rt,
172 * 0x0256; DMFC2 rt, 0x0257 - Pass2 */
173 unsigned long cop2_hsh_ivw
[8];
174 /* DMFC2 rt, 0x0258; DMFC2 rt, 0x0259 - Pass2 */
175 unsigned long cop2_gfm_mult
[2];
176 /* DMFC2 rt, 0x025E - Pass2 */
177 unsigned long cop2_gfm_poly
;
178 /* DMFC2 rt, 0x025A; DMFC2 rt, 0x025B - Pass2 */
179 unsigned long cop2_gfm_result
[2];
181 #define INIT_OCTEON_COP2 {0,}
183 struct octeon_cvmseg_state
{
184 unsigned long cvmseg
[CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE
]
185 [cpu_dcache_line_size() / sizeof(unsigned long)];
194 #define ARCH_MIN_TASKALIGN 8
199 * If you change thread_struct remember to change the #defines below too!
201 struct thread_struct
{
202 /* Saved main processor registers. */
204 unsigned long reg17
, reg18
, reg19
, reg20
, reg21
, reg22
, reg23
;
205 unsigned long reg29
, reg30
, reg31
;
207 /* Saved cp0 stuff. */
208 unsigned long cp0_status
;
210 /* Saved fpu/fpu emulator stuff. */
211 struct mips_fpu_struct fpu
;
212 #ifdef CONFIG_MIPS_MT_FPAFF
213 /* Emulated instruction count */
214 unsigned long emulated_fp
;
215 /* Saved per-thread scheduler affinity mask */
216 cpumask_t user_cpus_allowed
;
217 #endif /* CONFIG_MIPS_MT_FPAFF */
219 /* Saved state of the DSP ASE, if available. */
220 struct mips_dsp_state dsp
;
222 /* Saved watch register state, if available. */
223 union mips_watch_reg_state watch
;
225 /* Other stuff associated with the thread. */
226 unsigned long cp0_badvaddr
; /* Last user fault */
227 unsigned long cp0_baduaddr
; /* Last kernel fault accessing USEG */
228 unsigned long error_code
;
229 unsigned long irix_trampoline
; /* Wheee... */
230 unsigned long irix_oldctx
;
231 #ifdef CONFIG_CPU_CAVIUM_OCTEON
232 struct octeon_cop2_state cp2
__attribute__ ((__aligned__(128)));
233 struct octeon_cvmseg_state cvmseg
__attribute__ ((__aligned__(128)));
235 struct mips_abi
*abi
;
238 #ifdef CONFIG_MIPS_MT_FPAFF
241 .user_cpus_allowed = INIT_CPUMASK,
244 #endif /* CONFIG_MIPS_MT_FPAFF */
246 #ifdef CONFIG_CPU_CAVIUM_OCTEON
247 #define OCTEON_INIT \
248 .cp2 = INIT_OCTEON_COP2,
251 #endif /* CONFIG_CPU_CAVIUM_OCTEON */
253 #define INIT_THREAD { \
255 * Saved main processor registers \
273 * Saved FPU/FPU emulator stuff \
280 * FPU affinity state (null if not FPAFF) \
291 * saved watch register stuff \
293 .watch = {{{0,},},}, \
295 * Other stuff associated with the process \
300 .irix_trampoline = 0, \
303 * Cavium Octeon specifics (null if not Octeon) \
310 /* Free all resources held by a thread. */
311 #define release_thread(thread) do { } while(0)
313 /* Prepare to copy thread state - unlazy all lazy status */
314 #define prepare_to_copy(tsk) do { } while (0)
316 extern long kernel_thread(int (*fn
)(void *), void * arg
, unsigned long flags
);
318 extern unsigned long thread_saved_pc(struct task_struct
*tsk
);
321 * Do necessary setup to start up a newly executed thread.
323 extern void start_thread(struct pt_regs
* regs
, unsigned long pc
, unsigned long sp
);
325 unsigned long get_wchan(struct task_struct
*p
);
327 #define __KSTK_TOS(tsk) ((unsigned long)task_stack_page(tsk) + \
328 THREAD_SIZE - 32 - sizeof(struct pt_regs))
329 #define task_pt_regs(tsk) ((struct pt_regs *)__KSTK_TOS(tsk))
330 #define KSTK_EIP(tsk) (task_pt_regs(tsk)->cp0_epc)
331 #define KSTK_ESP(tsk) (task_pt_regs(tsk)->regs[29])
332 #define KSTK_STATUS(tsk) (task_pt_regs(tsk)->cp0_status)
334 #define cpu_relax() barrier()
337 * Return_address is a replacement for __builtin_return_address(count)
338 * which on certain architectures cannot reasonably be implemented in GCC
339 * (MIPS, Alpha) or is unusable with -fomit-frame-pointer (i386).
340 * Note that __builtin_return_address(x>=1) is forbidden because GCC
341 * aborts compilation on some CPUs. It's simply not possible to unwind
342 * some CPU's stackframes.
344 * __builtin_return_address works only for non-leaf functions. We avoid the
345 * overhead of a function call by forcing the compiler to save the return
346 * address register on the stack.
348 #define return_address() ({__asm__ __volatile__("":::"$31");__builtin_return_address(0);})
350 #ifdef CONFIG_CPU_HAS_PREFETCH
352 #define ARCH_HAS_PREFETCH
353 #define prefetch(x) __builtin_prefetch((x), 0, 1)
355 #define ARCH_HAS_PREFETCHW
356 #define prefetchw(x) __builtin_prefetch((x), 1, 1)
359 * See Documentation/scheduler/sched-arch.txt; prevents deadlock on SMP
362 #define __ARCH_WANT_UNLOCKED_CTXSW
366 #endif /* _ASM_PROCESSOR_H */