5 * This is the generic MTD driver for NAND flash devices. It should be
6 * capable of working with almost all NAND chips currently available.
7 * Basic support for AG-AND chips is provided.
9 * Additional technical information is available on
10 * http://www.linux-mtd.infradead.org/doc/nand.html
12 * Copyright (C) 2000 Steven J. Hill (sjhill@realitydiluted.com)
13 * 2002-2006 Thomas Gleixner (tglx@linutronix.de)
16 * David Woodhouse for adding multichip support
18 * Aleph One Ltd. and Toby Churchill Ltd. for supporting the
19 * rework for 2K page size chips
22 * Enable cached programming for 2k page size chips
23 * Check, if mtd->ecctype should be set to MTD_ECC_HW
24 * if we have HW ECC support.
25 * The AG-AND chips have nice features for speed improvement,
26 * which are not supported yet. Read / program 4 pages in one go.
27 * BBT table is not serialized, has to be fixed
29 * This program is free software; you can redistribute it and/or modify
30 * it under the terms of the GNU General Public License version 2 as
31 * published by the Free Software Foundation.
35 #include <linux/module.h>
36 #include <linux/delay.h>
37 #include <linux/errno.h>
38 #include <linux/err.h>
39 #include <linux/sched.h>
40 #include <linux/slab.h>
41 #include <linux/types.h>
42 #include <linux/mtd/mtd.h>
43 #include <linux/mtd/nand.h>
44 #include <linux/mtd/nand_ecc.h>
45 #include <linux/mtd/nand_bch.h>
46 #include <linux/interrupt.h>
47 #include <linux/bitops.h>
48 #include <linux/leds.h>
50 #include <linux/mtd/partitions.h>
52 /* Define default oob placement schemes for large and small page devices */
53 static struct nand_ecclayout nand_oob_8
= {
63 static struct nand_ecclayout nand_oob_16
= {
65 .eccpos
= {0, 1, 2, 3, 6, 7},
71 static struct nand_ecclayout nand_oob_64
= {
74 40, 41, 42, 43, 44, 45, 46, 47,
75 48, 49, 50, 51, 52, 53, 54, 55,
76 56, 57, 58, 59, 60, 61, 62, 63},
82 static struct nand_ecclayout nand_oob_128
= {
85 80, 81, 82, 83, 84, 85, 86, 87,
86 88, 89, 90, 91, 92, 93, 94, 95,
87 96, 97, 98, 99, 100, 101, 102, 103,
88 104, 105, 106, 107, 108, 109, 110, 111,
89 112, 113, 114, 115, 116, 117, 118, 119,
90 120, 121, 122, 123, 124, 125, 126, 127},
96 static int nand_get_device(struct mtd_info
*mtd
, int new_state
);
98 static int nand_do_write_oob(struct mtd_info
*mtd
, loff_t to
,
99 struct mtd_oob_ops
*ops
);
102 * For devices which display every fart in the system on a separate LED. Is
103 * compiled away when LED support is disabled.
105 DEFINE_LED_TRIGGER(nand_led_trigger
);
107 static int check_offs_len(struct mtd_info
*mtd
,
108 loff_t ofs
, uint64_t len
)
110 struct nand_chip
*chip
= mtd
->priv
;
113 /* Start address must align on block boundary */
114 if (ofs
& ((1 << chip
->phys_erase_shift
) - 1)) {
115 pr_debug("%s: unaligned address\n", __func__
);
119 /* Length must align on block boundary */
120 if (len
& ((1 << chip
->phys_erase_shift
) - 1)) {
121 pr_debug("%s: length not block aligned\n", __func__
);
129 * nand_release_device - [GENERIC] release chip
130 * @mtd: MTD device structure
132 * Release chip lock and wake up anyone waiting on the device.
134 static void nand_release_device(struct mtd_info
*mtd
)
136 struct nand_chip
*chip
= mtd
->priv
;
138 /* Release the controller and the chip */
139 spin_lock(&chip
->controller
->lock
);
140 chip
->controller
->active
= NULL
;
141 chip
->state
= FL_READY
;
142 wake_up(&chip
->controller
->wq
);
143 spin_unlock(&chip
->controller
->lock
);
147 * nand_read_byte - [DEFAULT] read one byte from the chip
148 * @mtd: MTD device structure
150 * Default read function for 8bit buswidth
152 static uint8_t nand_read_byte(struct mtd_info
*mtd
)
154 struct nand_chip
*chip
= mtd
->priv
;
155 return readb(chip
->IO_ADDR_R
);
159 * nand_read_byte16 - [DEFAULT] read one byte endianness aware from the chip
160 * nand_read_byte16 - [DEFAULT] read one byte endianness aware from the chip
161 * @mtd: MTD device structure
163 * Default read function for 16bit buswidth with endianness conversion.
166 static uint8_t nand_read_byte16(struct mtd_info
*mtd
)
168 struct nand_chip
*chip
= mtd
->priv
;
169 return (uint8_t) cpu_to_le16(readw(chip
->IO_ADDR_R
));
173 * nand_read_word - [DEFAULT] read one word from the chip
174 * @mtd: MTD device structure
176 * Default read function for 16bit buswidth without endianness conversion.
178 static u16
nand_read_word(struct mtd_info
*mtd
)
180 struct nand_chip
*chip
= mtd
->priv
;
181 return readw(chip
->IO_ADDR_R
);
185 * nand_select_chip - [DEFAULT] control CE line
186 * @mtd: MTD device structure
187 * @chipnr: chipnumber to select, -1 for deselect
189 * Default select function for 1 chip devices.
191 static void nand_select_chip(struct mtd_info
*mtd
, int chipnr
)
193 struct nand_chip
*chip
= mtd
->priv
;
197 chip
->cmd_ctrl(mtd
, NAND_CMD_NONE
, 0 | NAND_CTRL_CHANGE
);
208 * nand_write_buf - [DEFAULT] write buffer to chip
209 * @mtd: MTD device structure
211 * @len: number of bytes to write
213 * Default write function for 8bit buswidth.
215 static void nand_write_buf(struct mtd_info
*mtd
, const uint8_t *buf
, int len
)
218 struct nand_chip
*chip
= mtd
->priv
;
220 for (i
= 0; i
< len
; i
++)
221 writeb(buf
[i
], chip
->IO_ADDR_W
);
225 * nand_read_buf - [DEFAULT] read chip data into buffer
226 * @mtd: MTD device structure
227 * @buf: buffer to store date
228 * @len: number of bytes to read
230 * Default read function for 8bit buswidth.
232 static void nand_read_buf(struct mtd_info
*mtd
, uint8_t *buf
, int len
)
235 struct nand_chip
*chip
= mtd
->priv
;
237 for (i
= 0; i
< len
; i
++)
238 buf
[i
] = readb(chip
->IO_ADDR_R
);
242 * nand_write_buf16 - [DEFAULT] write buffer to chip
243 * @mtd: MTD device structure
245 * @len: number of bytes to write
247 * Default write function for 16bit buswidth.
249 static void nand_write_buf16(struct mtd_info
*mtd
, const uint8_t *buf
, int len
)
252 struct nand_chip
*chip
= mtd
->priv
;
253 u16
*p
= (u16
*) buf
;
256 for (i
= 0; i
< len
; i
++)
257 writew(p
[i
], chip
->IO_ADDR_W
);
262 * nand_read_buf16 - [DEFAULT] read chip data into buffer
263 * @mtd: MTD device structure
264 * @buf: buffer to store date
265 * @len: number of bytes to read
267 * Default read function for 16bit buswidth.
269 static void nand_read_buf16(struct mtd_info
*mtd
, uint8_t *buf
, int len
)
272 struct nand_chip
*chip
= mtd
->priv
;
273 u16
*p
= (u16
*) buf
;
276 for (i
= 0; i
< len
; i
++)
277 p
[i
] = readw(chip
->IO_ADDR_R
);
281 * nand_block_bad - [DEFAULT] Read bad block marker from the chip
282 * @mtd: MTD device structure
283 * @ofs: offset from device start
284 * @getchip: 0, if the chip is already selected
286 * Check, if the block is bad.
288 static int nand_block_bad(struct mtd_info
*mtd
, loff_t ofs
, int getchip
)
290 int page
, chipnr
, res
= 0, i
= 0;
291 struct nand_chip
*chip
= mtd
->priv
;
294 if (chip
->bbt_options
& NAND_BBT_SCANLASTPAGE
)
295 ofs
+= mtd
->erasesize
- mtd
->writesize
;
297 page
= (int)(ofs
>> chip
->page_shift
) & chip
->pagemask
;
300 chipnr
= (int)(ofs
>> chip
->chip_shift
);
302 nand_get_device(mtd
, FL_READING
);
304 /* Select the NAND device */
305 chip
->select_chip(mtd
, chipnr
);
309 if (chip
->options
& NAND_BUSWIDTH_16
) {
310 chip
->cmdfunc(mtd
, NAND_CMD_READOOB
,
311 chip
->badblockpos
& 0xFE, page
);
312 bad
= cpu_to_le16(chip
->read_word(mtd
));
313 if (chip
->badblockpos
& 0x1)
318 chip
->cmdfunc(mtd
, NAND_CMD_READOOB
, chip
->badblockpos
,
320 bad
= chip
->read_byte(mtd
);
323 if (likely(chip
->badblockbits
== 8))
326 res
= hweight8(bad
) < chip
->badblockbits
;
327 ofs
+= mtd
->writesize
;
328 page
= (int)(ofs
>> chip
->page_shift
) & chip
->pagemask
;
330 } while (!res
&& i
< 2 && (chip
->bbt_options
& NAND_BBT_SCAN2NDPAGE
));
333 chip
->select_chip(mtd
, -1);
334 nand_release_device(mtd
);
341 * nand_default_block_markbad - [DEFAULT] mark a block bad
342 * @mtd: MTD device structure
343 * @ofs: offset from device start
345 * This is the default implementation, which can be overridden by a hardware
346 * specific driver. We try operations in the following order, according to our
347 * bbt_options (NAND_BBT_NO_OOB_BBM and NAND_BBT_USE_FLASH):
348 * (1) erase the affected block, to allow OOB marker to be written cleanly
349 * (2) update in-memory BBT
350 * (3) write bad block marker to OOB area of affected block
351 * (4) update flash-based BBT
352 * Note that we retain the first error encountered in (3) or (4), finish the
353 * procedures, and dump the error in the end.
355 static int nand_default_block_markbad(struct mtd_info
*mtd
, loff_t ofs
)
357 struct nand_chip
*chip
= mtd
->priv
;
358 uint8_t buf
[2] = { 0, 0 };
359 int block
, res
, ret
= 0, i
= 0;
360 int write_oob
= !(chip
->bbt_options
& NAND_BBT_NO_OOB_BBM
);
363 struct erase_info einfo
;
365 /* Attempt erase before marking OOB */
366 memset(&einfo
, 0, sizeof(einfo
));
369 einfo
.len
= 1 << chip
->phys_erase_shift
;
370 nand_erase_nand(mtd
, &einfo
, 0);
373 /* Get block number */
374 block
= (int)(ofs
>> chip
->bbt_erase_shift
);
375 /* Mark block bad in memory-based BBT */
377 chip
->bbt
[block
>> 2] |= 0x01 << ((block
& 0x03) << 1);
379 /* Write bad block marker to OOB */
381 struct mtd_oob_ops ops
;
384 nand_get_device(mtd
, FL_WRITING
);
388 ops
.ooboffs
= chip
->badblockpos
;
389 if (chip
->options
& NAND_BUSWIDTH_16
) {
390 ops
.ooboffs
&= ~0x01;
391 ops
.len
= ops
.ooblen
= 2;
393 ops
.len
= ops
.ooblen
= 1;
395 ops
.mode
= MTD_OPS_PLACE_OOB
;
397 /* Write to first/last page(s) if necessary */
398 if (chip
->bbt_options
& NAND_BBT_SCANLASTPAGE
)
399 wr_ofs
+= mtd
->erasesize
- mtd
->writesize
;
401 res
= nand_do_write_oob(mtd
, wr_ofs
, &ops
);
406 wr_ofs
+= mtd
->writesize
;
407 } while ((chip
->bbt_options
& NAND_BBT_SCAN2NDPAGE
) && i
< 2);
409 nand_release_device(mtd
);
412 /* Update flash-based bad block table */
413 if (chip
->bbt_options
& NAND_BBT_USE_FLASH
) {
414 res
= nand_update_bbt(mtd
, ofs
);
420 mtd
->ecc_stats
.badblocks
++;
426 * nand_check_wp - [GENERIC] check if the chip is write protected
427 * @mtd: MTD device structure
429 * Check, if the device is write protected. The function expects, that the
430 * device is already selected.
432 static int nand_check_wp(struct mtd_info
*mtd
)
434 struct nand_chip
*chip
= mtd
->priv
;
436 /* Broken xD cards report WP despite being writable */
437 if (chip
->options
& NAND_BROKEN_XD
)
440 /* Check the WP bit */
441 chip
->cmdfunc(mtd
, NAND_CMD_STATUS
, -1, -1);
442 return (chip
->read_byte(mtd
) & NAND_STATUS_WP
) ? 0 : 1;
446 * nand_block_checkbad - [GENERIC] Check if a block is marked bad
447 * @mtd: MTD device structure
448 * @ofs: offset from device start
449 * @getchip: 0, if the chip is already selected
450 * @allowbbt: 1, if its allowed to access the bbt area
452 * Check, if the block is bad. Either by reading the bad block table or
453 * calling of the scan function.
455 static int nand_block_checkbad(struct mtd_info
*mtd
, loff_t ofs
, int getchip
,
458 struct nand_chip
*chip
= mtd
->priv
;
461 return chip
->block_bad(mtd
, ofs
, getchip
);
463 /* Return info from the table */
464 return nand_isbad_bbt(mtd
, ofs
, allowbbt
);
468 * panic_nand_wait_ready - [GENERIC] Wait for the ready pin after commands.
469 * @mtd: MTD device structure
472 * Helper function for nand_wait_ready used when needing to wait in interrupt
475 static void panic_nand_wait_ready(struct mtd_info
*mtd
, unsigned long timeo
)
477 struct nand_chip
*chip
= mtd
->priv
;
480 /* Wait for the device to get ready */
481 for (i
= 0; i
< timeo
; i
++) {
482 if (chip
->dev_ready(mtd
))
484 touch_softlockup_watchdog();
489 /* Wait for the ready pin, after a command. The timeout is caught later. */
490 void nand_wait_ready(struct mtd_info
*mtd
)
492 struct nand_chip
*chip
= mtd
->priv
;
493 unsigned long timeo
= jiffies
+ msecs_to_jiffies(20);
496 if (in_interrupt() || oops_in_progress
)
497 return panic_nand_wait_ready(mtd
, 400);
499 led_trigger_event(nand_led_trigger
, LED_FULL
);
500 /* Wait until command is processed or timeout occurs */
502 if (chip
->dev_ready(mtd
))
504 touch_softlockup_watchdog();
505 } while (time_before(jiffies
, timeo
));
506 led_trigger_event(nand_led_trigger
, LED_OFF
);
508 EXPORT_SYMBOL_GPL(nand_wait_ready
);
511 * nand_command - [DEFAULT] Send command to NAND device
512 * @mtd: MTD device structure
513 * @command: the command to be sent
514 * @column: the column address for this command, -1 if none
515 * @page_addr: the page address for this command, -1 if none
517 * Send command to NAND device. This function is used for small page devices
518 * (256/512 Bytes per page).
520 static void nand_command(struct mtd_info
*mtd
, unsigned int command
,
521 int column
, int page_addr
)
523 register struct nand_chip
*chip
= mtd
->priv
;
524 int ctrl
= NAND_CTRL_CLE
| NAND_CTRL_CHANGE
;
526 /* Write out the command to the device */
527 if (command
== NAND_CMD_SEQIN
) {
530 if (column
>= mtd
->writesize
) {
532 column
-= mtd
->writesize
;
533 readcmd
= NAND_CMD_READOOB
;
534 } else if (column
< 256) {
535 /* First 256 bytes --> READ0 */
536 readcmd
= NAND_CMD_READ0
;
539 readcmd
= NAND_CMD_READ1
;
541 chip
->cmd_ctrl(mtd
, readcmd
, ctrl
);
542 ctrl
&= ~NAND_CTRL_CHANGE
;
544 chip
->cmd_ctrl(mtd
, command
, ctrl
);
546 /* Address cycle, when necessary */
547 ctrl
= NAND_CTRL_ALE
| NAND_CTRL_CHANGE
;
548 /* Serially input address */
550 /* Adjust columns for 16 bit buswidth */
551 if (chip
->options
& NAND_BUSWIDTH_16
)
553 chip
->cmd_ctrl(mtd
, column
, ctrl
);
554 ctrl
&= ~NAND_CTRL_CHANGE
;
556 if (page_addr
!= -1) {
557 chip
->cmd_ctrl(mtd
, page_addr
, ctrl
);
558 ctrl
&= ~NAND_CTRL_CHANGE
;
559 chip
->cmd_ctrl(mtd
, page_addr
>> 8, ctrl
);
560 /* One more address cycle for devices > 32MiB */
561 if (chip
->chipsize
> (32 << 20))
562 chip
->cmd_ctrl(mtd
, page_addr
>> 16, ctrl
);
564 chip
->cmd_ctrl(mtd
, NAND_CMD_NONE
, NAND_NCE
| NAND_CTRL_CHANGE
);
567 * Program and erase have their own busy handlers status and sequential
572 case NAND_CMD_PAGEPROG
:
573 case NAND_CMD_ERASE1
:
574 case NAND_CMD_ERASE2
:
576 case NAND_CMD_STATUS
:
582 udelay(chip
->chip_delay
);
583 chip
->cmd_ctrl(mtd
, NAND_CMD_STATUS
,
584 NAND_CTRL_CLE
| NAND_CTRL_CHANGE
);
586 NAND_CMD_NONE
, NAND_NCE
| NAND_CTRL_CHANGE
);
587 while (!(chip
->read_byte(mtd
) & NAND_STATUS_READY
))
591 /* This applies to read commands */
594 * If we don't have access to the busy pin, we apply the given
597 if (!chip
->dev_ready
) {
598 udelay(chip
->chip_delay
);
603 * Apply this short delay always to ensure that we do wait tWB in
604 * any case on any machine.
608 nand_wait_ready(mtd
);
612 * nand_command_lp - [DEFAULT] Send command to NAND large page device
613 * @mtd: MTD device structure
614 * @command: the command to be sent
615 * @column: the column address for this command, -1 if none
616 * @page_addr: the page address for this command, -1 if none
618 * Send command to NAND device. This is the version for the new large page
619 * devices. We don't have the separate regions as we have in the small page
620 * devices. We must emulate NAND_CMD_READOOB to keep the code compatible.
622 static void nand_command_lp(struct mtd_info
*mtd
, unsigned int command
,
623 int column
, int page_addr
)
625 register struct nand_chip
*chip
= mtd
->priv
;
627 /* Emulate NAND_CMD_READOOB */
628 if (command
== NAND_CMD_READOOB
) {
629 column
+= mtd
->writesize
;
630 command
= NAND_CMD_READ0
;
633 /* Command latch cycle */
634 chip
->cmd_ctrl(mtd
, command
& 0xff,
635 NAND_NCE
| NAND_CLE
| NAND_CTRL_CHANGE
);
637 if (column
!= -1 || page_addr
!= -1) {
638 int ctrl
= NAND_CTRL_CHANGE
| NAND_NCE
| NAND_ALE
;
640 /* Serially input address */
642 /* Adjust columns for 16 bit buswidth */
643 if (chip
->options
& NAND_BUSWIDTH_16
)
645 chip
->cmd_ctrl(mtd
, column
, ctrl
);
646 ctrl
&= ~NAND_CTRL_CHANGE
;
647 chip
->cmd_ctrl(mtd
, column
>> 8, ctrl
);
649 if (page_addr
!= -1) {
650 chip
->cmd_ctrl(mtd
, page_addr
, ctrl
);
651 chip
->cmd_ctrl(mtd
, page_addr
>> 8,
652 NAND_NCE
| NAND_ALE
);
653 /* One more address cycle for devices > 128MiB */
654 if (chip
->chipsize
> (128 << 20))
655 chip
->cmd_ctrl(mtd
, page_addr
>> 16,
656 NAND_NCE
| NAND_ALE
);
659 chip
->cmd_ctrl(mtd
, NAND_CMD_NONE
, NAND_NCE
| NAND_CTRL_CHANGE
);
662 * Program and erase have their own busy handlers status, sequential
663 * in, and deplete1 need no delay.
667 case NAND_CMD_CACHEDPROG
:
668 case NAND_CMD_PAGEPROG
:
669 case NAND_CMD_ERASE1
:
670 case NAND_CMD_ERASE2
:
673 case NAND_CMD_STATUS
:
674 case NAND_CMD_DEPLETE1
:
677 case NAND_CMD_STATUS_ERROR
:
678 case NAND_CMD_STATUS_ERROR0
:
679 case NAND_CMD_STATUS_ERROR1
:
680 case NAND_CMD_STATUS_ERROR2
:
681 case NAND_CMD_STATUS_ERROR3
:
682 /* Read error status commands require only a short delay */
683 udelay(chip
->chip_delay
);
689 udelay(chip
->chip_delay
);
690 chip
->cmd_ctrl(mtd
, NAND_CMD_STATUS
,
691 NAND_NCE
| NAND_CLE
| NAND_CTRL_CHANGE
);
692 chip
->cmd_ctrl(mtd
, NAND_CMD_NONE
,
693 NAND_NCE
| NAND_CTRL_CHANGE
);
694 while (!(chip
->read_byte(mtd
) & NAND_STATUS_READY
))
698 case NAND_CMD_RNDOUT
:
699 /* No ready / busy check necessary */
700 chip
->cmd_ctrl(mtd
, NAND_CMD_RNDOUTSTART
,
701 NAND_NCE
| NAND_CLE
| NAND_CTRL_CHANGE
);
702 chip
->cmd_ctrl(mtd
, NAND_CMD_NONE
,
703 NAND_NCE
| NAND_CTRL_CHANGE
);
707 chip
->cmd_ctrl(mtd
, NAND_CMD_READSTART
,
708 NAND_NCE
| NAND_CLE
| NAND_CTRL_CHANGE
);
709 chip
->cmd_ctrl(mtd
, NAND_CMD_NONE
,
710 NAND_NCE
| NAND_CTRL_CHANGE
);
712 /* This applies to read commands */
715 * If we don't have access to the busy pin, we apply the given
718 if (!chip
->dev_ready
) {
719 udelay(chip
->chip_delay
);
725 * Apply this short delay always to ensure that we do wait tWB in
726 * any case on any machine.
730 nand_wait_ready(mtd
);
734 * panic_nand_get_device - [GENERIC] Get chip for selected access
735 * @chip: the nand chip descriptor
736 * @mtd: MTD device structure
737 * @new_state: the state which is requested
739 * Used when in panic, no locks are taken.
741 static void panic_nand_get_device(struct nand_chip
*chip
,
742 struct mtd_info
*mtd
, int new_state
)
744 /* Hardware controller shared among independent devices */
745 chip
->controller
->active
= chip
;
746 chip
->state
= new_state
;
750 * nand_get_device - [GENERIC] Get chip for selected access
751 * @mtd: MTD device structure
752 * @new_state: the state which is requested
754 * Get the device and lock it for exclusive access
757 nand_get_device(struct mtd_info
*mtd
, int new_state
)
759 struct nand_chip
*chip
= mtd
->priv
;
760 spinlock_t
*lock
= &chip
->controller
->lock
;
761 wait_queue_head_t
*wq
= &chip
->controller
->wq
;
762 DECLARE_WAITQUEUE(wait
, current
);
766 /* Hardware controller shared among independent devices */
767 if (!chip
->controller
->active
)
768 chip
->controller
->active
= chip
;
770 if (chip
->controller
->active
== chip
&& chip
->state
== FL_READY
) {
771 chip
->state
= new_state
;
775 if (new_state
== FL_PM_SUSPENDED
) {
776 if (chip
->controller
->active
->state
== FL_PM_SUSPENDED
) {
777 chip
->state
= FL_PM_SUSPENDED
;
782 set_current_state(TASK_UNINTERRUPTIBLE
);
783 add_wait_queue(wq
, &wait
);
786 remove_wait_queue(wq
, &wait
);
791 * panic_nand_wait - [GENERIC] wait until the command is done
792 * @mtd: MTD device structure
793 * @chip: NAND chip structure
796 * Wait for command done. This is a helper function for nand_wait used when
797 * we are in interrupt context. May happen when in panic and trying to write
798 * an oops through mtdoops.
800 static void panic_nand_wait(struct mtd_info
*mtd
, struct nand_chip
*chip
,
804 for (i
= 0; i
< timeo
; i
++) {
805 if (chip
->dev_ready
) {
806 if (chip
->dev_ready(mtd
))
809 if (chip
->read_byte(mtd
) & NAND_STATUS_READY
)
817 * nand_wait - [DEFAULT] wait until the command is done
818 * @mtd: MTD device structure
819 * @chip: NAND chip structure
821 * Wait for command done. This applies to erase and program only. Erase can
822 * take up to 400ms and program up to 20ms according to general NAND and
825 static int nand_wait(struct mtd_info
*mtd
, struct nand_chip
*chip
)
828 int status
, state
= chip
->state
;
829 unsigned long timeo
= (state
== FL_ERASING
? 400 : 20);
831 led_trigger_event(nand_led_trigger
, LED_FULL
);
834 * Apply this short delay always to ensure that we do wait tWB in any
835 * case on any machine.
839 if ((state
== FL_ERASING
) && (chip
->options
& NAND_IS_AND
))
840 chip
->cmdfunc(mtd
, NAND_CMD_STATUS_MULTI
, -1, -1);
842 chip
->cmdfunc(mtd
, NAND_CMD_STATUS
, -1, -1);
844 if (in_interrupt() || oops_in_progress
)
845 panic_nand_wait(mtd
, chip
, timeo
);
847 timeo
= jiffies
+ msecs_to_jiffies(timeo
);
848 while (time_before(jiffies
, timeo
)) {
849 if (chip
->dev_ready
) {
850 if (chip
->dev_ready(mtd
))
853 if (chip
->read_byte(mtd
) & NAND_STATUS_READY
)
859 led_trigger_event(nand_led_trigger
, LED_OFF
);
861 status
= (int)chip
->read_byte(mtd
);
862 /* This can happen if in case of timeout or buggy dev_ready */
863 WARN_ON(!(status
& NAND_STATUS_READY
));
868 * __nand_unlock - [REPLACEABLE] unlocks specified locked blocks
870 * @ofs: offset to start unlock from
871 * @len: length to unlock
872 * @invert: when = 0, unlock the range of blocks within the lower and
873 * upper boundary address
874 * when = 1, unlock the range of blocks outside the boundaries
875 * of the lower and upper boundary address
877 * Returs unlock status.
879 static int __nand_unlock(struct mtd_info
*mtd
, loff_t ofs
,
880 uint64_t len
, int invert
)
884 struct nand_chip
*chip
= mtd
->priv
;
886 /* Submit address of first page to unlock */
887 page
= ofs
>> chip
->page_shift
;
888 chip
->cmdfunc(mtd
, NAND_CMD_UNLOCK1
, -1, page
& chip
->pagemask
);
890 /* Submit address of last page to unlock */
891 page
= (ofs
+ len
) >> chip
->page_shift
;
892 chip
->cmdfunc(mtd
, NAND_CMD_UNLOCK2
, -1,
893 (page
| invert
) & chip
->pagemask
);
895 /* Call wait ready function */
896 status
= chip
->waitfunc(mtd
, chip
);
897 /* See if device thinks it succeeded */
898 if (status
& NAND_STATUS_FAIL
) {
899 pr_debug("%s: error status = 0x%08x\n",
908 * nand_unlock - [REPLACEABLE] unlocks specified locked blocks
910 * @ofs: offset to start unlock from
911 * @len: length to unlock
913 * Returns unlock status.
915 int nand_unlock(struct mtd_info
*mtd
, loff_t ofs
, uint64_t len
)
919 struct nand_chip
*chip
= mtd
->priv
;
921 pr_debug("%s: start = 0x%012llx, len = %llu\n",
922 __func__
, (unsigned long long)ofs
, len
);
924 if (check_offs_len(mtd
, ofs
, len
))
927 /* Align to last block address if size addresses end of the device */
928 if (ofs
+ len
== mtd
->size
)
929 len
-= mtd
->erasesize
;
931 nand_get_device(mtd
, FL_UNLOCKING
);
933 /* Shift to get chip number */
934 chipnr
= ofs
>> chip
->chip_shift
;
936 chip
->select_chip(mtd
, chipnr
);
938 /* Check, if it is write protected */
939 if (nand_check_wp(mtd
)) {
940 pr_debug("%s: device is write protected!\n",
946 ret
= __nand_unlock(mtd
, ofs
, len
, 0);
949 chip
->select_chip(mtd
, -1);
950 nand_release_device(mtd
);
954 EXPORT_SYMBOL(nand_unlock
);
957 * nand_lock - [REPLACEABLE] locks all blocks present in the device
959 * @ofs: offset to start unlock from
960 * @len: length to unlock
962 * This feature is not supported in many NAND parts. 'Micron' NAND parts do
963 * have this feature, but it allows only to lock all blocks, not for specified
964 * range for block. Implementing 'lock' feature by making use of 'unlock', for
967 * Returns lock status.
969 int nand_lock(struct mtd_info
*mtd
, loff_t ofs
, uint64_t len
)
972 int chipnr
, status
, page
;
973 struct nand_chip
*chip
= mtd
->priv
;
975 pr_debug("%s: start = 0x%012llx, len = %llu\n",
976 __func__
, (unsigned long long)ofs
, len
);
978 if (check_offs_len(mtd
, ofs
, len
))
981 nand_get_device(mtd
, FL_LOCKING
);
983 /* Shift to get chip number */
984 chipnr
= ofs
>> chip
->chip_shift
;
986 chip
->select_chip(mtd
, chipnr
);
988 /* Check, if it is write protected */
989 if (nand_check_wp(mtd
)) {
990 pr_debug("%s: device is write protected!\n",
992 status
= MTD_ERASE_FAILED
;
997 /* Submit address of first page to lock */
998 page
= ofs
>> chip
->page_shift
;
999 chip
->cmdfunc(mtd
, NAND_CMD_LOCK
, -1, page
& chip
->pagemask
);
1001 /* Call wait ready function */
1002 status
= chip
->waitfunc(mtd
, chip
);
1003 /* See if device thinks it succeeded */
1004 if (status
& NAND_STATUS_FAIL
) {
1005 pr_debug("%s: error status = 0x%08x\n",
1011 ret
= __nand_unlock(mtd
, ofs
, len
, 0x1);
1014 chip
->select_chip(mtd
, -1);
1015 nand_release_device(mtd
);
1019 EXPORT_SYMBOL(nand_lock
);
1022 * nand_read_page_raw - [INTERN] read raw page data without ecc
1023 * @mtd: mtd info structure
1024 * @chip: nand chip info structure
1025 * @buf: buffer to store read data
1026 * @oob_required: caller requires OOB data read to chip->oob_poi
1027 * @page: page number to read
1029 * Not for syndrome calculating ECC controllers, which use a special oob layout.
1031 static int nand_read_page_raw(struct mtd_info
*mtd
, struct nand_chip
*chip
,
1032 uint8_t *buf
, int oob_required
, int page
)
1034 chip
->read_buf(mtd
, buf
, mtd
->writesize
);
1036 chip
->read_buf(mtd
, chip
->oob_poi
, mtd
->oobsize
);
1041 * nand_read_page_raw_syndrome - [INTERN] read raw page data without ecc
1042 * @mtd: mtd info structure
1043 * @chip: nand chip info structure
1044 * @buf: buffer to store read data
1045 * @oob_required: caller requires OOB data read to chip->oob_poi
1046 * @page: page number to read
1048 * We need a special oob layout and handling even when OOB isn't used.
1050 static int nand_read_page_raw_syndrome(struct mtd_info
*mtd
,
1051 struct nand_chip
*chip
, uint8_t *buf
,
1052 int oob_required
, int page
)
1054 int eccsize
= chip
->ecc
.size
;
1055 int eccbytes
= chip
->ecc
.bytes
;
1056 uint8_t *oob
= chip
->oob_poi
;
1059 for (steps
= chip
->ecc
.steps
; steps
> 0; steps
--) {
1060 chip
->read_buf(mtd
, buf
, eccsize
);
1063 if (chip
->ecc
.prepad
) {
1064 chip
->read_buf(mtd
, oob
, chip
->ecc
.prepad
);
1065 oob
+= chip
->ecc
.prepad
;
1068 chip
->read_buf(mtd
, oob
, eccbytes
);
1071 if (chip
->ecc
.postpad
) {
1072 chip
->read_buf(mtd
, oob
, chip
->ecc
.postpad
);
1073 oob
+= chip
->ecc
.postpad
;
1077 size
= mtd
->oobsize
- (oob
- chip
->oob_poi
);
1079 chip
->read_buf(mtd
, oob
, size
);
1085 * nand_read_page_swecc - [REPLACEABLE] software ECC based page read function
1086 * @mtd: mtd info structure
1087 * @chip: nand chip info structure
1088 * @buf: buffer to store read data
1089 * @oob_required: caller requires OOB data read to chip->oob_poi
1090 * @page: page number to read
1092 static int nand_read_page_swecc(struct mtd_info
*mtd
, struct nand_chip
*chip
,
1093 uint8_t *buf
, int oob_required
, int page
)
1095 int i
, eccsize
= chip
->ecc
.size
;
1096 int eccbytes
= chip
->ecc
.bytes
;
1097 int eccsteps
= chip
->ecc
.steps
;
1099 uint8_t *ecc_calc
= chip
->buffers
->ecccalc
;
1100 uint8_t *ecc_code
= chip
->buffers
->ecccode
;
1101 uint32_t *eccpos
= chip
->ecc
.layout
->eccpos
;
1102 unsigned int max_bitflips
= 0;
1104 chip
->ecc
.read_page_raw(mtd
, chip
, buf
, 1, page
);
1106 for (i
= 0; eccsteps
; eccsteps
--, i
+= eccbytes
, p
+= eccsize
)
1107 chip
->ecc
.calculate(mtd
, p
, &ecc_calc
[i
]);
1109 for (i
= 0; i
< chip
->ecc
.total
; i
++)
1110 ecc_code
[i
] = chip
->oob_poi
[eccpos
[i
]];
1112 eccsteps
= chip
->ecc
.steps
;
1115 for (i
= 0 ; eccsteps
; eccsteps
--, i
+= eccbytes
, p
+= eccsize
) {
1118 stat
= chip
->ecc
.correct(mtd
, p
, &ecc_code
[i
], &ecc_calc
[i
]);
1120 mtd
->ecc_stats
.failed
++;
1122 mtd
->ecc_stats
.corrected
+= stat
;
1123 max_bitflips
= max_t(unsigned int, max_bitflips
, stat
);
1126 return max_bitflips
;
1130 * nand_read_subpage - [REPLACEABLE] software ECC based sub-page read function
1131 * @mtd: mtd info structure
1132 * @chip: nand chip info structure
1133 * @data_offs: offset of requested data within the page
1134 * @readlen: data length
1135 * @bufpoi: buffer to store read data
1137 static int nand_read_subpage(struct mtd_info
*mtd
, struct nand_chip
*chip
,
1138 uint32_t data_offs
, uint32_t readlen
, uint8_t *bufpoi
)
1140 int start_step
, end_step
, num_steps
;
1141 uint32_t *eccpos
= chip
->ecc
.layout
->eccpos
;
1143 int data_col_addr
, i
, gaps
= 0;
1144 int datafrag_len
, eccfrag_len
, aligned_len
, aligned_pos
;
1145 int busw
= (chip
->options
& NAND_BUSWIDTH_16
) ? 2 : 1;
1147 unsigned int max_bitflips
= 0;
1149 /* Column address within the page aligned to ECC size (256bytes) */
1150 start_step
= data_offs
/ chip
->ecc
.size
;
1151 end_step
= (data_offs
+ readlen
- 1) / chip
->ecc
.size
;
1152 num_steps
= end_step
- start_step
+ 1;
1154 /* Data size aligned to ECC ecc.size */
1155 datafrag_len
= num_steps
* chip
->ecc
.size
;
1156 eccfrag_len
= num_steps
* chip
->ecc
.bytes
;
1158 data_col_addr
= start_step
* chip
->ecc
.size
;
1159 /* If we read not a page aligned data */
1160 if (data_col_addr
!= 0)
1161 chip
->cmdfunc(mtd
, NAND_CMD_RNDOUT
, data_col_addr
, -1);
1163 p
= bufpoi
+ data_col_addr
;
1164 chip
->read_buf(mtd
, p
, datafrag_len
);
1167 for (i
= 0; i
< eccfrag_len
; i
+= chip
->ecc
.bytes
, p
+= chip
->ecc
.size
)
1168 chip
->ecc
.calculate(mtd
, p
, &chip
->buffers
->ecccalc
[i
]);
1171 * The performance is faster if we position offsets according to
1172 * ecc.pos. Let's make sure that there are no gaps in ECC positions.
1174 for (i
= 0; i
< eccfrag_len
- 1; i
++) {
1175 if (eccpos
[i
+ start_step
* chip
->ecc
.bytes
] + 1 !=
1176 eccpos
[i
+ start_step
* chip
->ecc
.bytes
+ 1]) {
1182 chip
->cmdfunc(mtd
, NAND_CMD_RNDOUT
, mtd
->writesize
, -1);
1183 chip
->read_buf(mtd
, chip
->oob_poi
, mtd
->oobsize
);
1186 * Send the command to read the particular ECC bytes take care
1187 * about buswidth alignment in read_buf.
1189 index
= start_step
* chip
->ecc
.bytes
;
1191 aligned_pos
= eccpos
[index
] & ~(busw
- 1);
1192 aligned_len
= eccfrag_len
;
1193 if (eccpos
[index
] & (busw
- 1))
1195 if (eccpos
[index
+ (num_steps
* chip
->ecc
.bytes
)] & (busw
- 1))
1198 chip
->cmdfunc(mtd
, NAND_CMD_RNDOUT
,
1199 mtd
->writesize
+ aligned_pos
, -1);
1200 chip
->read_buf(mtd
, &chip
->oob_poi
[aligned_pos
], aligned_len
);
1203 for (i
= 0; i
< eccfrag_len
; i
++)
1204 chip
->buffers
->ecccode
[i
] = chip
->oob_poi
[eccpos
[i
+ index
]];
1206 p
= bufpoi
+ data_col_addr
;
1207 for (i
= 0; i
< eccfrag_len
; i
+= chip
->ecc
.bytes
, p
+= chip
->ecc
.size
) {
1210 stat
= chip
->ecc
.correct(mtd
, p
,
1211 &chip
->buffers
->ecccode
[i
], &chip
->buffers
->ecccalc
[i
]);
1213 mtd
->ecc_stats
.failed
++;
1215 mtd
->ecc_stats
.corrected
+= stat
;
1216 max_bitflips
= max_t(unsigned int, max_bitflips
, stat
);
1219 return max_bitflips
;
1223 * nand_read_page_hwecc - [REPLACEABLE] hardware ECC based page read function
1224 * @mtd: mtd info structure
1225 * @chip: nand chip info structure
1226 * @buf: buffer to store read data
1227 * @oob_required: caller requires OOB data read to chip->oob_poi
1228 * @page: page number to read
1230 * Not for syndrome calculating ECC controllers which need a special oob layout.
1232 static int nand_read_page_hwecc(struct mtd_info
*mtd
, struct nand_chip
*chip
,
1233 uint8_t *buf
, int oob_required
, int page
)
1235 int i
, eccsize
= chip
->ecc
.size
;
1236 int eccbytes
= chip
->ecc
.bytes
;
1237 int eccsteps
= chip
->ecc
.steps
;
1239 uint8_t *ecc_calc
= chip
->buffers
->ecccalc
;
1240 uint8_t *ecc_code
= chip
->buffers
->ecccode
;
1241 uint32_t *eccpos
= chip
->ecc
.layout
->eccpos
;
1242 unsigned int max_bitflips
= 0;
1244 for (i
= 0; eccsteps
; eccsteps
--, i
+= eccbytes
, p
+= eccsize
) {
1245 chip
->ecc
.hwctl(mtd
, NAND_ECC_READ
);
1246 chip
->read_buf(mtd
, p
, eccsize
);
1247 chip
->ecc
.calculate(mtd
, p
, &ecc_calc
[i
]);
1249 chip
->read_buf(mtd
, chip
->oob_poi
, mtd
->oobsize
);
1251 for (i
= 0; i
< chip
->ecc
.total
; i
++)
1252 ecc_code
[i
] = chip
->oob_poi
[eccpos
[i
]];
1254 eccsteps
= chip
->ecc
.steps
;
1257 for (i
= 0 ; eccsteps
; eccsteps
--, i
+= eccbytes
, p
+= eccsize
) {
1260 stat
= chip
->ecc
.correct(mtd
, p
, &ecc_code
[i
], &ecc_calc
[i
]);
1262 mtd
->ecc_stats
.failed
++;
1264 mtd
->ecc_stats
.corrected
+= stat
;
1265 max_bitflips
= max_t(unsigned int, max_bitflips
, stat
);
1268 return max_bitflips
;
1272 * nand_read_page_hwecc_oob_first - [REPLACEABLE] hw ecc, read oob first
1273 * @mtd: mtd info structure
1274 * @chip: nand chip info structure
1275 * @buf: buffer to store read data
1276 * @oob_required: caller requires OOB data read to chip->oob_poi
1277 * @page: page number to read
1279 * Hardware ECC for large page chips, require OOB to be read first. For this
1280 * ECC mode, the write_page method is re-used from ECC_HW. These methods
1281 * read/write ECC from the OOB area, unlike the ECC_HW_SYNDROME support with
1282 * multiple ECC steps, follows the "infix ECC" scheme and reads/writes ECC from
1283 * the data area, by overwriting the NAND manufacturer bad block markings.
1285 static int nand_read_page_hwecc_oob_first(struct mtd_info
*mtd
,
1286 struct nand_chip
*chip
, uint8_t *buf
, int oob_required
, int page
)
1288 int i
, eccsize
= chip
->ecc
.size
;
1289 int eccbytes
= chip
->ecc
.bytes
;
1290 int eccsteps
= chip
->ecc
.steps
;
1292 uint8_t *ecc_code
= chip
->buffers
->ecccode
;
1293 uint32_t *eccpos
= chip
->ecc
.layout
->eccpos
;
1294 uint8_t *ecc_calc
= chip
->buffers
->ecccalc
;
1295 unsigned int max_bitflips
= 0;
1297 /* Read the OOB area first */
1298 chip
->cmdfunc(mtd
, NAND_CMD_READOOB
, 0, page
);
1299 chip
->read_buf(mtd
, chip
->oob_poi
, mtd
->oobsize
);
1300 chip
->cmdfunc(mtd
, NAND_CMD_READ0
, 0, page
);
1302 for (i
= 0; i
< chip
->ecc
.total
; i
++)
1303 ecc_code
[i
] = chip
->oob_poi
[eccpos
[i
]];
1305 for (i
= 0; eccsteps
; eccsteps
--, i
+= eccbytes
, p
+= eccsize
) {
1308 chip
->ecc
.hwctl(mtd
, NAND_ECC_READ
);
1309 chip
->read_buf(mtd
, p
, eccsize
);
1310 chip
->ecc
.calculate(mtd
, p
, &ecc_calc
[i
]);
1312 stat
= chip
->ecc
.correct(mtd
, p
, &ecc_code
[i
], NULL
);
1314 mtd
->ecc_stats
.failed
++;
1316 mtd
->ecc_stats
.corrected
+= stat
;
1317 max_bitflips
= max_t(unsigned int, max_bitflips
, stat
);
1320 return max_bitflips
;
1324 * nand_read_page_syndrome - [REPLACEABLE] hardware ECC syndrome based page read
1325 * @mtd: mtd info structure
1326 * @chip: nand chip info structure
1327 * @buf: buffer to store read data
1328 * @oob_required: caller requires OOB data read to chip->oob_poi
1329 * @page: page number to read
1331 * The hw generator calculates the error syndrome automatically. Therefore we
1332 * need a special oob layout and handling.
1334 static int nand_read_page_syndrome(struct mtd_info
*mtd
, struct nand_chip
*chip
,
1335 uint8_t *buf
, int oob_required
, int page
)
1337 int i
, eccsize
= chip
->ecc
.size
;
1338 int eccbytes
= chip
->ecc
.bytes
;
1339 int eccsteps
= chip
->ecc
.steps
;
1341 uint8_t *oob
= chip
->oob_poi
;
1342 unsigned int max_bitflips
= 0;
1344 for (i
= 0; eccsteps
; eccsteps
--, i
+= eccbytes
, p
+= eccsize
) {
1347 chip
->ecc
.hwctl(mtd
, NAND_ECC_READ
);
1348 chip
->read_buf(mtd
, p
, eccsize
);
1350 if (chip
->ecc
.prepad
) {
1351 chip
->read_buf(mtd
, oob
, chip
->ecc
.prepad
);
1352 oob
+= chip
->ecc
.prepad
;
1355 chip
->ecc
.hwctl(mtd
, NAND_ECC_READSYN
);
1356 chip
->read_buf(mtd
, oob
, eccbytes
);
1357 stat
= chip
->ecc
.correct(mtd
, p
, oob
, NULL
);
1360 mtd
->ecc_stats
.failed
++;
1362 mtd
->ecc_stats
.corrected
+= stat
;
1363 max_bitflips
= max_t(unsigned int, max_bitflips
, stat
);
1368 if (chip
->ecc
.postpad
) {
1369 chip
->read_buf(mtd
, oob
, chip
->ecc
.postpad
);
1370 oob
+= chip
->ecc
.postpad
;
1374 /* Calculate remaining oob bytes */
1375 i
= mtd
->oobsize
- (oob
- chip
->oob_poi
);
1377 chip
->read_buf(mtd
, oob
, i
);
1379 return max_bitflips
;
1383 * nand_transfer_oob - [INTERN] Transfer oob to client buffer
1384 * @chip: nand chip structure
1385 * @oob: oob destination address
1386 * @ops: oob ops structure
1387 * @len: size of oob to transfer
1389 static uint8_t *nand_transfer_oob(struct nand_chip
*chip
, uint8_t *oob
,
1390 struct mtd_oob_ops
*ops
, size_t len
)
1392 switch (ops
->mode
) {
1394 case MTD_OPS_PLACE_OOB
:
1396 memcpy(oob
, chip
->oob_poi
+ ops
->ooboffs
, len
);
1399 case MTD_OPS_AUTO_OOB
: {
1400 struct nand_oobfree
*free
= chip
->ecc
.layout
->oobfree
;
1401 uint32_t boffs
= 0, roffs
= ops
->ooboffs
;
1404 for (; free
->length
&& len
; free
++, len
-= bytes
) {
1405 /* Read request not from offset 0? */
1406 if (unlikely(roffs
)) {
1407 if (roffs
>= free
->length
) {
1408 roffs
-= free
->length
;
1411 boffs
= free
->offset
+ roffs
;
1412 bytes
= min_t(size_t, len
,
1413 (free
->length
- roffs
));
1416 bytes
= min_t(size_t, len
, free
->length
);
1417 boffs
= free
->offset
;
1419 memcpy(oob
, chip
->oob_poi
+ boffs
, bytes
);
1431 * nand_do_read_ops - [INTERN] Read data with ECC
1432 * @mtd: MTD device structure
1433 * @from: offset to read from
1434 * @ops: oob ops structure
1436 * Internal function. Called with chip held.
1438 static int nand_do_read_ops(struct mtd_info
*mtd
, loff_t from
,
1439 struct mtd_oob_ops
*ops
)
1441 int chipnr
, page
, realpage
, col
, bytes
, aligned
, oob_required
;
1442 struct nand_chip
*chip
= mtd
->priv
;
1443 struct mtd_ecc_stats stats
;
1445 uint32_t readlen
= ops
->len
;
1446 uint32_t oobreadlen
= ops
->ooblen
;
1447 uint32_t max_oobsize
= ops
->mode
== MTD_OPS_AUTO_OOB
?
1448 mtd
->oobavail
: mtd
->oobsize
;
1450 uint8_t *bufpoi
, *oob
, *buf
;
1451 unsigned int max_bitflips
= 0;
1453 stats
= mtd
->ecc_stats
;
1455 chipnr
= (int)(from
>> chip
->chip_shift
);
1456 chip
->select_chip(mtd
, chipnr
);
1458 realpage
= (int)(from
>> chip
->page_shift
);
1459 page
= realpage
& chip
->pagemask
;
1461 col
= (int)(from
& (mtd
->writesize
- 1));
1465 oob_required
= oob
? 1 : 0;
1468 bytes
= min(mtd
->writesize
- col
, readlen
);
1469 aligned
= (bytes
== mtd
->writesize
);
1471 /* Is the current page in the buffer? */
1472 if (realpage
!= chip
->pagebuf
|| oob
) {
1473 bufpoi
= aligned
? buf
: chip
->buffers
->databuf
;
1475 chip
->cmdfunc(mtd
, NAND_CMD_READ0
, 0x00, page
);
1478 * Now read the page into the buffer. Absent an error,
1479 * the read methods return max bitflips per ecc step.
1481 if (unlikely(ops
->mode
== MTD_OPS_RAW
))
1482 ret
= chip
->ecc
.read_page_raw(mtd
, chip
, bufpoi
,
1485 else if (!aligned
&& NAND_HAS_SUBPAGE_READ(chip
) &&
1487 ret
= chip
->ecc
.read_subpage(mtd
, chip
,
1488 col
, bytes
, bufpoi
);
1490 ret
= chip
->ecc
.read_page(mtd
, chip
, bufpoi
,
1491 oob_required
, page
);
1494 /* Invalidate page cache */
1499 max_bitflips
= max_t(unsigned int, max_bitflips
, ret
);
1501 /* Transfer not aligned data */
1503 if (!NAND_HAS_SUBPAGE_READ(chip
) && !oob
&&
1504 !(mtd
->ecc_stats
.failed
- stats
.failed
) &&
1505 (ops
->mode
!= MTD_OPS_RAW
)) {
1506 chip
->pagebuf
= realpage
;
1507 chip
->pagebuf_bitflips
= ret
;
1509 /* Invalidate page cache */
1512 memcpy(buf
, chip
->buffers
->databuf
+ col
, bytes
);
1517 if (unlikely(oob
)) {
1518 int toread
= min(oobreadlen
, max_oobsize
);
1521 oob
= nand_transfer_oob(chip
,
1523 oobreadlen
-= toread
;
1527 memcpy(buf
, chip
->buffers
->databuf
+ col
, bytes
);
1529 max_bitflips
= max_t(unsigned int, max_bitflips
,
1530 chip
->pagebuf_bitflips
);
1538 /* For subsequent reads align to page boundary */
1540 /* Increment page address */
1543 page
= realpage
& chip
->pagemask
;
1544 /* Check, if we cross a chip boundary */
1547 chip
->select_chip(mtd
, -1);
1548 chip
->select_chip(mtd
, chipnr
);
1551 chip
->select_chip(mtd
, -1);
1553 ops
->retlen
= ops
->len
- (size_t) readlen
;
1555 ops
->oobretlen
= ops
->ooblen
- oobreadlen
;
1560 if (mtd
->ecc_stats
.failed
- stats
.failed
)
1563 return max_bitflips
;
1567 * nand_read - [MTD Interface] MTD compatibility function for nand_do_read_ecc
1568 * @mtd: MTD device structure
1569 * @from: offset to read from
1570 * @len: number of bytes to read
1571 * @retlen: pointer to variable to store the number of read bytes
1572 * @buf: the databuffer to put data
1574 * Get hold of the chip and call nand_do_read.
1576 static int nand_read(struct mtd_info
*mtd
, loff_t from
, size_t len
,
1577 size_t *retlen
, uint8_t *buf
)
1579 struct mtd_oob_ops ops
;
1582 nand_get_device(mtd
, FL_READING
);
1586 ops
.mode
= MTD_OPS_PLACE_OOB
;
1587 ret
= nand_do_read_ops(mtd
, from
, &ops
);
1588 *retlen
= ops
.retlen
;
1589 nand_release_device(mtd
);
1594 * nand_read_oob_std - [REPLACEABLE] the most common OOB data read function
1595 * @mtd: mtd info structure
1596 * @chip: nand chip info structure
1597 * @page: page number to read
1599 static int nand_read_oob_std(struct mtd_info
*mtd
, struct nand_chip
*chip
,
1602 chip
->cmdfunc(mtd
, NAND_CMD_READOOB
, 0, page
);
1603 chip
->read_buf(mtd
, chip
->oob_poi
, mtd
->oobsize
);
1608 * nand_read_oob_syndrome - [REPLACEABLE] OOB data read function for HW ECC
1610 * @mtd: mtd info structure
1611 * @chip: nand chip info structure
1612 * @page: page number to read
1614 static int nand_read_oob_syndrome(struct mtd_info
*mtd
, struct nand_chip
*chip
,
1617 uint8_t *buf
= chip
->oob_poi
;
1618 int length
= mtd
->oobsize
;
1619 int chunk
= chip
->ecc
.bytes
+ chip
->ecc
.prepad
+ chip
->ecc
.postpad
;
1620 int eccsize
= chip
->ecc
.size
;
1621 uint8_t *bufpoi
= buf
;
1622 int i
, toread
, sndrnd
= 0, pos
;
1624 chip
->cmdfunc(mtd
, NAND_CMD_READ0
, chip
->ecc
.size
, page
);
1625 for (i
= 0; i
< chip
->ecc
.steps
; i
++) {
1627 pos
= eccsize
+ i
* (eccsize
+ chunk
);
1628 if (mtd
->writesize
> 512)
1629 chip
->cmdfunc(mtd
, NAND_CMD_RNDOUT
, pos
, -1);
1631 chip
->cmdfunc(mtd
, NAND_CMD_READ0
, pos
, page
);
1634 toread
= min_t(int, length
, chunk
);
1635 chip
->read_buf(mtd
, bufpoi
, toread
);
1640 chip
->read_buf(mtd
, bufpoi
, length
);
1646 * nand_write_oob_std - [REPLACEABLE] the most common OOB data write function
1647 * @mtd: mtd info structure
1648 * @chip: nand chip info structure
1649 * @page: page number to write
1651 static int nand_write_oob_std(struct mtd_info
*mtd
, struct nand_chip
*chip
,
1655 const uint8_t *buf
= chip
->oob_poi
;
1656 int length
= mtd
->oobsize
;
1658 chip
->cmdfunc(mtd
, NAND_CMD_SEQIN
, mtd
->writesize
, page
);
1659 chip
->write_buf(mtd
, buf
, length
);
1660 /* Send command to program the OOB data */
1661 chip
->cmdfunc(mtd
, NAND_CMD_PAGEPROG
, -1, -1);
1663 status
= chip
->waitfunc(mtd
, chip
);
1665 return status
& NAND_STATUS_FAIL
? -EIO
: 0;
1669 * nand_write_oob_syndrome - [REPLACEABLE] OOB data write function for HW ECC
1670 * with syndrome - only for large page flash
1671 * @mtd: mtd info structure
1672 * @chip: nand chip info structure
1673 * @page: page number to write
1675 static int nand_write_oob_syndrome(struct mtd_info
*mtd
,
1676 struct nand_chip
*chip
, int page
)
1678 int chunk
= chip
->ecc
.bytes
+ chip
->ecc
.prepad
+ chip
->ecc
.postpad
;
1679 int eccsize
= chip
->ecc
.size
, length
= mtd
->oobsize
;
1680 int i
, len
, pos
, status
= 0, sndcmd
= 0, steps
= chip
->ecc
.steps
;
1681 const uint8_t *bufpoi
= chip
->oob_poi
;
1684 * data-ecc-data-ecc ... ecc-oob
1686 * data-pad-ecc-pad-data-pad .... ecc-pad-oob
1688 if (!chip
->ecc
.prepad
&& !chip
->ecc
.postpad
) {
1689 pos
= steps
* (eccsize
+ chunk
);
1694 chip
->cmdfunc(mtd
, NAND_CMD_SEQIN
, pos
, page
);
1695 for (i
= 0; i
< steps
; i
++) {
1697 if (mtd
->writesize
<= 512) {
1698 uint32_t fill
= 0xFFFFFFFF;
1702 int num
= min_t(int, len
, 4);
1703 chip
->write_buf(mtd
, (uint8_t *)&fill
,
1708 pos
= eccsize
+ i
* (eccsize
+ chunk
);
1709 chip
->cmdfunc(mtd
, NAND_CMD_RNDIN
, pos
, -1);
1713 len
= min_t(int, length
, chunk
);
1714 chip
->write_buf(mtd
, bufpoi
, len
);
1719 chip
->write_buf(mtd
, bufpoi
, length
);
1721 chip
->cmdfunc(mtd
, NAND_CMD_PAGEPROG
, -1, -1);
1722 status
= chip
->waitfunc(mtd
, chip
);
1724 return status
& NAND_STATUS_FAIL
? -EIO
: 0;
1728 * nand_do_read_oob - [INTERN] NAND read out-of-band
1729 * @mtd: MTD device structure
1730 * @from: offset to read from
1731 * @ops: oob operations description structure
1733 * NAND read out-of-band data from the spare area.
1735 static int nand_do_read_oob(struct mtd_info
*mtd
, loff_t from
,
1736 struct mtd_oob_ops
*ops
)
1738 int page
, realpage
, chipnr
;
1739 struct nand_chip
*chip
= mtd
->priv
;
1740 struct mtd_ecc_stats stats
;
1741 int readlen
= ops
->ooblen
;
1743 uint8_t *buf
= ops
->oobbuf
;
1746 pr_debug("%s: from = 0x%08Lx, len = %i\n",
1747 __func__
, (unsigned long long)from
, readlen
);
1749 stats
= mtd
->ecc_stats
;
1751 if (ops
->mode
== MTD_OPS_AUTO_OOB
)
1752 len
= chip
->ecc
.layout
->oobavail
;
1756 if (unlikely(ops
->ooboffs
>= len
)) {
1757 pr_debug("%s: attempt to start read outside oob\n",
1762 /* Do not allow reads past end of device */
1763 if (unlikely(from
>= mtd
->size
||
1764 ops
->ooboffs
+ readlen
> ((mtd
->size
>> chip
->page_shift
) -
1765 (from
>> chip
->page_shift
)) * len
)) {
1766 pr_debug("%s: attempt to read beyond end of device\n",
1771 chipnr
= (int)(from
>> chip
->chip_shift
);
1772 chip
->select_chip(mtd
, chipnr
);
1774 /* Shift to get page */
1775 realpage
= (int)(from
>> chip
->page_shift
);
1776 page
= realpage
& chip
->pagemask
;
1779 if (ops
->mode
== MTD_OPS_RAW
)
1780 ret
= chip
->ecc
.read_oob_raw(mtd
, chip
, page
);
1782 ret
= chip
->ecc
.read_oob(mtd
, chip
, page
);
1787 len
= min(len
, readlen
);
1788 buf
= nand_transfer_oob(chip
, buf
, ops
, len
);
1794 /* Increment page address */
1797 page
= realpage
& chip
->pagemask
;
1798 /* Check, if we cross a chip boundary */
1801 chip
->select_chip(mtd
, -1);
1802 chip
->select_chip(mtd
, chipnr
);
1805 chip
->select_chip(mtd
, -1);
1807 ops
->oobretlen
= ops
->ooblen
- readlen
;
1812 if (mtd
->ecc_stats
.failed
- stats
.failed
)
1815 return mtd
->ecc_stats
.corrected
- stats
.corrected
? -EUCLEAN
: 0;
1819 * nand_read_oob - [MTD Interface] NAND read data and/or out-of-band
1820 * @mtd: MTD device structure
1821 * @from: offset to read from
1822 * @ops: oob operation description structure
1824 * NAND read data and/or out-of-band data.
1826 static int nand_read_oob(struct mtd_info
*mtd
, loff_t from
,
1827 struct mtd_oob_ops
*ops
)
1829 int ret
= -ENOTSUPP
;
1833 /* Do not allow reads past end of device */
1834 if (ops
->datbuf
&& (from
+ ops
->len
) > mtd
->size
) {
1835 pr_debug("%s: attempt to read beyond end of device\n",
1840 nand_get_device(mtd
, FL_READING
);
1842 switch (ops
->mode
) {
1843 case MTD_OPS_PLACE_OOB
:
1844 case MTD_OPS_AUTO_OOB
:
1853 ret
= nand_do_read_oob(mtd
, from
, ops
);
1855 ret
= nand_do_read_ops(mtd
, from
, ops
);
1858 nand_release_device(mtd
);
1864 * nand_write_page_raw - [INTERN] raw page write function
1865 * @mtd: mtd info structure
1866 * @chip: nand chip info structure
1868 * @oob_required: must write chip->oob_poi to OOB
1870 * Not for syndrome calculating ECC controllers, which use a special oob layout.
1872 static int nand_write_page_raw(struct mtd_info
*mtd
, struct nand_chip
*chip
,
1873 const uint8_t *buf
, int oob_required
)
1875 chip
->write_buf(mtd
, buf
, mtd
->writesize
);
1877 chip
->write_buf(mtd
, chip
->oob_poi
, mtd
->oobsize
);
1883 * nand_write_page_raw_syndrome - [INTERN] raw page write function
1884 * @mtd: mtd info structure
1885 * @chip: nand chip info structure
1887 * @oob_required: must write chip->oob_poi to OOB
1889 * We need a special oob layout and handling even when ECC isn't checked.
1891 static int nand_write_page_raw_syndrome(struct mtd_info
*mtd
,
1892 struct nand_chip
*chip
,
1893 const uint8_t *buf
, int oob_required
)
1895 int eccsize
= chip
->ecc
.size
;
1896 int eccbytes
= chip
->ecc
.bytes
;
1897 uint8_t *oob
= chip
->oob_poi
;
1900 for (steps
= chip
->ecc
.steps
; steps
> 0; steps
--) {
1901 chip
->write_buf(mtd
, buf
, eccsize
);
1904 if (chip
->ecc
.prepad
) {
1905 chip
->write_buf(mtd
, oob
, chip
->ecc
.prepad
);
1906 oob
+= chip
->ecc
.prepad
;
1909 chip
->read_buf(mtd
, oob
, eccbytes
);
1912 if (chip
->ecc
.postpad
) {
1913 chip
->write_buf(mtd
, oob
, chip
->ecc
.postpad
);
1914 oob
+= chip
->ecc
.postpad
;
1918 size
= mtd
->oobsize
- (oob
- chip
->oob_poi
);
1920 chip
->write_buf(mtd
, oob
, size
);
1925 * nand_write_page_swecc - [REPLACEABLE] software ECC based page write function
1926 * @mtd: mtd info structure
1927 * @chip: nand chip info structure
1929 * @oob_required: must write chip->oob_poi to OOB
1931 static int nand_write_page_swecc(struct mtd_info
*mtd
, struct nand_chip
*chip
,
1932 const uint8_t *buf
, int oob_required
)
1934 int i
, eccsize
= chip
->ecc
.size
;
1935 int eccbytes
= chip
->ecc
.bytes
;
1936 int eccsteps
= chip
->ecc
.steps
;
1937 uint8_t *ecc_calc
= chip
->buffers
->ecccalc
;
1938 const uint8_t *p
= buf
;
1939 uint32_t *eccpos
= chip
->ecc
.layout
->eccpos
;
1941 /* Software ECC calculation */
1942 for (i
= 0; eccsteps
; eccsteps
--, i
+= eccbytes
, p
+= eccsize
)
1943 chip
->ecc
.calculate(mtd
, p
, &ecc_calc
[i
]);
1945 for (i
= 0; i
< chip
->ecc
.total
; i
++)
1946 chip
->oob_poi
[eccpos
[i
]] = ecc_calc
[i
];
1948 return chip
->ecc
.write_page_raw(mtd
, chip
, buf
, 1);
1952 * nand_write_page_hwecc - [REPLACEABLE] hardware ECC based page write function
1953 * @mtd: mtd info structure
1954 * @chip: nand chip info structure
1956 * @oob_required: must write chip->oob_poi to OOB
1958 static int nand_write_page_hwecc(struct mtd_info
*mtd
, struct nand_chip
*chip
,
1959 const uint8_t *buf
, int oob_required
)
1961 int i
, eccsize
= chip
->ecc
.size
;
1962 int eccbytes
= chip
->ecc
.bytes
;
1963 int eccsteps
= chip
->ecc
.steps
;
1964 uint8_t *ecc_calc
= chip
->buffers
->ecccalc
;
1965 const uint8_t *p
= buf
;
1966 uint32_t *eccpos
= chip
->ecc
.layout
->eccpos
;
1968 for (i
= 0; eccsteps
; eccsteps
--, i
+= eccbytes
, p
+= eccsize
) {
1969 chip
->ecc
.hwctl(mtd
, NAND_ECC_WRITE
);
1970 chip
->write_buf(mtd
, p
, eccsize
);
1971 chip
->ecc
.calculate(mtd
, p
, &ecc_calc
[i
]);
1974 for (i
= 0; i
< chip
->ecc
.total
; i
++)
1975 chip
->oob_poi
[eccpos
[i
]] = ecc_calc
[i
];
1977 chip
->write_buf(mtd
, chip
->oob_poi
, mtd
->oobsize
);
1983 * nand_write_page_syndrome - [REPLACEABLE] hardware ECC syndrome based page write
1984 * @mtd: mtd info structure
1985 * @chip: nand chip info structure
1987 * @oob_required: must write chip->oob_poi to OOB
1989 * The hw generator calculates the error syndrome automatically. Therefore we
1990 * need a special oob layout and handling.
1992 static int nand_write_page_syndrome(struct mtd_info
*mtd
,
1993 struct nand_chip
*chip
,
1994 const uint8_t *buf
, int oob_required
)
1996 int i
, eccsize
= chip
->ecc
.size
;
1997 int eccbytes
= chip
->ecc
.bytes
;
1998 int eccsteps
= chip
->ecc
.steps
;
1999 const uint8_t *p
= buf
;
2000 uint8_t *oob
= chip
->oob_poi
;
2002 for (i
= 0; eccsteps
; eccsteps
--, i
+= eccbytes
, p
+= eccsize
) {
2004 chip
->ecc
.hwctl(mtd
, NAND_ECC_WRITE
);
2005 chip
->write_buf(mtd
, p
, eccsize
);
2007 if (chip
->ecc
.prepad
) {
2008 chip
->write_buf(mtd
, oob
, chip
->ecc
.prepad
);
2009 oob
+= chip
->ecc
.prepad
;
2012 chip
->ecc
.calculate(mtd
, p
, oob
);
2013 chip
->write_buf(mtd
, oob
, eccbytes
);
2016 if (chip
->ecc
.postpad
) {
2017 chip
->write_buf(mtd
, oob
, chip
->ecc
.postpad
);
2018 oob
+= chip
->ecc
.postpad
;
2022 /* Calculate remaining oob bytes */
2023 i
= mtd
->oobsize
- (oob
- chip
->oob_poi
);
2025 chip
->write_buf(mtd
, oob
, i
);
2031 * nand_write_page - [REPLACEABLE] write one page
2032 * @mtd: MTD device structure
2033 * @chip: NAND chip descriptor
2034 * @buf: the data to write
2035 * @oob_required: must write chip->oob_poi to OOB
2036 * @page: page number to write
2037 * @cached: cached programming
2038 * @raw: use _raw version of write_page
2040 static int nand_write_page(struct mtd_info
*mtd
, struct nand_chip
*chip
,
2041 const uint8_t *buf
, int oob_required
, int page
,
2042 int cached
, int raw
)
2046 chip
->cmdfunc(mtd
, NAND_CMD_SEQIN
, 0x00, page
);
2049 status
= chip
->ecc
.write_page_raw(mtd
, chip
, buf
, oob_required
);
2051 status
= chip
->ecc
.write_page(mtd
, chip
, buf
, oob_required
);
2057 * Cached progamming disabled for now. Not sure if it's worth the
2058 * trouble. The speed gain is not very impressive. (2.3->2.6Mib/s).
2062 if (!cached
|| !(chip
->options
& NAND_CACHEPRG
)) {
2064 chip
->cmdfunc(mtd
, NAND_CMD_PAGEPROG
, -1, -1);
2065 status
= chip
->waitfunc(mtd
, chip
);
2067 * See if operation failed and additional status checks are
2070 if ((status
& NAND_STATUS_FAIL
) && (chip
->errstat
))
2071 status
= chip
->errstat(mtd
, chip
, FL_WRITING
, status
,
2074 if (status
& NAND_STATUS_FAIL
)
2077 chip
->cmdfunc(mtd
, NAND_CMD_CACHEDPROG
, -1, -1);
2078 status
= chip
->waitfunc(mtd
, chip
);
2085 * nand_fill_oob - [INTERN] Transfer client buffer to oob
2086 * @mtd: MTD device structure
2087 * @oob: oob data buffer
2088 * @len: oob data write length
2089 * @ops: oob ops structure
2091 static uint8_t *nand_fill_oob(struct mtd_info
*mtd
, uint8_t *oob
, size_t len
,
2092 struct mtd_oob_ops
*ops
)
2094 struct nand_chip
*chip
= mtd
->priv
;
2097 * Initialise to all 0xFF, to avoid the possibility of left over OOB
2098 * data from a previous OOB read.
2100 memset(chip
->oob_poi
, 0xff, mtd
->oobsize
);
2102 switch (ops
->mode
) {
2104 case MTD_OPS_PLACE_OOB
:
2106 memcpy(chip
->oob_poi
+ ops
->ooboffs
, oob
, len
);
2109 case MTD_OPS_AUTO_OOB
: {
2110 struct nand_oobfree
*free
= chip
->ecc
.layout
->oobfree
;
2111 uint32_t boffs
= 0, woffs
= ops
->ooboffs
;
2114 for (; free
->length
&& len
; free
++, len
-= bytes
) {
2115 /* Write request not from offset 0? */
2116 if (unlikely(woffs
)) {
2117 if (woffs
>= free
->length
) {
2118 woffs
-= free
->length
;
2121 boffs
= free
->offset
+ woffs
;
2122 bytes
= min_t(size_t, len
,
2123 (free
->length
- woffs
));
2126 bytes
= min_t(size_t, len
, free
->length
);
2127 boffs
= free
->offset
;
2129 memcpy(chip
->oob_poi
+ boffs
, oob
, bytes
);
2140 #define NOTALIGNED(x) ((x & (chip->subpagesize - 1)) != 0)
2143 * nand_do_write_ops - [INTERN] NAND write with ECC
2144 * @mtd: MTD device structure
2145 * @to: offset to write to
2146 * @ops: oob operations description structure
2148 * NAND write with ECC.
2150 static int nand_do_write_ops(struct mtd_info
*mtd
, loff_t to
,
2151 struct mtd_oob_ops
*ops
)
2153 int chipnr
, realpage
, page
, blockmask
, column
;
2154 struct nand_chip
*chip
= mtd
->priv
;
2155 uint32_t writelen
= ops
->len
;
2157 uint32_t oobwritelen
= ops
->ooblen
;
2158 uint32_t oobmaxlen
= ops
->mode
== MTD_OPS_AUTO_OOB
?
2159 mtd
->oobavail
: mtd
->oobsize
;
2161 uint8_t *oob
= ops
->oobbuf
;
2162 uint8_t *buf
= ops
->datbuf
;
2164 int oob_required
= oob
? 1 : 0;
2170 /* Reject writes, which are not page aligned */
2171 if (NOTALIGNED(to
) || NOTALIGNED(ops
->len
)) {
2172 pr_notice("%s: attempt to write non page aligned data\n",
2177 column
= to
& (mtd
->writesize
- 1);
2178 subpage
= column
|| (writelen
& (mtd
->writesize
- 1));
2183 chipnr
= (int)(to
>> chip
->chip_shift
);
2184 chip
->select_chip(mtd
, chipnr
);
2186 /* Check, if it is write protected */
2187 if (nand_check_wp(mtd
)) {
2192 realpage
= (int)(to
>> chip
->page_shift
);
2193 page
= realpage
& chip
->pagemask
;
2194 blockmask
= (1 << (chip
->phys_erase_shift
- chip
->page_shift
)) - 1;
2196 /* Invalidate the page cache, when we write to the cached page */
2197 if (to
<= (chip
->pagebuf
<< chip
->page_shift
) &&
2198 (chip
->pagebuf
<< chip
->page_shift
) < (to
+ ops
->len
))
2201 /* Don't allow multipage oob writes with offset */
2202 if (oob
&& ops
->ooboffs
&& (ops
->ooboffs
+ ops
->ooblen
> oobmaxlen
)) {
2208 int bytes
= mtd
->writesize
;
2209 int cached
= writelen
> bytes
&& page
!= blockmask
;
2210 uint8_t *wbuf
= buf
;
2212 /* Partial page write? */
2213 if (unlikely(column
|| writelen
< (mtd
->writesize
- 1))) {
2215 bytes
= min_t(int, bytes
- column
, (int) writelen
);
2217 memset(chip
->buffers
->databuf
, 0xff, mtd
->writesize
);
2218 memcpy(&chip
->buffers
->databuf
[column
], buf
, bytes
);
2219 wbuf
= chip
->buffers
->databuf
;
2222 if (unlikely(oob
)) {
2223 size_t len
= min(oobwritelen
, oobmaxlen
);
2224 oob
= nand_fill_oob(mtd
, oob
, len
, ops
);
2227 /* We still need to erase leftover OOB data */
2228 memset(chip
->oob_poi
, 0xff, mtd
->oobsize
);
2231 ret
= chip
->write_page(mtd
, chip
, wbuf
, oob_required
, page
,
2232 cached
, (ops
->mode
== MTD_OPS_RAW
));
2244 page
= realpage
& chip
->pagemask
;
2245 /* Check, if we cross a chip boundary */
2248 chip
->select_chip(mtd
, -1);
2249 chip
->select_chip(mtd
, chipnr
);
2253 ops
->retlen
= ops
->len
- writelen
;
2255 ops
->oobretlen
= ops
->ooblen
;
2258 chip
->select_chip(mtd
, -1);
2263 * panic_nand_write - [MTD Interface] NAND write with ECC
2264 * @mtd: MTD device structure
2265 * @to: offset to write to
2266 * @len: number of bytes to write
2267 * @retlen: pointer to variable to store the number of written bytes
2268 * @buf: the data to write
2270 * NAND write with ECC. Used when performing writes in interrupt context, this
2271 * may for example be called by mtdoops when writing an oops while in panic.
2273 static int panic_nand_write(struct mtd_info
*mtd
, loff_t to
, size_t len
,
2274 size_t *retlen
, const uint8_t *buf
)
2276 struct nand_chip
*chip
= mtd
->priv
;
2277 struct mtd_oob_ops ops
;
2280 /* Wait for the device to get ready */
2281 panic_nand_wait(mtd
, chip
, 400);
2283 /* Grab the device */
2284 panic_nand_get_device(chip
, mtd
, FL_WRITING
);
2287 ops
.datbuf
= (uint8_t *)buf
;
2289 ops
.mode
= MTD_OPS_PLACE_OOB
;
2291 ret
= nand_do_write_ops(mtd
, to
, &ops
);
2293 *retlen
= ops
.retlen
;
2298 * nand_write - [MTD Interface] NAND write with ECC
2299 * @mtd: MTD device structure
2300 * @to: offset to write to
2301 * @len: number of bytes to write
2302 * @retlen: pointer to variable to store the number of written bytes
2303 * @buf: the data to write
2305 * NAND write with ECC.
2307 static int nand_write(struct mtd_info
*mtd
, loff_t to
, size_t len
,
2308 size_t *retlen
, const uint8_t *buf
)
2310 struct mtd_oob_ops ops
;
2313 nand_get_device(mtd
, FL_WRITING
);
2315 ops
.datbuf
= (uint8_t *)buf
;
2317 ops
.mode
= MTD_OPS_PLACE_OOB
;
2318 ret
= nand_do_write_ops(mtd
, to
, &ops
);
2319 *retlen
= ops
.retlen
;
2320 nand_release_device(mtd
);
2325 * nand_do_write_oob - [MTD Interface] NAND write out-of-band
2326 * @mtd: MTD device structure
2327 * @to: offset to write to
2328 * @ops: oob operation description structure
2330 * NAND write out-of-band.
2332 static int nand_do_write_oob(struct mtd_info
*mtd
, loff_t to
,
2333 struct mtd_oob_ops
*ops
)
2335 int chipnr
, page
, status
, len
;
2336 struct nand_chip
*chip
= mtd
->priv
;
2338 pr_debug("%s: to = 0x%08x, len = %i\n",
2339 __func__
, (unsigned int)to
, (int)ops
->ooblen
);
2341 if (ops
->mode
== MTD_OPS_AUTO_OOB
)
2342 len
= chip
->ecc
.layout
->oobavail
;
2346 /* Do not allow write past end of page */
2347 if ((ops
->ooboffs
+ ops
->ooblen
) > len
) {
2348 pr_debug("%s: attempt to write past end of page\n",
2353 if (unlikely(ops
->ooboffs
>= len
)) {
2354 pr_debug("%s: attempt to start write outside oob\n",
2359 /* Do not allow write past end of device */
2360 if (unlikely(to
>= mtd
->size
||
2361 ops
->ooboffs
+ ops
->ooblen
>
2362 ((mtd
->size
>> chip
->page_shift
) -
2363 (to
>> chip
->page_shift
)) * len
)) {
2364 pr_debug("%s: attempt to write beyond end of device\n",
2369 chipnr
= (int)(to
>> chip
->chip_shift
);
2370 chip
->select_chip(mtd
, chipnr
);
2372 /* Shift to get page */
2373 page
= (int)(to
>> chip
->page_shift
);
2376 * Reset the chip. Some chips (like the Toshiba TC5832DC found in one
2377 * of my DiskOnChip 2000 test units) will clear the whole data page too
2378 * if we don't do this. I have no clue why, but I seem to have 'fixed'
2379 * it in the doc2000 driver in August 1999. dwmw2.
2381 chip
->cmdfunc(mtd
, NAND_CMD_RESET
, -1, -1);
2383 /* Check, if it is write protected */
2384 if (nand_check_wp(mtd
)) {
2385 chip
->select_chip(mtd
, -1);
2389 /* Invalidate the page cache, if we write to the cached page */
2390 if (page
== chip
->pagebuf
)
2393 nand_fill_oob(mtd
, ops
->oobbuf
, ops
->ooblen
, ops
);
2395 if (ops
->mode
== MTD_OPS_RAW
)
2396 status
= chip
->ecc
.write_oob_raw(mtd
, chip
, page
& chip
->pagemask
);
2398 status
= chip
->ecc
.write_oob(mtd
, chip
, page
& chip
->pagemask
);
2400 chip
->select_chip(mtd
, -1);
2405 ops
->oobretlen
= ops
->ooblen
;
2411 * nand_write_oob - [MTD Interface] NAND write data and/or out-of-band
2412 * @mtd: MTD device structure
2413 * @to: offset to write to
2414 * @ops: oob operation description structure
2416 static int nand_write_oob(struct mtd_info
*mtd
, loff_t to
,
2417 struct mtd_oob_ops
*ops
)
2419 int ret
= -ENOTSUPP
;
2423 /* Do not allow writes past end of device */
2424 if (ops
->datbuf
&& (to
+ ops
->len
) > mtd
->size
) {
2425 pr_debug("%s: attempt to write beyond end of device\n",
2430 nand_get_device(mtd
, FL_WRITING
);
2432 switch (ops
->mode
) {
2433 case MTD_OPS_PLACE_OOB
:
2434 case MTD_OPS_AUTO_OOB
:
2443 ret
= nand_do_write_oob(mtd
, to
, ops
);
2445 ret
= nand_do_write_ops(mtd
, to
, ops
);
2448 nand_release_device(mtd
);
2453 * single_erase_cmd - [GENERIC] NAND standard block erase command function
2454 * @mtd: MTD device structure
2455 * @page: the page address of the block which will be erased
2457 * Standard erase command for NAND chips.
2459 static void single_erase_cmd(struct mtd_info
*mtd
, int page
)
2461 struct nand_chip
*chip
= mtd
->priv
;
2462 /* Send commands to erase a block */
2463 chip
->cmdfunc(mtd
, NAND_CMD_ERASE1
, -1, page
);
2464 chip
->cmdfunc(mtd
, NAND_CMD_ERASE2
, -1, -1);
2468 * multi_erase_cmd - [GENERIC] AND specific block erase command function
2469 * @mtd: MTD device structure
2470 * @page: the page address of the block which will be erased
2472 * AND multi block erase command function. Erase 4 consecutive blocks.
2474 static void multi_erase_cmd(struct mtd_info
*mtd
, int page
)
2476 struct nand_chip
*chip
= mtd
->priv
;
2477 /* Send commands to erase a block */
2478 chip
->cmdfunc(mtd
, NAND_CMD_ERASE1
, -1, page
++);
2479 chip
->cmdfunc(mtd
, NAND_CMD_ERASE1
, -1, page
++);
2480 chip
->cmdfunc(mtd
, NAND_CMD_ERASE1
, -1, page
++);
2481 chip
->cmdfunc(mtd
, NAND_CMD_ERASE1
, -1, page
);
2482 chip
->cmdfunc(mtd
, NAND_CMD_ERASE2
, -1, -1);
2486 * nand_erase - [MTD Interface] erase block(s)
2487 * @mtd: MTD device structure
2488 * @instr: erase instruction
2490 * Erase one ore more blocks.
2492 static int nand_erase(struct mtd_info
*mtd
, struct erase_info
*instr
)
2494 return nand_erase_nand(mtd
, instr
, 0);
2497 #define BBT_PAGE_MASK 0xffffff3f
2499 * nand_erase_nand - [INTERN] erase block(s)
2500 * @mtd: MTD device structure
2501 * @instr: erase instruction
2502 * @allowbbt: allow erasing the bbt area
2504 * Erase one ore more blocks.
2506 int nand_erase_nand(struct mtd_info
*mtd
, struct erase_info
*instr
,
2509 int page
, status
, pages_per_block
, ret
, chipnr
;
2510 struct nand_chip
*chip
= mtd
->priv
;
2511 loff_t rewrite_bbt
[NAND_MAX_CHIPS
] = {0};
2512 unsigned int bbt_masked_page
= 0xffffffff;
2515 pr_debug("%s: start = 0x%012llx, len = %llu\n",
2516 __func__
, (unsigned long long)instr
->addr
,
2517 (unsigned long long)instr
->len
);
2519 if (check_offs_len(mtd
, instr
->addr
, instr
->len
))
2522 /* Grab the lock and see if the device is available */
2523 nand_get_device(mtd
, FL_ERASING
);
2525 /* Shift to get first page */
2526 page
= (int)(instr
->addr
>> chip
->page_shift
);
2527 chipnr
= (int)(instr
->addr
>> chip
->chip_shift
);
2529 /* Calculate pages in each block */
2530 pages_per_block
= 1 << (chip
->phys_erase_shift
- chip
->page_shift
);
2532 /* Select the NAND device */
2533 chip
->select_chip(mtd
, chipnr
);
2535 /* Check, if it is write protected */
2536 if (nand_check_wp(mtd
)) {
2537 pr_debug("%s: device is write protected!\n",
2539 instr
->state
= MTD_ERASE_FAILED
;
2544 * If BBT requires refresh, set the BBT page mask to see if the BBT
2545 * should be rewritten. Otherwise the mask is set to 0xffffffff which
2546 * can not be matched. This is also done when the bbt is actually
2547 * erased to avoid recursive updates.
2549 if (chip
->options
& BBT_AUTO_REFRESH
&& !allowbbt
)
2550 bbt_masked_page
= chip
->bbt_td
->pages
[chipnr
] & BBT_PAGE_MASK
;
2552 /* Loop through the pages */
2555 instr
->state
= MTD_ERASING
;
2558 /* Check if we have a bad block, we do not erase bad blocks! */
2559 if (nand_block_checkbad(mtd
, ((loff_t
) page
) <<
2560 chip
->page_shift
, 0, allowbbt
)) {
2561 pr_warn("%s: attempt to erase a bad block at page 0x%08x\n",
2563 instr
->state
= MTD_ERASE_FAILED
;
2568 * Invalidate the page cache, if we erase the block which
2569 * contains the current cached page.
2571 if (page
<= chip
->pagebuf
&& chip
->pagebuf
<
2572 (page
+ pages_per_block
))
2575 chip
->erase_cmd(mtd
, page
& chip
->pagemask
);
2577 status
= chip
->waitfunc(mtd
, chip
);
2580 * See if operation failed and additional status checks are
2583 if ((status
& NAND_STATUS_FAIL
) && (chip
->errstat
))
2584 status
= chip
->errstat(mtd
, chip
, FL_ERASING
,
2587 /* See if block erase succeeded */
2588 if (status
& NAND_STATUS_FAIL
) {
2589 pr_debug("%s: failed erase, page 0x%08x\n",
2591 instr
->state
= MTD_ERASE_FAILED
;
2593 ((loff_t
)page
<< chip
->page_shift
);
2598 * If BBT requires refresh, set the BBT rewrite flag to the
2599 * page being erased.
2601 if (bbt_masked_page
!= 0xffffffff &&
2602 (page
& BBT_PAGE_MASK
) == bbt_masked_page
)
2603 rewrite_bbt
[chipnr
] =
2604 ((loff_t
)page
<< chip
->page_shift
);
2606 /* Increment page address and decrement length */
2607 len
-= (1 << chip
->phys_erase_shift
);
2608 page
+= pages_per_block
;
2610 /* Check, if we cross a chip boundary */
2611 if (len
&& !(page
& chip
->pagemask
)) {
2613 chip
->select_chip(mtd
, -1);
2614 chip
->select_chip(mtd
, chipnr
);
2617 * If BBT requires refresh and BBT-PERCHIP, set the BBT
2618 * page mask to see if this BBT should be rewritten.
2620 if (bbt_masked_page
!= 0xffffffff &&
2621 (chip
->bbt_td
->options
& NAND_BBT_PERCHIP
))
2622 bbt_masked_page
= chip
->bbt_td
->pages
[chipnr
] &
2626 instr
->state
= MTD_ERASE_DONE
;
2630 ret
= instr
->state
== MTD_ERASE_DONE
? 0 : -EIO
;
2632 /* Deselect and wake up anyone waiting on the device */
2633 chip
->select_chip(mtd
, -1);
2634 nand_release_device(mtd
);
2636 /* Do call back function */
2638 mtd_erase_callback(instr
);
2641 * If BBT requires refresh and erase was successful, rewrite any
2642 * selected bad block tables.
2644 if (bbt_masked_page
== 0xffffffff || ret
)
2647 for (chipnr
= 0; chipnr
< chip
->numchips
; chipnr
++) {
2648 if (!rewrite_bbt
[chipnr
])
2650 /* Update the BBT for chip */
2651 pr_debug("%s: nand_update_bbt (%d:0x%0llx 0x%0x)\n",
2652 __func__
, chipnr
, rewrite_bbt
[chipnr
],
2653 chip
->bbt_td
->pages
[chipnr
]);
2654 nand_update_bbt(mtd
, rewrite_bbt
[chipnr
]);
2657 /* Return more or less happy */
2662 * nand_sync - [MTD Interface] sync
2663 * @mtd: MTD device structure
2665 * Sync is actually a wait for chip ready function.
2667 static void nand_sync(struct mtd_info
*mtd
)
2669 pr_debug("%s: called\n", __func__
);
2671 /* Grab the lock and see if the device is available */
2672 nand_get_device(mtd
, FL_SYNCING
);
2673 /* Release it and go back */
2674 nand_release_device(mtd
);
2678 * nand_block_isbad - [MTD Interface] Check if block at offset is bad
2679 * @mtd: MTD device structure
2680 * @offs: offset relative to mtd start
2682 static int nand_block_isbad(struct mtd_info
*mtd
, loff_t offs
)
2684 return nand_block_checkbad(mtd
, offs
, 1, 0);
2688 * nand_block_markbad - [MTD Interface] Mark block at the given offset as bad
2689 * @mtd: MTD device structure
2690 * @ofs: offset relative to mtd start
2692 static int nand_block_markbad(struct mtd_info
*mtd
, loff_t ofs
)
2694 struct nand_chip
*chip
= mtd
->priv
;
2697 ret
= nand_block_isbad(mtd
, ofs
);
2699 /* If it was bad already, return success and do nothing */
2705 return chip
->block_markbad(mtd
, ofs
);
2709 * nand_onfi_set_features- [REPLACEABLE] set features for ONFI nand
2710 * @mtd: MTD device structure
2711 * @chip: nand chip info structure
2712 * @addr: feature address.
2713 * @subfeature_param: the subfeature parameters, a four bytes array.
2715 static int nand_onfi_set_features(struct mtd_info
*mtd
, struct nand_chip
*chip
,
2716 int addr
, uint8_t *subfeature_param
)
2720 if (!chip
->onfi_version
)
2723 chip
->cmdfunc(mtd
, NAND_CMD_SET_FEATURES
, addr
, -1);
2724 chip
->write_buf(mtd
, subfeature_param
, ONFI_SUBFEATURE_PARAM_LEN
);
2725 status
= chip
->waitfunc(mtd
, chip
);
2726 if (status
& NAND_STATUS_FAIL
)
2732 * nand_onfi_get_features- [REPLACEABLE] get features for ONFI nand
2733 * @mtd: MTD device structure
2734 * @chip: nand chip info structure
2735 * @addr: feature address.
2736 * @subfeature_param: the subfeature parameters, a four bytes array.
2738 static int nand_onfi_get_features(struct mtd_info
*mtd
, struct nand_chip
*chip
,
2739 int addr
, uint8_t *subfeature_param
)
2741 if (!chip
->onfi_version
)
2744 /* clear the sub feature parameters */
2745 memset(subfeature_param
, 0, ONFI_SUBFEATURE_PARAM_LEN
);
2747 chip
->cmdfunc(mtd
, NAND_CMD_GET_FEATURES
, addr
, -1);
2748 chip
->read_buf(mtd
, subfeature_param
, ONFI_SUBFEATURE_PARAM_LEN
);
2753 * nand_suspend - [MTD Interface] Suspend the NAND flash
2754 * @mtd: MTD device structure
2756 static int nand_suspend(struct mtd_info
*mtd
)
2758 return nand_get_device(mtd
, FL_PM_SUSPENDED
);
2762 * nand_resume - [MTD Interface] Resume the NAND flash
2763 * @mtd: MTD device structure
2765 static void nand_resume(struct mtd_info
*mtd
)
2767 struct nand_chip
*chip
= mtd
->priv
;
2769 if (chip
->state
== FL_PM_SUSPENDED
)
2770 nand_release_device(mtd
);
2772 pr_err("%s called for a chip which is not in suspended state\n",
2776 /* Set default functions */
2777 static void nand_set_defaults(struct nand_chip
*chip
, int busw
)
2779 /* check for proper chip_delay setup, set 20us if not */
2780 if (!chip
->chip_delay
)
2781 chip
->chip_delay
= 20;
2783 /* check, if a user supplied command function given */
2784 if (chip
->cmdfunc
== NULL
)
2785 chip
->cmdfunc
= nand_command
;
2787 /* check, if a user supplied wait function given */
2788 if (chip
->waitfunc
== NULL
)
2789 chip
->waitfunc
= nand_wait
;
2791 if (!chip
->select_chip
)
2792 chip
->select_chip
= nand_select_chip
;
2793 if (!chip
->read_byte
)
2794 chip
->read_byte
= busw
? nand_read_byte16
: nand_read_byte
;
2795 if (!chip
->read_word
)
2796 chip
->read_word
= nand_read_word
;
2797 if (!chip
->block_bad
)
2798 chip
->block_bad
= nand_block_bad
;
2799 if (!chip
->block_markbad
)
2800 chip
->block_markbad
= nand_default_block_markbad
;
2801 if (!chip
->write_buf
)
2802 chip
->write_buf
= busw
? nand_write_buf16
: nand_write_buf
;
2803 if (!chip
->read_buf
)
2804 chip
->read_buf
= busw
? nand_read_buf16
: nand_read_buf
;
2805 if (!chip
->scan_bbt
)
2806 chip
->scan_bbt
= nand_default_bbt
;
2808 if (!chip
->controller
) {
2809 chip
->controller
= &chip
->hwcontrol
;
2810 spin_lock_init(&chip
->controller
->lock
);
2811 init_waitqueue_head(&chip
->controller
->wq
);
2816 /* Sanitize ONFI strings so we can safely print them */
2817 static void sanitize_string(uint8_t *s
, size_t len
)
2821 /* Null terminate */
2824 /* Remove non printable chars */
2825 for (i
= 0; i
< len
- 1; i
++) {
2826 if (s
[i
] < ' ' || s
[i
] > 127)
2830 /* Remove trailing spaces */
2834 static u16
onfi_crc16(u16 crc
, u8
const *p
, size_t len
)
2839 for (i
= 0; i
< 8; i
++)
2840 crc
= (crc
<< 1) ^ ((crc
& 0x8000) ? 0x8005 : 0);
2847 * Check if the NAND chip is ONFI compliant, returns 1 if it is, 0 otherwise.
2849 static int nand_flash_detect_onfi(struct mtd_info
*mtd
, struct nand_chip
*chip
,
2852 struct nand_onfi_params
*p
= &chip
->onfi_params
;
2856 /* ONFI need to be probed in 8 bits mode, and 16 bits should be selected with NAND_BUSWIDTH_AUTO */
2857 if (chip
->options
& NAND_BUSWIDTH_16
) {
2858 pr_err("Trying ONFI probe in 16 bits mode, aborting !\n");
2861 /* Try ONFI for unknown chip or LP */
2862 chip
->cmdfunc(mtd
, NAND_CMD_READID
, 0x20, -1);
2863 if (chip
->read_byte(mtd
) != 'O' || chip
->read_byte(mtd
) != 'N' ||
2864 chip
->read_byte(mtd
) != 'F' || chip
->read_byte(mtd
) != 'I')
2867 chip
->cmdfunc(mtd
, NAND_CMD_PARAM
, 0, -1);
2868 for (i
= 0; i
< 3; i
++) {
2869 chip
->read_buf(mtd
, (uint8_t *)p
, sizeof(*p
));
2870 if (onfi_crc16(ONFI_CRC_BASE
, (uint8_t *)p
, 254) ==
2871 le16_to_cpu(p
->crc
)) {
2872 pr_info("ONFI param page %d valid\n", i
);
2881 val
= le16_to_cpu(p
->revision
);
2883 chip
->onfi_version
= 23;
2884 else if (val
& (1 << 4))
2885 chip
->onfi_version
= 22;
2886 else if (val
& (1 << 3))
2887 chip
->onfi_version
= 21;
2888 else if (val
& (1 << 2))
2889 chip
->onfi_version
= 20;
2890 else if (val
& (1 << 1))
2891 chip
->onfi_version
= 10;
2893 chip
->onfi_version
= 0;
2895 if (!chip
->onfi_version
) {
2896 pr_info("%s: unsupported ONFI version: %d\n", __func__
, val
);
2900 sanitize_string(p
->manufacturer
, sizeof(p
->manufacturer
));
2901 sanitize_string(p
->model
, sizeof(p
->model
));
2903 mtd
->name
= p
->model
;
2904 mtd
->writesize
= le32_to_cpu(p
->byte_per_page
);
2905 mtd
->erasesize
= le32_to_cpu(p
->pages_per_block
) * mtd
->writesize
;
2906 mtd
->oobsize
= le16_to_cpu(p
->spare_bytes_per_page
);
2907 chip
->chipsize
= le32_to_cpu(p
->blocks_per_lun
);
2908 chip
->chipsize
*= (uint64_t)mtd
->erasesize
* p
->lun_count
;
2910 if (le16_to_cpu(p
->features
) & 1)
2911 *busw
= NAND_BUSWIDTH_16
;
2913 pr_info("ONFI flash detected\n");
2918 * nand_id_has_period - Check if an ID string has a given wraparound period
2919 * @id_data: the ID string
2920 * @arrlen: the length of the @id_data array
2921 * @period: the period of repitition
2923 * Check if an ID string is repeated within a given sequence of bytes at
2924 * specific repetition interval period (e.g., {0x20,0x01,0x7F,0x20} has a
2925 * period of 3). This is a helper function for nand_id_len(). Returns non-zero
2926 * if the repetition has a period of @period; otherwise, returns zero.
2928 static int nand_id_has_period(u8
*id_data
, int arrlen
, int period
)
2931 for (i
= 0; i
< period
; i
++)
2932 for (j
= i
+ period
; j
< arrlen
; j
+= period
)
2933 if (id_data
[i
] != id_data
[j
])
2939 * nand_id_len - Get the length of an ID string returned by CMD_READID
2940 * @id_data: the ID string
2941 * @arrlen: the length of the @id_data array
2943 * Returns the length of the ID string, according to known wraparound/trailing
2944 * zero patterns. If no pattern exists, returns the length of the array.
2946 static int nand_id_len(u8
*id_data
, int arrlen
)
2948 int last_nonzero
, period
;
2950 /* Find last non-zero byte */
2951 for (last_nonzero
= arrlen
- 1; last_nonzero
>= 0; last_nonzero
--)
2952 if (id_data
[last_nonzero
])
2956 if (last_nonzero
< 0)
2959 /* Calculate wraparound period */
2960 for (period
= 1; period
< arrlen
; period
++)
2961 if (nand_id_has_period(id_data
, arrlen
, period
))
2964 /* There's a repeated pattern */
2965 if (period
< arrlen
)
2968 /* There are trailing zeros */
2969 if (last_nonzero
< arrlen
- 1)
2970 return last_nonzero
+ 1;
2972 /* No pattern detected */
2977 * Many new NAND share similar device ID codes, which represent the size of the
2978 * chip. The rest of the parameters must be decoded according to generic or
2979 * manufacturer-specific "extended ID" decoding patterns.
2981 static void nand_decode_ext_id(struct mtd_info
*mtd
, struct nand_chip
*chip
,
2982 u8 id_data
[8], int *busw
)
2985 /* The 3rd id byte holds MLC / multichip data */
2986 chip
->cellinfo
= id_data
[2];
2987 /* The 4th id byte is the important one */
2990 id_len
= nand_id_len(id_data
, 8);
2993 * Field definitions are in the following datasheets:
2994 * Old style (4,5 byte ID): Samsung K9GAG08U0M (p.32)
2995 * New Samsung (6 byte ID): Samsung K9GAG08U0F (p.44)
2996 * Hynix MLC (6 byte ID): Hynix H27UBG8T2B (p.22)
2998 * Check for ID length, non-zero 6th byte, cell type, and Hynix/Samsung
2999 * ID to decide what to do.
3001 if (id_len
== 6 && id_data
[0] == NAND_MFR_SAMSUNG
&&
3002 (chip
->cellinfo
& NAND_CI_CELLTYPE_MSK
) &&
3003 id_data
[5] != 0x00) {
3005 mtd
->writesize
= 2048 << (extid
& 0x03);
3008 switch (((extid
>> 2) & 0x04) | (extid
& 0x03)) {
3025 default: /* Other cases are "reserved" (unknown) */
3030 /* Calc blocksize */
3031 mtd
->erasesize
= (128 * 1024) <<
3032 (((extid
>> 1) & 0x04) | (extid
& 0x03));
3034 } else if (id_len
== 6 && id_data
[0] == NAND_MFR_HYNIX
&&
3035 (chip
->cellinfo
& NAND_CI_CELLTYPE_MSK
)) {
3039 mtd
->writesize
= 2048 << (extid
& 0x03);
3042 switch (((extid
>> 2) & 0x04) | (extid
& 0x03)) {
3066 /* Calc blocksize */
3067 tmp
= ((extid
>> 1) & 0x04) | (extid
& 0x03);
3069 mtd
->erasesize
= (128 * 1024) << tmp
;
3070 else if (tmp
== 0x03)
3071 mtd
->erasesize
= 768 * 1024;
3073 mtd
->erasesize
= (64 * 1024) << tmp
;
3077 mtd
->writesize
= 1024 << (extid
& 0x03);
3080 mtd
->oobsize
= (8 << (extid
& 0x01)) *
3081 (mtd
->writesize
>> 9);
3083 /* Calc blocksize. Blocksize is multiples of 64KiB */
3084 mtd
->erasesize
= (64 * 1024) << (extid
& 0x03);
3086 /* Get buswidth information */
3087 *busw
= (extid
& 0x01) ? NAND_BUSWIDTH_16
: 0;
3092 * Old devices have chip data hardcoded in the device ID table. nand_decode_id
3093 * decodes a matching ID table entry and assigns the MTD size parameters for
3096 static void nand_decode_id(struct mtd_info
*mtd
, struct nand_chip
*chip
,
3097 struct nand_flash_dev
*type
, u8 id_data
[8],
3100 int maf_id
= id_data
[0];
3102 mtd
->erasesize
= type
->erasesize
;
3103 mtd
->writesize
= type
->pagesize
;
3104 mtd
->oobsize
= mtd
->writesize
/ 32;
3105 *busw
= type
->options
& NAND_BUSWIDTH_16
;
3108 * Check for Spansion/AMD ID + repeating 5th, 6th byte since
3109 * some Spansion chips have erasesize that conflicts with size
3110 * listed in nand_ids table.
3111 * Data sheet (5 byte ID): Spansion S30ML-P ORNAND (p.39)
3113 if (maf_id
== NAND_MFR_AMD
&& id_data
[4] != 0x00 && id_data
[5] == 0x00
3114 && id_data
[6] == 0x00 && id_data
[7] == 0x00
3115 && mtd
->writesize
== 512) {
3116 mtd
->erasesize
= 128 * 1024;
3117 mtd
->erasesize
<<= ((id_data
[3] & 0x03) << 1);
3122 * Set the bad block marker/indicator (BBM/BBI) patterns according to some
3123 * heuristic patterns using various detected parameters (e.g., manufacturer,
3124 * page size, cell-type information).
3126 static void nand_decode_bbm_options(struct mtd_info
*mtd
,
3127 struct nand_chip
*chip
, u8 id_data
[8])
3129 int maf_id
= id_data
[0];
3131 /* Set the bad block position */
3132 if (mtd
->writesize
> 512 || (chip
->options
& NAND_BUSWIDTH_16
))
3133 chip
->badblockpos
= NAND_LARGE_BADBLOCK_POS
;
3135 chip
->badblockpos
= NAND_SMALL_BADBLOCK_POS
;
3138 * Bad block marker is stored in the last page of each block on Samsung
3139 * and Hynix MLC devices; stored in first two pages of each block on
3140 * Micron devices with 2KiB pages and on SLC Samsung, Hynix, Toshiba,
3141 * AMD/Spansion, and Macronix. All others scan only the first page.
3143 if ((chip
->cellinfo
& NAND_CI_CELLTYPE_MSK
) &&
3144 (maf_id
== NAND_MFR_SAMSUNG
||
3145 maf_id
== NAND_MFR_HYNIX
))
3146 chip
->bbt_options
|= NAND_BBT_SCANLASTPAGE
;
3147 else if ((!(chip
->cellinfo
& NAND_CI_CELLTYPE_MSK
) &&
3148 (maf_id
== NAND_MFR_SAMSUNG
||
3149 maf_id
== NAND_MFR_HYNIX
||
3150 maf_id
== NAND_MFR_TOSHIBA
||
3151 maf_id
== NAND_MFR_AMD
||
3152 maf_id
== NAND_MFR_MACRONIX
)) ||
3153 (mtd
->writesize
== 2048 &&
3154 maf_id
== NAND_MFR_MICRON
))
3155 chip
->bbt_options
|= NAND_BBT_SCAN2NDPAGE
;
3159 * Get the flash and manufacturer id and lookup if the type is supported.
3161 static struct nand_flash_dev
*nand_get_flash_type(struct mtd_info
*mtd
,
3162 struct nand_chip
*chip
,
3164 int *maf_id
, int *dev_id
,
3165 struct nand_flash_dev
*type
)
3170 /* Select the device */
3171 chip
->select_chip(mtd
, 0);
3174 * Reset the chip, required by some chips (e.g. Micron MT29FxGxxxxx)
3177 chip
->cmdfunc(mtd
, NAND_CMD_RESET
, -1, -1);
3179 /* Send the command for reading device ID */
3180 chip
->cmdfunc(mtd
, NAND_CMD_READID
, 0x00, -1);
3182 /* Read manufacturer and device IDs */
3183 *maf_id
= chip
->read_byte(mtd
);
3184 *dev_id
= chip
->read_byte(mtd
);
3187 * Try again to make sure, as some systems the bus-hold or other
3188 * interface concerns can cause random data which looks like a
3189 * possibly credible NAND flash to appear. If the two results do
3190 * not match, ignore the device completely.
3193 chip
->cmdfunc(mtd
, NAND_CMD_READID
, 0x00, -1);
3195 /* Read entire ID string */
3196 for (i
= 0; i
< 8; i
++)
3197 id_data
[i
] = chip
->read_byte(mtd
);
3199 if (id_data
[0] != *maf_id
|| id_data
[1] != *dev_id
) {
3200 pr_info("%s: second ID read did not match "
3201 "%02x,%02x against %02x,%02x\n", __func__
,
3202 *maf_id
, *dev_id
, id_data
[0], id_data
[1]);
3203 return ERR_PTR(-ENODEV
);
3207 type
= nand_flash_ids
;
3209 for (; type
->name
!= NULL
; type
++)
3210 if (*dev_id
== type
->id
)
3213 chip
->onfi_version
= 0;
3214 if (!type
->name
|| !type
->pagesize
) {
3215 /* Check is chip is ONFI compliant */
3216 if (nand_flash_detect_onfi(mtd
, chip
, &busw
))
3221 return ERR_PTR(-ENODEV
);
3224 mtd
->name
= type
->name
;
3226 chip
->chipsize
= (uint64_t)type
->chipsize
<< 20;
3228 if (!type
->pagesize
&& chip
->init_size
) {
3229 /* Set the pagesize, oobsize, erasesize by the driver */
3230 busw
= chip
->init_size(mtd
, chip
, id_data
);
3231 } else if (!type
->pagesize
) {
3232 /* Decode parameters from extended ID */
3233 nand_decode_ext_id(mtd
, chip
, id_data
, &busw
);
3235 nand_decode_id(mtd
, chip
, type
, id_data
, &busw
);
3237 /* Get chip options */
3238 chip
->options
|= type
->options
;
3241 * Check if chip is not a Samsung device. Do not clear the
3242 * options for chips which do not have an extended id.
3244 if (*maf_id
!= NAND_MFR_SAMSUNG
&& !type
->pagesize
)
3245 chip
->options
&= ~NAND_SAMSUNG_LP_OPTIONS
;
3248 /* Try to identify manufacturer */
3249 for (maf_idx
= 0; nand_manuf_ids
[maf_idx
].id
!= 0x0; maf_idx
++) {
3250 if (nand_manuf_ids
[maf_idx
].id
== *maf_id
)
3254 if (chip
->options
& NAND_BUSWIDTH_AUTO
) {
3255 WARN_ON(chip
->options
& NAND_BUSWIDTH_16
);
3256 chip
->options
|= busw
;
3257 nand_set_defaults(chip
, busw
);
3258 } else if (busw
!= (chip
->options
& NAND_BUSWIDTH_16
)) {
3260 * Check, if buswidth is correct. Hardware drivers should set
3263 pr_info("NAND device: Manufacturer ID:"
3264 " 0x%02x, Chip ID: 0x%02x (%s %s)\n", *maf_id
,
3265 *dev_id
, nand_manuf_ids
[maf_idx
].name
, mtd
->name
);
3266 pr_warn("NAND bus width %d instead %d bit\n",
3267 (chip
->options
& NAND_BUSWIDTH_16
) ? 16 : 8,
3269 return ERR_PTR(-EINVAL
);
3272 nand_decode_bbm_options(mtd
, chip
, id_data
);
3274 /* Calculate the address shift from the page size */
3275 chip
->page_shift
= ffs(mtd
->writesize
) - 1;
3276 /* Convert chipsize to number of pages per chip -1 */
3277 chip
->pagemask
= (chip
->chipsize
>> chip
->page_shift
) - 1;
3279 chip
->bbt_erase_shift
= chip
->phys_erase_shift
=
3280 ffs(mtd
->erasesize
) - 1;
3281 if (chip
->chipsize
& 0xffffffff)
3282 chip
->chip_shift
= ffs((unsigned)chip
->chipsize
) - 1;
3284 chip
->chip_shift
= ffs((unsigned)(chip
->chipsize
>> 32));
3285 chip
->chip_shift
+= 32 - 1;
3288 chip
->badblockbits
= 8;
3290 /* Check for AND chips with 4 page planes */
3291 if (chip
->options
& NAND_4PAGE_ARRAY
)
3292 chip
->erase_cmd
= multi_erase_cmd
;
3294 chip
->erase_cmd
= single_erase_cmd
;
3296 /* Do not replace user supplied command function! */
3297 if (mtd
->writesize
> 512 && chip
->cmdfunc
== nand_command
)
3298 chip
->cmdfunc
= nand_command_lp
;
3300 pr_info("NAND device: Manufacturer ID: 0x%02x, Chip ID: 0x%02x (%s %s),"
3301 " %dMiB, page size: %d, OOB size: %d\n",
3302 *maf_id
, *dev_id
, nand_manuf_ids
[maf_idx
].name
,
3303 chip
->onfi_version
? chip
->onfi_params
.model
: type
->name
,
3304 (int)(chip
->chipsize
>> 20), mtd
->writesize
, mtd
->oobsize
);
3310 * nand_scan_ident - [NAND Interface] Scan for the NAND device
3311 * @mtd: MTD device structure
3312 * @maxchips: number of chips to scan for
3313 * @table: alternative NAND ID table
3315 * This is the first phase of the normal nand_scan() function. It reads the
3316 * flash ID and sets up MTD fields accordingly.
3318 * The mtd->owner field must be set to the module of the caller.
3320 int nand_scan_ident(struct mtd_info
*mtd
, int maxchips
,
3321 struct nand_flash_dev
*table
)
3323 int i
, busw
, nand_maf_id
, nand_dev_id
;
3324 struct nand_chip
*chip
= mtd
->priv
;
3325 struct nand_flash_dev
*type
;
3327 /* Get buswidth to select the correct functions */
3328 busw
= chip
->options
& NAND_BUSWIDTH_16
;
3329 /* Set the default functions */
3330 nand_set_defaults(chip
, busw
);
3332 /* Read the flash type */
3333 type
= nand_get_flash_type(mtd
, chip
, busw
,
3334 &nand_maf_id
, &nand_dev_id
, table
);
3337 if (!(chip
->options
& NAND_SCAN_SILENT_NODEV
))
3338 pr_warn("No NAND device found\n");
3339 chip
->select_chip(mtd
, -1);
3340 return PTR_ERR(type
);
3343 chip
->select_chip(mtd
, -1);
3345 /* Check for a chip array */
3346 for (i
= 1; i
< maxchips
; i
++) {
3347 chip
->select_chip(mtd
, i
);
3348 /* See comment in nand_get_flash_type for reset */
3349 chip
->cmdfunc(mtd
, NAND_CMD_RESET
, -1, -1);
3350 /* Send the command for reading device ID */
3351 chip
->cmdfunc(mtd
, NAND_CMD_READID
, 0x00, -1);
3352 /* Read manufacturer and device IDs */
3353 if (nand_maf_id
!= chip
->read_byte(mtd
) ||
3354 nand_dev_id
!= chip
->read_byte(mtd
)) {
3355 chip
->select_chip(mtd
, -1);
3358 chip
->select_chip(mtd
, -1);
3361 pr_info("%d NAND chips detected\n", i
);
3363 /* Store the number of chips and calc total size for mtd */
3365 mtd
->size
= i
* chip
->chipsize
;
3369 EXPORT_SYMBOL(nand_scan_ident
);
3373 * nand_scan_tail - [NAND Interface] Scan for the NAND device
3374 * @mtd: MTD device structure
3376 * This is the second phase of the normal nand_scan() function. It fills out
3377 * all the uninitialized function pointers with the defaults and scans for a
3378 * bad block table if appropriate.
3380 int nand_scan_tail(struct mtd_info
*mtd
)
3383 struct nand_chip
*chip
= mtd
->priv
;
3385 /* New bad blocks should be marked in OOB, flash-based BBT, or both */
3386 BUG_ON((chip
->bbt_options
& NAND_BBT_NO_OOB_BBM
) &&
3387 !(chip
->bbt_options
& NAND_BBT_USE_FLASH
));
3389 if (!(chip
->options
& NAND_OWN_BUFFERS
))
3390 chip
->buffers
= kmalloc(sizeof(*chip
->buffers
), GFP_KERNEL
);
3394 /* Set the internal oob buffer location, just after the page data */
3395 chip
->oob_poi
= chip
->buffers
->databuf
+ mtd
->writesize
;
3398 * If no default placement scheme is given, select an appropriate one.
3400 if (!chip
->ecc
.layout
&& (chip
->ecc
.mode
!= NAND_ECC_SOFT_BCH
)) {
3401 switch (mtd
->oobsize
) {
3403 chip
->ecc
.layout
= &nand_oob_8
;
3406 chip
->ecc
.layout
= &nand_oob_16
;
3409 chip
->ecc
.layout
= &nand_oob_64
;
3412 chip
->ecc
.layout
= &nand_oob_128
;
3415 pr_warn("No oob scheme defined for oobsize %d\n",
3421 if (!chip
->write_page
)
3422 chip
->write_page
= nand_write_page
;
3424 /* set for ONFI nand */
3425 if (!chip
->onfi_set_features
)
3426 chip
->onfi_set_features
= nand_onfi_set_features
;
3427 if (!chip
->onfi_get_features
)
3428 chip
->onfi_get_features
= nand_onfi_get_features
;
3431 * Check ECC mode, default to software if 3byte/512byte hardware ECC is
3432 * selected and we have 256 byte pagesize fallback to software ECC
3435 switch (chip
->ecc
.mode
) {
3436 case NAND_ECC_HW_OOB_FIRST
:
3437 /* Similar to NAND_ECC_HW, but a separate read_page handle */
3438 if (!chip
->ecc
.calculate
|| !chip
->ecc
.correct
||
3440 pr_warn("No ECC functions supplied; "
3441 "hardware ECC not possible\n");
3444 if (!chip
->ecc
.read_page
)
3445 chip
->ecc
.read_page
= nand_read_page_hwecc_oob_first
;
3448 /* Use standard hwecc read page function? */
3449 if (!chip
->ecc
.read_page
)
3450 chip
->ecc
.read_page
= nand_read_page_hwecc
;
3451 if (!chip
->ecc
.write_page
)
3452 chip
->ecc
.write_page
= nand_write_page_hwecc
;
3453 if (!chip
->ecc
.read_page_raw
)
3454 chip
->ecc
.read_page_raw
= nand_read_page_raw
;
3455 if (!chip
->ecc
.write_page_raw
)
3456 chip
->ecc
.write_page_raw
= nand_write_page_raw
;
3457 if (!chip
->ecc
.read_oob
)
3458 chip
->ecc
.read_oob
= nand_read_oob_std
;
3459 if (!chip
->ecc
.write_oob
)
3460 chip
->ecc
.write_oob
= nand_write_oob_std
;
3462 case NAND_ECC_HW_SYNDROME
:
3463 if ((!chip
->ecc
.calculate
|| !chip
->ecc
.correct
||
3464 !chip
->ecc
.hwctl
) &&
3465 (!chip
->ecc
.read_page
||
3466 chip
->ecc
.read_page
== nand_read_page_hwecc
||
3467 !chip
->ecc
.write_page
||
3468 chip
->ecc
.write_page
== nand_write_page_hwecc
)) {
3469 pr_warn("No ECC functions supplied; "
3470 "hardware ECC not possible\n");
3473 /* Use standard syndrome read/write page function? */
3474 if (!chip
->ecc
.read_page
)
3475 chip
->ecc
.read_page
= nand_read_page_syndrome
;
3476 if (!chip
->ecc
.write_page
)
3477 chip
->ecc
.write_page
= nand_write_page_syndrome
;
3478 if (!chip
->ecc
.read_page_raw
)
3479 chip
->ecc
.read_page_raw
= nand_read_page_raw_syndrome
;
3480 if (!chip
->ecc
.write_page_raw
)
3481 chip
->ecc
.write_page_raw
= nand_write_page_raw_syndrome
;
3482 if (!chip
->ecc
.read_oob
)
3483 chip
->ecc
.read_oob
= nand_read_oob_syndrome
;
3484 if (!chip
->ecc
.write_oob
)
3485 chip
->ecc
.write_oob
= nand_write_oob_syndrome
;
3487 if (mtd
->writesize
>= chip
->ecc
.size
) {
3488 if (!chip
->ecc
.strength
) {
3489 pr_warn("Driver must set ecc.strength when using hardware ECC\n");
3494 pr_warn("%d byte HW ECC not possible on "
3495 "%d byte page size, fallback to SW ECC\n",
3496 chip
->ecc
.size
, mtd
->writesize
);
3497 chip
->ecc
.mode
= NAND_ECC_SOFT
;
3500 chip
->ecc
.calculate
= nand_calculate_ecc
;
3501 chip
->ecc
.correct
= nand_correct_data
;
3502 chip
->ecc
.read_page
= nand_read_page_swecc
;
3503 chip
->ecc
.read_subpage
= nand_read_subpage
;
3504 chip
->ecc
.write_page
= nand_write_page_swecc
;
3505 chip
->ecc
.read_page_raw
= nand_read_page_raw
;
3506 chip
->ecc
.write_page_raw
= nand_write_page_raw
;
3507 chip
->ecc
.read_oob
= nand_read_oob_std
;
3508 chip
->ecc
.write_oob
= nand_write_oob_std
;
3509 if (!chip
->ecc
.size
)
3510 chip
->ecc
.size
= 256;
3511 chip
->ecc
.bytes
= 3;
3512 chip
->ecc
.strength
= 1;
3515 case NAND_ECC_SOFT_BCH
:
3516 if (!mtd_nand_has_bch()) {
3517 pr_warn("CONFIG_MTD_ECC_BCH not enabled\n");
3520 chip
->ecc
.calculate
= nand_bch_calculate_ecc
;
3521 chip
->ecc
.correct
= nand_bch_correct_data
;
3522 chip
->ecc
.read_page
= nand_read_page_swecc
;
3523 chip
->ecc
.read_subpage
= nand_read_subpage
;
3524 chip
->ecc
.write_page
= nand_write_page_swecc
;
3525 chip
->ecc
.read_page_raw
= nand_read_page_raw
;
3526 chip
->ecc
.write_page_raw
= nand_write_page_raw
;
3527 chip
->ecc
.read_oob
= nand_read_oob_std
;
3528 chip
->ecc
.write_oob
= nand_write_oob_std
;
3530 * Board driver should supply ecc.size and ecc.bytes values to
3531 * select how many bits are correctable; see nand_bch_init()
3532 * for details. Otherwise, default to 4 bits for large page
3535 if (!chip
->ecc
.size
&& (mtd
->oobsize
>= 64)) {
3536 chip
->ecc
.size
= 512;
3537 chip
->ecc
.bytes
= 7;
3539 chip
->ecc
.priv
= nand_bch_init(mtd
,
3543 if (!chip
->ecc
.priv
) {
3544 pr_warn("BCH ECC initialization failed!\n");
3547 chip
->ecc
.strength
=
3548 chip
->ecc
.bytes
* 8 / fls(8 * chip
->ecc
.size
);
3552 pr_warn("NAND_ECC_NONE selected by board driver. "
3553 "This is not recommended!\n");
3554 chip
->ecc
.read_page
= nand_read_page_raw
;
3555 chip
->ecc
.write_page
= nand_write_page_raw
;
3556 chip
->ecc
.read_oob
= nand_read_oob_std
;
3557 chip
->ecc
.read_page_raw
= nand_read_page_raw
;
3558 chip
->ecc
.write_page_raw
= nand_write_page_raw
;
3559 chip
->ecc
.write_oob
= nand_write_oob_std
;
3560 chip
->ecc
.size
= mtd
->writesize
;
3561 chip
->ecc
.bytes
= 0;
3562 chip
->ecc
.strength
= 0;
3566 pr_warn("Invalid NAND_ECC_MODE %d\n", chip
->ecc
.mode
);
3570 /* For many systems, the standard OOB write also works for raw */
3571 if (!chip
->ecc
.read_oob_raw
)
3572 chip
->ecc
.read_oob_raw
= chip
->ecc
.read_oob
;
3573 if (!chip
->ecc
.write_oob_raw
)
3574 chip
->ecc
.write_oob_raw
= chip
->ecc
.write_oob
;
3577 * The number of bytes available for a client to place data into
3578 * the out of band area.
3580 chip
->ecc
.layout
->oobavail
= 0;
3581 for (i
= 0; chip
->ecc
.layout
->oobfree
[i
].length
3582 && i
< ARRAY_SIZE(chip
->ecc
.layout
->oobfree
); i
++)
3583 chip
->ecc
.layout
->oobavail
+=
3584 chip
->ecc
.layout
->oobfree
[i
].length
;
3585 mtd
->oobavail
= chip
->ecc
.layout
->oobavail
;
3588 * Set the number of read / write steps for one page depending on ECC
3591 chip
->ecc
.steps
= mtd
->writesize
/ chip
->ecc
.size
;
3592 if (chip
->ecc
.steps
* chip
->ecc
.size
!= mtd
->writesize
) {
3593 pr_warn("Invalid ECC parameters\n");
3596 chip
->ecc
.total
= chip
->ecc
.steps
* chip
->ecc
.bytes
;
3598 /* Allow subpage writes up to ecc.steps. Not possible for MLC flash */
3599 if (!(chip
->options
& NAND_NO_SUBPAGE_WRITE
) &&
3600 !(chip
->cellinfo
& NAND_CI_CELLTYPE_MSK
)) {
3601 switch (chip
->ecc
.steps
) {
3603 mtd
->subpage_sft
= 1;
3608 mtd
->subpage_sft
= 2;
3612 chip
->subpagesize
= mtd
->writesize
>> mtd
->subpage_sft
;
3614 /* Initialize state */
3615 chip
->state
= FL_READY
;
3617 /* Invalidate the pagebuffer reference */
3620 /* Large page NAND with SOFT_ECC should support subpage reads */
3621 if ((chip
->ecc
.mode
== NAND_ECC_SOFT
) && (chip
->page_shift
> 9))
3622 chip
->options
|= NAND_SUBPAGE_READ
;
3624 /* Fill in remaining MTD driver data */
3625 mtd
->type
= MTD_NANDFLASH
;
3626 mtd
->flags
= (chip
->options
& NAND_ROM
) ? MTD_CAP_ROM
:
3628 mtd
->_erase
= nand_erase
;
3630 mtd
->_unpoint
= NULL
;
3631 mtd
->_read
= nand_read
;
3632 mtd
->_write
= nand_write
;
3633 mtd
->_panic_write
= panic_nand_write
;
3634 mtd
->_read_oob
= nand_read_oob
;
3635 mtd
->_write_oob
= nand_write_oob
;
3636 mtd
->_sync
= nand_sync
;
3638 mtd
->_unlock
= NULL
;
3639 mtd
->_suspend
= nand_suspend
;
3640 mtd
->_resume
= nand_resume
;
3641 mtd
->_block_isbad
= nand_block_isbad
;
3642 mtd
->_block_markbad
= nand_block_markbad
;
3643 mtd
->writebufsize
= mtd
->writesize
;
3645 /* propagate ecc info to mtd_info */
3646 mtd
->ecclayout
= chip
->ecc
.layout
;
3647 mtd
->ecc_strength
= chip
->ecc
.strength
;
3649 * Initialize bitflip_threshold to its default prior scan_bbt() call.
3650 * scan_bbt() might invoke mtd_read(), thus bitflip_threshold must be
3653 if (!mtd
->bitflip_threshold
)
3654 mtd
->bitflip_threshold
= mtd
->ecc_strength
;
3656 /* Check, if we should skip the bad block table scan */
3657 if (chip
->options
& NAND_SKIP_BBTSCAN
)
3660 /* Build bad block table */
3661 return chip
->scan_bbt(mtd
);
3663 EXPORT_SYMBOL(nand_scan_tail
);
3666 * is_module_text_address() isn't exported, and it's mostly a pointless
3667 * test if this is a module _anyway_ -- they'd have to try _really_ hard
3668 * to call us from in-kernel code if the core NAND support is modular.
3671 #define caller_is_module() (1)
3673 #define caller_is_module() \
3674 is_module_text_address((unsigned long)__builtin_return_address(0))
3678 * nand_scan - [NAND Interface] Scan for the NAND device
3679 * @mtd: MTD device structure
3680 * @maxchips: number of chips to scan for
3682 * This fills out all the uninitialized function pointers with the defaults.
3683 * The flash ID is read and the mtd/chip structures are filled with the
3684 * appropriate values. The mtd->owner field must be set to the module of the
3687 int nand_scan(struct mtd_info
*mtd
, int maxchips
)
3691 /* Many callers got this wrong, so check for it for a while... */
3692 if (!mtd
->owner
&& caller_is_module()) {
3693 pr_crit("%s called with NULL mtd->owner!\n", __func__
);
3697 ret
= nand_scan_ident(mtd
, maxchips
, NULL
);
3699 ret
= nand_scan_tail(mtd
);
3702 EXPORT_SYMBOL(nand_scan
);
3705 * nand_release - [NAND Interface] Free resources held by the NAND device
3706 * @mtd: MTD device structure
3708 void nand_release(struct mtd_info
*mtd
)
3710 struct nand_chip
*chip
= mtd
->priv
;
3712 if (chip
->ecc
.mode
== NAND_ECC_SOFT_BCH
)
3713 nand_bch_free((struct nand_bch_control
*)chip
->ecc
.priv
);
3715 mtd_device_unregister(mtd
);
3717 /* Free bad block table memory */
3719 if (!(chip
->options
& NAND_OWN_BUFFERS
))
3720 kfree(chip
->buffers
);
3722 /* Free bad block descriptor memory */
3723 if (chip
->badblock_pattern
&& chip
->badblock_pattern
->options
3724 & NAND_BBT_DYNAMICSTRUCT
)
3725 kfree(chip
->badblock_pattern
);
3727 EXPORT_SYMBOL_GPL(nand_release
);
3729 static int __init
nand_base_init(void)
3731 led_trigger_register_simple("nand-disk", &nand_led_trigger
);
3735 static void __exit
nand_base_exit(void)
3737 led_trigger_unregister_simple(nand_led_trigger
);
3740 module_init(nand_base_init
);
3741 module_exit(nand_base_exit
);
3743 MODULE_LICENSE("GPL");
3744 MODULE_AUTHOR("Steven J. Hill <sjhill@realitydiluted.com>");
3745 MODULE_AUTHOR("Thomas Gleixner <tglx@linutronix.de>");
3746 MODULE_DESCRIPTION("Generic NAND flash driver code");