| blob | 389f9f8b570c751dcdbf94d50e8e09521588dec7 |
1 /*
2 * OMAP2/3 CM module functions
3 *
4 * Copyright (C) 2009 Nokia Corporation
5 * Paul Walmsley
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 */
12 #include <linux/kernel.h>
13 #include <linux/types.h>
14 #include <linux/delay.h>
15 #include <linux/spinlock.h>
16 #include <linux/list.h>
17 #include <linux/errno.h>
18 #include <linux/err.h>
19 #include <linux/io.h>
21 #include <plat/hardware.h>
30 /* CM_AUTOIDLE_PLL.AUTO_* bit values for DPLLs */
31 #define DPLL_AUTOIDLE_DISABLE 0x0
32 #define OMAP2XXX_DPLL_AUTOIDLE_LOW_POWER_STOP 0x3
34 /* CM_AUTOIDLE_PLL.AUTO_* bit values for APLLs (OMAP2xxx only) */
35 #define OMAP2XXX_APLL_AUTOIDLE_DISABLE 0x0
36 #define OMAP2XXX_APLL_AUTOIDLE_LOW_POWER_STOP 0x3
40 };
43 {
45 }
48 {
50 }
52 /* Read-modify-write a register in a CM module. Caller must lock */
54 {
55 u32 v;
63 }
66 {
68 }
71 {
73 }
75 /*
76 *
77 */
80 {
81 u32 v;
87 }
90 {
91 u32 v;
102 else
106 }
109 {
111 }
114 {
116 }
119 {
121 }
124 {
126 }
129 {
131 }
134 {
136 }
138 /*
139 * DPLL autoidle control
140 */
143 {
144 u32 v;
150 }
153 {
155 }
158 {
160 }
162 /*
163 * APLL autoidle control
164 */
167 {
168 u32 v;
174 }
177 {
179 OMAP24XX_AUTO_54M_MASK);
180 }
183 {
185 OMAP24XX_AUTO_54M_MASK);
186 }
189 {
191 OMAP24XX_AUTO_96M_MASK);
192 }
195 {
197 OMAP24XX_AUTO_96M_MASK);
198 }
200 /*
201 *
202 */
204 /**
205 * omap2_cm_wait_idlest_ready - wait for a module to leave idle or standby
206 * @prcm_mod: PRCM module offset
207 * @idlest_id: CM_IDLESTx register ID (i.e., x = 1, 2, 3)
208 * @idlest_shift: shift of the bit in the CM_IDLEST* register to check
209 *
210 * XXX document
211 */
213 {
215 u8 cm_idlest_reg;
216 u32 mask;
229 else
236 }
238 /*
239 * Context save/restore code - OMAP3 only
240 */
241 #ifdef CONFIG_ARCH_OMAP3
243 u32 iva2_cm_clksel1;
244 u32 iva2_cm_clksel2;
245 u32 cm_sysconfig;
246 u32 sgx_cm_clksel;
247 u32 dss_cm_clksel;
248 u32 cam_cm_clksel;
249 u32 per_cm_clksel;
250 u32 emu_cm_clksel;
251 u32 emu_cm_clkstctrl;
252 u32 pll_cm_autoidle;
253 u32 pll_cm_autoidle2;
254 u32 pll_cm_clksel4;
255 u32 pll_cm_clksel5;
256 u32 pll_cm_clken2;
257 u32 cm_polctrl;
258 u32 iva2_cm_fclken;
259 u32 iva2_cm_clken_pll;
260 u32 core_cm_fclken1;
261 u32 core_cm_fclken3;
262 u32 sgx_cm_fclken;
263 u32 wkup_cm_fclken;
264 u32 dss_cm_fclken;
265 u32 cam_cm_fclken;
266 u32 per_cm_fclken;
267 u32 usbhost_cm_fclken;
268 u32 core_cm_iclken1;
269 u32 core_cm_iclken2;
270 u32 core_cm_iclken3;
271 u32 sgx_cm_iclken;
272 u32 wkup_cm_iclken;
273 u32 dss_cm_iclken;
274 u32 cam_cm_iclken;
275 u32 per_cm_iclken;
276 u32 usbhost_cm_iclken;
277 u32 iva2_cm_autoidle2;
278 u32 mpu_cm_autoidle2;
279 u32 iva2_cm_clkstctrl;
280 u32 mpu_cm_clkstctrl;
281 u32 core_cm_clkstctrl;
282 u32 sgx_cm_clkstctrl;
283 u32 dss_cm_clkstctrl;
284 u32 cam_cm_clkstctrl;
285 u32 per_cm_clkstctrl;
286 u32 neon_cm_clkstctrl;
287 u32 usbhost_cm_clkstctrl;
288 u32 core_cm_autoidle1;
289 u32 core_cm_autoidle2;
290 u32 core_cm_autoidle3;
291 u32 wkup_cm_autoidle;
292 u32 dss_cm_autoidle;
293 u32 cam_cm_autoidle;
294 u32 per_cm_autoidle;
295 u32 usbhost_cm_autoidle;
296 u32 sgx_cm_sleepdep;
297 u32 dss_cm_sleepdep;
298 u32 cam_cm_sleepdep;
299 u32 per_cm_sleepdep;
300 u32 usbhost_cm_sleepdep;
301 u32 cm_clkout_ctrl;
302 };
307 {
325 /*
326 * As per erratum i671, ROM code does not respect the PER DPLL
327 * programming scheme if CM_AUTOIDLE_PLL.AUTO_PERIPH_DPLL == 1.
328 * In this case, even though this register has been saved in
329 * scratchpad contents, we need to restore AUTO_PERIPH_DPLL
330 * by ourselves. So, we need to save it anyway.
331 */
403 OMAP2_CM_CLKSTCTRL);
422 OMAP3430_CM_SLEEPDEP);
431 OMAP3430_CM_SLEEPDEP);
434 OMAP3_CM_CLKOUT_CTRL_OFFSET);
435 }
438 {
440 CM_CLKSEL1);
442 CM_CLKSEL2);
445 CM_CLKSEL);
447 CM_CLKSEL);
449 CM_CLKSEL);
451 CM_CLKSEL);
453 CM_CLKSEL1);
455 OMAP2_CM_CLKSTCTRL);
456 /*
457 * As per erratum i671, ROM code does not respect the PER DPLL
458 * programming scheme if CM_AUTOIDLE_PLL.AUTO_PERIPH_DPLL == 1.
459 * In this case, we need to restore AUTO_PERIPH_DPLL by ourselves.
460 */
462 CM_AUTOIDLE);
464 CM_AUTOIDLE2);
466 OMAP3430ES2_CM_CLKSEL4);
468 OMAP3430ES2_CM_CLKSEL5);
470 OMAP3430ES2_CM_CLKEN2);
473 CM_FCLKEN);
475 OMAP3430_CM_CLKEN_PLL);
477 CM_FCLKEN1);
479 OMAP3430ES2_CM_FCLKEN3);
481 CM_FCLKEN);
484 CM_FCLKEN);
486 CM_FCLKEN);
488 CM_FCLKEN);
492 CM_ICLKEN1);
494 CM_ICLKEN2);
496 CM_ICLKEN3);
498 CM_ICLKEN);
501 CM_ICLKEN);
503 CM_ICLKEN);
505 CM_ICLKEN);
509 CM_AUTOIDLE2);
511 CM_AUTOIDLE2);
513 OMAP2_CM_CLKSTCTRL);
515 OMAP2_CM_CLKSTCTRL);
517 OMAP2_CM_CLKSTCTRL);
519 OMAP2_CM_CLKSTCTRL);
521 OMAP2_CM_CLKSTCTRL);
523 OMAP2_CM_CLKSTCTRL);
525 OMAP2_CM_CLKSTCTRL);
527 OMAP2_CM_CLKSTCTRL);
531 CM_AUTOIDLE1);
533 CM_AUTOIDLE2);
535 CM_AUTOIDLE3);
537 CM_AUTOIDLE);
539 CM_AUTOIDLE);
541 CM_AUTOIDLE);
543 CM_AUTOIDLE);
547 OMAP3430_CM_SLEEPDEP);
549 OMAP3430_CM_SLEEPDEP);
551 OMAP3430_CM_SLEEPDEP);
553 OMAP3430_CM_SLEEPDEP);
557 OMAP3_CM_CLKOUT_CTRL_OFFSET);
558 }
559 #endif