1 /*******************************************************************************
4 Copyright(c) 1999 - 2005 Intel Corporation. All rights reserved.
6 This program is free software; you can redistribute it and/or modify it
7 under the terms of the GNU General Public License as published by the Free
8 Software Foundation; either version 2 of the License, or (at your option)
11 This program is distributed in the hope that it will be useful, but WITHOUT
12 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
16 You should have received a copy of the GNU General Public License along with
17 this program; if not, write to the Free Software Foundation, Inc., 59
18 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
20 The full GNU General Public License is included in this distribution in the
24 Linux NICS <linux.nics@intel.com>
25 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
27 *******************************************************************************/
30 * Shared functions for accessing and configuring the MAC
35 static int32_t e1000_set_phy_type(struct e1000_hw
*hw
);
36 static void e1000_phy_init_script(struct e1000_hw
*hw
);
37 static int32_t e1000_setup_copper_link(struct e1000_hw
*hw
);
38 static int32_t e1000_setup_fiber_serdes_link(struct e1000_hw
*hw
);
39 static int32_t e1000_adjust_serdes_amplitude(struct e1000_hw
*hw
);
40 static int32_t e1000_phy_force_speed_duplex(struct e1000_hw
*hw
);
41 static int32_t e1000_config_mac_to_phy(struct e1000_hw
*hw
);
42 static void e1000_raise_mdi_clk(struct e1000_hw
*hw
, uint32_t *ctrl
);
43 static void e1000_lower_mdi_clk(struct e1000_hw
*hw
, uint32_t *ctrl
);
44 static void e1000_shift_out_mdi_bits(struct e1000_hw
*hw
, uint32_t data
,
46 static uint16_t e1000_shift_in_mdi_bits(struct e1000_hw
*hw
);
47 static int32_t e1000_phy_reset_dsp(struct e1000_hw
*hw
);
48 static int32_t e1000_write_eeprom_spi(struct e1000_hw
*hw
, uint16_t offset
,
49 uint16_t words
, uint16_t *data
);
50 static int32_t e1000_write_eeprom_microwire(struct e1000_hw
*hw
,
51 uint16_t offset
, uint16_t words
,
53 static int32_t e1000_spi_eeprom_ready(struct e1000_hw
*hw
);
54 static void e1000_raise_ee_clk(struct e1000_hw
*hw
, uint32_t *eecd
);
55 static void e1000_lower_ee_clk(struct e1000_hw
*hw
, uint32_t *eecd
);
56 static void e1000_shift_out_ee_bits(struct e1000_hw
*hw
, uint16_t data
,
58 static int32_t e1000_write_phy_reg_ex(struct e1000_hw
*hw
, uint32_t reg_addr
,
60 static int32_t e1000_read_phy_reg_ex(struct e1000_hw
*hw
,uint32_t reg_addr
,
62 static uint16_t e1000_shift_in_ee_bits(struct e1000_hw
*hw
, uint16_t count
);
63 static int32_t e1000_acquire_eeprom(struct e1000_hw
*hw
);
64 static void e1000_release_eeprom(struct e1000_hw
*hw
);
65 static void e1000_standby_eeprom(struct e1000_hw
*hw
);
66 static int32_t e1000_set_vco_speed(struct e1000_hw
*hw
);
67 static int32_t e1000_polarity_reversal_workaround(struct e1000_hw
*hw
);
68 static int32_t e1000_set_phy_mode(struct e1000_hw
*hw
);
69 static int32_t e1000_host_if_read_cookie(struct e1000_hw
*hw
, uint8_t *buffer
);
70 static uint8_t e1000_calculate_mng_checksum(char *buffer
, uint32_t length
);
71 static uint8_t e1000_arc_subsystem_valid(struct e1000_hw
*hw
);
72 static int32_t e1000_check_downshift(struct e1000_hw
*hw
);
73 static int32_t e1000_check_polarity(struct e1000_hw
*hw
, uint16_t *polarity
);
74 static void e1000_clear_hw_cntrs(struct e1000_hw
*hw
);
75 static void e1000_clear_vfta(struct e1000_hw
*hw
);
76 static int32_t e1000_commit_shadow_ram(struct e1000_hw
*hw
);
77 static int32_t e1000_config_dsp_after_link_change(struct e1000_hw
*hw
,
79 static int32_t e1000_config_fc_after_link_up(struct e1000_hw
*hw
);
80 static int32_t e1000_detect_gig_phy(struct e1000_hw
*hw
);
81 static int32_t e1000_get_auto_rd_done(struct e1000_hw
*hw
);
82 static int32_t e1000_get_cable_length(struct e1000_hw
*hw
,
84 uint16_t *max_length
);
85 static int32_t e1000_get_hw_eeprom_semaphore(struct e1000_hw
*hw
);
86 static int32_t e1000_get_phy_cfg_done(struct e1000_hw
*hw
);
87 static int32_t e1000_id_led_init(struct e1000_hw
* hw
);
88 static void e1000_init_rx_addrs(struct e1000_hw
*hw
);
89 static boolean_t
e1000_is_onboard_nvm_eeprom(struct e1000_hw
*hw
);
90 static int32_t e1000_poll_eerd_eewr_done(struct e1000_hw
*hw
, int eerd
);
91 static void e1000_put_hw_eeprom_semaphore(struct e1000_hw
*hw
);
92 static int32_t e1000_read_eeprom_eerd(struct e1000_hw
*hw
, uint16_t offset
,
93 uint16_t words
, uint16_t *data
);
94 static int32_t e1000_set_d0_lplu_state(struct e1000_hw
*hw
, boolean_t active
);
95 static int32_t e1000_set_d3_lplu_state(struct e1000_hw
*hw
, boolean_t active
);
96 static int32_t e1000_wait_autoneg(struct e1000_hw
*hw
);
98 static void e1000_write_reg_io(struct e1000_hw
*hw
, uint32_t offset
,
101 #define E1000_WRITE_REG_IO(a, reg, val) \
102 e1000_write_reg_io((a), E1000_##reg, val)
104 /* IGP cable length table */
106 uint16_t e1000_igp_cable_length_table
[IGP01E1000_AGC_LENGTH_TABLE_SIZE
] =
107 { 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5,
108 5, 10, 10, 10, 10, 10, 10, 10, 20, 20, 20, 20, 20, 25, 25, 25,
109 25, 25, 25, 25, 30, 30, 30, 30, 40, 40, 40, 40, 40, 40, 40, 40,
110 40, 50, 50, 50, 50, 50, 50, 50, 60, 60, 60, 60, 60, 60, 60, 60,
111 60, 70, 70, 70, 70, 70, 70, 80, 80, 80, 80, 80, 80, 90, 90, 90,
112 90, 90, 90, 90, 90, 90, 100, 100, 100, 100, 100, 100, 100, 100, 100, 100,
113 100, 100, 100, 100, 110, 110, 110, 110, 110, 110, 110, 110, 110, 110, 110, 110,
114 110, 110, 110, 110, 110, 110, 120, 120, 120, 120, 120, 120, 120, 120, 120, 120};
117 uint16_t e1000_igp_2_cable_length_table
[IGP02E1000_AGC_LENGTH_TABLE_SIZE
] =
118 { 0, 0, 0, 0, 0, 0, 0, 0, 3, 5, 8, 11, 13, 16, 18, 21,
119 0, 0, 0, 3, 6, 10, 13, 16, 19, 23, 26, 29, 32, 35, 38, 41,
120 6, 10, 14, 18, 22, 26, 30, 33, 37, 41, 44, 48, 51, 54, 58, 61,
121 21, 26, 31, 35, 40, 44, 49, 53, 57, 61, 65, 68, 72, 75, 79, 82,
122 40, 45, 51, 56, 61, 66, 70, 75, 79, 83, 87, 91, 94, 98, 101, 104,
123 60, 66, 72, 77, 82, 87, 92, 96, 100, 104, 108, 111, 114, 117, 119, 121,
124 83, 89, 95, 100, 105, 109, 113, 116, 119, 122, 124,
125 104, 109, 114, 118, 121, 124};
128 /******************************************************************************
129 * Set the phy type member in the hw struct.
131 * hw - Struct containing variables accessed by shared code
132 *****************************************************************************/
134 e1000_set_phy_type(struct e1000_hw
*hw
)
136 DEBUGFUNC("e1000_set_phy_type");
138 if(hw
->mac_type
== e1000_undefined
)
139 return -E1000_ERR_PHY_TYPE
;
142 case M88E1000_E_PHY_ID
:
143 case M88E1000_I_PHY_ID
:
144 case M88E1011_I_PHY_ID
:
145 case M88E1111_I_PHY_ID
:
146 hw
->phy_type
= e1000_phy_m88
;
148 case IGP01E1000_I_PHY_ID
:
149 if(hw
->mac_type
== e1000_82541
||
150 hw
->mac_type
== e1000_82541_rev_2
||
151 hw
->mac_type
== e1000_82547
||
152 hw
->mac_type
== e1000_82547_rev_2
) {
153 hw
->phy_type
= e1000_phy_igp
;
158 /* Should never have loaded on this device */
159 hw
->phy_type
= e1000_phy_undefined
;
160 return -E1000_ERR_PHY_TYPE
;
163 return E1000_SUCCESS
;
166 /******************************************************************************
167 * IGP phy init script - initializes the GbE PHY
169 * hw - Struct containing variables accessed by shared code
170 *****************************************************************************/
172 e1000_phy_init_script(struct e1000_hw
*hw
)
175 uint16_t phy_saved_data
;
177 DEBUGFUNC("e1000_phy_init_script");
179 if(hw
->phy_init_script
) {
182 /* Save off the current value of register 0x2F5B to be restored at
183 * the end of this routine. */
184 ret_val
= e1000_read_phy_reg(hw
, 0x2F5B, &phy_saved_data
);
186 /* Disabled the PHY transmitter */
187 e1000_write_phy_reg(hw
, 0x2F5B, 0x0003);
191 e1000_write_phy_reg(hw
,0x0000,0x0140);
195 switch(hw
->mac_type
) {
198 e1000_write_phy_reg(hw
, 0x1F95, 0x0001);
200 e1000_write_phy_reg(hw
, 0x1F71, 0xBD21);
202 e1000_write_phy_reg(hw
, 0x1F79, 0x0018);
204 e1000_write_phy_reg(hw
, 0x1F30, 0x1600);
206 e1000_write_phy_reg(hw
, 0x1F31, 0x0014);
208 e1000_write_phy_reg(hw
, 0x1F32, 0x161C);
210 e1000_write_phy_reg(hw
, 0x1F94, 0x0003);
212 e1000_write_phy_reg(hw
, 0x1F96, 0x003F);
214 e1000_write_phy_reg(hw
, 0x2010, 0x0008);
217 case e1000_82541_rev_2
:
218 case e1000_82547_rev_2
:
219 e1000_write_phy_reg(hw
, 0x1F73, 0x0099);
225 e1000_write_phy_reg(hw
, 0x0000, 0x3300);
229 /* Now enable the transmitter */
230 e1000_write_phy_reg(hw
, 0x2F5B, phy_saved_data
);
232 if(hw
->mac_type
== e1000_82547
) {
233 uint16_t fused
, fine
, coarse
;
235 /* Move to analog registers page */
236 e1000_read_phy_reg(hw
, IGP01E1000_ANALOG_SPARE_FUSE_STATUS
, &fused
);
238 if(!(fused
& IGP01E1000_ANALOG_SPARE_FUSE_ENABLED
)) {
239 e1000_read_phy_reg(hw
, IGP01E1000_ANALOG_FUSE_STATUS
, &fused
);
241 fine
= fused
& IGP01E1000_ANALOG_FUSE_FINE_MASK
;
242 coarse
= fused
& IGP01E1000_ANALOG_FUSE_COARSE_MASK
;
244 if(coarse
> IGP01E1000_ANALOG_FUSE_COARSE_THRESH
) {
245 coarse
-= IGP01E1000_ANALOG_FUSE_COARSE_10
;
246 fine
-= IGP01E1000_ANALOG_FUSE_FINE_1
;
247 } else if(coarse
== IGP01E1000_ANALOG_FUSE_COARSE_THRESH
)
248 fine
-= IGP01E1000_ANALOG_FUSE_FINE_10
;
250 fused
= (fused
& IGP01E1000_ANALOG_FUSE_POLY_MASK
) |
251 (fine
& IGP01E1000_ANALOG_FUSE_FINE_MASK
) |
252 (coarse
& IGP01E1000_ANALOG_FUSE_COARSE_MASK
);
254 e1000_write_phy_reg(hw
, IGP01E1000_ANALOG_FUSE_CONTROL
, fused
);
255 e1000_write_phy_reg(hw
, IGP01E1000_ANALOG_FUSE_BYPASS
,
256 IGP01E1000_ANALOG_FUSE_ENABLE_SW_CONTROL
);
262 /******************************************************************************
263 * Set the mac type member in the hw struct.
265 * hw - Struct containing variables accessed by shared code
266 *****************************************************************************/
268 e1000_set_mac_type(struct e1000_hw
*hw
)
270 DEBUGFUNC("e1000_set_mac_type");
272 switch (hw
->device_id
) {
273 case E1000_DEV_ID_82542
:
274 switch (hw
->revision_id
) {
275 case E1000_82542_2_0_REV_ID
:
276 hw
->mac_type
= e1000_82542_rev2_0
;
278 case E1000_82542_2_1_REV_ID
:
279 hw
->mac_type
= e1000_82542_rev2_1
;
282 /* Invalid 82542 revision ID */
283 return -E1000_ERR_MAC_TYPE
;
286 case E1000_DEV_ID_82543GC_FIBER
:
287 case E1000_DEV_ID_82543GC_COPPER
:
288 hw
->mac_type
= e1000_82543
;
290 case E1000_DEV_ID_82544EI_COPPER
:
291 case E1000_DEV_ID_82544EI_FIBER
:
292 case E1000_DEV_ID_82544GC_COPPER
:
293 case E1000_DEV_ID_82544GC_LOM
:
294 hw
->mac_type
= e1000_82544
;
296 case E1000_DEV_ID_82540EM
:
297 case E1000_DEV_ID_82540EM_LOM
:
298 case E1000_DEV_ID_82540EP
:
299 case E1000_DEV_ID_82540EP_LOM
:
300 case E1000_DEV_ID_82540EP_LP
:
301 hw
->mac_type
= e1000_82540
;
303 case E1000_DEV_ID_82545EM_COPPER
:
304 case E1000_DEV_ID_82545EM_FIBER
:
305 hw
->mac_type
= e1000_82545
;
307 case E1000_DEV_ID_82545GM_COPPER
:
308 case E1000_DEV_ID_82545GM_FIBER
:
309 case E1000_DEV_ID_82545GM_SERDES
:
310 hw
->mac_type
= e1000_82545_rev_3
;
312 case E1000_DEV_ID_82546EB_COPPER
:
313 case E1000_DEV_ID_82546EB_FIBER
:
314 case E1000_DEV_ID_82546EB_QUAD_COPPER
:
315 hw
->mac_type
= e1000_82546
;
317 case E1000_DEV_ID_82546GB_COPPER
:
318 case E1000_DEV_ID_82546GB_FIBER
:
319 case E1000_DEV_ID_82546GB_SERDES
:
320 case E1000_DEV_ID_82546GB_PCIE
:
321 hw
->mac_type
= e1000_82546_rev_3
;
323 case E1000_DEV_ID_82541EI
:
324 case E1000_DEV_ID_82541EI_MOBILE
:
325 hw
->mac_type
= e1000_82541
;
327 case E1000_DEV_ID_82541ER
:
328 case E1000_DEV_ID_82541GI
:
329 case E1000_DEV_ID_82541GI_LF
:
330 case E1000_DEV_ID_82541GI_MOBILE
:
331 hw
->mac_type
= e1000_82541_rev_2
;
333 case E1000_DEV_ID_82547EI
:
334 hw
->mac_type
= e1000_82547
;
336 case E1000_DEV_ID_82547GI
:
337 hw
->mac_type
= e1000_82547_rev_2
;
339 case E1000_DEV_ID_82571EB_COPPER
:
340 case E1000_DEV_ID_82571EB_FIBER
:
341 case E1000_DEV_ID_82571EB_SERDES
:
342 hw
->mac_type
= e1000_82571
;
344 case E1000_DEV_ID_82572EI_COPPER
:
345 case E1000_DEV_ID_82572EI_FIBER
:
346 case E1000_DEV_ID_82572EI_SERDES
:
347 hw
->mac_type
= e1000_82572
;
349 case E1000_DEV_ID_82573E
:
350 case E1000_DEV_ID_82573E_IAMT
:
351 case E1000_DEV_ID_82573L
:
352 hw
->mac_type
= e1000_82573
;
355 /* Should never have loaded on this device */
356 return -E1000_ERR_MAC_TYPE
;
359 switch(hw
->mac_type
) {
363 hw
->eeprom_semaphore_present
= TRUE
;
367 case e1000_82541_rev_2
:
368 case e1000_82547_rev_2
:
369 hw
->asf_firmware_present
= TRUE
;
375 return E1000_SUCCESS
;
378 /*****************************************************************************
379 * Set media type and TBI compatibility.
381 * hw - Struct containing variables accessed by shared code
382 * **************************************************************************/
384 e1000_set_media_type(struct e1000_hw
*hw
)
388 DEBUGFUNC("e1000_set_media_type");
390 if(hw
->mac_type
!= e1000_82543
) {
391 /* tbi_compatibility is only valid on 82543 */
392 hw
->tbi_compatibility_en
= FALSE
;
395 switch (hw
->device_id
) {
396 case E1000_DEV_ID_82545GM_SERDES
:
397 case E1000_DEV_ID_82546GB_SERDES
:
398 case E1000_DEV_ID_82571EB_SERDES
:
399 case E1000_DEV_ID_82572EI_SERDES
:
400 hw
->media_type
= e1000_media_type_internal_serdes
;
403 switch (hw
->mac_type
) {
404 case e1000_82542_rev2_0
:
405 case e1000_82542_rev2_1
:
406 hw
->media_type
= e1000_media_type_fiber
;
409 /* The STATUS_TBIMODE bit is reserved or reused for the this
412 hw
->media_type
= e1000_media_type_copper
;
415 status
= E1000_READ_REG(hw
, STATUS
);
416 if (status
& E1000_STATUS_TBIMODE
) {
417 hw
->media_type
= e1000_media_type_fiber
;
418 /* tbi_compatibility not valid on fiber */
419 hw
->tbi_compatibility_en
= FALSE
;
421 hw
->media_type
= e1000_media_type_copper
;
428 /******************************************************************************
429 * Reset the transmit and receive units; mask and clear all interrupts.
431 * hw - Struct containing variables accessed by shared code
432 *****************************************************************************/
434 e1000_reset_hw(struct e1000_hw
*hw
)
442 uint32_t extcnf_ctrl
;
445 DEBUGFUNC("e1000_reset_hw");
447 /* For 82542 (rev 2.0), disable MWI before issuing a device reset */
448 if(hw
->mac_type
== e1000_82542_rev2_0
) {
449 DEBUGOUT("Disabling MWI on 82542 rev 2.0\n");
450 e1000_pci_clear_mwi(hw
);
453 if(hw
->bus_type
== e1000_bus_type_pci_express
) {
454 /* Prevent the PCI-E bus from sticking if there is no TLP connection
455 * on the last TLP read/write transaction when MAC is reset.
457 if(e1000_disable_pciex_master(hw
) != E1000_SUCCESS
) {
458 DEBUGOUT("PCI-E Master disable polling has failed.\n");
462 /* Clear interrupt mask to stop board from generating interrupts */
463 DEBUGOUT("Masking off all interrupts\n");
464 E1000_WRITE_REG(hw
, IMC
, 0xffffffff);
466 /* Disable the Transmit and Receive units. Then delay to allow
467 * any pending transactions to complete before we hit the MAC with
470 E1000_WRITE_REG(hw
, RCTL
, 0);
471 E1000_WRITE_REG(hw
, TCTL
, E1000_TCTL_PSP
);
472 E1000_WRITE_FLUSH(hw
);
474 /* The tbi_compatibility_on Flag must be cleared when Rctl is cleared. */
475 hw
->tbi_compatibility_on
= FALSE
;
477 /* Delay to allow any outstanding PCI transactions to complete before
478 * resetting the device
482 ctrl
= E1000_READ_REG(hw
, CTRL
);
484 /* Must reset the PHY before resetting the MAC */
485 if((hw
->mac_type
== e1000_82541
) || (hw
->mac_type
== e1000_82547
)) {
486 E1000_WRITE_REG(hw
, CTRL
, (ctrl
| E1000_CTRL_PHY_RST
));
490 /* Must acquire the MDIO ownership before MAC reset.
491 * Ownership defaults to firmware after a reset. */
492 if(hw
->mac_type
== e1000_82573
) {
495 extcnf_ctrl
= E1000_READ_REG(hw
, EXTCNF_CTRL
);
496 extcnf_ctrl
|= E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP
;
499 E1000_WRITE_REG(hw
, EXTCNF_CTRL
, extcnf_ctrl
);
500 extcnf_ctrl
= E1000_READ_REG(hw
, EXTCNF_CTRL
);
502 if(extcnf_ctrl
& E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP
)
505 extcnf_ctrl
|= E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP
;
512 /* Issue a global reset to the MAC. This will reset the chip's
513 * transmit, receive, DMA, and link units. It will not effect
514 * the current PCI configuration. The global reset bit is self-
515 * clearing, and should clear within a microsecond.
517 DEBUGOUT("Issuing a global reset to MAC\n");
519 switch(hw
->mac_type
) {
525 case e1000_82541_rev_2
:
526 /* These controllers can't ack the 64-bit write when issuing the
527 * reset, so use IO-mapping as a workaround to issue the reset */
528 E1000_WRITE_REG_IO(hw
, CTRL
, (ctrl
| E1000_CTRL_RST
));
530 case e1000_82545_rev_3
:
531 case e1000_82546_rev_3
:
532 /* Reset is performed on a shadow of the control register */
533 E1000_WRITE_REG(hw
, CTRL_DUP
, (ctrl
| E1000_CTRL_RST
));
536 E1000_WRITE_REG(hw
, CTRL
, (ctrl
| E1000_CTRL_RST
));
540 /* After MAC reset, force reload of EEPROM to restore power-on settings to
541 * device. Later controllers reload the EEPROM automatically, so just wait
542 * for reload to complete.
544 switch(hw
->mac_type
) {
545 case e1000_82542_rev2_0
:
546 case e1000_82542_rev2_1
:
549 /* Wait for reset to complete */
551 ctrl_ext
= E1000_READ_REG(hw
, CTRL_EXT
);
552 ctrl_ext
|= E1000_CTRL_EXT_EE_RST
;
553 E1000_WRITE_REG(hw
, CTRL_EXT
, ctrl_ext
);
554 E1000_WRITE_FLUSH(hw
);
555 /* Wait for EEPROM reload */
559 case e1000_82541_rev_2
:
561 case e1000_82547_rev_2
:
562 /* Wait for EEPROM reload */
566 if (e1000_is_onboard_nvm_eeprom(hw
) == FALSE
) {
568 ctrl_ext
= E1000_READ_REG(hw
, CTRL_EXT
);
569 ctrl_ext
|= E1000_CTRL_EXT_EE_RST
;
570 E1000_WRITE_REG(hw
, CTRL_EXT
, ctrl_ext
);
571 E1000_WRITE_FLUSH(hw
);
576 ret_val
= e1000_get_auto_rd_done(hw
);
578 /* We don't want to continue accessing MAC registers. */
582 /* Wait for EEPROM reload (it happens automatically) */
587 /* Disable HW ARPs on ASF enabled adapters */
588 if(hw
->mac_type
>= e1000_82540
&& hw
->mac_type
<= e1000_82547_rev_2
) {
589 manc
= E1000_READ_REG(hw
, MANC
);
590 manc
&= ~(E1000_MANC_ARP_EN
);
591 E1000_WRITE_REG(hw
, MANC
, manc
);
594 if((hw
->mac_type
== e1000_82541
) || (hw
->mac_type
== e1000_82547
)) {
595 e1000_phy_init_script(hw
);
597 /* Configure activity LED after PHY reset */
598 led_ctrl
= E1000_READ_REG(hw
, LEDCTL
);
599 led_ctrl
&= IGP_ACTIVITY_LED_MASK
;
600 led_ctrl
|= (IGP_ACTIVITY_LED_ENABLE
| IGP_LED3_MODE
);
601 E1000_WRITE_REG(hw
, LEDCTL
, led_ctrl
);
604 /* Clear interrupt mask to stop board from generating interrupts */
605 DEBUGOUT("Masking off all interrupts\n");
606 E1000_WRITE_REG(hw
, IMC
, 0xffffffff);
608 /* Clear any pending interrupt events. */
609 icr
= E1000_READ_REG(hw
, ICR
);
611 /* If MWI was previously enabled, reenable it. */
612 if(hw
->mac_type
== e1000_82542_rev2_0
) {
613 if(hw
->pci_cmd_word
& CMD_MEM_WRT_INVALIDATE
)
614 e1000_pci_set_mwi(hw
);
617 return E1000_SUCCESS
;
620 /******************************************************************************
621 * Performs basic configuration of the adapter.
623 * hw - Struct containing variables accessed by shared code
625 * Assumes that the controller has previously been reset and is in a
626 * post-reset uninitialized state. Initializes the receive address registers,
627 * multicast table, and VLAN filter table. Calls routines to setup link
628 * configuration and flow control settings. Clears all on-chip counters. Leaves
629 * the transmit and receive units disabled and uninitialized.
630 *****************************************************************************/
632 e1000_init_hw(struct e1000_hw
*hw
)
637 uint16_t pcix_cmd_word
;
638 uint16_t pcix_stat_hi_word
;
643 DEBUGFUNC("e1000_init_hw");
645 /* Initialize Identification LED */
646 ret_val
= e1000_id_led_init(hw
);
648 DEBUGOUT("Error Initializing Identification LED\n");
652 /* Set the media type and TBI compatibility */
653 e1000_set_media_type(hw
);
655 /* Disabling VLAN filtering. */
656 DEBUGOUT("Initializing the IEEE VLAN\n");
657 if (hw
->mac_type
< e1000_82545_rev_3
)
658 E1000_WRITE_REG(hw
, VET
, 0);
659 e1000_clear_vfta(hw
);
661 /* For 82542 (rev 2.0), disable MWI and put the receiver into reset */
662 if(hw
->mac_type
== e1000_82542_rev2_0
) {
663 DEBUGOUT("Disabling MWI on 82542 rev 2.0\n");
664 e1000_pci_clear_mwi(hw
);
665 E1000_WRITE_REG(hw
, RCTL
, E1000_RCTL_RST
);
666 E1000_WRITE_FLUSH(hw
);
670 /* Setup the receive address. This involves initializing all of the Receive
671 * Address Registers (RARs 0 - 15).
673 e1000_init_rx_addrs(hw
);
675 /* For 82542 (rev 2.0), take the receiver out of reset and enable MWI */
676 if(hw
->mac_type
== e1000_82542_rev2_0
) {
677 E1000_WRITE_REG(hw
, RCTL
, 0);
678 E1000_WRITE_FLUSH(hw
);
680 if(hw
->pci_cmd_word
& CMD_MEM_WRT_INVALIDATE
)
681 e1000_pci_set_mwi(hw
);
684 /* Zero out the Multicast HASH table */
685 DEBUGOUT("Zeroing the MTA\n");
686 mta_size
= E1000_MC_TBL_SIZE
;
687 for(i
= 0; i
< mta_size
; i
++)
688 E1000_WRITE_REG_ARRAY(hw
, MTA
, i
, 0);
690 /* Set the PCI priority bit correctly in the CTRL register. This
691 * determines if the adapter gives priority to receives, or if it
692 * gives equal priority to transmits and receives. Valid only on
693 * 82542 and 82543 silicon.
695 if(hw
->dma_fairness
&& hw
->mac_type
<= e1000_82543
) {
696 ctrl
= E1000_READ_REG(hw
, CTRL
);
697 E1000_WRITE_REG(hw
, CTRL
, ctrl
| E1000_CTRL_PRIOR
);
700 switch(hw
->mac_type
) {
701 case e1000_82545_rev_3
:
702 case e1000_82546_rev_3
:
705 /* Workaround for PCI-X problem when BIOS sets MMRBC incorrectly. */
706 if(hw
->bus_type
== e1000_bus_type_pcix
) {
707 e1000_read_pci_cfg(hw
, PCIX_COMMAND_REGISTER
, &pcix_cmd_word
);
708 e1000_read_pci_cfg(hw
, PCIX_STATUS_REGISTER_HI
,
710 cmd_mmrbc
= (pcix_cmd_word
& PCIX_COMMAND_MMRBC_MASK
) >>
711 PCIX_COMMAND_MMRBC_SHIFT
;
712 stat_mmrbc
= (pcix_stat_hi_word
& PCIX_STATUS_HI_MMRBC_MASK
) >>
713 PCIX_STATUS_HI_MMRBC_SHIFT
;
714 if(stat_mmrbc
== PCIX_STATUS_HI_MMRBC_4K
)
715 stat_mmrbc
= PCIX_STATUS_HI_MMRBC_2K
;
716 if(cmd_mmrbc
> stat_mmrbc
) {
717 pcix_cmd_word
&= ~PCIX_COMMAND_MMRBC_MASK
;
718 pcix_cmd_word
|= stat_mmrbc
<< PCIX_COMMAND_MMRBC_SHIFT
;
719 e1000_write_pci_cfg(hw
, PCIX_COMMAND_REGISTER
,
726 /* Call a subroutine to configure the link and setup flow control. */
727 ret_val
= e1000_setup_link(hw
);
729 /* Set the transmit descriptor write-back policy */
730 if(hw
->mac_type
> e1000_82544
) {
731 ctrl
= E1000_READ_REG(hw
, TXDCTL
);
732 ctrl
= (ctrl
& ~E1000_TXDCTL_WTHRESH
) | E1000_TXDCTL_FULL_TX_DESC_WB
;
733 switch (hw
->mac_type
) {
739 ctrl
|= E1000_TXDCTL_COUNT_DESC
;
742 E1000_WRITE_REG(hw
, TXDCTL
, ctrl
);
745 if (hw
->mac_type
== e1000_82573
) {
746 e1000_enable_tx_pkt_filtering(hw
);
749 switch (hw
->mac_type
) {
754 ctrl
= E1000_READ_REG(hw
, TXDCTL1
);
755 ctrl
&= ~E1000_TXDCTL_WTHRESH
;
756 ctrl
|= E1000_TXDCTL_COUNT_DESC
| E1000_TXDCTL_FULL_TX_DESC_WB
;
758 E1000_WRITE_REG(hw
, TXDCTL1
, ctrl
);
764 if (hw
->mac_type
== e1000_82573
) {
765 uint32_t gcr
= E1000_READ_REG(hw
, GCR
);
766 gcr
|= E1000_GCR_L1_ACT_WITHOUT_L0S_RX
;
767 E1000_WRITE_REG(hw
, GCR
, gcr
);
770 /* Clear all of the statistics registers (clear on read). It is
771 * important that we do this after we have tried to establish link
772 * because the symbol error count will increment wildly if there
775 e1000_clear_hw_cntrs(hw
);
780 /******************************************************************************
781 * Adjust SERDES output amplitude based on EEPROM setting.
783 * hw - Struct containing variables accessed by shared code.
784 *****************************************************************************/
786 e1000_adjust_serdes_amplitude(struct e1000_hw
*hw
)
788 uint16_t eeprom_data
;
791 DEBUGFUNC("e1000_adjust_serdes_amplitude");
793 if(hw
->media_type
!= e1000_media_type_internal_serdes
)
794 return E1000_SUCCESS
;
796 switch(hw
->mac_type
) {
797 case e1000_82545_rev_3
:
798 case e1000_82546_rev_3
:
801 return E1000_SUCCESS
;
804 ret_val
= e1000_read_eeprom(hw
, EEPROM_SERDES_AMPLITUDE
, 1, &eeprom_data
);
809 if(eeprom_data
!= EEPROM_RESERVED_WORD
) {
810 /* Adjust SERDES output amplitude only. */
811 eeprom_data
&= EEPROM_SERDES_AMPLITUDE_MASK
;
812 ret_val
= e1000_write_phy_reg(hw
, M88E1000_PHY_EXT_CTRL
, eeprom_data
);
817 return E1000_SUCCESS
;
820 /******************************************************************************
821 * Configures flow control and link settings.
823 * hw - Struct containing variables accessed by shared code
825 * Determines which flow control settings to use. Calls the apropriate media-
826 * specific link configuration function. Configures the flow control settings.
827 * Assuming the adapter has a valid link partner, a valid link should be
828 * established. Assumes the hardware has previously been reset and the
829 * transmitter and receiver are not enabled.
830 *****************************************************************************/
832 e1000_setup_link(struct e1000_hw
*hw
)
836 uint16_t eeprom_data
;
838 DEBUGFUNC("e1000_setup_link");
840 /* In the case of the phy reset being blocked, we already have a link.
841 * We do not have to set it up again. */
842 if (e1000_check_phy_reset_block(hw
))
843 return E1000_SUCCESS
;
845 /* Read and store word 0x0F of the EEPROM. This word contains bits
846 * that determine the hardware's default PAUSE (flow control) mode,
847 * a bit that determines whether the HW defaults to enabling or
848 * disabling auto-negotiation, and the direction of the
849 * SW defined pins. If there is no SW over-ride of the flow
850 * control setting, then the variable hw->fc will
851 * be initialized based on a value in the EEPROM.
853 if (hw
->fc
== e1000_fc_default
) {
854 switch (hw
->mac_type
) {
856 hw
->fc
= e1000_fc_full
;
859 ret_val
= e1000_read_eeprom(hw
, EEPROM_INIT_CONTROL2_REG
,
862 DEBUGOUT("EEPROM Read Error\n");
863 return -E1000_ERR_EEPROM
;
865 if ((eeprom_data
& EEPROM_WORD0F_PAUSE_MASK
) == 0)
866 hw
->fc
= e1000_fc_none
;
867 else if ((eeprom_data
& EEPROM_WORD0F_PAUSE_MASK
) ==
868 EEPROM_WORD0F_ASM_DIR
)
869 hw
->fc
= e1000_fc_tx_pause
;
871 hw
->fc
= e1000_fc_full
;
876 /* We want to save off the original Flow Control configuration just
877 * in case we get disconnected and then reconnected into a different
878 * hub or switch with different Flow Control capabilities.
880 if(hw
->mac_type
== e1000_82542_rev2_0
)
881 hw
->fc
&= (~e1000_fc_tx_pause
);
883 if((hw
->mac_type
< e1000_82543
) && (hw
->report_tx_early
== 1))
884 hw
->fc
&= (~e1000_fc_rx_pause
);
886 hw
->original_fc
= hw
->fc
;
888 DEBUGOUT1("After fix-ups FlowControl is now = %x\n", hw
->fc
);
890 /* Take the 4 bits from EEPROM word 0x0F that determine the initial
891 * polarity value for the SW controlled pins, and setup the
892 * Extended Device Control reg with that info.
893 * This is needed because one of the SW controlled pins is used for
894 * signal detection. So this should be done before e1000_setup_pcs_link()
895 * or e1000_phy_setup() is called.
897 if(hw
->mac_type
== e1000_82543
) {
898 ctrl_ext
= ((eeprom_data
& EEPROM_WORD0F_SWPDIO_EXT
) <<
900 E1000_WRITE_REG(hw
, CTRL_EXT
, ctrl_ext
);
903 /* Call the necessary subroutine to configure the link. */
904 ret_val
= (hw
->media_type
== e1000_media_type_copper
) ?
905 e1000_setup_copper_link(hw
) :
906 e1000_setup_fiber_serdes_link(hw
);
908 /* Initialize the flow control address, type, and PAUSE timer
909 * registers to their default values. This is done even if flow
910 * control is disabled, because it does not hurt anything to
911 * initialize these registers.
913 DEBUGOUT("Initializing the Flow Control address, type and timer regs\n");
915 E1000_WRITE_REG(hw
, FCAL
, FLOW_CONTROL_ADDRESS_LOW
);
916 E1000_WRITE_REG(hw
, FCAH
, FLOW_CONTROL_ADDRESS_HIGH
);
917 E1000_WRITE_REG(hw
, FCT
, FLOW_CONTROL_TYPE
);
919 E1000_WRITE_REG(hw
, FCTTV
, hw
->fc_pause_time
);
921 /* Set the flow control receive threshold registers. Normally,
922 * these registers will be set to a default threshold that may be
923 * adjusted later by the driver's runtime code. However, if the
924 * ability to transmit pause frames in not enabled, then these
925 * registers will be set to 0.
927 if(!(hw
->fc
& e1000_fc_tx_pause
)) {
928 E1000_WRITE_REG(hw
, FCRTL
, 0);
929 E1000_WRITE_REG(hw
, FCRTH
, 0);
931 /* We need to set up the Receive Threshold high and low water marks
932 * as well as (optionally) enabling the transmission of XON frames.
934 if(hw
->fc_send_xon
) {
935 E1000_WRITE_REG(hw
, FCRTL
, (hw
->fc_low_water
| E1000_FCRTL_XONE
));
936 E1000_WRITE_REG(hw
, FCRTH
, hw
->fc_high_water
);
938 E1000_WRITE_REG(hw
, FCRTL
, hw
->fc_low_water
);
939 E1000_WRITE_REG(hw
, FCRTH
, hw
->fc_high_water
);
945 /******************************************************************************
946 * Sets up link for a fiber based or serdes based adapter
948 * hw - Struct containing variables accessed by shared code
950 * Manipulates Physical Coding Sublayer functions in order to configure
951 * link. Assumes the hardware has been previously reset and the transmitter
952 * and receiver are not enabled.
953 *****************************************************************************/
955 e1000_setup_fiber_serdes_link(struct e1000_hw
*hw
)
964 DEBUGFUNC("e1000_setup_fiber_serdes_link");
966 /* On 82571 and 82572 Fiber connections, SerDes loopback mode persists
967 * until explicitly turned off or a power cycle is performed. A read to
968 * the register does not indicate its status. Therefore, we ensure
969 * loopback mode is disabled during initialization.
971 if (hw
->mac_type
== e1000_82571
|| hw
->mac_type
== e1000_82572
)
972 E1000_WRITE_REG(hw
, SCTL
, E1000_DISABLE_SERDES_LOOPBACK
);
974 /* On adapters with a MAC newer than 82544, SW Defineable pin 1 will be
975 * set when the optics detect a signal. On older adapters, it will be
976 * cleared when there is a signal. This applies to fiber media only.
977 * If we're on serdes media, adjust the output amplitude to value set in
980 ctrl
= E1000_READ_REG(hw
, CTRL
);
981 if(hw
->media_type
== e1000_media_type_fiber
)
982 signal
= (hw
->mac_type
> e1000_82544
) ? E1000_CTRL_SWDPIN1
: 0;
984 ret_val
= e1000_adjust_serdes_amplitude(hw
);
988 /* Take the link out of reset */
989 ctrl
&= ~(E1000_CTRL_LRST
);
991 /* Adjust VCO speed to improve BER performance */
992 ret_val
= e1000_set_vco_speed(hw
);
996 e1000_config_collision_dist(hw
);
998 /* Check for a software override of the flow control settings, and setup
999 * the device accordingly. If auto-negotiation is enabled, then software
1000 * will have to set the "PAUSE" bits to the correct value in the Tranmsit
1001 * Config Word Register (TXCW) and re-start auto-negotiation. However, if
1002 * auto-negotiation is disabled, then software will have to manually
1003 * configure the two flow control enable bits in the CTRL register.
1005 * The possible values of the "fc" parameter are:
1006 * 0: Flow control is completely disabled
1007 * 1: Rx flow control is enabled (we can receive pause frames, but
1008 * not send pause frames).
1009 * 2: Tx flow control is enabled (we can send pause frames but we do
1010 * not support receiving pause frames).
1011 * 3: Both Rx and TX flow control (symmetric) are enabled.
1015 /* Flow control is completely disabled by a software over-ride. */
1016 txcw
= (E1000_TXCW_ANE
| E1000_TXCW_FD
);
1018 case e1000_fc_rx_pause
:
1019 /* RX Flow control is enabled and TX Flow control is disabled by a
1020 * software over-ride. Since there really isn't a way to advertise
1021 * that we are capable of RX Pause ONLY, we will advertise that we
1022 * support both symmetric and asymmetric RX PAUSE. Later, we will
1023 * disable the adapter's ability to send PAUSE frames.
1025 txcw
= (E1000_TXCW_ANE
| E1000_TXCW_FD
| E1000_TXCW_PAUSE_MASK
);
1027 case e1000_fc_tx_pause
:
1028 /* TX Flow control is enabled, and RX Flow control is disabled, by a
1029 * software over-ride.
1031 txcw
= (E1000_TXCW_ANE
| E1000_TXCW_FD
| E1000_TXCW_ASM_DIR
);
1034 /* Flow control (both RX and TX) is enabled by a software over-ride. */
1035 txcw
= (E1000_TXCW_ANE
| E1000_TXCW_FD
| E1000_TXCW_PAUSE_MASK
);
1038 DEBUGOUT("Flow control param set incorrectly\n");
1039 return -E1000_ERR_CONFIG
;
1043 /* Since auto-negotiation is enabled, take the link out of reset (the link
1044 * will be in reset, because we previously reset the chip). This will
1045 * restart auto-negotiation. If auto-neogtiation is successful then the
1046 * link-up status bit will be set and the flow control enable bits (RFCE
1047 * and TFCE) will be set according to their negotiated value.
1049 DEBUGOUT("Auto-negotiation enabled\n");
1051 E1000_WRITE_REG(hw
, TXCW
, txcw
);
1052 E1000_WRITE_REG(hw
, CTRL
, ctrl
);
1053 E1000_WRITE_FLUSH(hw
);
1058 /* If we have a signal (the cable is plugged in) then poll for a "Link-Up"
1059 * indication in the Device Status Register. Time-out if a link isn't
1060 * seen in 500 milliseconds seconds (Auto-negotiation should complete in
1061 * less than 500 milliseconds even if the other end is doing it in SW).
1062 * For internal serdes, we just assume a signal is present, then poll.
1064 if(hw
->media_type
== e1000_media_type_internal_serdes
||
1065 (E1000_READ_REG(hw
, CTRL
) & E1000_CTRL_SWDPIN1
) == signal
) {
1066 DEBUGOUT("Looking for Link\n");
1067 for(i
= 0; i
< (LINK_UP_TIMEOUT
/ 10); i
++) {
1069 status
= E1000_READ_REG(hw
, STATUS
);
1070 if(status
& E1000_STATUS_LU
) break;
1072 if(i
== (LINK_UP_TIMEOUT
/ 10)) {
1073 DEBUGOUT("Never got a valid link from auto-neg!!!\n");
1074 hw
->autoneg_failed
= 1;
1075 /* AutoNeg failed to achieve a link, so we'll call
1076 * e1000_check_for_link. This routine will force the link up if
1077 * we detect a signal. This will allow us to communicate with
1078 * non-autonegotiating link partners.
1080 ret_val
= e1000_check_for_link(hw
);
1082 DEBUGOUT("Error while checking for link\n");
1085 hw
->autoneg_failed
= 0;
1087 hw
->autoneg_failed
= 0;
1088 DEBUGOUT("Valid Link Found\n");
1091 DEBUGOUT("No Signal Detected\n");
1093 return E1000_SUCCESS
;
1096 /******************************************************************************
1097 * Make sure we have a valid PHY and change PHY mode before link setup.
1099 * hw - Struct containing variables accessed by shared code
1100 ******************************************************************************/
1102 e1000_copper_link_preconfig(struct e1000_hw
*hw
)
1108 DEBUGFUNC("e1000_copper_link_preconfig");
1110 ctrl
= E1000_READ_REG(hw
, CTRL
);
1111 /* With 82543, we need to force speed and duplex on the MAC equal to what
1112 * the PHY speed and duplex configuration is. In addition, we need to
1113 * perform a hardware reset on the PHY to take it out of reset.
1115 if(hw
->mac_type
> e1000_82543
) {
1116 ctrl
|= E1000_CTRL_SLU
;
1117 ctrl
&= ~(E1000_CTRL_FRCSPD
| E1000_CTRL_FRCDPX
);
1118 E1000_WRITE_REG(hw
, CTRL
, ctrl
);
1120 ctrl
|= (E1000_CTRL_FRCSPD
| E1000_CTRL_FRCDPX
| E1000_CTRL_SLU
);
1121 E1000_WRITE_REG(hw
, CTRL
, ctrl
);
1122 ret_val
= e1000_phy_hw_reset(hw
);
1127 /* Make sure we have a valid PHY */
1128 ret_val
= e1000_detect_gig_phy(hw
);
1130 DEBUGOUT("Error, did not detect valid phy.\n");
1133 DEBUGOUT1("Phy ID = %x \n", hw
->phy_id
);
1135 /* Set PHY to class A mode (if necessary) */
1136 ret_val
= e1000_set_phy_mode(hw
);
1140 if((hw
->mac_type
== e1000_82545_rev_3
) ||
1141 (hw
->mac_type
== e1000_82546_rev_3
)) {
1142 ret_val
= e1000_read_phy_reg(hw
, M88E1000_PHY_SPEC_CTRL
, &phy_data
);
1143 phy_data
|= 0x00000008;
1144 ret_val
= e1000_write_phy_reg(hw
, M88E1000_PHY_SPEC_CTRL
, phy_data
);
1147 if(hw
->mac_type
<= e1000_82543
||
1148 hw
->mac_type
== e1000_82541
|| hw
->mac_type
== e1000_82547
||
1149 hw
->mac_type
== e1000_82541_rev_2
|| hw
->mac_type
== e1000_82547_rev_2
)
1150 hw
->phy_reset_disable
= FALSE
;
1152 return E1000_SUCCESS
;
1156 /********************************************************************
1157 * Copper link setup for e1000_phy_igp series.
1159 * hw - Struct containing variables accessed by shared code
1160 *********************************************************************/
1162 e1000_copper_link_igp_setup(struct e1000_hw
*hw
)
1168 DEBUGFUNC("e1000_copper_link_igp_setup");
1170 if (hw
->phy_reset_disable
)
1171 return E1000_SUCCESS
;
1173 ret_val
= e1000_phy_reset(hw
);
1175 DEBUGOUT("Error Resetting the PHY\n");
1179 /* Wait 10ms for MAC to configure PHY from eeprom settings */
1182 /* Configure activity LED after PHY reset */
1183 led_ctrl
= E1000_READ_REG(hw
, LEDCTL
);
1184 led_ctrl
&= IGP_ACTIVITY_LED_MASK
;
1185 led_ctrl
|= (IGP_ACTIVITY_LED_ENABLE
| IGP_LED3_MODE
);
1186 E1000_WRITE_REG(hw
, LEDCTL
, led_ctrl
);
1188 /* disable lplu d3 during driver init */
1189 ret_val
= e1000_set_d3_lplu_state(hw
, FALSE
);
1191 DEBUGOUT("Error Disabling LPLU D3\n");
1195 /* disable lplu d0 during driver init */
1196 ret_val
= e1000_set_d0_lplu_state(hw
, FALSE
);
1198 DEBUGOUT("Error Disabling LPLU D0\n");
1201 /* Configure mdi-mdix settings */
1202 ret_val
= e1000_read_phy_reg(hw
, IGP01E1000_PHY_PORT_CTRL
, &phy_data
);
1206 if ((hw
->mac_type
== e1000_82541
) || (hw
->mac_type
== e1000_82547
)) {
1207 hw
->dsp_config_state
= e1000_dsp_config_disabled
;
1208 /* Force MDI for earlier revs of the IGP PHY */
1209 phy_data
&= ~(IGP01E1000_PSCR_AUTO_MDIX
| IGP01E1000_PSCR_FORCE_MDI_MDIX
);
1213 hw
->dsp_config_state
= e1000_dsp_config_enabled
;
1214 phy_data
&= ~IGP01E1000_PSCR_AUTO_MDIX
;
1218 phy_data
&= ~IGP01E1000_PSCR_FORCE_MDI_MDIX
;
1221 phy_data
|= IGP01E1000_PSCR_FORCE_MDI_MDIX
;
1225 phy_data
|= IGP01E1000_PSCR_AUTO_MDIX
;
1229 ret_val
= e1000_write_phy_reg(hw
, IGP01E1000_PHY_PORT_CTRL
, phy_data
);
1233 /* set auto-master slave resolution settings */
1235 e1000_ms_type phy_ms_setting
= hw
->master_slave
;
1237 if(hw
->ffe_config_state
== e1000_ffe_config_active
)
1238 hw
->ffe_config_state
= e1000_ffe_config_enabled
;
1240 if(hw
->dsp_config_state
== e1000_dsp_config_activated
)
1241 hw
->dsp_config_state
= e1000_dsp_config_enabled
;
1243 /* when autonegotiation advertisment is only 1000Mbps then we
1244 * should disable SmartSpeed and enable Auto MasterSlave
1245 * resolution as hardware default. */
1246 if(hw
->autoneg_advertised
== ADVERTISE_1000_FULL
) {
1247 /* Disable SmartSpeed */
1248 ret_val
= e1000_read_phy_reg(hw
, IGP01E1000_PHY_PORT_CONFIG
, &phy_data
);
1251 phy_data
&= ~IGP01E1000_PSCFR_SMART_SPEED
;
1252 ret_val
= e1000_write_phy_reg(hw
,
1253 IGP01E1000_PHY_PORT_CONFIG
,
1257 /* Set auto Master/Slave resolution process */
1258 ret_val
= e1000_read_phy_reg(hw
, PHY_1000T_CTRL
, &phy_data
);
1261 phy_data
&= ~CR_1000T_MS_ENABLE
;
1262 ret_val
= e1000_write_phy_reg(hw
, PHY_1000T_CTRL
, phy_data
);
1267 ret_val
= e1000_read_phy_reg(hw
, PHY_1000T_CTRL
, &phy_data
);
1271 /* load defaults for future use */
1272 hw
->original_master_slave
= (phy_data
& CR_1000T_MS_ENABLE
) ?
1273 ((phy_data
& CR_1000T_MS_VALUE
) ?
1274 e1000_ms_force_master
:
1275 e1000_ms_force_slave
) :
1278 switch (phy_ms_setting
) {
1279 case e1000_ms_force_master
:
1280 phy_data
|= (CR_1000T_MS_ENABLE
| CR_1000T_MS_VALUE
);
1282 case e1000_ms_force_slave
:
1283 phy_data
|= CR_1000T_MS_ENABLE
;
1284 phy_data
&= ~(CR_1000T_MS_VALUE
);
1287 phy_data
&= ~CR_1000T_MS_ENABLE
;
1291 ret_val
= e1000_write_phy_reg(hw
, PHY_1000T_CTRL
, phy_data
);
1296 return E1000_SUCCESS
;
1300 /********************************************************************
1301 * Copper link setup for e1000_phy_m88 series.
1303 * hw - Struct containing variables accessed by shared code
1304 *********************************************************************/
1306 e1000_copper_link_mgp_setup(struct e1000_hw
*hw
)
1311 DEBUGFUNC("e1000_copper_link_mgp_setup");
1313 if(hw
->phy_reset_disable
)
1314 return E1000_SUCCESS
;
1316 /* Enable CRS on TX. This must be set for half-duplex operation. */
1317 ret_val
= e1000_read_phy_reg(hw
, M88E1000_PHY_SPEC_CTRL
, &phy_data
);
1321 phy_data
|= M88E1000_PSCR_ASSERT_CRS_ON_TX
;
1324 * MDI/MDI-X = 0 (default)
1325 * 0 - Auto for all speeds
1328 * 3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes)
1330 phy_data
&= ~M88E1000_PSCR_AUTO_X_MODE
;
1334 phy_data
|= M88E1000_PSCR_MDI_MANUAL_MODE
;
1337 phy_data
|= M88E1000_PSCR_MDIX_MANUAL_MODE
;
1340 phy_data
|= M88E1000_PSCR_AUTO_X_1000T
;
1344 phy_data
|= M88E1000_PSCR_AUTO_X_MODE
;
1349 * disable_polarity_correction = 0 (default)
1350 * Automatic Correction for Reversed Cable Polarity
1354 phy_data
&= ~M88E1000_PSCR_POLARITY_REVERSAL
;
1355 if(hw
->disable_polarity_correction
== 1)
1356 phy_data
|= M88E1000_PSCR_POLARITY_REVERSAL
;
1357 ret_val
= e1000_write_phy_reg(hw
, M88E1000_PHY_SPEC_CTRL
, phy_data
);
1361 /* Force TX_CLK in the Extended PHY Specific Control Register
1364 ret_val
= e1000_read_phy_reg(hw
, M88E1000_EXT_PHY_SPEC_CTRL
, &phy_data
);
1368 phy_data
|= M88E1000_EPSCR_TX_CLK_25
;
1370 if (hw
->phy_revision
< M88E1011_I_REV_4
) {
1371 /* Configure Master and Slave downshift values */
1372 phy_data
&= ~(M88E1000_EPSCR_MASTER_DOWNSHIFT_MASK
|
1373 M88E1000_EPSCR_SLAVE_DOWNSHIFT_MASK
);
1374 phy_data
|= (M88E1000_EPSCR_MASTER_DOWNSHIFT_1X
|
1375 M88E1000_EPSCR_SLAVE_DOWNSHIFT_1X
);
1376 ret_val
= e1000_write_phy_reg(hw
, M88E1000_EXT_PHY_SPEC_CTRL
, phy_data
);
1381 /* SW Reset the PHY so all changes take effect */
1382 ret_val
= e1000_phy_reset(hw
);
1384 DEBUGOUT("Error Resetting the PHY\n");
1388 return E1000_SUCCESS
;
1391 /********************************************************************
1392 * Setup auto-negotiation and flow control advertisements,
1393 * and then perform auto-negotiation.
1395 * hw - Struct containing variables accessed by shared code
1396 *********************************************************************/
1398 e1000_copper_link_autoneg(struct e1000_hw
*hw
)
1403 DEBUGFUNC("e1000_copper_link_autoneg");
1405 /* Perform some bounds checking on the hw->autoneg_advertised
1406 * parameter. If this variable is zero, then set it to the default.
1408 hw
->autoneg_advertised
&= AUTONEG_ADVERTISE_SPEED_DEFAULT
;
1410 /* If autoneg_advertised is zero, we assume it was not defaulted
1411 * by the calling code so we set to advertise full capability.
1413 if(hw
->autoneg_advertised
== 0)
1414 hw
->autoneg_advertised
= AUTONEG_ADVERTISE_SPEED_DEFAULT
;
1416 DEBUGOUT("Reconfiguring auto-neg advertisement params\n");
1417 ret_val
= e1000_phy_setup_autoneg(hw
);
1419 DEBUGOUT("Error Setting up Auto-Negotiation\n");
1422 DEBUGOUT("Restarting Auto-Neg\n");
1424 /* Restart auto-negotiation by setting the Auto Neg Enable bit and
1425 * the Auto Neg Restart bit in the PHY control register.
1427 ret_val
= e1000_read_phy_reg(hw
, PHY_CTRL
, &phy_data
);
1431 phy_data
|= (MII_CR_AUTO_NEG_EN
| MII_CR_RESTART_AUTO_NEG
);
1432 ret_val
= e1000_write_phy_reg(hw
, PHY_CTRL
, phy_data
);
1436 /* Does the user want to wait for Auto-Neg to complete here, or
1437 * check at a later time (for example, callback routine).
1439 if(hw
->wait_autoneg_complete
) {
1440 ret_val
= e1000_wait_autoneg(hw
);
1442 DEBUGOUT("Error while waiting for autoneg to complete\n");
1447 hw
->get_link_status
= TRUE
;
1449 return E1000_SUCCESS
;
1453 /******************************************************************************
1454 * Config the MAC and the PHY after link is up.
1455 * 1) Set up the MAC to the current PHY speed/duplex
1456 * if we are on 82543. If we
1457 * are on newer silicon, we only need to configure
1458 * collision distance in the Transmit Control Register.
1459 * 2) Set up flow control on the MAC to that established with
1461 * 3) Config DSP to improve Gigabit link quality for some PHY revisions.
1463 * hw - Struct containing variables accessed by shared code
1464 ******************************************************************************/
1466 e1000_copper_link_postconfig(struct e1000_hw
*hw
)
1469 DEBUGFUNC("e1000_copper_link_postconfig");
1471 if(hw
->mac_type
>= e1000_82544
) {
1472 e1000_config_collision_dist(hw
);
1474 ret_val
= e1000_config_mac_to_phy(hw
);
1476 DEBUGOUT("Error configuring MAC to PHY settings\n");
1480 ret_val
= e1000_config_fc_after_link_up(hw
);
1482 DEBUGOUT("Error Configuring Flow Control\n");
1486 /* Config DSP to improve Giga link quality */
1487 if(hw
->phy_type
== e1000_phy_igp
) {
1488 ret_val
= e1000_config_dsp_after_link_change(hw
, TRUE
);
1490 DEBUGOUT("Error Configuring DSP after link up\n");
1495 return E1000_SUCCESS
;
1498 /******************************************************************************
1499 * Detects which PHY is present and setup the speed and duplex
1501 * hw - Struct containing variables accessed by shared code
1502 ******************************************************************************/
1504 e1000_setup_copper_link(struct e1000_hw
*hw
)
1510 DEBUGFUNC("e1000_setup_copper_link");
1512 /* Check if it is a valid PHY and set PHY mode if necessary. */
1513 ret_val
= e1000_copper_link_preconfig(hw
);
1517 if (hw
->phy_type
== e1000_phy_igp
||
1518 hw
->phy_type
== e1000_phy_igp_2
) {
1519 ret_val
= e1000_copper_link_igp_setup(hw
);
1522 } else if (hw
->phy_type
== e1000_phy_m88
) {
1523 ret_val
= e1000_copper_link_mgp_setup(hw
);
1529 /* Setup autoneg and flow control advertisement
1530 * and perform autonegotiation */
1531 ret_val
= e1000_copper_link_autoneg(hw
);
1535 /* PHY will be set to 10H, 10F, 100H,or 100F
1536 * depending on value from forced_speed_duplex. */
1537 DEBUGOUT("Forcing speed and duplex\n");
1538 ret_val
= e1000_phy_force_speed_duplex(hw
);
1540 DEBUGOUT("Error Forcing Speed and Duplex\n");
1545 /* Check link status. Wait up to 100 microseconds for link to become
1548 for(i
= 0; i
< 10; i
++) {
1549 ret_val
= e1000_read_phy_reg(hw
, PHY_STATUS
, &phy_data
);
1552 ret_val
= e1000_read_phy_reg(hw
, PHY_STATUS
, &phy_data
);
1556 if(phy_data
& MII_SR_LINK_STATUS
) {
1557 /* Config the MAC and PHY after link is up */
1558 ret_val
= e1000_copper_link_postconfig(hw
);
1562 DEBUGOUT("Valid link established!!!\n");
1563 return E1000_SUCCESS
;
1568 DEBUGOUT("Unable to establish link!!!\n");
1569 return E1000_SUCCESS
;
1572 /******************************************************************************
1573 * Configures PHY autoneg and flow control advertisement settings
1575 * hw - Struct containing variables accessed by shared code
1576 ******************************************************************************/
1578 e1000_phy_setup_autoneg(struct e1000_hw
*hw
)
1581 uint16_t mii_autoneg_adv_reg
;
1582 uint16_t mii_1000t_ctrl_reg
;
1584 DEBUGFUNC("e1000_phy_setup_autoneg");
1586 /* Read the MII Auto-Neg Advertisement Register (Address 4). */
1587 ret_val
= e1000_read_phy_reg(hw
, PHY_AUTONEG_ADV
, &mii_autoneg_adv_reg
);
1591 /* Read the MII 1000Base-T Control Register (Address 9). */
1592 ret_val
= e1000_read_phy_reg(hw
, PHY_1000T_CTRL
, &mii_1000t_ctrl_reg
);
1596 /* Need to parse both autoneg_advertised and fc and set up
1597 * the appropriate PHY registers. First we will parse for
1598 * autoneg_advertised software override. Since we can advertise
1599 * a plethora of combinations, we need to check each bit
1603 /* First we clear all the 10/100 mb speed bits in the Auto-Neg
1604 * Advertisement Register (Address 4) and the 1000 mb speed bits in
1605 * the 1000Base-T Control Register (Address 9).
1607 mii_autoneg_adv_reg
&= ~REG4_SPEED_MASK
;
1608 mii_1000t_ctrl_reg
&= ~REG9_SPEED_MASK
;
1610 DEBUGOUT1("autoneg_advertised %x\n", hw
->autoneg_advertised
);
1612 /* Do we want to advertise 10 Mb Half Duplex? */
1613 if(hw
->autoneg_advertised
& ADVERTISE_10_HALF
) {
1614 DEBUGOUT("Advertise 10mb Half duplex\n");
1615 mii_autoneg_adv_reg
|= NWAY_AR_10T_HD_CAPS
;
1618 /* Do we want to advertise 10 Mb Full Duplex? */
1619 if(hw
->autoneg_advertised
& ADVERTISE_10_FULL
) {
1620 DEBUGOUT("Advertise 10mb Full duplex\n");
1621 mii_autoneg_adv_reg
|= NWAY_AR_10T_FD_CAPS
;
1624 /* Do we want to advertise 100 Mb Half Duplex? */
1625 if(hw
->autoneg_advertised
& ADVERTISE_100_HALF
) {
1626 DEBUGOUT("Advertise 100mb Half duplex\n");
1627 mii_autoneg_adv_reg
|= NWAY_AR_100TX_HD_CAPS
;
1630 /* Do we want to advertise 100 Mb Full Duplex? */
1631 if(hw
->autoneg_advertised
& ADVERTISE_100_FULL
) {
1632 DEBUGOUT("Advertise 100mb Full duplex\n");
1633 mii_autoneg_adv_reg
|= NWAY_AR_100TX_FD_CAPS
;
1636 /* We do not allow the Phy to advertise 1000 Mb Half Duplex */
1637 if(hw
->autoneg_advertised
& ADVERTISE_1000_HALF
) {
1638 DEBUGOUT("Advertise 1000mb Half duplex requested, request denied!\n");
1641 /* Do we want to advertise 1000 Mb Full Duplex? */
1642 if(hw
->autoneg_advertised
& ADVERTISE_1000_FULL
) {
1643 DEBUGOUT("Advertise 1000mb Full duplex\n");
1644 mii_1000t_ctrl_reg
|= CR_1000T_FD_CAPS
;
1647 /* Check for a software override of the flow control settings, and
1648 * setup the PHY advertisement registers accordingly. If
1649 * auto-negotiation is enabled, then software will have to set the
1650 * "PAUSE" bits to the correct value in the Auto-Negotiation
1651 * Advertisement Register (PHY_AUTONEG_ADV) and re-start auto-negotiation.
1653 * The possible values of the "fc" parameter are:
1654 * 0: Flow control is completely disabled
1655 * 1: Rx flow control is enabled (we can receive pause frames
1656 * but not send pause frames).
1657 * 2: Tx flow control is enabled (we can send pause frames
1658 * but we do not support receiving pause frames).
1659 * 3: Both Rx and TX flow control (symmetric) are enabled.
1660 * other: No software override. The flow control configuration
1661 * in the EEPROM is used.
1664 case e1000_fc_none
: /* 0 */
1665 /* Flow control (RX & TX) is completely disabled by a
1666 * software over-ride.
1668 mii_autoneg_adv_reg
&= ~(NWAY_AR_ASM_DIR
| NWAY_AR_PAUSE
);
1670 case e1000_fc_rx_pause
: /* 1 */
1671 /* RX Flow control is enabled, and TX Flow control is
1672 * disabled, by a software over-ride.
1674 /* Since there really isn't a way to advertise that we are
1675 * capable of RX Pause ONLY, we will advertise that we
1676 * support both symmetric and asymmetric RX PAUSE. Later
1677 * (in e1000_config_fc_after_link_up) we will disable the
1678 *hw's ability to send PAUSE frames.
1680 mii_autoneg_adv_reg
|= (NWAY_AR_ASM_DIR
| NWAY_AR_PAUSE
);
1682 case e1000_fc_tx_pause
: /* 2 */
1683 /* TX Flow control is enabled, and RX Flow control is
1684 * disabled, by a software over-ride.
1686 mii_autoneg_adv_reg
|= NWAY_AR_ASM_DIR
;
1687 mii_autoneg_adv_reg
&= ~NWAY_AR_PAUSE
;
1689 case e1000_fc_full
: /* 3 */
1690 /* Flow control (both RX and TX) is enabled by a software
1693 mii_autoneg_adv_reg
|= (NWAY_AR_ASM_DIR
| NWAY_AR_PAUSE
);
1696 DEBUGOUT("Flow control param set incorrectly\n");
1697 return -E1000_ERR_CONFIG
;
1700 ret_val
= e1000_write_phy_reg(hw
, PHY_AUTONEG_ADV
, mii_autoneg_adv_reg
);
1704 DEBUGOUT1("Auto-Neg Advertising %x\n", mii_autoneg_adv_reg
);
1706 ret_val
= e1000_write_phy_reg(hw
, PHY_1000T_CTRL
, mii_1000t_ctrl_reg
);
1710 return E1000_SUCCESS
;
1713 /******************************************************************************
1714 * Force PHY speed and duplex settings to hw->forced_speed_duplex
1716 * hw - Struct containing variables accessed by shared code
1717 ******************************************************************************/
1719 e1000_phy_force_speed_duplex(struct e1000_hw
*hw
)
1723 uint16_t mii_ctrl_reg
;
1724 uint16_t mii_status_reg
;
1728 DEBUGFUNC("e1000_phy_force_speed_duplex");
1730 /* Turn off Flow control if we are forcing speed and duplex. */
1731 hw
->fc
= e1000_fc_none
;
1733 DEBUGOUT1("hw->fc = %d\n", hw
->fc
);
1735 /* Read the Device Control Register. */
1736 ctrl
= E1000_READ_REG(hw
, CTRL
);
1738 /* Set the bits to Force Speed and Duplex in the Device Ctrl Reg. */
1739 ctrl
|= (E1000_CTRL_FRCSPD
| E1000_CTRL_FRCDPX
);
1740 ctrl
&= ~(DEVICE_SPEED_MASK
);
1742 /* Clear the Auto Speed Detect Enable bit. */
1743 ctrl
&= ~E1000_CTRL_ASDE
;
1745 /* Read the MII Control Register. */
1746 ret_val
= e1000_read_phy_reg(hw
, PHY_CTRL
, &mii_ctrl_reg
);
1750 /* We need to disable autoneg in order to force link and duplex. */
1752 mii_ctrl_reg
&= ~MII_CR_AUTO_NEG_EN
;
1754 /* Are we forcing Full or Half Duplex? */
1755 if(hw
->forced_speed_duplex
== e1000_100_full
||
1756 hw
->forced_speed_duplex
== e1000_10_full
) {
1757 /* We want to force full duplex so we SET the full duplex bits in the
1758 * Device and MII Control Registers.
1760 ctrl
|= E1000_CTRL_FD
;
1761 mii_ctrl_reg
|= MII_CR_FULL_DUPLEX
;
1762 DEBUGOUT("Full Duplex\n");
1764 /* We want to force half duplex so we CLEAR the full duplex bits in
1765 * the Device and MII Control Registers.
1767 ctrl
&= ~E1000_CTRL_FD
;
1768 mii_ctrl_reg
&= ~MII_CR_FULL_DUPLEX
;
1769 DEBUGOUT("Half Duplex\n");
1772 /* Are we forcing 100Mbps??? */
1773 if(hw
->forced_speed_duplex
== e1000_100_full
||
1774 hw
->forced_speed_duplex
== e1000_100_half
) {
1775 /* Set the 100Mb bit and turn off the 1000Mb and 10Mb bits. */
1776 ctrl
|= E1000_CTRL_SPD_100
;
1777 mii_ctrl_reg
|= MII_CR_SPEED_100
;
1778 mii_ctrl_reg
&= ~(MII_CR_SPEED_1000
| MII_CR_SPEED_10
);
1779 DEBUGOUT("Forcing 100mb ");
1781 /* Set the 10Mb bit and turn off the 1000Mb and 100Mb bits. */
1782 ctrl
&= ~(E1000_CTRL_SPD_1000
| E1000_CTRL_SPD_100
);
1783 mii_ctrl_reg
|= MII_CR_SPEED_10
;
1784 mii_ctrl_reg
&= ~(MII_CR_SPEED_1000
| MII_CR_SPEED_100
);
1785 DEBUGOUT("Forcing 10mb ");
1788 e1000_config_collision_dist(hw
);
1790 /* Write the configured values back to the Device Control Reg. */
1791 E1000_WRITE_REG(hw
, CTRL
, ctrl
);
1793 if (hw
->phy_type
== e1000_phy_m88
) {
1794 ret_val
= e1000_read_phy_reg(hw
, M88E1000_PHY_SPEC_CTRL
, &phy_data
);
1798 /* Clear Auto-Crossover to force MDI manually. M88E1000 requires MDI
1799 * forced whenever speed are duplex are forced.
1801 phy_data
&= ~M88E1000_PSCR_AUTO_X_MODE
;
1802 ret_val
= e1000_write_phy_reg(hw
, M88E1000_PHY_SPEC_CTRL
, phy_data
);
1806 DEBUGOUT1("M88E1000 PSCR: %x \n", phy_data
);
1808 /* Need to reset the PHY or these changes will be ignored */
1809 mii_ctrl_reg
|= MII_CR_RESET
;
1811 /* Clear Auto-Crossover to force MDI manually. IGP requires MDI
1812 * forced whenever speed or duplex are forced.
1814 ret_val
= e1000_read_phy_reg(hw
, IGP01E1000_PHY_PORT_CTRL
, &phy_data
);
1818 phy_data
&= ~IGP01E1000_PSCR_AUTO_MDIX
;
1819 phy_data
&= ~IGP01E1000_PSCR_FORCE_MDI_MDIX
;
1821 ret_val
= e1000_write_phy_reg(hw
, IGP01E1000_PHY_PORT_CTRL
, phy_data
);
1826 /* Write back the modified PHY MII control register. */
1827 ret_val
= e1000_write_phy_reg(hw
, PHY_CTRL
, mii_ctrl_reg
);
1833 /* The wait_autoneg_complete flag may be a little misleading here.
1834 * Since we are forcing speed and duplex, Auto-Neg is not enabled.
1835 * But we do want to delay for a period while forcing only so we
1836 * don't generate false No Link messages. So we will wait here
1837 * only if the user has set wait_autoneg_complete to 1, which is
1840 if(hw
->wait_autoneg_complete
) {
1841 /* We will wait for autoneg to complete. */
1842 DEBUGOUT("Waiting for forced speed/duplex link.\n");
1845 /* We will wait for autoneg to complete or 4.5 seconds to expire. */
1846 for(i
= PHY_FORCE_TIME
; i
> 0; i
--) {
1847 /* Read the MII Status Register and wait for Auto-Neg Complete bit
1850 ret_val
= e1000_read_phy_reg(hw
, PHY_STATUS
, &mii_status_reg
);
1854 ret_val
= e1000_read_phy_reg(hw
, PHY_STATUS
, &mii_status_reg
);
1858 if(mii_status_reg
& MII_SR_LINK_STATUS
) break;
1862 (hw
->phy_type
== e1000_phy_m88
)) {
1863 /* We didn't get link. Reset the DSP and wait again for link. */
1864 ret_val
= e1000_phy_reset_dsp(hw
);
1866 DEBUGOUT("Error Resetting PHY DSP\n");
1870 /* This loop will early-out if the link condition has been met. */
1871 for(i
= PHY_FORCE_TIME
; i
> 0; i
--) {
1872 if(mii_status_reg
& MII_SR_LINK_STATUS
) break;
1874 /* Read the MII Status Register and wait for Auto-Neg Complete bit
1877 ret_val
= e1000_read_phy_reg(hw
, PHY_STATUS
, &mii_status_reg
);
1881 ret_val
= e1000_read_phy_reg(hw
, PHY_STATUS
, &mii_status_reg
);
1887 if (hw
->phy_type
== e1000_phy_m88
) {
1888 /* Because we reset the PHY above, we need to re-force TX_CLK in the
1889 * Extended PHY Specific Control Register to 25MHz clock. This value
1890 * defaults back to a 2.5MHz clock when the PHY is reset.
1892 ret_val
= e1000_read_phy_reg(hw
, M88E1000_EXT_PHY_SPEC_CTRL
, &phy_data
);
1896 phy_data
|= M88E1000_EPSCR_TX_CLK_25
;
1897 ret_val
= e1000_write_phy_reg(hw
, M88E1000_EXT_PHY_SPEC_CTRL
, phy_data
);
1901 /* In addition, because of the s/w reset above, we need to enable CRS on
1902 * TX. This must be set for both full and half duplex operation.
1904 ret_val
= e1000_read_phy_reg(hw
, M88E1000_PHY_SPEC_CTRL
, &phy_data
);
1908 phy_data
|= M88E1000_PSCR_ASSERT_CRS_ON_TX
;
1909 ret_val
= e1000_write_phy_reg(hw
, M88E1000_PHY_SPEC_CTRL
, phy_data
);
1913 if((hw
->mac_type
== e1000_82544
|| hw
->mac_type
== e1000_82543
) &&
1915 (hw
->forced_speed_duplex
== e1000_10_full
||
1916 hw
->forced_speed_duplex
== e1000_10_half
)) {
1917 ret_val
= e1000_polarity_reversal_workaround(hw
);
1922 return E1000_SUCCESS
;
1925 /******************************************************************************
1926 * Sets the collision distance in the Transmit Control register
1928 * hw - Struct containing variables accessed by shared code
1930 * Link should have been established previously. Reads the speed and duplex
1931 * information from the Device Status register.
1932 ******************************************************************************/
1934 e1000_config_collision_dist(struct e1000_hw
*hw
)
1938 DEBUGFUNC("e1000_config_collision_dist");
1940 tctl
= E1000_READ_REG(hw
, TCTL
);
1942 tctl
&= ~E1000_TCTL_COLD
;
1943 tctl
|= E1000_COLLISION_DISTANCE
<< E1000_COLD_SHIFT
;
1945 E1000_WRITE_REG(hw
, TCTL
, tctl
);
1946 E1000_WRITE_FLUSH(hw
);
1949 /******************************************************************************
1950 * Sets MAC speed and duplex settings to reflect the those in the PHY
1952 * hw - Struct containing variables accessed by shared code
1953 * mii_reg - data to write to the MII control register
1955 * The contents of the PHY register containing the needed information need to
1957 ******************************************************************************/
1959 e1000_config_mac_to_phy(struct e1000_hw
*hw
)
1965 DEBUGFUNC("e1000_config_mac_to_phy");
1967 /* 82544 or newer MAC, Auto Speed Detection takes care of
1968 * MAC speed/duplex configuration.*/
1969 if (hw
->mac_type
>= e1000_82544
)
1970 return E1000_SUCCESS
;
1972 /* Read the Device Control Register and set the bits to Force Speed
1975 ctrl
= E1000_READ_REG(hw
, CTRL
);
1976 ctrl
|= (E1000_CTRL_FRCSPD
| E1000_CTRL_FRCDPX
);
1977 ctrl
&= ~(E1000_CTRL_SPD_SEL
| E1000_CTRL_ILOS
);
1979 /* Set up duplex in the Device Control and Transmit Control
1980 * registers depending on negotiated values.
1982 ret_val
= e1000_read_phy_reg(hw
, M88E1000_PHY_SPEC_STATUS
, &phy_data
);
1986 if(phy_data
& M88E1000_PSSR_DPLX
)
1987 ctrl
|= E1000_CTRL_FD
;
1989 ctrl
&= ~E1000_CTRL_FD
;
1991 e1000_config_collision_dist(hw
);
1993 /* Set up speed in the Device Control register depending on
1994 * negotiated values.
1996 if((phy_data
& M88E1000_PSSR_SPEED
) == M88E1000_PSSR_1000MBS
)
1997 ctrl
|= E1000_CTRL_SPD_1000
;
1998 else if((phy_data
& M88E1000_PSSR_SPEED
) == M88E1000_PSSR_100MBS
)
1999 ctrl
|= E1000_CTRL_SPD_100
;
2001 /* Write the configured values back to the Device Control Reg. */
2002 E1000_WRITE_REG(hw
, CTRL
, ctrl
);
2003 return E1000_SUCCESS
;
2006 /******************************************************************************
2007 * Forces the MAC's flow control settings.
2009 * hw - Struct containing variables accessed by shared code
2011 * Sets the TFCE and RFCE bits in the device control register to reflect
2012 * the adapter settings. TFCE and RFCE need to be explicitly set by
2013 * software when a Copper PHY is used because autonegotiation is managed
2014 * by the PHY rather than the MAC. Software must also configure these
2015 * bits when link is forced on a fiber connection.
2016 *****************************************************************************/
2018 e1000_force_mac_fc(struct e1000_hw
*hw
)
2022 DEBUGFUNC("e1000_force_mac_fc");
2024 /* Get the current configuration of the Device Control Register */
2025 ctrl
= E1000_READ_REG(hw
, CTRL
);
2027 /* Because we didn't get link via the internal auto-negotiation
2028 * mechanism (we either forced link or we got link via PHY
2029 * auto-neg), we have to manually enable/disable transmit an
2030 * receive flow control.
2032 * The "Case" statement below enables/disable flow control
2033 * according to the "hw->fc" parameter.
2035 * The possible values of the "fc" parameter are:
2036 * 0: Flow control is completely disabled
2037 * 1: Rx flow control is enabled (we can receive pause
2038 * frames but not send pause frames).
2039 * 2: Tx flow control is enabled (we can send pause frames
2040 * frames but we do not receive pause frames).
2041 * 3: Both Rx and TX flow control (symmetric) is enabled.
2042 * other: No other values should be possible at this point.
2047 ctrl
&= (~(E1000_CTRL_TFCE
| E1000_CTRL_RFCE
));
2049 case e1000_fc_rx_pause
:
2050 ctrl
&= (~E1000_CTRL_TFCE
);
2051 ctrl
|= E1000_CTRL_RFCE
;
2053 case e1000_fc_tx_pause
:
2054 ctrl
&= (~E1000_CTRL_RFCE
);
2055 ctrl
|= E1000_CTRL_TFCE
;
2058 ctrl
|= (E1000_CTRL_TFCE
| E1000_CTRL_RFCE
);
2061 DEBUGOUT("Flow control param set incorrectly\n");
2062 return -E1000_ERR_CONFIG
;
2065 /* Disable TX Flow Control for 82542 (rev 2.0) */
2066 if(hw
->mac_type
== e1000_82542_rev2_0
)
2067 ctrl
&= (~E1000_CTRL_TFCE
);
2069 E1000_WRITE_REG(hw
, CTRL
, ctrl
);
2070 return E1000_SUCCESS
;
2073 /******************************************************************************
2074 * Configures flow control settings after link is established
2076 * hw - Struct containing variables accessed by shared code
2078 * Should be called immediately after a valid link has been established.
2079 * Forces MAC flow control settings if link was forced. When in MII/GMII mode
2080 * and autonegotiation is enabled, the MAC flow control settings will be set
2081 * based on the flow control negotiated by the PHY. In TBI mode, the TFCE
2082 * and RFCE bits will be automaticaly set to the negotiated flow control mode.
2083 *****************************************************************************/
2085 e1000_config_fc_after_link_up(struct e1000_hw
*hw
)
2088 uint16_t mii_status_reg
;
2089 uint16_t mii_nway_adv_reg
;
2090 uint16_t mii_nway_lp_ability_reg
;
2094 DEBUGFUNC("e1000_config_fc_after_link_up");
2096 /* Check for the case where we have fiber media and auto-neg failed
2097 * so we had to force link. In this case, we need to force the
2098 * configuration of the MAC to match the "fc" parameter.
2100 if(((hw
->media_type
== e1000_media_type_fiber
) && (hw
->autoneg_failed
)) ||
2101 ((hw
->media_type
== e1000_media_type_internal_serdes
) && (hw
->autoneg_failed
)) ||
2102 ((hw
->media_type
== e1000_media_type_copper
) && (!hw
->autoneg
))) {
2103 ret_val
= e1000_force_mac_fc(hw
);
2105 DEBUGOUT("Error forcing flow control settings\n");
2110 /* Check for the case where we have copper media and auto-neg is
2111 * enabled. In this case, we need to check and see if Auto-Neg
2112 * has completed, and if so, how the PHY and link partner has
2113 * flow control configured.
2115 if((hw
->media_type
== e1000_media_type_copper
) && hw
->autoneg
) {
2116 /* Read the MII Status Register and check to see if AutoNeg
2117 * has completed. We read this twice because this reg has
2118 * some "sticky" (latched) bits.
2120 ret_val
= e1000_read_phy_reg(hw
, PHY_STATUS
, &mii_status_reg
);
2123 ret_val
= e1000_read_phy_reg(hw
, PHY_STATUS
, &mii_status_reg
);
2127 if(mii_status_reg
& MII_SR_AUTONEG_COMPLETE
) {
2128 /* The AutoNeg process has completed, so we now need to
2129 * read both the Auto Negotiation Advertisement Register
2130 * (Address 4) and the Auto_Negotiation Base Page Ability
2131 * Register (Address 5) to determine how flow control was
2134 ret_val
= e1000_read_phy_reg(hw
, PHY_AUTONEG_ADV
,
2138 ret_val
= e1000_read_phy_reg(hw
, PHY_LP_ABILITY
,
2139 &mii_nway_lp_ability_reg
);
2143 /* Two bits in the Auto Negotiation Advertisement Register
2144 * (Address 4) and two bits in the Auto Negotiation Base
2145 * Page Ability Register (Address 5) determine flow control
2146 * for both the PHY and the link partner. The following
2147 * table, taken out of the IEEE 802.3ab/D6.0 dated March 25,
2148 * 1999, describes these PAUSE resolution bits and how flow
2149 * control is determined based upon these settings.
2150 * NOTE: DC = Don't Care
2152 * LOCAL DEVICE | LINK PARTNER
2153 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | NIC Resolution
2154 *-------|---------|-------|---------|--------------------
2155 * 0 | 0 | DC | DC | e1000_fc_none
2156 * 0 | 1 | 0 | DC | e1000_fc_none
2157 * 0 | 1 | 1 | 0 | e1000_fc_none
2158 * 0 | 1 | 1 | 1 | e1000_fc_tx_pause
2159 * 1 | 0 | 0 | DC | e1000_fc_none
2160 * 1 | DC | 1 | DC | e1000_fc_full
2161 * 1 | 1 | 0 | 0 | e1000_fc_none
2162 * 1 | 1 | 0 | 1 | e1000_fc_rx_pause
2165 /* Are both PAUSE bits set to 1? If so, this implies
2166 * Symmetric Flow Control is enabled at both ends. The
2167 * ASM_DIR bits are irrelevant per the spec.
2169 * For Symmetric Flow Control:
2171 * LOCAL DEVICE | LINK PARTNER
2172 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
2173 *-------|---------|-------|---------|--------------------
2174 * 1 | DC | 1 | DC | e1000_fc_full
2177 if((mii_nway_adv_reg
& NWAY_AR_PAUSE
) &&
2178 (mii_nway_lp_ability_reg
& NWAY_LPAR_PAUSE
)) {
2179 /* Now we need to check if the user selected RX ONLY
2180 * of pause frames. In this case, we had to advertise
2181 * FULL flow control because we could not advertise RX
2182 * ONLY. Hence, we must now check to see if we need to
2183 * turn OFF the TRANSMISSION of PAUSE frames.
2185 if(hw
->original_fc
== e1000_fc_full
) {
2186 hw
->fc
= e1000_fc_full
;
2187 DEBUGOUT("Flow Control = FULL.\r\n");
2189 hw
->fc
= e1000_fc_rx_pause
;
2190 DEBUGOUT("Flow Control = RX PAUSE frames only.\r\n");
2193 /* For receiving PAUSE frames ONLY.
2195 * LOCAL DEVICE | LINK PARTNER
2196 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
2197 *-------|---------|-------|---------|--------------------
2198 * 0 | 1 | 1 | 1 | e1000_fc_tx_pause
2201 else if(!(mii_nway_adv_reg
& NWAY_AR_PAUSE
) &&
2202 (mii_nway_adv_reg
& NWAY_AR_ASM_DIR
) &&
2203 (mii_nway_lp_ability_reg
& NWAY_LPAR_PAUSE
) &&
2204 (mii_nway_lp_ability_reg
& NWAY_LPAR_ASM_DIR
)) {
2205 hw
->fc
= e1000_fc_tx_pause
;
2206 DEBUGOUT("Flow Control = TX PAUSE frames only.\r\n");
2208 /* For transmitting PAUSE frames ONLY.
2210 * LOCAL DEVICE | LINK PARTNER
2211 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
2212 *-------|---------|-------|---------|--------------------
2213 * 1 | 1 | 0 | 1 | e1000_fc_rx_pause
2216 else if((mii_nway_adv_reg
& NWAY_AR_PAUSE
) &&
2217 (mii_nway_adv_reg
& NWAY_AR_ASM_DIR
) &&
2218 !(mii_nway_lp_ability_reg
& NWAY_LPAR_PAUSE
) &&
2219 (mii_nway_lp_ability_reg
& NWAY_LPAR_ASM_DIR
)) {
2220 hw
->fc
= e1000_fc_rx_pause
;
2221 DEBUGOUT("Flow Control = RX PAUSE frames only.\r\n");
2223 /* Per the IEEE spec, at this point flow control should be
2224 * disabled. However, we want to consider that we could
2225 * be connected to a legacy switch that doesn't advertise
2226 * desired flow control, but can be forced on the link
2227 * partner. So if we advertised no flow control, that is
2228 * what we will resolve to. If we advertised some kind of
2229 * receive capability (Rx Pause Only or Full Flow Control)
2230 * and the link partner advertised none, we will configure
2231 * ourselves to enable Rx Flow Control only. We can do
2232 * this safely for two reasons: If the link partner really
2233 * didn't want flow control enabled, and we enable Rx, no
2234 * harm done since we won't be receiving any PAUSE frames
2235 * anyway. If the intent on the link partner was to have
2236 * flow control enabled, then by us enabling RX only, we
2237 * can at least receive pause frames and process them.
2238 * This is a good idea because in most cases, since we are
2239 * predominantly a server NIC, more times than not we will
2240 * be asked to delay transmission of packets than asking
2241 * our link partner to pause transmission of frames.
2243 else if((hw
->original_fc
== e1000_fc_none
||
2244 hw
->original_fc
== e1000_fc_tx_pause
) ||
2245 hw
->fc_strict_ieee
) {
2246 hw
->fc
= e1000_fc_none
;
2247 DEBUGOUT("Flow Control = NONE.\r\n");
2249 hw
->fc
= e1000_fc_rx_pause
;
2250 DEBUGOUT("Flow Control = RX PAUSE frames only.\r\n");
2253 /* Now we need to do one last check... If we auto-
2254 * negotiated to HALF DUPLEX, flow control should not be
2255 * enabled per IEEE 802.3 spec.
2257 ret_val
= e1000_get_speed_and_duplex(hw
, &speed
, &duplex
);
2259 DEBUGOUT("Error getting link speed and duplex\n");
2263 if(duplex
== HALF_DUPLEX
)
2264 hw
->fc
= e1000_fc_none
;
2266 /* Now we call a subroutine to actually force the MAC
2267 * controller to use the correct flow control settings.
2269 ret_val
= e1000_force_mac_fc(hw
);
2271 DEBUGOUT("Error forcing flow control settings\n");
2275 DEBUGOUT("Copper PHY and Auto Neg has not completed.\r\n");
2278 return E1000_SUCCESS
;
2281 /******************************************************************************
2282 * Checks to see if the link status of the hardware has changed.
2284 * hw - Struct containing variables accessed by shared code
2286 * Called by any function that needs to check the link status of the adapter.
2287 *****************************************************************************/
2289 e1000_check_for_link(struct e1000_hw
*hw
)
2296 uint32_t signal
= 0;
2300 DEBUGFUNC("e1000_check_for_link");
2302 ctrl
= E1000_READ_REG(hw
, CTRL
);
2303 status
= E1000_READ_REG(hw
, STATUS
);
2305 /* On adapters with a MAC newer than 82544, SW Defineable pin 1 will be
2306 * set when the optics detect a signal. On older adapters, it will be
2307 * cleared when there is a signal. This applies to fiber media only.
2309 if((hw
->media_type
== e1000_media_type_fiber
) ||
2310 (hw
->media_type
== e1000_media_type_internal_serdes
)) {
2311 rxcw
= E1000_READ_REG(hw
, RXCW
);
2313 if(hw
->media_type
== e1000_media_type_fiber
) {
2314 signal
= (hw
->mac_type
> e1000_82544
) ? E1000_CTRL_SWDPIN1
: 0;
2315 if(status
& E1000_STATUS_LU
)
2316 hw
->get_link_status
= FALSE
;
2320 /* If we have a copper PHY then we only want to go out to the PHY
2321 * registers to see if Auto-Neg has completed and/or if our link
2322 * status has changed. The get_link_status flag will be set if we
2323 * receive a Link Status Change interrupt or we have Rx Sequence
2326 if((hw
->media_type
== e1000_media_type_copper
) && hw
->get_link_status
) {
2327 /* First we want to see if the MII Status Register reports
2328 * link. If so, then we want to get the current speed/duplex
2330 * Read the register twice since the link bit is sticky.
2332 ret_val
= e1000_read_phy_reg(hw
, PHY_STATUS
, &phy_data
);
2335 ret_val
= e1000_read_phy_reg(hw
, PHY_STATUS
, &phy_data
);
2339 if(phy_data
& MII_SR_LINK_STATUS
) {
2340 hw
->get_link_status
= FALSE
;
2341 /* Check if there was DownShift, must be checked immediately after
2343 e1000_check_downshift(hw
);
2345 /* If we are on 82544 or 82543 silicon and speed/duplex
2346 * are forced to 10H or 10F, then we will implement the polarity
2347 * reversal workaround. We disable interrupts first, and upon
2348 * returning, place the devices interrupt state to its previous
2349 * value except for the link status change interrupt which will
2350 * happen due to the execution of this workaround.
2353 if((hw
->mac_type
== e1000_82544
|| hw
->mac_type
== e1000_82543
) &&
2355 (hw
->forced_speed_duplex
== e1000_10_full
||
2356 hw
->forced_speed_duplex
== e1000_10_half
)) {
2357 E1000_WRITE_REG(hw
, IMC
, 0xffffffff);
2358 ret_val
= e1000_polarity_reversal_workaround(hw
);
2359 icr
= E1000_READ_REG(hw
, ICR
);
2360 E1000_WRITE_REG(hw
, ICS
, (icr
& ~E1000_ICS_LSC
));
2361 E1000_WRITE_REG(hw
, IMS
, IMS_ENABLE_MASK
);
2365 /* No link detected */
2366 e1000_config_dsp_after_link_change(hw
, FALSE
);
2370 /* If we are forcing speed/duplex, then we simply return since
2371 * we have already determined whether we have link or not.
2373 if(!hw
->autoneg
) return -E1000_ERR_CONFIG
;
2375 /* optimize the dsp settings for the igp phy */
2376 e1000_config_dsp_after_link_change(hw
, TRUE
);
2378 /* We have a M88E1000 PHY and Auto-Neg is enabled. If we
2379 * have Si on board that is 82544 or newer, Auto
2380 * Speed Detection takes care of MAC speed/duplex
2381 * configuration. So we only need to configure Collision
2382 * Distance in the MAC. Otherwise, we need to force
2383 * speed/duplex on the MAC to the current PHY speed/duplex
2386 if(hw
->mac_type
>= e1000_82544
)
2387 e1000_config_collision_dist(hw
);
2389 ret_val
= e1000_config_mac_to_phy(hw
);
2391 DEBUGOUT("Error configuring MAC to PHY settings\n");
2396 /* Configure Flow Control now that Auto-Neg has completed. First, we
2397 * need to restore the desired flow control settings because we may
2398 * have had to re-autoneg with a different link partner.
2400 ret_val
= e1000_config_fc_after_link_up(hw
);
2402 DEBUGOUT("Error configuring flow control\n");
2406 /* At this point we know that we are on copper and we have
2407 * auto-negotiated link. These are conditions for checking the link
2408 * partner capability register. We use the link speed to determine if
2409 * TBI compatibility needs to be turned on or off. If the link is not
2410 * at gigabit speed, then TBI compatibility is not needed. If we are
2411 * at gigabit speed, we turn on TBI compatibility.
2413 if(hw
->tbi_compatibility_en
) {
2414 uint16_t speed
, duplex
;
2415 e1000_get_speed_and_duplex(hw
, &speed
, &duplex
);
2416 if(speed
!= SPEED_1000
) {
2417 /* If link speed is not set to gigabit speed, we do not need
2418 * to enable TBI compatibility.
2420 if(hw
->tbi_compatibility_on
) {
2421 /* If we previously were in the mode, turn it off. */
2422 rctl
= E1000_READ_REG(hw
, RCTL
);
2423 rctl
&= ~E1000_RCTL_SBP
;
2424 E1000_WRITE_REG(hw
, RCTL
, rctl
);
2425 hw
->tbi_compatibility_on
= FALSE
;
2428 /* If TBI compatibility is was previously off, turn it on. For
2429 * compatibility with a TBI link partner, we will store bad
2430 * packets. Some frames have an additional byte on the end and
2431 * will look like CRC errors to to the hardware.
2433 if(!hw
->tbi_compatibility_on
) {
2434 hw
->tbi_compatibility_on
= TRUE
;
2435 rctl
= E1000_READ_REG(hw
, RCTL
);
2436 rctl
|= E1000_RCTL_SBP
;
2437 E1000_WRITE_REG(hw
, RCTL
, rctl
);
2442 /* If we don't have link (auto-negotiation failed or link partner cannot
2443 * auto-negotiate), the cable is plugged in (we have signal), and our
2444 * link partner is not trying to auto-negotiate with us (we are receiving
2445 * idles or data), we need to force link up. We also need to give
2446 * auto-negotiation time to complete, in case the cable was just plugged
2447 * in. The autoneg_failed flag does this.
2449 else if((((hw
->media_type
== e1000_media_type_fiber
) &&
2450 ((ctrl
& E1000_CTRL_SWDPIN1
) == signal
)) ||
2451 (hw
->media_type
== e1000_media_type_internal_serdes
)) &&
2452 (!(status
& E1000_STATUS_LU
)) &&
2453 (!(rxcw
& E1000_RXCW_C
))) {
2454 if(hw
->autoneg_failed
== 0) {
2455 hw
->autoneg_failed
= 1;
2458 DEBUGOUT("NOT RXing /C/, disable AutoNeg and force link.\r\n");
2460 /* Disable auto-negotiation in the TXCW register */
2461 E1000_WRITE_REG(hw
, TXCW
, (hw
->txcw
& ~E1000_TXCW_ANE
));
2463 /* Force link-up and also force full-duplex. */
2464 ctrl
= E1000_READ_REG(hw
, CTRL
);
2465 ctrl
|= (E1000_CTRL_SLU
| E1000_CTRL_FD
);
2466 E1000_WRITE_REG(hw
, CTRL
, ctrl
);
2468 /* Configure Flow Control after forcing link up. */
2469 ret_val
= e1000_config_fc_after_link_up(hw
);
2471 DEBUGOUT("Error configuring flow control\n");
2475 /* If we are forcing link and we are receiving /C/ ordered sets, re-enable
2476 * auto-negotiation in the TXCW register and disable forced link in the
2477 * Device Control register in an attempt to auto-negotiate with our link
2480 else if(((hw
->media_type
== e1000_media_type_fiber
) ||
2481 (hw
->media_type
== e1000_media_type_internal_serdes
)) &&
2482 (ctrl
& E1000_CTRL_SLU
) && (rxcw
& E1000_RXCW_C
)) {
2483 DEBUGOUT("RXing /C/, enable AutoNeg and stop forcing link.\r\n");
2484 E1000_WRITE_REG(hw
, TXCW
, hw
->txcw
);
2485 E1000_WRITE_REG(hw
, CTRL
, (ctrl
& ~E1000_CTRL_SLU
));
2487 hw
->serdes_link_down
= FALSE
;
2489 /* If we force link for non-auto-negotiation switch, check link status
2490 * based on MAC synchronization for internal serdes media type.
2492 else if((hw
->media_type
== e1000_media_type_internal_serdes
) &&
2493 !(E1000_TXCW_ANE
& E1000_READ_REG(hw
, TXCW
))) {
2494 /* SYNCH bit and IV bit are sticky. */
2496 if(E1000_RXCW_SYNCH
& E1000_READ_REG(hw
, RXCW
)) {
2497 if(!(rxcw
& E1000_RXCW_IV
)) {
2498 hw
->serdes_link_down
= FALSE
;
2499 DEBUGOUT("SERDES: Link is up.\n");
2502 hw
->serdes_link_down
= TRUE
;
2503 DEBUGOUT("SERDES: Link is down.\n");
2506 if((hw
->media_type
== e1000_media_type_internal_serdes
) &&
2507 (E1000_TXCW_ANE
& E1000_READ_REG(hw
, TXCW
))) {
2508 hw
->serdes_link_down
= !(E1000_STATUS_LU
& E1000_READ_REG(hw
, STATUS
));
2510 return E1000_SUCCESS
;
2513 /******************************************************************************
2514 * Detects the current speed and duplex settings of the hardware.
2516 * hw - Struct containing variables accessed by shared code
2517 * speed - Speed of the connection
2518 * duplex - Duplex setting of the connection
2519 *****************************************************************************/
2521 e1000_get_speed_and_duplex(struct e1000_hw
*hw
,
2529 DEBUGFUNC("e1000_get_speed_and_duplex");
2531 if(hw
->mac_type
>= e1000_82543
) {
2532 status
= E1000_READ_REG(hw
, STATUS
);
2533 if(status
& E1000_STATUS_SPEED_1000
) {
2534 *speed
= SPEED_1000
;
2535 DEBUGOUT("1000 Mbs, ");
2536 } else if(status
& E1000_STATUS_SPEED_100
) {
2538 DEBUGOUT("100 Mbs, ");
2541 DEBUGOUT("10 Mbs, ");
2544 if(status
& E1000_STATUS_FD
) {
2545 *duplex
= FULL_DUPLEX
;
2546 DEBUGOUT("Full Duplex\r\n");
2548 *duplex
= HALF_DUPLEX
;
2549 DEBUGOUT(" Half Duplex\r\n");
2552 DEBUGOUT("1000 Mbs, Full Duplex\r\n");
2553 *speed
= SPEED_1000
;
2554 *duplex
= FULL_DUPLEX
;
2557 /* IGP01 PHY may advertise full duplex operation after speed downgrade even
2558 * if it is operating at half duplex. Here we set the duplex settings to
2559 * match the duplex in the link partner's capabilities.
2561 if(hw
->phy_type
== e1000_phy_igp
&& hw
->speed_downgraded
) {
2562 ret_val
= e1000_read_phy_reg(hw
, PHY_AUTONEG_EXP
, &phy_data
);
2566 if(!(phy_data
& NWAY_ER_LP_NWAY_CAPS
))
2567 *duplex
= HALF_DUPLEX
;
2569 ret_val
= e1000_read_phy_reg(hw
, PHY_LP_ABILITY
, &phy_data
);
2572 if((*speed
== SPEED_100
&& !(phy_data
& NWAY_LPAR_100TX_FD_CAPS
)) ||
2573 (*speed
== SPEED_10
&& !(phy_data
& NWAY_LPAR_10T_FD_CAPS
)))
2574 *duplex
= HALF_DUPLEX
;
2578 return E1000_SUCCESS
;
2581 /******************************************************************************
2582 * Blocks until autoneg completes or times out (~4.5 seconds)
2584 * hw - Struct containing variables accessed by shared code
2585 ******************************************************************************/
2587 e1000_wait_autoneg(struct e1000_hw
*hw
)
2593 DEBUGFUNC("e1000_wait_autoneg");
2594 DEBUGOUT("Waiting for Auto-Neg to complete.\n");
2596 /* We will wait for autoneg to complete or 4.5 seconds to expire. */
2597 for(i
= PHY_AUTO_NEG_TIME
; i
> 0; i
--) {
2598 /* Read the MII Status Register and wait for Auto-Neg
2599 * Complete bit to be set.
2601 ret_val
= e1000_read_phy_reg(hw
, PHY_STATUS
, &phy_data
);
2604 ret_val
= e1000_read_phy_reg(hw
, PHY_STATUS
, &phy_data
);
2607 if(phy_data
& MII_SR_AUTONEG_COMPLETE
) {
2608 return E1000_SUCCESS
;
2612 return E1000_SUCCESS
;
2615 /******************************************************************************
2616 * Raises the Management Data Clock
2618 * hw - Struct containing variables accessed by shared code
2619 * ctrl - Device control register's current value
2620 ******************************************************************************/
2622 e1000_raise_mdi_clk(struct e1000_hw
*hw
,
2625 /* Raise the clock input to the Management Data Clock (by setting the MDC
2626 * bit), and then delay 10 microseconds.
2628 E1000_WRITE_REG(hw
, CTRL
, (*ctrl
| E1000_CTRL_MDC
));
2629 E1000_WRITE_FLUSH(hw
);
2633 /******************************************************************************
2634 * Lowers the Management Data Clock
2636 * hw - Struct containing variables accessed by shared code
2637 * ctrl - Device control register's current value
2638 ******************************************************************************/
2640 e1000_lower_mdi_clk(struct e1000_hw
*hw
,
2643 /* Lower the clock input to the Management Data Clock (by clearing the MDC
2644 * bit), and then delay 10 microseconds.
2646 E1000_WRITE_REG(hw
, CTRL
, (*ctrl
& ~E1000_CTRL_MDC
));
2647 E1000_WRITE_FLUSH(hw
);
2651 /******************************************************************************
2652 * Shifts data bits out to the PHY
2654 * hw - Struct containing variables accessed by shared code
2655 * data - Data to send out to the PHY
2656 * count - Number of bits to shift out
2658 * Bits are shifted out in MSB to LSB order.
2659 ******************************************************************************/
2661 e1000_shift_out_mdi_bits(struct e1000_hw
*hw
,
2668 /* We need to shift "count" number of bits out to the PHY. So, the value
2669 * in the "data" parameter will be shifted out to the PHY one bit at a
2670 * time. In order to do this, "data" must be broken down into bits.
2673 mask
<<= (count
- 1);
2675 ctrl
= E1000_READ_REG(hw
, CTRL
);
2677 /* Set MDIO_DIR and MDC_DIR direction bits to be used as output pins. */
2678 ctrl
|= (E1000_CTRL_MDIO_DIR
| E1000_CTRL_MDC_DIR
);
2681 /* A "1" is shifted out to the PHY by setting the MDIO bit to "1" and
2682 * then raising and lowering the Management Data Clock. A "0" is
2683 * shifted out to the PHY by setting the MDIO bit to "0" and then
2684 * raising and lowering the clock.
2686 if(data
& mask
) ctrl
|= E1000_CTRL_MDIO
;
2687 else ctrl
&= ~E1000_CTRL_MDIO
;
2689 E1000_WRITE_REG(hw
, CTRL
, ctrl
);
2690 E1000_WRITE_FLUSH(hw
);
2694 e1000_raise_mdi_clk(hw
, &ctrl
);
2695 e1000_lower_mdi_clk(hw
, &ctrl
);
2701 /******************************************************************************
2702 * Shifts data bits in from the PHY
2704 * hw - Struct containing variables accessed by shared code
2706 * Bits are shifted in in MSB to LSB order.
2707 ******************************************************************************/
2709 e1000_shift_in_mdi_bits(struct e1000_hw
*hw
)
2715 /* In order to read a register from the PHY, we need to shift in a total
2716 * of 18 bits from the PHY. The first two bit (turnaround) times are used
2717 * to avoid contention on the MDIO pin when a read operation is performed.
2718 * These two bits are ignored by us and thrown away. Bits are "shifted in"
2719 * by raising the input to the Management Data Clock (setting the MDC bit),
2720 * and then reading the value of the MDIO bit.
2722 ctrl
= E1000_READ_REG(hw
, CTRL
);
2724 /* Clear MDIO_DIR (SWDPIO1) to indicate this bit is to be used as input. */
2725 ctrl
&= ~E1000_CTRL_MDIO_DIR
;
2726 ctrl
&= ~E1000_CTRL_MDIO
;
2728 E1000_WRITE_REG(hw
, CTRL
, ctrl
);
2729 E1000_WRITE_FLUSH(hw
);
2731 /* Raise and Lower the clock before reading in the data. This accounts for
2732 * the turnaround bits. The first clock occurred when we clocked out the
2733 * last bit of the Register Address.
2735 e1000_raise_mdi_clk(hw
, &ctrl
);
2736 e1000_lower_mdi_clk(hw
, &ctrl
);
2738 for(data
= 0, i
= 0; i
< 16; i
++) {
2740 e1000_raise_mdi_clk(hw
, &ctrl
);
2741 ctrl
= E1000_READ_REG(hw
, CTRL
);
2742 /* Check to see if we shifted in a "1". */
2743 if(ctrl
& E1000_CTRL_MDIO
) data
|= 1;
2744 e1000_lower_mdi_clk(hw
, &ctrl
);
2747 e1000_raise_mdi_clk(hw
, &ctrl
);
2748 e1000_lower_mdi_clk(hw
, &ctrl
);
2753 /*****************************************************************************
2754 * Reads the value from a PHY register, if the value is on a specific non zero
2755 * page, sets the page first.
2756 * hw - Struct containing variables accessed by shared code
2757 * reg_addr - address of the PHY register to read
2758 ******************************************************************************/
2760 e1000_read_phy_reg(struct e1000_hw
*hw
,
2766 DEBUGFUNC("e1000_read_phy_reg");
2768 if((hw
->phy_type
== e1000_phy_igp
||
2769 hw
->phy_type
== e1000_phy_igp_2
) &&
2770 (reg_addr
> MAX_PHY_MULTI_PAGE_REG
)) {
2771 ret_val
= e1000_write_phy_reg_ex(hw
, IGP01E1000_PHY_PAGE_SELECT
,
2772 (uint16_t)reg_addr
);
2778 ret_val
= e1000_read_phy_reg_ex(hw
, MAX_PHY_REG_ADDRESS
& reg_addr
,
2785 e1000_read_phy_reg_ex(struct e1000_hw
*hw
,
2791 const uint32_t phy_addr
= 1;
2793 DEBUGFUNC("e1000_read_phy_reg_ex");
2795 if(reg_addr
> MAX_PHY_REG_ADDRESS
) {
2796 DEBUGOUT1("PHY Address %d is out of range\n", reg_addr
);
2797 return -E1000_ERR_PARAM
;
2800 if(hw
->mac_type
> e1000_82543
) {
2801 /* Set up Op-code, Phy Address, and register address in the MDI
2802 * Control register. The MAC will take care of interfacing with the
2803 * PHY to retrieve the desired data.
2805 mdic
= ((reg_addr
<< E1000_MDIC_REG_SHIFT
) |
2806 (phy_addr
<< E1000_MDIC_PHY_SHIFT
) |
2807 (E1000_MDIC_OP_READ
));
2809 E1000_WRITE_REG(hw
, MDIC
, mdic
);
2811 /* Poll the ready bit to see if the MDI read completed */
2812 for(i
= 0; i
< 64; i
++) {
2814 mdic
= E1000_READ_REG(hw
, MDIC
);
2815 if(mdic
& E1000_MDIC_READY
) break;
2817 if(!(mdic
& E1000_MDIC_READY
)) {
2818 DEBUGOUT("MDI Read did not complete\n");
2819 return -E1000_ERR_PHY
;
2821 if(mdic
& E1000_MDIC_ERROR
) {
2822 DEBUGOUT("MDI Error\n");
2823 return -E1000_ERR_PHY
;
2825 *phy_data
= (uint16_t) mdic
;
2827 /* We must first send a preamble through the MDIO pin to signal the
2828 * beginning of an MII instruction. This is done by sending 32
2829 * consecutive "1" bits.
2831 e1000_shift_out_mdi_bits(hw
, PHY_PREAMBLE
, PHY_PREAMBLE_SIZE
);
2833 /* Now combine the next few fields that are required for a read
2834 * operation. We use this method instead of calling the
2835 * e1000_shift_out_mdi_bits routine five different times. The format of
2836 * a MII read instruction consists of a shift out of 14 bits and is
2837 * defined as follows:
2838 * <Preamble><SOF><Op Code><Phy Addr><Reg Addr>
2839 * followed by a shift in of 18 bits. This first two bits shifted in
2840 * are TurnAround bits used to avoid contention on the MDIO pin when a
2841 * READ operation is performed. These two bits are thrown away
2842 * followed by a shift in of 16 bits which contains the desired data.
2844 mdic
= ((reg_addr
) | (phy_addr
<< 5) |
2845 (PHY_OP_READ
<< 10) | (PHY_SOF
<< 12));
2847 e1000_shift_out_mdi_bits(hw
, mdic
, 14);
2849 /* Now that we've shifted out the read command to the MII, we need to
2850 * "shift in" the 16-bit value (18 total bits) of the requested PHY
2853 *phy_data
= e1000_shift_in_mdi_bits(hw
);
2855 return E1000_SUCCESS
;
2858 /******************************************************************************
2859 * Writes a value to a PHY register
2861 * hw - Struct containing variables accessed by shared code
2862 * reg_addr - address of the PHY register to write
2863 * data - data to write to the PHY
2864 ******************************************************************************/
2866 e1000_write_phy_reg(struct e1000_hw
*hw
,
2872 DEBUGFUNC("e1000_write_phy_reg");
2874 if((hw
->phy_type
== e1000_phy_igp
||
2875 hw
->phy_type
== e1000_phy_igp_2
) &&
2876 (reg_addr
> MAX_PHY_MULTI_PAGE_REG
)) {
2877 ret_val
= e1000_write_phy_reg_ex(hw
, IGP01E1000_PHY_PAGE_SELECT
,
2878 (uint16_t)reg_addr
);
2884 ret_val
= e1000_write_phy_reg_ex(hw
, MAX_PHY_REG_ADDRESS
& reg_addr
,
2891 e1000_write_phy_reg_ex(struct e1000_hw
*hw
,
2897 const uint32_t phy_addr
= 1;
2899 DEBUGFUNC("e1000_write_phy_reg_ex");
2901 if(reg_addr
> MAX_PHY_REG_ADDRESS
) {
2902 DEBUGOUT1("PHY Address %d is out of range\n", reg_addr
);
2903 return -E1000_ERR_PARAM
;
2906 if(hw
->mac_type
> e1000_82543
) {
2907 /* Set up Op-code, Phy Address, register address, and data intended
2908 * for the PHY register in the MDI Control register. The MAC will take
2909 * care of interfacing with the PHY to send the desired data.
2911 mdic
= (((uint32_t) phy_data
) |
2912 (reg_addr
<< E1000_MDIC_REG_SHIFT
) |
2913 (phy_addr
<< E1000_MDIC_PHY_SHIFT
) |
2914 (E1000_MDIC_OP_WRITE
));
2916 E1000_WRITE_REG(hw
, MDIC
, mdic
);
2918 /* Poll the ready bit to see if the MDI read completed */
2919 for(i
= 0; i
< 640; i
++) {
2921 mdic
= E1000_READ_REG(hw
, MDIC
);
2922 if(mdic
& E1000_MDIC_READY
) break;
2924 if(!(mdic
& E1000_MDIC_READY
)) {
2925 DEBUGOUT("MDI Write did not complete\n");
2926 return -E1000_ERR_PHY
;
2929 /* We'll need to use the SW defined pins to shift the write command
2930 * out to the PHY. We first send a preamble to the PHY to signal the
2931 * beginning of the MII instruction. This is done by sending 32
2932 * consecutive "1" bits.
2934 e1000_shift_out_mdi_bits(hw
, PHY_PREAMBLE
, PHY_PREAMBLE_SIZE
);
2936 /* Now combine the remaining required fields that will indicate a
2937 * write operation. We use this method instead of calling the
2938 * e1000_shift_out_mdi_bits routine for each field in the command. The
2939 * format of a MII write instruction is as follows:
2940 * <Preamble><SOF><Op Code><Phy Addr><Reg Addr><Turnaround><Data>.
2942 mdic
= ((PHY_TURNAROUND
) | (reg_addr
<< 2) | (phy_addr
<< 7) |
2943 (PHY_OP_WRITE
<< 12) | (PHY_SOF
<< 14));
2945 mdic
|= (uint32_t) phy_data
;
2947 e1000_shift_out_mdi_bits(hw
, mdic
, 32);
2950 return E1000_SUCCESS
;
2954 /******************************************************************************
2955 * Returns the PHY to the power-on reset state
2957 * hw - Struct containing variables accessed by shared code
2958 ******************************************************************************/
2960 e1000_phy_hw_reset(struct e1000_hw
*hw
)
2962 uint32_t ctrl
, ctrl_ext
;
2966 DEBUGFUNC("e1000_phy_hw_reset");
2968 /* In the case of the phy reset being blocked, it's not an error, we
2969 * simply return success without performing the reset. */
2970 ret_val
= e1000_check_phy_reset_block(hw
);
2972 return E1000_SUCCESS
;
2974 DEBUGOUT("Resetting Phy...\n");
2976 if(hw
->mac_type
> e1000_82543
) {
2977 /* Read the device control register and assert the E1000_CTRL_PHY_RST
2978 * bit. Then, take it out of reset.
2979 * For pre-e1000_82571 hardware, we delay for 10ms between the assert
2980 * and deassert. For e1000_82571 hardware and later, we instead delay
2981 * for 10ms after the deassertion.
2983 ctrl
= E1000_READ_REG(hw
, CTRL
);
2984 E1000_WRITE_REG(hw
, CTRL
, ctrl
| E1000_CTRL_PHY_RST
);
2985 E1000_WRITE_FLUSH(hw
);
2987 if (hw
->mac_type
< e1000_82571
)
2992 E1000_WRITE_REG(hw
, CTRL
, ctrl
);
2993 E1000_WRITE_FLUSH(hw
);
2995 if (hw
->mac_type
>= e1000_82571
)
2998 /* Read the Extended Device Control Register, assert the PHY_RESET_DIR
2999 * bit to put the PHY into reset. Then, take it out of reset.
3001 ctrl_ext
= E1000_READ_REG(hw
, CTRL_EXT
);
3002 ctrl_ext
|= E1000_CTRL_EXT_SDP4_DIR
;
3003 ctrl_ext
&= ~E1000_CTRL_EXT_SDP4_DATA
;
3004 E1000_WRITE_REG(hw
, CTRL_EXT
, ctrl_ext
);
3005 E1000_WRITE_FLUSH(hw
);
3007 ctrl_ext
|= E1000_CTRL_EXT_SDP4_DATA
;
3008 E1000_WRITE_REG(hw
, CTRL_EXT
, ctrl_ext
);
3009 E1000_WRITE_FLUSH(hw
);
3013 if((hw
->mac_type
== e1000_82541
) || (hw
->mac_type
== e1000_82547
)) {
3014 /* Configure activity LED after PHY reset */
3015 led_ctrl
= E1000_READ_REG(hw
, LEDCTL
);
3016 led_ctrl
&= IGP_ACTIVITY_LED_MASK
;
3017 led_ctrl
|= (IGP_ACTIVITY_LED_ENABLE
| IGP_LED3_MODE
);
3018 E1000_WRITE_REG(hw
, LEDCTL
, led_ctrl
);
3021 /* Wait for FW to finish PHY configuration. */
3022 ret_val
= e1000_get_phy_cfg_done(hw
);
3027 /******************************************************************************
3030 * hw - Struct containing variables accessed by shared code
3032 * Sets bit 15 of the MII Control regiser
3033 ******************************************************************************/
3035 e1000_phy_reset(struct e1000_hw
*hw
)
3040 DEBUGFUNC("e1000_phy_reset");
3042 /* In the case of the phy reset being blocked, it's not an error, we
3043 * simply return success without performing the reset. */
3044 ret_val
= e1000_check_phy_reset_block(hw
);
3046 return E1000_SUCCESS
;
3048 switch (hw
->mac_type
) {
3049 case e1000_82541_rev_2
:
3052 ret_val
= e1000_phy_hw_reset(hw
);
3057 ret_val
= e1000_read_phy_reg(hw
, PHY_CTRL
, &phy_data
);
3061 phy_data
|= MII_CR_RESET
;
3062 ret_val
= e1000_write_phy_reg(hw
, PHY_CTRL
, phy_data
);
3070 if(hw
->phy_type
== e1000_phy_igp
|| hw
->phy_type
== e1000_phy_igp_2
)
3071 e1000_phy_init_script(hw
);
3073 return E1000_SUCCESS
;
3076 /******************************************************************************
3077 * Probes the expected PHY address for known PHY IDs
3079 * hw - Struct containing variables accessed by shared code
3080 ******************************************************************************/
3082 e1000_detect_gig_phy(struct e1000_hw
*hw
)
3084 int32_t phy_init_status
, ret_val
;
3085 uint16_t phy_id_high
, phy_id_low
;
3086 boolean_t match
= FALSE
;
3088 DEBUGFUNC("e1000_detect_gig_phy");
3090 /* The 82571 firmware may still be configuring the PHY. In this
3091 * case, we cannot access the PHY until the configuration is done. So
3092 * we explicitly set the PHY values. */
3093 if(hw
->mac_type
== e1000_82571
||
3094 hw
->mac_type
== e1000_82572
) {
3095 hw
->phy_id
= IGP01E1000_I_PHY_ID
;
3096 hw
->phy_type
= e1000_phy_igp_2
;
3097 return E1000_SUCCESS
;
3100 /* Read the PHY ID Registers to identify which PHY is onboard. */
3101 ret_val
= e1000_read_phy_reg(hw
, PHY_ID1
, &phy_id_high
);
3105 hw
->phy_id
= (uint32_t) (phy_id_high
<< 16);
3107 ret_val
= e1000_read_phy_reg(hw
, PHY_ID2
, &phy_id_low
);
3111 hw
->phy_id
|= (uint32_t) (phy_id_low
& PHY_REVISION_MASK
);
3112 hw
->phy_revision
= (uint32_t) phy_id_low
& ~PHY_REVISION_MASK
;
3114 switch(hw
->mac_type
) {
3116 if(hw
->phy_id
== M88E1000_E_PHY_ID
) match
= TRUE
;
3119 if(hw
->phy_id
== M88E1000_I_PHY_ID
) match
= TRUE
;
3123 case e1000_82545_rev_3
:
3125 case e1000_82546_rev_3
:
3126 if(hw
->phy_id
== M88E1011_I_PHY_ID
) match
= TRUE
;
3129 case e1000_82541_rev_2
:
3131 case e1000_82547_rev_2
:
3132 if(hw
->phy_id
== IGP01E1000_I_PHY_ID
) match
= TRUE
;
3135 if(hw
->phy_id
== M88E1111_I_PHY_ID
) match
= TRUE
;
3138 DEBUGOUT1("Invalid MAC type %d\n", hw
->mac_type
);
3139 return -E1000_ERR_CONFIG
;
3141 phy_init_status
= e1000_set_phy_type(hw
);
3143 if ((match
) && (phy_init_status
== E1000_SUCCESS
)) {
3144 DEBUGOUT1("PHY ID 0x%X detected\n", hw
->phy_id
);
3145 return E1000_SUCCESS
;
3147 DEBUGOUT1("Invalid PHY ID 0x%X\n", hw
->phy_id
);
3148 return -E1000_ERR_PHY
;
3151 /******************************************************************************
3152 * Resets the PHY's DSP
3154 * hw - Struct containing variables accessed by shared code
3155 ******************************************************************************/
3157 e1000_phy_reset_dsp(struct e1000_hw
*hw
)
3160 DEBUGFUNC("e1000_phy_reset_dsp");
3163 ret_val
= e1000_write_phy_reg(hw
, 29, 0x001d);
3165 ret_val
= e1000_write_phy_reg(hw
, 30, 0x00c1);
3167 ret_val
= e1000_write_phy_reg(hw
, 30, 0x0000);
3169 ret_val
= E1000_SUCCESS
;
3175 /******************************************************************************
3176 * Get PHY information from various PHY registers for igp PHY only.
3178 * hw - Struct containing variables accessed by shared code
3179 * phy_info - PHY information structure
3180 ******************************************************************************/
3182 e1000_phy_igp_get_info(struct e1000_hw
*hw
,
3183 struct e1000_phy_info
*phy_info
)
3186 uint16_t phy_data
, polarity
, min_length
, max_length
, average
;
3188 DEBUGFUNC("e1000_phy_igp_get_info");
3190 /* The downshift status is checked only once, after link is established,
3191 * and it stored in the hw->speed_downgraded parameter. */
3192 phy_info
->downshift
= (e1000_downshift
)hw
->speed_downgraded
;
3194 /* IGP01E1000 does not need to support it. */
3195 phy_info
->extended_10bt_distance
= e1000_10bt_ext_dist_enable_normal
;
3197 /* IGP01E1000 always correct polarity reversal */
3198 phy_info
->polarity_correction
= e1000_polarity_reversal_enabled
;
3200 /* Check polarity status */
3201 ret_val
= e1000_check_polarity(hw
, &polarity
);
3205 phy_info
->cable_polarity
= polarity
;
3207 ret_val
= e1000_read_phy_reg(hw
, IGP01E1000_PHY_PORT_STATUS
, &phy_data
);
3211 phy_info
->mdix_mode
= (phy_data
& IGP01E1000_PSSR_MDIX
) >>
3212 IGP01E1000_PSSR_MDIX_SHIFT
;
3214 if((phy_data
& IGP01E1000_PSSR_SPEED_MASK
) ==
3215 IGP01E1000_PSSR_SPEED_1000MBPS
) {
3216 /* Local/Remote Receiver Information are only valid at 1000 Mbps */
3217 ret_val
= e1000_read_phy_reg(hw
, PHY_1000T_STATUS
, &phy_data
);
3221 phy_info
->local_rx
= (phy_data
& SR_1000T_LOCAL_RX_STATUS
) >>
3222 SR_1000T_LOCAL_RX_STATUS_SHIFT
;
3223 phy_info
->remote_rx
= (phy_data
& SR_1000T_REMOTE_RX_STATUS
) >>
3224 SR_1000T_REMOTE_RX_STATUS_SHIFT
;
3226 /* Get cable length */
3227 ret_val
= e1000_get_cable_length(hw
, &min_length
, &max_length
);
3231 /* Translate to old method */
3232 average
= (max_length
+ min_length
) / 2;
3234 if(average
<= e1000_igp_cable_length_50
)
3235 phy_info
->cable_length
= e1000_cable_length_50
;
3236 else if(average
<= e1000_igp_cable_length_80
)
3237 phy_info
->cable_length
= e1000_cable_length_50_80
;
3238 else if(average
<= e1000_igp_cable_length_110
)
3239 phy_info
->cable_length
= e1000_cable_length_80_110
;
3240 else if(average
<= e1000_igp_cable_length_140
)
3241 phy_info
->cable_length
= e1000_cable_length_110_140
;
3243 phy_info
->cable_length
= e1000_cable_length_140
;
3246 return E1000_SUCCESS
;
3249 /******************************************************************************
3250 * Get PHY information from various PHY registers fot m88 PHY only.
3252 * hw - Struct containing variables accessed by shared code
3253 * phy_info - PHY information structure
3254 ******************************************************************************/
3256 e1000_phy_m88_get_info(struct e1000_hw
*hw
,
3257 struct e1000_phy_info
*phy_info
)
3260 uint16_t phy_data
, polarity
;
3262 DEBUGFUNC("e1000_phy_m88_get_info");
3264 /* The downshift status is checked only once, after link is established,
3265 * and it stored in the hw->speed_downgraded parameter. */
3266 phy_info
->downshift
= (e1000_downshift
)hw
->speed_downgraded
;
3268 ret_val
= e1000_read_phy_reg(hw
, M88E1000_PHY_SPEC_CTRL
, &phy_data
);
3272 phy_info
->extended_10bt_distance
=
3273 (phy_data
& M88E1000_PSCR_10BT_EXT_DIST_ENABLE
) >>
3274 M88E1000_PSCR_10BT_EXT_DIST_ENABLE_SHIFT
;
3275 phy_info
->polarity_correction
=
3276 (phy_data
& M88E1000_PSCR_POLARITY_REVERSAL
) >>
3277 M88E1000_PSCR_POLARITY_REVERSAL_SHIFT
;
3279 /* Check polarity status */
3280 ret_val
= e1000_check_polarity(hw
, &polarity
);
3283 phy_info
->cable_polarity
= polarity
;
3285 ret_val
= e1000_read_phy_reg(hw
, M88E1000_PHY_SPEC_STATUS
, &phy_data
);
3289 phy_info
->mdix_mode
= (phy_data
& M88E1000_PSSR_MDIX
) >>
3290 M88E1000_PSSR_MDIX_SHIFT
;
3292 if ((phy_data
& M88E1000_PSSR_SPEED
) == M88E1000_PSSR_1000MBS
) {
3293 /* Cable Length Estimation and Local/Remote Receiver Information
3294 * are only valid at 1000 Mbps.
3296 phy_info
->cable_length
= ((phy_data
& M88E1000_PSSR_CABLE_LENGTH
) >>
3297 M88E1000_PSSR_CABLE_LENGTH_SHIFT
);
3299 ret_val
= e1000_read_phy_reg(hw
, PHY_1000T_STATUS
, &phy_data
);
3303 phy_info
->local_rx
= (phy_data
& SR_1000T_LOCAL_RX_STATUS
) >>
3304 SR_1000T_LOCAL_RX_STATUS_SHIFT
;
3306 phy_info
->remote_rx
= (phy_data
& SR_1000T_REMOTE_RX_STATUS
) >>
3307 SR_1000T_REMOTE_RX_STATUS_SHIFT
;
3310 return E1000_SUCCESS
;
3313 /******************************************************************************
3314 * Get PHY information from various PHY registers
3316 * hw - Struct containing variables accessed by shared code
3317 * phy_info - PHY information structure
3318 ******************************************************************************/
3320 e1000_phy_get_info(struct e1000_hw
*hw
,
3321 struct e1000_phy_info
*phy_info
)
3326 DEBUGFUNC("e1000_phy_get_info");
3328 phy_info
->cable_length
= e1000_cable_length_undefined
;
3329 phy_info
->extended_10bt_distance
= e1000_10bt_ext_dist_enable_undefined
;
3330 phy_info
->cable_polarity
= e1000_rev_polarity_undefined
;
3331 phy_info
->downshift
= e1000_downshift_undefined
;
3332 phy_info
->polarity_correction
= e1000_polarity_reversal_undefined
;
3333 phy_info
->mdix_mode
= e1000_auto_x_mode_undefined
;
3334 phy_info
->local_rx
= e1000_1000t_rx_status_undefined
;
3335 phy_info
->remote_rx
= e1000_1000t_rx_status_undefined
;
3337 if(hw
->media_type
!= e1000_media_type_copper
) {
3338 DEBUGOUT("PHY info is only valid for copper media\n");
3339 return -E1000_ERR_CONFIG
;
3342 ret_val
= e1000_read_phy_reg(hw
, PHY_STATUS
, &phy_data
);
3346 ret_val
= e1000_read_phy_reg(hw
, PHY_STATUS
, &phy_data
);
3350 if((phy_data
& MII_SR_LINK_STATUS
) != MII_SR_LINK_STATUS
) {
3351 DEBUGOUT("PHY info is only valid if link is up\n");
3352 return -E1000_ERR_CONFIG
;
3355 if(hw
->phy_type
== e1000_phy_igp
||
3356 hw
->phy_type
== e1000_phy_igp_2
)
3357 return e1000_phy_igp_get_info(hw
, phy_info
);
3359 return e1000_phy_m88_get_info(hw
, phy_info
);
3363 e1000_validate_mdi_setting(struct e1000_hw
*hw
)
3365 DEBUGFUNC("e1000_validate_mdi_settings");
3367 if(!hw
->autoneg
&& (hw
->mdix
== 0 || hw
->mdix
== 3)) {
3368 DEBUGOUT("Invalid MDI setting detected\n");
3370 return -E1000_ERR_CONFIG
;
3372 return E1000_SUCCESS
;
3376 /******************************************************************************
3377 * Sets up eeprom variables in the hw struct. Must be called after mac_type
3380 * hw - Struct containing variables accessed by shared code
3381 *****************************************************************************/
3383 e1000_init_eeprom_params(struct e1000_hw
*hw
)
3385 struct e1000_eeprom_info
*eeprom
= &hw
->eeprom
;
3386 uint32_t eecd
= E1000_READ_REG(hw
, EECD
);
3387 int32_t ret_val
= E1000_SUCCESS
;
3388 uint16_t eeprom_size
;
3390 DEBUGFUNC("e1000_init_eeprom_params");
3392 switch (hw
->mac_type
) {
3393 case e1000_82542_rev2_0
:
3394 case e1000_82542_rev2_1
:
3397 eeprom
->type
= e1000_eeprom_microwire
;
3398 eeprom
->word_size
= 64;
3399 eeprom
->opcode_bits
= 3;
3400 eeprom
->address_bits
= 6;
3401 eeprom
->delay_usec
= 50;
3402 eeprom
->use_eerd
= FALSE
;
3403 eeprom
->use_eewr
= FALSE
;
3407 case e1000_82545_rev_3
:
3409 case e1000_82546_rev_3
:
3410 eeprom
->type
= e1000_eeprom_microwire
;
3411 eeprom
->opcode_bits
= 3;
3412 eeprom
->delay_usec
= 50;
3413 if(eecd
& E1000_EECD_SIZE
) {
3414 eeprom
->word_size
= 256;
3415 eeprom
->address_bits
= 8;
3417 eeprom
->word_size
= 64;
3418 eeprom
->address_bits
= 6;
3420 eeprom
->use_eerd
= FALSE
;
3421 eeprom
->use_eewr
= FALSE
;
3424 case e1000_82541_rev_2
:
3426 case e1000_82547_rev_2
:
3427 if (eecd
& E1000_EECD_TYPE
) {
3428 eeprom
->type
= e1000_eeprom_spi
;
3429 eeprom
->opcode_bits
= 8;
3430 eeprom
->delay_usec
= 1;
3431 if (eecd
& E1000_EECD_ADDR_BITS
) {
3432 eeprom
->page_size
= 32;
3433 eeprom
->address_bits
= 16;
3435 eeprom
->page_size
= 8;
3436 eeprom
->address_bits
= 8;
3439 eeprom
->type
= e1000_eeprom_microwire
;
3440 eeprom
->opcode_bits
= 3;
3441 eeprom
->delay_usec
= 50;
3442 if (eecd
& E1000_EECD_ADDR_BITS
) {
3443 eeprom
->word_size
= 256;
3444 eeprom
->address_bits
= 8;
3446 eeprom
->word_size
= 64;
3447 eeprom
->address_bits
= 6;
3450 eeprom
->use_eerd
= FALSE
;
3451 eeprom
->use_eewr
= FALSE
;
3455 eeprom
->type
= e1000_eeprom_spi
;
3456 eeprom
->opcode_bits
= 8;
3457 eeprom
->delay_usec
= 1;
3458 if (eecd
& E1000_EECD_ADDR_BITS
) {
3459 eeprom
->page_size
= 32;
3460 eeprom
->address_bits
= 16;
3462 eeprom
->page_size
= 8;
3463 eeprom
->address_bits
= 8;
3465 eeprom
->use_eerd
= FALSE
;
3466 eeprom
->use_eewr
= FALSE
;
3469 eeprom
->type
= e1000_eeprom_spi
;
3470 eeprom
->opcode_bits
= 8;
3471 eeprom
->delay_usec
= 1;
3472 if (eecd
& E1000_EECD_ADDR_BITS
) {
3473 eeprom
->page_size
= 32;
3474 eeprom
->address_bits
= 16;
3476 eeprom
->page_size
= 8;
3477 eeprom
->address_bits
= 8;
3479 eeprom
->use_eerd
= TRUE
;
3480 eeprom
->use_eewr
= TRUE
;
3481 if(e1000_is_onboard_nvm_eeprom(hw
) == FALSE
) {
3482 eeprom
->type
= e1000_eeprom_flash
;
3483 eeprom
->word_size
= 2048;
3485 /* Ensure that the Autonomous FLASH update bit is cleared due to
3486 * Flash update issue on parts which use a FLASH for NVM. */
3487 eecd
&= ~E1000_EECD_AUPDEN
;
3488 E1000_WRITE_REG(hw
, EECD
, eecd
);
3495 if (eeprom
->type
== e1000_eeprom_spi
) {
3496 /* eeprom_size will be an enum [0..8] that maps to eeprom sizes 128B to
3497 * 32KB (incremented by powers of 2).
3499 if(hw
->mac_type
<= e1000_82547_rev_2
) {
3500 /* Set to default value for initial eeprom read. */
3501 eeprom
->word_size
= 64;
3502 ret_val
= e1000_read_eeprom(hw
, EEPROM_CFG
, 1, &eeprom_size
);
3505 eeprom_size
= (eeprom_size
& EEPROM_SIZE_MASK
) >> EEPROM_SIZE_SHIFT
;
3506 /* 256B eeprom size was not supported in earlier hardware, so we
3507 * bump eeprom_size up one to ensure that "1" (which maps to 256B)
3508 * is never the result used in the shifting logic below. */
3512 eeprom_size
= (uint16_t)((eecd
& E1000_EECD_SIZE_EX_MASK
) >>
3513 E1000_EECD_SIZE_EX_SHIFT
);
3516 eeprom
->word_size
= 1 << (eeprom_size
+ EEPROM_WORD_SIZE_SHIFT
);
3521 /******************************************************************************
3522 * Raises the EEPROM's clock input.
3524 * hw - Struct containing variables accessed by shared code
3525 * eecd - EECD's current value
3526 *****************************************************************************/
3528 e1000_raise_ee_clk(struct e1000_hw
*hw
,
3531 /* Raise the clock input to the EEPROM (by setting the SK bit), and then
3532 * wait <delay> microseconds.
3534 *eecd
= *eecd
| E1000_EECD_SK
;
3535 E1000_WRITE_REG(hw
, EECD
, *eecd
);
3536 E1000_WRITE_FLUSH(hw
);
3537 udelay(hw
->eeprom
.delay_usec
);
3540 /******************************************************************************
3541 * Lowers the EEPROM's clock input.
3543 * hw - Struct containing variables accessed by shared code
3544 * eecd - EECD's current value
3545 *****************************************************************************/
3547 e1000_lower_ee_clk(struct e1000_hw
*hw
,
3550 /* Lower the clock input to the EEPROM (by clearing the SK bit), and then
3551 * wait 50 microseconds.
3553 *eecd
= *eecd
& ~E1000_EECD_SK
;
3554 E1000_WRITE_REG(hw
, EECD
, *eecd
);
3555 E1000_WRITE_FLUSH(hw
);
3556 udelay(hw
->eeprom
.delay_usec
);
3559 /******************************************************************************
3560 * Shift data bits out to the EEPROM.
3562 * hw - Struct containing variables accessed by shared code
3563 * data - data to send to the EEPROM
3564 * count - number of bits to shift out
3565 *****************************************************************************/
3567 e1000_shift_out_ee_bits(struct e1000_hw
*hw
,
3571 struct e1000_eeprom_info
*eeprom
= &hw
->eeprom
;
3575 /* We need to shift "count" bits out to the EEPROM. So, value in the
3576 * "data" parameter will be shifted out to the EEPROM one bit at a time.
3577 * In order to do this, "data" must be broken down into bits.
3579 mask
= 0x01 << (count
- 1);
3580 eecd
= E1000_READ_REG(hw
, EECD
);
3581 if (eeprom
->type
== e1000_eeprom_microwire
) {
3582 eecd
&= ~E1000_EECD_DO
;
3583 } else if (eeprom
->type
== e1000_eeprom_spi
) {
3584 eecd
|= E1000_EECD_DO
;
3587 /* A "1" is shifted out to the EEPROM by setting bit "DI" to a "1",
3588 * and then raising and then lowering the clock (the SK bit controls
3589 * the clock input to the EEPROM). A "0" is shifted out to the EEPROM
3590 * by setting "DI" to "0" and then raising and then lowering the clock.
3592 eecd
&= ~E1000_EECD_DI
;
3595 eecd
|= E1000_EECD_DI
;
3597 E1000_WRITE_REG(hw
, EECD
, eecd
);
3598 E1000_WRITE_FLUSH(hw
);
3600 udelay(eeprom
->delay_usec
);
3602 e1000_raise_ee_clk(hw
, &eecd
);
3603 e1000_lower_ee_clk(hw
, &eecd
);
3609 /* We leave the "DI" bit set to "0" when we leave this routine. */
3610 eecd
&= ~E1000_EECD_DI
;
3611 E1000_WRITE_REG(hw
, EECD
, eecd
);
3614 /******************************************************************************
3615 * Shift data bits in from the EEPROM
3617 * hw - Struct containing variables accessed by shared code
3618 *****************************************************************************/
3620 e1000_shift_in_ee_bits(struct e1000_hw
*hw
,
3627 /* In order to read a register from the EEPROM, we need to shift 'count'
3628 * bits in from the EEPROM. Bits are "shifted in" by raising the clock
3629 * input to the EEPROM (setting the SK bit), and then reading the value of
3630 * the "DO" bit. During this "shifting in" process the "DI" bit should
3634 eecd
= E1000_READ_REG(hw
, EECD
);
3636 eecd
&= ~(E1000_EECD_DO
| E1000_EECD_DI
);
3639 for(i
= 0; i
< count
; i
++) {
3641 e1000_raise_ee_clk(hw
, &eecd
);
3643 eecd
= E1000_READ_REG(hw
, EECD
);
3645 eecd
&= ~(E1000_EECD_DI
);
3646 if(eecd
& E1000_EECD_DO
)
3649 e1000_lower_ee_clk(hw
, &eecd
);
3655 /******************************************************************************
3656 * Prepares EEPROM for access
3658 * hw - Struct containing variables accessed by shared code
3660 * Lowers EEPROM clock. Clears input pin. Sets the chip select pin. This
3661 * function should be called before issuing a command to the EEPROM.
3662 *****************************************************************************/
3664 e1000_acquire_eeprom(struct e1000_hw
*hw
)
3666 struct e1000_eeprom_info
*eeprom
= &hw
->eeprom
;
3669 DEBUGFUNC("e1000_acquire_eeprom");
3671 if(e1000_get_hw_eeprom_semaphore(hw
))
3672 return -E1000_ERR_EEPROM
;
3674 eecd
= E1000_READ_REG(hw
, EECD
);
3676 if (hw
->mac_type
!= e1000_82573
) {
3677 /* Request EEPROM Access */
3678 if(hw
->mac_type
> e1000_82544
) {
3679 eecd
|= E1000_EECD_REQ
;
3680 E1000_WRITE_REG(hw
, EECD
, eecd
);
3681 eecd
= E1000_READ_REG(hw
, EECD
);
3682 while((!(eecd
& E1000_EECD_GNT
)) &&
3683 (i
< E1000_EEPROM_GRANT_ATTEMPTS
)) {
3686 eecd
= E1000_READ_REG(hw
, EECD
);
3688 if(!(eecd
& E1000_EECD_GNT
)) {
3689 eecd
&= ~E1000_EECD_REQ
;
3690 E1000_WRITE_REG(hw
, EECD
, eecd
);
3691 DEBUGOUT("Could not acquire EEPROM grant\n");
3692 e1000_put_hw_eeprom_semaphore(hw
);
3693 return -E1000_ERR_EEPROM
;
3698 /* Setup EEPROM for Read/Write */
3700 if (eeprom
->type
== e1000_eeprom_microwire
) {
3701 /* Clear SK and DI */
3702 eecd
&= ~(E1000_EECD_DI
| E1000_EECD_SK
);
3703 E1000_WRITE_REG(hw
, EECD
, eecd
);
3706 eecd
|= E1000_EECD_CS
;
3707 E1000_WRITE_REG(hw
, EECD
, eecd
);
3708 } else if (eeprom
->type
== e1000_eeprom_spi
) {
3709 /* Clear SK and CS */
3710 eecd
&= ~(E1000_EECD_CS
| E1000_EECD_SK
);
3711 E1000_WRITE_REG(hw
, EECD
, eecd
);
3715 return E1000_SUCCESS
;
3718 /******************************************************************************
3719 * Returns EEPROM to a "standby" state
3721 * hw - Struct containing variables accessed by shared code
3722 *****************************************************************************/
3724 e1000_standby_eeprom(struct e1000_hw
*hw
)
3726 struct e1000_eeprom_info
*eeprom
= &hw
->eeprom
;
3729 eecd
= E1000_READ_REG(hw
, EECD
);
3731 if(eeprom
->type
== e1000_eeprom_microwire
) {
3732 eecd
&= ~(E1000_EECD_CS
| E1000_EECD_SK
);
3733 E1000_WRITE_REG(hw
, EECD
, eecd
);
3734 E1000_WRITE_FLUSH(hw
);
3735 udelay(eeprom
->delay_usec
);
3738 eecd
|= E1000_EECD_SK
;
3739 E1000_WRITE_REG(hw
, EECD
, eecd
);
3740 E1000_WRITE_FLUSH(hw
);
3741 udelay(eeprom
->delay_usec
);
3744 eecd
|= E1000_EECD_CS
;
3745 E1000_WRITE_REG(hw
, EECD
, eecd
);
3746 E1000_WRITE_FLUSH(hw
);
3747 udelay(eeprom
->delay_usec
);
3750 eecd
&= ~E1000_EECD_SK
;
3751 E1000_WRITE_REG(hw
, EECD
, eecd
);
3752 E1000_WRITE_FLUSH(hw
);
3753 udelay(eeprom
->delay_usec
);
3754 } else if(eeprom
->type
== e1000_eeprom_spi
) {
3755 /* Toggle CS to flush commands */
3756 eecd
|= E1000_EECD_CS
;
3757 E1000_WRITE_REG(hw
, EECD
, eecd
);
3758 E1000_WRITE_FLUSH(hw
);
3759 udelay(eeprom
->delay_usec
);
3760 eecd
&= ~E1000_EECD_CS
;
3761 E1000_WRITE_REG(hw
, EECD
, eecd
);
3762 E1000_WRITE_FLUSH(hw
);
3763 udelay(eeprom
->delay_usec
);
3767 /******************************************************************************
3768 * Terminates a command by inverting the EEPROM's chip select pin
3770 * hw - Struct containing variables accessed by shared code
3771 *****************************************************************************/
3773 e1000_release_eeprom(struct e1000_hw
*hw
)
3777 DEBUGFUNC("e1000_release_eeprom");
3779 eecd
= E1000_READ_REG(hw
, EECD
);
3781 if (hw
->eeprom
.type
== e1000_eeprom_spi
) {
3782 eecd
|= E1000_EECD_CS
; /* Pull CS high */
3783 eecd
&= ~E1000_EECD_SK
; /* Lower SCK */
3785 E1000_WRITE_REG(hw
, EECD
, eecd
);
3787 udelay(hw
->eeprom
.delay_usec
);
3788 } else if(hw
->eeprom
.type
== e1000_eeprom_microwire
) {
3789 /* cleanup eeprom */
3791 /* CS on Microwire is active-high */
3792 eecd
&= ~(E1000_EECD_CS
| E1000_EECD_DI
);
3794 E1000_WRITE_REG(hw
, EECD
, eecd
);
3796 /* Rising edge of clock */
3797 eecd
|= E1000_EECD_SK
;
3798 E1000_WRITE_REG(hw
, EECD
, eecd
);
3799 E1000_WRITE_FLUSH(hw
);
3800 udelay(hw
->eeprom
.delay_usec
);
3802 /* Falling edge of clock */
3803 eecd
&= ~E1000_EECD_SK
;
3804 E1000_WRITE_REG(hw
, EECD
, eecd
);
3805 E1000_WRITE_FLUSH(hw
);
3806 udelay(hw
->eeprom
.delay_usec
);
3809 /* Stop requesting EEPROM access */
3810 if(hw
->mac_type
> e1000_82544
) {
3811 eecd
&= ~E1000_EECD_REQ
;
3812 E1000_WRITE_REG(hw
, EECD
, eecd
);
3815 e1000_put_hw_eeprom_semaphore(hw
);
3818 /******************************************************************************
3819 * Reads a 16 bit word from the EEPROM.
3821 * hw - Struct containing variables accessed by shared code
3822 *****************************************************************************/
3824 e1000_spi_eeprom_ready(struct e1000_hw
*hw
)
3826 uint16_t retry_count
= 0;
3827 uint8_t spi_stat_reg
;
3829 DEBUGFUNC("e1000_spi_eeprom_ready");
3831 /* Read "Status Register" repeatedly until the LSB is cleared. The
3832 * EEPROM will signal that the command has been completed by clearing
3833 * bit 0 of the internal status register. If it's not cleared within
3834 * 5 milliseconds, then error out.
3838 e1000_shift_out_ee_bits(hw
, EEPROM_RDSR_OPCODE_SPI
,
3839 hw
->eeprom
.opcode_bits
);
3840 spi_stat_reg
= (uint8_t)e1000_shift_in_ee_bits(hw
, 8);
3841 if (!(spi_stat_reg
& EEPROM_STATUS_RDY_SPI
))
3847 e1000_standby_eeprom(hw
);
3848 } while(retry_count
< EEPROM_MAX_RETRY_SPI
);
3850 /* ATMEL SPI write time could vary from 0-20mSec on 3.3V devices (and
3851 * only 0-5mSec on 5V devices)
3853 if(retry_count
>= EEPROM_MAX_RETRY_SPI
) {
3854 DEBUGOUT("SPI EEPROM Status error\n");
3855 return -E1000_ERR_EEPROM
;
3858 return E1000_SUCCESS
;
3861 /******************************************************************************
3862 * Reads a 16 bit word from the EEPROM.
3864 * hw - Struct containing variables accessed by shared code
3865 * offset - offset of word in the EEPROM to read
3866 * data - word read from the EEPROM
3867 * words - number of words to read
3868 *****************************************************************************/
3870 e1000_read_eeprom(struct e1000_hw
*hw
,
3875 struct e1000_eeprom_info
*eeprom
= &hw
->eeprom
;
3879 DEBUGFUNC("e1000_read_eeprom");
3881 /* A check for invalid values: offset too large, too many words, and not
3884 if((offset
>= eeprom
->word_size
) || (words
> eeprom
->word_size
- offset
) ||
3886 DEBUGOUT("\"words\" parameter out of bounds\n");
3887 return -E1000_ERR_EEPROM
;
3890 /* FLASH reads without acquiring the semaphore are safe */
3891 if (e1000_is_onboard_nvm_eeprom(hw
) == TRUE
&&
3892 hw
->eeprom
.use_eerd
== FALSE
) {
3893 switch (hw
->mac_type
) {
3895 /* Prepare the EEPROM for reading */
3896 if (e1000_acquire_eeprom(hw
) != E1000_SUCCESS
)
3897 return -E1000_ERR_EEPROM
;
3902 if(eeprom
->use_eerd
== TRUE
) {
3903 ret_val
= e1000_read_eeprom_eerd(hw
, offset
, words
, data
);
3904 if ((e1000_is_onboard_nvm_eeprom(hw
) == TRUE
) ||
3905 (hw
->mac_type
!= e1000_82573
))
3906 e1000_release_eeprom(hw
);
3910 if(eeprom
->type
== e1000_eeprom_spi
) {
3912 uint8_t read_opcode
= EEPROM_READ_OPCODE_SPI
;
3914 if(e1000_spi_eeprom_ready(hw
)) {
3915 e1000_release_eeprom(hw
);
3916 return -E1000_ERR_EEPROM
;
3919 e1000_standby_eeprom(hw
);
3921 /* Some SPI eeproms use the 8th address bit embedded in the opcode */
3922 if((eeprom
->address_bits
== 8) && (offset
>= 128))
3923 read_opcode
|= EEPROM_A8_OPCODE_SPI
;
3925 /* Send the READ command (opcode + addr) */
3926 e1000_shift_out_ee_bits(hw
, read_opcode
, eeprom
->opcode_bits
);
3927 e1000_shift_out_ee_bits(hw
, (uint16_t)(offset
*2), eeprom
->address_bits
);
3929 /* Read the data. The address of the eeprom internally increments with
3930 * each byte (spi) being read, saving on the overhead of eeprom setup
3931 * and tear-down. The address counter will roll over if reading beyond
3932 * the size of the eeprom, thus allowing the entire memory to be read
3933 * starting from any offset. */
3934 for (i
= 0; i
< words
; i
++) {
3935 word_in
= e1000_shift_in_ee_bits(hw
, 16);
3936 data
[i
] = (word_in
>> 8) | (word_in
<< 8);
3938 } else if(eeprom
->type
== e1000_eeprom_microwire
) {
3939 for (i
= 0; i
< words
; i
++) {
3940 /* Send the READ command (opcode + addr) */
3941 e1000_shift_out_ee_bits(hw
, EEPROM_READ_OPCODE_MICROWIRE
,
3942 eeprom
->opcode_bits
);
3943 e1000_shift_out_ee_bits(hw
, (uint16_t)(offset
+ i
),
3944 eeprom
->address_bits
);
3946 /* Read the data. For microwire, each word requires the overhead
3947 * of eeprom setup and tear-down. */
3948 data
[i
] = e1000_shift_in_ee_bits(hw
, 16);
3949 e1000_standby_eeprom(hw
);
3953 /* End this read operation */
3954 e1000_release_eeprom(hw
);
3956 return E1000_SUCCESS
;
3959 /******************************************************************************
3960 * Reads a 16 bit word from the EEPROM using the EERD register.
3962 * hw - Struct containing variables accessed by shared code
3963 * offset - offset of word in the EEPROM to read
3964 * data - word read from the EEPROM
3965 * words - number of words to read
3966 *****************************************************************************/
3968 e1000_read_eeprom_eerd(struct e1000_hw
*hw
,
3973 uint32_t i
, eerd
= 0;
3976 for (i
= 0; i
< words
; i
++) {
3977 eerd
= ((offset
+i
) << E1000_EEPROM_RW_ADDR_SHIFT
) +
3978 E1000_EEPROM_RW_REG_START
;
3980 E1000_WRITE_REG(hw
, EERD
, eerd
);
3981 error
= e1000_poll_eerd_eewr_done(hw
, E1000_EEPROM_POLL_READ
);
3986 data
[i
] = (E1000_READ_REG(hw
, EERD
) >> E1000_EEPROM_RW_REG_DATA
);
3993 /******************************************************************************
3994 * Writes a 16 bit word from the EEPROM using the EEWR register.
3996 * hw - Struct containing variables accessed by shared code
3997 * offset - offset of word in the EEPROM to read
3998 * data - word read from the EEPROM
3999 * words - number of words to read
4000 *****************************************************************************/
4002 e1000_write_eeprom_eewr(struct e1000_hw
*hw
,
4007 uint32_t register_value
= 0;
4011 for (i
= 0; i
< words
; i
++) {
4012 register_value
= (data
[i
] << E1000_EEPROM_RW_REG_DATA
) |
4013 ((offset
+i
) << E1000_EEPROM_RW_ADDR_SHIFT
) |
4014 E1000_EEPROM_RW_REG_START
;
4016 error
= e1000_poll_eerd_eewr_done(hw
, E1000_EEPROM_POLL_WRITE
);
4021 E1000_WRITE_REG(hw
, EEWR
, register_value
);
4023 error
= e1000_poll_eerd_eewr_done(hw
, E1000_EEPROM_POLL_WRITE
);
4033 /******************************************************************************
4034 * Polls the status bit (bit 1) of the EERD to determine when the read is done.
4036 * hw - Struct containing variables accessed by shared code
4037 *****************************************************************************/
4039 e1000_poll_eerd_eewr_done(struct e1000_hw
*hw
, int eerd
)
4041 uint32_t attempts
= 100000;
4042 uint32_t i
, reg
= 0;
4043 int32_t done
= E1000_ERR_EEPROM
;
4045 for(i
= 0; i
< attempts
; i
++) {
4046 if(eerd
== E1000_EEPROM_POLL_READ
)
4047 reg
= E1000_READ_REG(hw
, EERD
);
4049 reg
= E1000_READ_REG(hw
, EEWR
);
4051 if(reg
& E1000_EEPROM_RW_REG_DONE
) {
4052 done
= E1000_SUCCESS
;
4061 /***************************************************************************
4062 * Description: Determines if the onboard NVM is FLASH or EEPROM.
4064 * hw - Struct containing variables accessed by shared code
4065 ****************************************************************************/
4067 e1000_is_onboard_nvm_eeprom(struct e1000_hw
*hw
)
4071 if(hw
->mac_type
== e1000_82573
) {
4072 eecd
= E1000_READ_REG(hw
, EECD
);
4074 /* Isolate bits 15 & 16 */
4075 eecd
= ((eecd
>> 15) & 0x03);
4077 /* If both bits are set, device is Flash type */
4085 /******************************************************************************
4086 * Verifies that the EEPROM has a valid checksum
4088 * hw - Struct containing variables accessed by shared code
4090 * Reads the first 64 16 bit words of the EEPROM and sums the values read.
4091 * If the the sum of the 64 16 bit words is 0xBABA, the EEPROM's checksum is
4093 *****************************************************************************/
4095 e1000_validate_eeprom_checksum(struct e1000_hw
*hw
)
4097 uint16_t checksum
= 0;
4098 uint16_t i
, eeprom_data
;
4100 DEBUGFUNC("e1000_validate_eeprom_checksum");
4102 if ((hw
->mac_type
== e1000_82573
) &&
4103 (e1000_is_onboard_nvm_eeprom(hw
) == FALSE
)) {
4104 /* Check bit 4 of word 10h. If it is 0, firmware is done updating
4105 * 10h-12h. Checksum may need to be fixed. */
4106 e1000_read_eeprom(hw
, 0x10, 1, &eeprom_data
);
4107 if ((eeprom_data
& 0x10) == 0) {
4108 /* Read 0x23 and check bit 15. This bit is a 1 when the checksum
4109 * has already been fixed. If the checksum is still wrong and this
4110 * bit is a 1, we need to return bad checksum. Otherwise, we need
4111 * to set this bit to a 1 and update the checksum. */
4112 e1000_read_eeprom(hw
, 0x23, 1, &eeprom_data
);
4113 if ((eeprom_data
& 0x8000) == 0) {
4114 eeprom_data
|= 0x8000;
4115 e1000_write_eeprom(hw
, 0x23, 1, &eeprom_data
);
4116 e1000_update_eeprom_checksum(hw
);
4121 for(i
= 0; i
< (EEPROM_CHECKSUM_REG
+ 1); i
++) {
4122 if(e1000_read_eeprom(hw
, i
, 1, &eeprom_data
) < 0) {
4123 DEBUGOUT("EEPROM Read Error\n");
4124 return -E1000_ERR_EEPROM
;
4126 checksum
+= eeprom_data
;
4129 if(checksum
== (uint16_t) EEPROM_SUM
)
4130 return E1000_SUCCESS
;
4132 DEBUGOUT("EEPROM Checksum Invalid\n");
4133 return -E1000_ERR_EEPROM
;
4137 /******************************************************************************
4138 * Calculates the EEPROM checksum and writes it to the EEPROM
4140 * hw - Struct containing variables accessed by shared code
4142 * Sums the first 63 16 bit words of the EEPROM. Subtracts the sum from 0xBABA.
4143 * Writes the difference to word offset 63 of the EEPROM.
4144 *****************************************************************************/
4146 e1000_update_eeprom_checksum(struct e1000_hw
*hw
)
4148 uint16_t checksum
= 0;
4149 uint16_t i
, eeprom_data
;
4151 DEBUGFUNC("e1000_update_eeprom_checksum");
4153 for(i
= 0; i
< EEPROM_CHECKSUM_REG
; i
++) {
4154 if(e1000_read_eeprom(hw
, i
, 1, &eeprom_data
) < 0) {
4155 DEBUGOUT("EEPROM Read Error\n");
4156 return -E1000_ERR_EEPROM
;
4158 checksum
+= eeprom_data
;
4160 checksum
= (uint16_t) EEPROM_SUM
- checksum
;
4161 if(e1000_write_eeprom(hw
, EEPROM_CHECKSUM_REG
, 1, &checksum
) < 0) {
4162 DEBUGOUT("EEPROM Write Error\n");
4163 return -E1000_ERR_EEPROM
;
4164 } else if (hw
->eeprom
.type
== e1000_eeprom_flash
) {
4165 e1000_commit_shadow_ram(hw
);
4167 return E1000_SUCCESS
;
4170 /******************************************************************************
4171 * Parent function for writing words to the different EEPROM types.
4173 * hw - Struct containing variables accessed by shared code
4174 * offset - offset within the EEPROM to be written to
4175 * words - number of words to write
4176 * data - 16 bit word to be written to the EEPROM
4178 * If e1000_update_eeprom_checksum is not called after this function, the
4179 * EEPROM will most likely contain an invalid checksum.
4180 *****************************************************************************/
4182 e1000_write_eeprom(struct e1000_hw
*hw
,
4187 struct e1000_eeprom_info
*eeprom
= &hw
->eeprom
;
4190 DEBUGFUNC("e1000_write_eeprom");
4192 /* A check for invalid values: offset too large, too many words, and not
4195 if((offset
>= eeprom
->word_size
) || (words
> eeprom
->word_size
- offset
) ||
4197 DEBUGOUT("\"words\" parameter out of bounds\n");
4198 return -E1000_ERR_EEPROM
;
4201 /* 82573 writes only through eewr */
4202 if(eeprom
->use_eewr
== TRUE
)
4203 return e1000_write_eeprom_eewr(hw
, offset
, words
, data
);
4205 /* Prepare the EEPROM for writing */
4206 if (e1000_acquire_eeprom(hw
) != E1000_SUCCESS
)
4207 return -E1000_ERR_EEPROM
;
4209 if(eeprom
->type
== e1000_eeprom_microwire
) {
4210 status
= e1000_write_eeprom_microwire(hw
, offset
, words
, data
);
4212 status
= e1000_write_eeprom_spi(hw
, offset
, words
, data
);
4216 /* Done with writing */
4217 e1000_release_eeprom(hw
);
4222 /******************************************************************************
4223 * Writes a 16 bit word to a given offset in an SPI EEPROM.
4225 * hw - Struct containing variables accessed by shared code
4226 * offset - offset within the EEPROM to be written to
4227 * words - number of words to write
4228 * data - pointer to array of 8 bit words to be written to the EEPROM
4230 *****************************************************************************/
4232 e1000_write_eeprom_spi(struct e1000_hw
*hw
,
4237 struct e1000_eeprom_info
*eeprom
= &hw
->eeprom
;
4240 DEBUGFUNC("e1000_write_eeprom_spi");
4242 while (widx
< words
) {
4243 uint8_t write_opcode
= EEPROM_WRITE_OPCODE_SPI
;
4245 if(e1000_spi_eeprom_ready(hw
)) return -E1000_ERR_EEPROM
;
4247 e1000_standby_eeprom(hw
);
4249 /* Send the WRITE ENABLE command (8 bit opcode ) */
4250 e1000_shift_out_ee_bits(hw
, EEPROM_WREN_OPCODE_SPI
,
4251 eeprom
->opcode_bits
);
4253 e1000_standby_eeprom(hw
);
4255 /* Some SPI eeproms use the 8th address bit embedded in the opcode */
4256 if((eeprom
->address_bits
== 8) && (offset
>= 128))
4257 write_opcode
|= EEPROM_A8_OPCODE_SPI
;
4259 /* Send the Write command (8-bit opcode + addr) */
4260 e1000_shift_out_ee_bits(hw
, write_opcode
, eeprom
->opcode_bits
);
4262 e1000_shift_out_ee_bits(hw
, (uint16_t)((offset
+ widx
)*2),
4263 eeprom
->address_bits
);
4267 /* Loop to allow for up to whole page write (32 bytes) of eeprom */
4268 while (widx
< words
) {
4269 uint16_t word_out
= data
[widx
];
4270 word_out
= (word_out
>> 8) | (word_out
<< 8);
4271 e1000_shift_out_ee_bits(hw
, word_out
, 16);
4274 /* Some larger eeprom sizes are capable of a 32-byte PAGE WRITE
4275 * operation, while the smaller eeproms are capable of an 8-byte
4276 * PAGE WRITE operation. Break the inner loop to pass new address
4278 if((((offset
+ widx
)*2) % eeprom
->page_size
) == 0) {
4279 e1000_standby_eeprom(hw
);
4285 return E1000_SUCCESS
;
4288 /******************************************************************************
4289 * Writes a 16 bit word to a given offset in a Microwire EEPROM.
4291 * hw - Struct containing variables accessed by shared code
4292 * offset - offset within the EEPROM to be written to
4293 * words - number of words to write
4294 * data - pointer to array of 16 bit words to be written to the EEPROM
4296 *****************************************************************************/
4298 e1000_write_eeprom_microwire(struct e1000_hw
*hw
,
4303 struct e1000_eeprom_info
*eeprom
= &hw
->eeprom
;
4305 uint16_t words_written
= 0;
4308 DEBUGFUNC("e1000_write_eeprom_microwire");
4310 /* Send the write enable command to the EEPROM (3-bit opcode plus
4311 * 6/8-bit dummy address beginning with 11). It's less work to include
4312 * the 11 of the dummy address as part of the opcode than it is to shift
4313 * it over the correct number of bits for the address. This puts the
4314 * EEPROM into write/erase mode.
4316 e1000_shift_out_ee_bits(hw
, EEPROM_EWEN_OPCODE_MICROWIRE
,
4317 (uint16_t)(eeprom
->opcode_bits
+ 2));
4319 e1000_shift_out_ee_bits(hw
, 0, (uint16_t)(eeprom
->address_bits
- 2));
4321 /* Prepare the EEPROM */
4322 e1000_standby_eeprom(hw
);
4324 while (words_written
< words
) {
4325 /* Send the Write command (3-bit opcode + addr) */
4326 e1000_shift_out_ee_bits(hw
, EEPROM_WRITE_OPCODE_MICROWIRE
,
4327 eeprom
->opcode_bits
);
4329 e1000_shift_out_ee_bits(hw
, (uint16_t)(offset
+ words_written
),
4330 eeprom
->address_bits
);
4333 e1000_shift_out_ee_bits(hw
, data
[words_written
], 16);
4335 /* Toggle the CS line. This in effect tells the EEPROM to execute
4336 * the previous command.
4338 e1000_standby_eeprom(hw
);
4340 /* Read DO repeatedly until it is high (equal to '1'). The EEPROM will
4341 * signal that the command has been completed by raising the DO signal.
4342 * If DO does not go high in 10 milliseconds, then error out.
4344 for(i
= 0; i
< 200; i
++) {
4345 eecd
= E1000_READ_REG(hw
, EECD
);
4346 if(eecd
& E1000_EECD_DO
) break;
4350 DEBUGOUT("EEPROM Write did not complete\n");
4351 return -E1000_ERR_EEPROM
;
4354 /* Recover from write */
4355 e1000_standby_eeprom(hw
);
4360 /* Send the write disable command to the EEPROM (3-bit opcode plus
4361 * 6/8-bit dummy address beginning with 10). It's less work to include
4362 * the 10 of the dummy address as part of the opcode than it is to shift
4363 * it over the correct number of bits for the address. This takes the
4364 * EEPROM out of write/erase mode.
4366 e1000_shift_out_ee_bits(hw
, EEPROM_EWDS_OPCODE_MICROWIRE
,
4367 (uint16_t)(eeprom
->opcode_bits
+ 2));
4369 e1000_shift_out_ee_bits(hw
, 0, (uint16_t)(eeprom
->address_bits
- 2));
4371 return E1000_SUCCESS
;
4374 /******************************************************************************
4375 * Flushes the cached eeprom to NVM. This is done by saving the modified values
4376 * in the eeprom cache and the non modified values in the currently active bank
4379 * hw - Struct containing variables accessed by shared code
4380 * offset - offset of word in the EEPROM to read
4381 * data - word read from the EEPROM
4382 * words - number of words to read
4383 *****************************************************************************/
4385 e1000_commit_shadow_ram(struct e1000_hw
*hw
)
4387 uint32_t attempts
= 100000;
4391 int32_t error
= E1000_SUCCESS
;
4393 /* The flop register will be used to determine if flash type is STM */
4394 flop
= E1000_READ_REG(hw
, FLOP
);
4396 if (hw
->mac_type
== e1000_82573
) {
4397 for (i
=0; i
< attempts
; i
++) {
4398 eecd
= E1000_READ_REG(hw
, EECD
);
4399 if ((eecd
& E1000_EECD_FLUPD
) == 0) {
4405 if (i
== attempts
) {
4406 return -E1000_ERR_EEPROM
;
4409 /* If STM opcode located in bits 15:8 of flop, reset firmware */
4410 if ((flop
& 0xFF00) == E1000_STM_OPCODE
) {
4411 E1000_WRITE_REG(hw
, HICR
, E1000_HICR_FW_RESET
);
4414 /* Perform the flash update */
4415 E1000_WRITE_REG(hw
, EECD
, eecd
| E1000_EECD_FLUPD
);
4417 for (i
=0; i
< attempts
; i
++) {
4418 eecd
= E1000_READ_REG(hw
, EECD
);
4419 if ((eecd
& E1000_EECD_FLUPD
) == 0) {
4425 if (i
== attempts
) {
4426 return -E1000_ERR_EEPROM
;
4433 /******************************************************************************
4434 * Reads the adapter's part number from the EEPROM
4436 * hw - Struct containing variables accessed by shared code
4437 * part_num - Adapter's part number
4438 *****************************************************************************/
4440 e1000_read_part_num(struct e1000_hw
*hw
,
4443 uint16_t offset
= EEPROM_PBA_BYTE_1
;
4444 uint16_t eeprom_data
;
4446 DEBUGFUNC("e1000_read_part_num");
4448 /* Get word 0 from EEPROM */
4449 if(e1000_read_eeprom(hw
, offset
, 1, &eeprom_data
) < 0) {
4450 DEBUGOUT("EEPROM Read Error\n");
4451 return -E1000_ERR_EEPROM
;
4453 /* Save word 0 in upper half of part_num */
4454 *part_num
= (uint32_t) (eeprom_data
<< 16);
4456 /* Get word 1 from EEPROM */
4457 if(e1000_read_eeprom(hw
, ++offset
, 1, &eeprom_data
) < 0) {
4458 DEBUGOUT("EEPROM Read Error\n");
4459 return -E1000_ERR_EEPROM
;
4461 /* Save word 1 in lower half of part_num */
4462 *part_num
|= eeprom_data
;
4464 return E1000_SUCCESS
;
4467 /******************************************************************************
4468 * Reads the adapter's MAC address from the EEPROM and inverts the LSB for the
4469 * second function of dual function devices
4471 * hw - Struct containing variables accessed by shared code
4472 *****************************************************************************/
4474 e1000_read_mac_addr(struct e1000_hw
* hw
)
4477 uint16_t eeprom_data
, i
;
4479 DEBUGFUNC("e1000_read_mac_addr");
4481 for(i
= 0; i
< NODE_ADDRESS_SIZE
; i
+= 2) {
4483 if(e1000_read_eeprom(hw
, offset
, 1, &eeprom_data
) < 0) {
4484 DEBUGOUT("EEPROM Read Error\n");
4485 return -E1000_ERR_EEPROM
;
4487 hw
->perm_mac_addr
[i
] = (uint8_t) (eeprom_data
& 0x00FF);
4488 hw
->perm_mac_addr
[i
+1] = (uint8_t) (eeprom_data
>> 8);
4490 switch (hw
->mac_type
) {
4494 case e1000_82546_rev_3
:
4496 if(E1000_READ_REG(hw
, STATUS
) & E1000_STATUS_FUNC_1
)
4497 hw
->perm_mac_addr
[5] ^= 0x01;
4501 for(i
= 0; i
< NODE_ADDRESS_SIZE
; i
++)
4502 hw
->mac_addr
[i
] = hw
->perm_mac_addr
[i
];
4503 return E1000_SUCCESS
;
4506 /******************************************************************************
4507 * Initializes receive address filters.
4509 * hw - Struct containing variables accessed by shared code
4511 * Places the MAC address in receive address register 0 and clears the rest
4512 * of the receive addresss registers. Clears the multicast table. Assumes
4513 * the receiver is in reset when the routine is called.
4514 *****************************************************************************/
4516 e1000_init_rx_addrs(struct e1000_hw
*hw
)
4521 DEBUGFUNC("e1000_init_rx_addrs");
4523 /* Setup the receive address. */
4524 DEBUGOUT("Programming MAC Address into RAR[0]\n");
4526 e1000_rar_set(hw
, hw
->mac_addr
, 0);
4528 rar_num
= E1000_RAR_ENTRIES
;
4530 /* Reserve a spot for the Locally Administered Address to work around
4531 * an 82571 issue in which a reset on one port will reload the MAC on
4532 * the other port. */
4533 if ((hw
->mac_type
== e1000_82571
) && (hw
->laa_is_present
== TRUE
))
4535 /* Zero out the other 15 receive addresses. */
4536 DEBUGOUT("Clearing RAR[1-15]\n");
4537 for(i
= 1; i
< rar_num
; i
++) {
4538 E1000_WRITE_REG_ARRAY(hw
, RA
, (i
<< 1), 0);
4539 E1000_WRITE_REG_ARRAY(hw
, RA
, ((i
<< 1) + 1), 0);
4544 /******************************************************************************
4545 * Updates the MAC's list of multicast addresses.
4547 * hw - Struct containing variables accessed by shared code
4548 * mc_addr_list - the list of new multicast addresses
4549 * mc_addr_count - number of addresses
4550 * pad - number of bytes between addresses in the list
4551 * rar_used_count - offset where to start adding mc addresses into the RAR's
4553 * The given list replaces any existing list. Clears the last 15 receive
4554 * address registers and the multicast table. Uses receive address registers
4555 * for the first 15 multicast addresses, and hashes the rest into the
4557 *****************************************************************************/
4559 e1000_mc_addr_list_update(struct e1000_hw
*hw
,
4560 uint8_t *mc_addr_list
,
4561 uint32_t mc_addr_count
,
4563 uint32_t rar_used_count
)
4565 uint32_t hash_value
;
4567 uint32_t num_rar_entry
;
4568 uint32_t num_mta_entry
;
4570 DEBUGFUNC("e1000_mc_addr_list_update");
4572 /* Set the new number of MC addresses that we are being requested to use. */
4573 hw
->num_mc_addrs
= mc_addr_count
;
4575 /* Clear RAR[1-15] */
4576 DEBUGOUT(" Clearing RAR[1-15]\n");
4577 num_rar_entry
= E1000_RAR_ENTRIES
;
4578 /* Reserve a spot for the Locally Administered Address to work around
4579 * an 82571 issue in which a reset on one port will reload the MAC on
4580 * the other port. */
4581 if ((hw
->mac_type
== e1000_82571
) && (hw
->laa_is_present
== TRUE
))
4584 for(i
= rar_used_count
; i
< num_rar_entry
; i
++) {
4585 E1000_WRITE_REG_ARRAY(hw
, RA
, (i
<< 1), 0);
4586 E1000_WRITE_REG_ARRAY(hw
, RA
, ((i
<< 1) + 1), 0);
4590 DEBUGOUT(" Clearing MTA\n");
4591 num_mta_entry
= E1000_NUM_MTA_REGISTERS
;
4592 for(i
= 0; i
< num_mta_entry
; i
++) {
4593 E1000_WRITE_REG_ARRAY(hw
, MTA
, i
, 0);
4596 /* Add the new addresses */
4597 for(i
= 0; i
< mc_addr_count
; i
++) {
4598 DEBUGOUT(" Adding the multicast addresses:\n");
4599 DEBUGOUT7(" MC Addr #%d =%.2X %.2X %.2X %.2X %.2X %.2X\n", i
,
4600 mc_addr_list
[i
* (ETH_LENGTH_OF_ADDRESS
+ pad
)],
4601 mc_addr_list
[i
* (ETH_LENGTH_OF_ADDRESS
+ pad
) + 1],
4602 mc_addr_list
[i
* (ETH_LENGTH_OF_ADDRESS
+ pad
) + 2],
4603 mc_addr_list
[i
* (ETH_LENGTH_OF_ADDRESS
+ pad
) + 3],
4604 mc_addr_list
[i
* (ETH_LENGTH_OF_ADDRESS
+ pad
) + 4],
4605 mc_addr_list
[i
* (ETH_LENGTH_OF_ADDRESS
+ pad
) + 5]);
4607 hash_value
= e1000_hash_mc_addr(hw
,
4609 (i
* (ETH_LENGTH_OF_ADDRESS
+ pad
)));
4611 DEBUGOUT1(" Hash value = 0x%03X\n", hash_value
);
4613 /* Place this multicast address in the RAR if there is room, *
4614 * else put it in the MTA
4616 if (rar_used_count
< num_rar_entry
) {
4618 mc_addr_list
+ (i
* (ETH_LENGTH_OF_ADDRESS
+ pad
)),
4622 e1000_mta_set(hw
, hash_value
);
4625 DEBUGOUT("MC Update Complete\n");
4629 /******************************************************************************
4630 * Hashes an address to determine its location in the multicast table
4632 * hw - Struct containing variables accessed by shared code
4633 * mc_addr - the multicast address to hash
4634 *****************************************************************************/
4636 e1000_hash_mc_addr(struct e1000_hw
*hw
,
4639 uint32_t hash_value
= 0;
4641 /* The portion of the address that is used for the hash table is
4642 * determined by the mc_filter_type setting.
4644 switch (hw
->mc_filter_type
) {
4645 /* [0] [1] [2] [3] [4] [5]
4650 /* [47:36] i.e. 0x563 for above example address */
4651 hash_value
= ((mc_addr
[4] >> 4) | (((uint16_t) mc_addr
[5]) << 4));
4654 /* [46:35] i.e. 0xAC6 for above example address */
4655 hash_value
= ((mc_addr
[4] >> 3) | (((uint16_t) mc_addr
[5]) << 5));
4658 /* [45:34] i.e. 0x5D8 for above example address */
4659 hash_value
= ((mc_addr
[4] >> 2) | (((uint16_t) mc_addr
[5]) << 6));
4662 /* [43:32] i.e. 0x634 for above example address */
4663 hash_value
= ((mc_addr
[4]) | (((uint16_t) mc_addr
[5]) << 8));
4667 hash_value
&= 0xFFF;
4672 /******************************************************************************
4673 * Sets the bit in the multicast table corresponding to the hash value.
4675 * hw - Struct containing variables accessed by shared code
4676 * hash_value - Multicast address hash value
4677 *****************************************************************************/
4679 e1000_mta_set(struct e1000_hw
*hw
,
4680 uint32_t hash_value
)
4682 uint32_t hash_bit
, hash_reg
;
4686 /* The MTA is a register array of 128 32-bit registers.
4687 * It is treated like an array of 4096 bits. We want to set
4688 * bit BitArray[hash_value]. So we figure out what register
4689 * the bit is in, read it, OR in the new bit, then write
4690 * back the new value. The register is determined by the
4691 * upper 7 bits of the hash value and the bit within that
4692 * register are determined by the lower 5 bits of the value.
4694 hash_reg
= (hash_value
>> 5) & 0x7F;
4695 hash_bit
= hash_value
& 0x1F;
4697 mta
= E1000_READ_REG_ARRAY(hw
, MTA
, hash_reg
);
4699 mta
|= (1 << hash_bit
);
4701 /* If we are on an 82544 and we are trying to write an odd offset
4702 * in the MTA, save off the previous entry before writing and
4703 * restore the old value after writing.
4705 if((hw
->mac_type
== e1000_82544
) && ((hash_reg
& 0x1) == 1)) {
4706 temp
= E1000_READ_REG_ARRAY(hw
, MTA
, (hash_reg
- 1));
4707 E1000_WRITE_REG_ARRAY(hw
, MTA
, hash_reg
, mta
);
4708 E1000_WRITE_REG_ARRAY(hw
, MTA
, (hash_reg
- 1), temp
);
4710 E1000_WRITE_REG_ARRAY(hw
, MTA
, hash_reg
, mta
);
4714 /******************************************************************************
4715 * Puts an ethernet address into a receive address register.
4717 * hw - Struct containing variables accessed by shared code
4718 * addr - Address to put into receive address register
4719 * index - Receive address register to write
4720 *****************************************************************************/
4722 e1000_rar_set(struct e1000_hw
*hw
,
4726 uint32_t rar_low
, rar_high
;
4728 /* HW expects these in little endian so we reverse the byte order
4729 * from network order (big endian) to little endian
4731 rar_low
= ((uint32_t) addr
[0] |
4732 ((uint32_t) addr
[1] << 8) |
4733 ((uint32_t) addr
[2] << 16) | ((uint32_t) addr
[3] << 24));
4735 rar_high
= ((uint32_t) addr
[4] | ((uint32_t) addr
[5] << 8) | E1000_RAH_AV
);
4737 E1000_WRITE_REG_ARRAY(hw
, RA
, (index
<< 1), rar_low
);
4738 E1000_WRITE_REG_ARRAY(hw
, RA
, ((index
<< 1) + 1), rar_high
);
4741 /******************************************************************************
4742 * Writes a value to the specified offset in the VLAN filter table.
4744 * hw - Struct containing variables accessed by shared code
4745 * offset - Offset in VLAN filer table to write
4746 * value - Value to write into VLAN filter table
4747 *****************************************************************************/
4749 e1000_write_vfta(struct e1000_hw
*hw
,
4755 if((hw
->mac_type
== e1000_82544
) && ((offset
& 0x1) == 1)) {
4756 temp
= E1000_READ_REG_ARRAY(hw
, VFTA
, (offset
- 1));
4757 E1000_WRITE_REG_ARRAY(hw
, VFTA
, offset
, value
);
4758 E1000_WRITE_REG_ARRAY(hw
, VFTA
, (offset
- 1), temp
);
4760 E1000_WRITE_REG_ARRAY(hw
, VFTA
, offset
, value
);
4764 /******************************************************************************
4765 * Clears the VLAN filer table
4767 * hw - Struct containing variables accessed by shared code
4768 *****************************************************************************/
4770 e1000_clear_vfta(struct e1000_hw
*hw
)
4773 uint32_t vfta_value
= 0;
4774 uint32_t vfta_offset
= 0;
4775 uint32_t vfta_bit_in_reg
= 0;
4777 if (hw
->mac_type
== e1000_82573
) {
4778 if (hw
->mng_cookie
.vlan_id
!= 0) {
4779 /* The VFTA is a 4096b bit-field, each identifying a single VLAN
4780 * ID. The following operations determine which 32b entry
4781 * (i.e. offset) into the array we want to set the VLAN ID
4782 * (i.e. bit) of the manageability unit. */
4783 vfta_offset
= (hw
->mng_cookie
.vlan_id
>>
4784 E1000_VFTA_ENTRY_SHIFT
) &
4785 E1000_VFTA_ENTRY_MASK
;
4786 vfta_bit_in_reg
= 1 << (hw
->mng_cookie
.vlan_id
&
4787 E1000_VFTA_ENTRY_BIT_SHIFT_MASK
);
4790 for (offset
= 0; offset
< E1000_VLAN_FILTER_TBL_SIZE
; offset
++) {
4791 /* If the offset we want to clear is the same offset of the
4792 * manageability VLAN ID, then clear all bits except that of the
4793 * manageability unit */
4794 vfta_value
= (offset
== vfta_offset
) ? vfta_bit_in_reg
: 0;
4795 E1000_WRITE_REG_ARRAY(hw
, VFTA
, offset
, vfta_value
);
4800 e1000_id_led_init(struct e1000_hw
* hw
)
4803 const uint32_t ledctl_mask
= 0x000000FF;
4804 const uint32_t ledctl_on
= E1000_LEDCTL_MODE_LED_ON
;
4805 const uint32_t ledctl_off
= E1000_LEDCTL_MODE_LED_OFF
;
4806 uint16_t eeprom_data
, i
, temp
;
4807 const uint16_t led_mask
= 0x0F;
4809 DEBUGFUNC("e1000_id_led_init");
4811 if(hw
->mac_type
< e1000_82540
) {
4813 return E1000_SUCCESS
;
4816 ledctl
= E1000_READ_REG(hw
, LEDCTL
);
4817 hw
->ledctl_default
= ledctl
;
4818 hw
->ledctl_mode1
= hw
->ledctl_default
;
4819 hw
->ledctl_mode2
= hw
->ledctl_default
;
4821 if(e1000_read_eeprom(hw
, EEPROM_ID_LED_SETTINGS
, 1, &eeprom_data
) < 0) {
4822 DEBUGOUT("EEPROM Read Error\n");
4823 return -E1000_ERR_EEPROM
;
4825 if((eeprom_data
== ID_LED_RESERVED_0000
) ||
4826 (eeprom_data
== ID_LED_RESERVED_FFFF
)) eeprom_data
= ID_LED_DEFAULT
;
4827 for(i
= 0; i
< 4; i
++) {
4828 temp
= (eeprom_data
>> (i
<< 2)) & led_mask
;
4830 case ID_LED_ON1_DEF2
:
4831 case ID_LED_ON1_ON2
:
4832 case ID_LED_ON1_OFF2
:
4833 hw
->ledctl_mode1
&= ~(ledctl_mask
<< (i
<< 3));
4834 hw
->ledctl_mode1
|= ledctl_on
<< (i
<< 3);
4836 case ID_LED_OFF1_DEF2
:
4837 case ID_LED_OFF1_ON2
:
4838 case ID_LED_OFF1_OFF2
:
4839 hw
->ledctl_mode1
&= ~(ledctl_mask
<< (i
<< 3));
4840 hw
->ledctl_mode1
|= ledctl_off
<< (i
<< 3);
4847 case ID_LED_DEF1_ON2
:
4848 case ID_LED_ON1_ON2
:
4849 case ID_LED_OFF1_ON2
:
4850 hw
->ledctl_mode2
&= ~(ledctl_mask
<< (i
<< 3));
4851 hw
->ledctl_mode2
|= ledctl_on
<< (i
<< 3);
4853 case ID_LED_DEF1_OFF2
:
4854 case ID_LED_ON1_OFF2
:
4855 case ID_LED_OFF1_OFF2
:
4856 hw
->ledctl_mode2
&= ~(ledctl_mask
<< (i
<< 3));
4857 hw
->ledctl_mode2
|= ledctl_off
<< (i
<< 3);
4864 return E1000_SUCCESS
;
4867 /******************************************************************************
4868 * Prepares SW controlable LED for use and saves the current state of the LED.
4870 * hw - Struct containing variables accessed by shared code
4871 *****************************************************************************/
4873 e1000_setup_led(struct e1000_hw
*hw
)
4876 int32_t ret_val
= E1000_SUCCESS
;
4878 DEBUGFUNC("e1000_setup_led");
4880 switch(hw
->mac_type
) {
4881 case e1000_82542_rev2_0
:
4882 case e1000_82542_rev2_1
:
4885 /* No setup necessary */
4889 case e1000_82541_rev_2
:
4890 case e1000_82547_rev_2
:
4891 /* Turn off PHY Smart Power Down (if enabled) */
4892 ret_val
= e1000_read_phy_reg(hw
, IGP01E1000_GMII_FIFO
,
4893 &hw
->phy_spd_default
);
4896 ret_val
= e1000_write_phy_reg(hw
, IGP01E1000_GMII_FIFO
,
4897 (uint16_t)(hw
->phy_spd_default
&
4898 ~IGP01E1000_GMII_SPD
));
4903 if(hw
->media_type
== e1000_media_type_fiber
) {
4904 ledctl
= E1000_READ_REG(hw
, LEDCTL
);
4905 /* Save current LEDCTL settings */
4906 hw
->ledctl_default
= ledctl
;
4908 ledctl
&= ~(E1000_LEDCTL_LED0_IVRT
|
4909 E1000_LEDCTL_LED0_BLINK
|
4910 E1000_LEDCTL_LED0_MODE_MASK
);
4911 ledctl
|= (E1000_LEDCTL_MODE_LED_OFF
<<
4912 E1000_LEDCTL_LED0_MODE_SHIFT
);
4913 E1000_WRITE_REG(hw
, LEDCTL
, ledctl
);
4914 } else if(hw
->media_type
== e1000_media_type_copper
)
4915 E1000_WRITE_REG(hw
, LEDCTL
, hw
->ledctl_mode1
);
4919 return E1000_SUCCESS
;
4922 /******************************************************************************
4923 * Restores the saved state of the SW controlable LED.
4925 * hw - Struct containing variables accessed by shared code
4926 *****************************************************************************/
4928 e1000_cleanup_led(struct e1000_hw
*hw
)
4930 int32_t ret_val
= E1000_SUCCESS
;
4932 DEBUGFUNC("e1000_cleanup_led");
4934 switch(hw
->mac_type
) {
4935 case e1000_82542_rev2_0
:
4936 case e1000_82542_rev2_1
:
4939 /* No cleanup necessary */
4943 case e1000_82541_rev_2
:
4944 case e1000_82547_rev_2
:
4945 /* Turn on PHY Smart Power Down (if previously enabled) */
4946 ret_val
= e1000_write_phy_reg(hw
, IGP01E1000_GMII_FIFO
,
4947 hw
->phy_spd_default
);
4952 /* Restore LEDCTL settings */
4953 E1000_WRITE_REG(hw
, LEDCTL
, hw
->ledctl_default
);
4957 return E1000_SUCCESS
;
4960 /******************************************************************************
4961 * Turns on the software controllable LED
4963 * hw - Struct containing variables accessed by shared code
4964 *****************************************************************************/
4966 e1000_led_on(struct e1000_hw
*hw
)
4968 uint32_t ctrl
= E1000_READ_REG(hw
, CTRL
);
4970 DEBUGFUNC("e1000_led_on");
4972 switch(hw
->mac_type
) {
4973 case e1000_82542_rev2_0
:
4974 case e1000_82542_rev2_1
:
4976 /* Set SW Defineable Pin 0 to turn on the LED */
4977 ctrl
|= E1000_CTRL_SWDPIN0
;
4978 ctrl
|= E1000_CTRL_SWDPIO0
;
4981 if(hw
->media_type
== e1000_media_type_fiber
) {
4982 /* Set SW Defineable Pin 0 to turn on the LED */
4983 ctrl
|= E1000_CTRL_SWDPIN0
;
4984 ctrl
|= E1000_CTRL_SWDPIO0
;
4986 /* Clear SW Defineable Pin 0 to turn on the LED */
4987 ctrl
&= ~E1000_CTRL_SWDPIN0
;
4988 ctrl
|= E1000_CTRL_SWDPIO0
;
4992 if(hw
->media_type
== e1000_media_type_fiber
) {
4993 /* Clear SW Defineable Pin 0 to turn on the LED */
4994 ctrl
&= ~E1000_CTRL_SWDPIN0
;
4995 ctrl
|= E1000_CTRL_SWDPIO0
;
4996 } else if(hw
->media_type
== e1000_media_type_copper
) {
4997 E1000_WRITE_REG(hw
, LEDCTL
, hw
->ledctl_mode2
);
4998 return E1000_SUCCESS
;
5003 E1000_WRITE_REG(hw
, CTRL
, ctrl
);
5005 return E1000_SUCCESS
;
5008 /******************************************************************************
5009 * Turns off the software controllable LED
5011 * hw - Struct containing variables accessed by shared code
5012 *****************************************************************************/
5014 e1000_led_off(struct e1000_hw
*hw
)
5016 uint32_t ctrl
= E1000_READ_REG(hw
, CTRL
);
5018 DEBUGFUNC("e1000_led_off");
5020 switch(hw
->mac_type
) {
5021 case e1000_82542_rev2_0
:
5022 case e1000_82542_rev2_1
:
5024 /* Clear SW Defineable Pin 0 to turn off the LED */
5025 ctrl
&= ~E1000_CTRL_SWDPIN0
;
5026 ctrl
|= E1000_CTRL_SWDPIO0
;
5029 if(hw
->media_type
== e1000_media_type_fiber
) {
5030 /* Clear SW Defineable Pin 0 to turn off the LED */
5031 ctrl
&= ~E1000_CTRL_SWDPIN0
;
5032 ctrl
|= E1000_CTRL_SWDPIO0
;
5034 /* Set SW Defineable Pin 0 to turn off the LED */
5035 ctrl
|= E1000_CTRL_SWDPIN0
;
5036 ctrl
|= E1000_CTRL_SWDPIO0
;
5040 if(hw
->media_type
== e1000_media_type_fiber
) {
5041 /* Set SW Defineable Pin 0 to turn off the LED */
5042 ctrl
|= E1000_CTRL_SWDPIN0
;
5043 ctrl
|= E1000_CTRL_SWDPIO0
;
5044 } else if(hw
->media_type
== e1000_media_type_copper
) {
5045 E1000_WRITE_REG(hw
, LEDCTL
, hw
->ledctl_mode1
);
5046 return E1000_SUCCESS
;
5051 E1000_WRITE_REG(hw
, CTRL
, ctrl
);
5053 return E1000_SUCCESS
;
5056 /******************************************************************************
5057 * Clears all hardware statistics counters.
5059 * hw - Struct containing variables accessed by shared code
5060 *****************************************************************************/
5062 e1000_clear_hw_cntrs(struct e1000_hw
*hw
)
5064 volatile uint32_t temp
;
5066 temp
= E1000_READ_REG(hw
, CRCERRS
);
5067 temp
= E1000_READ_REG(hw
, SYMERRS
);
5068 temp
= E1000_READ_REG(hw
, MPC
);
5069 temp
= E1000_READ_REG(hw
, SCC
);
5070 temp
= E1000_READ_REG(hw
, ECOL
);
5071 temp
= E1000_READ_REG(hw
, MCC
);
5072 temp
= E1000_READ_REG(hw
, LATECOL
);
5073 temp
= E1000_READ_REG(hw
, COLC
);
5074 temp
= E1000_READ_REG(hw
, DC
);
5075 temp
= E1000_READ_REG(hw
, SEC
);
5076 temp
= E1000_READ_REG(hw
, RLEC
);
5077 temp
= E1000_READ_REG(hw
, XONRXC
);
5078 temp
= E1000_READ_REG(hw
, XONTXC
);
5079 temp
= E1000_READ_REG(hw
, XOFFRXC
);
5080 temp
= E1000_READ_REG(hw
, XOFFTXC
);
5081 temp
= E1000_READ_REG(hw
, FCRUC
);
5082 temp
= E1000_READ_REG(hw
, PRC64
);
5083 temp
= E1000_READ_REG(hw
, PRC127
);
5084 temp
= E1000_READ_REG(hw
, PRC255
);
5085 temp
= E1000_READ_REG(hw
, PRC511
);
5086 temp
= E1000_READ_REG(hw
, PRC1023
);
5087 temp
= E1000_READ_REG(hw
, PRC1522
);
5088 temp
= E1000_READ_REG(hw
, GPRC
);
5089 temp
= E1000_READ_REG(hw
, BPRC
);
5090 temp
= E1000_READ_REG(hw
, MPRC
);
5091 temp
= E1000_READ_REG(hw
, GPTC
);
5092 temp
= E1000_READ_REG(hw
, GORCL
);
5093 temp
= E1000_READ_REG(hw
, GORCH
);
5094 temp
= E1000_READ_REG(hw
, GOTCL
);
5095 temp
= E1000_READ_REG(hw
, GOTCH
);
5096 temp
= E1000_READ_REG(hw
, RNBC
);
5097 temp
= E1000_READ_REG(hw
, RUC
);
5098 temp
= E1000_READ_REG(hw
, RFC
);
5099 temp
= E1000_READ_REG(hw
, ROC
);
5100 temp
= E1000_READ_REG(hw
, RJC
);
5101 temp
= E1000_READ_REG(hw
, TORL
);
5102 temp
= E1000_READ_REG(hw
, TORH
);
5103 temp
= E1000_READ_REG(hw
, TOTL
);
5104 temp
= E1000_READ_REG(hw
, TOTH
);
5105 temp
= E1000_READ_REG(hw
, TPR
);
5106 temp
= E1000_READ_REG(hw
, TPT
);
5107 temp
= E1000_READ_REG(hw
, PTC64
);
5108 temp
= E1000_READ_REG(hw
, PTC127
);
5109 temp
= E1000_READ_REG(hw
, PTC255
);
5110 temp
= E1000_READ_REG(hw
, PTC511
);
5111 temp
= E1000_READ_REG(hw
, PTC1023
);
5112 temp
= E1000_READ_REG(hw
, PTC1522
);
5113 temp
= E1000_READ_REG(hw
, MPTC
);
5114 temp
= E1000_READ_REG(hw
, BPTC
);
5116 if(hw
->mac_type
< e1000_82543
) return;
5118 temp
= E1000_READ_REG(hw
, ALGNERRC
);
5119 temp
= E1000_READ_REG(hw
, RXERRC
);
5120 temp
= E1000_READ_REG(hw
, TNCRS
);
5121 temp
= E1000_READ_REG(hw
, CEXTERR
);
5122 temp
= E1000_READ_REG(hw
, TSCTC
);
5123 temp
= E1000_READ_REG(hw
, TSCTFC
);
5125 if(hw
->mac_type
<= e1000_82544
) return;
5127 temp
= E1000_READ_REG(hw
, MGTPRC
);
5128 temp
= E1000_READ_REG(hw
, MGTPDC
);
5129 temp
= E1000_READ_REG(hw
, MGTPTC
);
5131 if(hw
->mac_type
<= e1000_82547_rev_2
) return;
5133 temp
= E1000_READ_REG(hw
, IAC
);
5134 temp
= E1000_READ_REG(hw
, ICRXOC
);
5135 temp
= E1000_READ_REG(hw
, ICRXPTC
);
5136 temp
= E1000_READ_REG(hw
, ICRXATC
);
5137 temp
= E1000_READ_REG(hw
, ICTXPTC
);
5138 temp
= E1000_READ_REG(hw
, ICTXATC
);
5139 temp
= E1000_READ_REG(hw
, ICTXQEC
);
5140 temp
= E1000_READ_REG(hw
, ICTXQMTC
);
5141 temp
= E1000_READ_REG(hw
, ICRXDMTC
);
5144 /******************************************************************************
5145 * Resets Adaptive IFS to its default state.
5147 * hw - Struct containing variables accessed by shared code
5149 * Call this after e1000_init_hw. You may override the IFS defaults by setting
5150 * hw->ifs_params_forced to TRUE. However, you must initialize hw->
5151 * current_ifs_val, ifs_min_val, ifs_max_val, ifs_step_size, and ifs_ratio
5152 * before calling this function.
5153 *****************************************************************************/
5155 e1000_reset_adaptive(struct e1000_hw
*hw
)
5157 DEBUGFUNC("e1000_reset_adaptive");
5159 if(hw
->adaptive_ifs
) {
5160 if(!hw
->ifs_params_forced
) {
5161 hw
->current_ifs_val
= 0;
5162 hw
->ifs_min_val
= IFS_MIN
;
5163 hw
->ifs_max_val
= IFS_MAX
;
5164 hw
->ifs_step_size
= IFS_STEP
;
5165 hw
->ifs_ratio
= IFS_RATIO
;
5167 hw
->in_ifs_mode
= FALSE
;
5168 E1000_WRITE_REG(hw
, AIT
, 0);
5170 DEBUGOUT("Not in Adaptive IFS mode!\n");
5174 /******************************************************************************
5175 * Called during the callback/watchdog routine to update IFS value based on
5176 * the ratio of transmits to collisions.
5178 * hw - Struct containing variables accessed by shared code
5179 * tx_packets - Number of transmits since last callback
5180 * total_collisions - Number of collisions since last callback
5181 *****************************************************************************/
5183 e1000_update_adaptive(struct e1000_hw
*hw
)
5185 DEBUGFUNC("e1000_update_adaptive");
5187 if(hw
->adaptive_ifs
) {
5188 if((hw
->collision_delta
* hw
->ifs_ratio
) > hw
->tx_packet_delta
) {
5189 if(hw
->tx_packet_delta
> MIN_NUM_XMITS
) {
5190 hw
->in_ifs_mode
= TRUE
;
5191 if(hw
->current_ifs_val
< hw
->ifs_max_val
) {
5192 if(hw
->current_ifs_val
== 0)
5193 hw
->current_ifs_val
= hw
->ifs_min_val
;
5195 hw
->current_ifs_val
+= hw
->ifs_step_size
;
5196 E1000_WRITE_REG(hw
, AIT
, hw
->current_ifs_val
);
5200 if(hw
->in_ifs_mode
&& (hw
->tx_packet_delta
<= MIN_NUM_XMITS
)) {
5201 hw
->current_ifs_val
= 0;
5202 hw
->in_ifs_mode
= FALSE
;
5203 E1000_WRITE_REG(hw
, AIT
, 0);
5207 DEBUGOUT("Not in Adaptive IFS mode!\n");
5211 /******************************************************************************
5212 * Adjusts the statistic counters when a frame is accepted by TBI_ACCEPT
5214 * hw - Struct containing variables accessed by shared code
5215 * frame_len - The length of the frame in question
5216 * mac_addr - The Ethernet destination address of the frame in question
5217 *****************************************************************************/
5219 e1000_tbi_adjust_stats(struct e1000_hw
*hw
,
5220 struct e1000_hw_stats
*stats
,
5226 /* First adjust the frame length. */
5228 /* We need to adjust the statistics counters, since the hardware
5229 * counters overcount this packet as a CRC error and undercount
5230 * the packet as a good packet
5232 /* This packet should not be counted as a CRC error. */
5234 /* This packet does count as a Good Packet Received. */
5237 /* Adjust the Good Octets received counters */
5238 carry_bit
= 0x80000000 & stats
->gorcl
;
5239 stats
->gorcl
+= frame_len
;
5240 /* If the high bit of Gorcl (the low 32 bits of the Good Octets
5241 * Received Count) was one before the addition,
5242 * AND it is zero after, then we lost the carry out,
5243 * need to add one to Gorch (Good Octets Received Count High).
5244 * This could be simplified if all environments supported
5247 if(carry_bit
&& ((stats
->gorcl
& 0x80000000) == 0))
5249 /* Is this a broadcast or multicast? Check broadcast first,
5250 * since the test for a multicast frame will test positive on
5251 * a broadcast frame.
5253 if((mac_addr
[0] == (uint8_t) 0xff) && (mac_addr
[1] == (uint8_t) 0xff))
5254 /* Broadcast packet */
5256 else if(*mac_addr
& 0x01)
5257 /* Multicast packet */
5260 if(frame_len
== hw
->max_frame_size
) {
5261 /* In this case, the hardware has overcounted the number of
5268 /* Adjust the bin counters when the extra byte put the frame in the
5269 * wrong bin. Remember that the frame_len was adjusted above.
5271 if(frame_len
== 64) {
5274 } else if(frame_len
== 127) {
5277 } else if(frame_len
== 255) {
5280 } else if(frame_len
== 511) {
5283 } else if(frame_len
== 1023) {
5286 } else if(frame_len
== 1522) {
5291 /******************************************************************************
5292 * Gets the current PCI bus type, speed, and width of the hardware
5294 * hw - Struct containing variables accessed by shared code
5295 *****************************************************************************/
5297 e1000_get_bus_info(struct e1000_hw
*hw
)
5301 switch (hw
->mac_type
) {
5302 case e1000_82542_rev2_0
:
5303 case e1000_82542_rev2_1
:
5304 hw
->bus_type
= e1000_bus_type_unknown
;
5305 hw
->bus_speed
= e1000_bus_speed_unknown
;
5306 hw
->bus_width
= e1000_bus_width_unknown
;
5310 hw
->bus_type
= e1000_bus_type_pci_express
;
5311 hw
->bus_speed
= e1000_bus_speed_2500
;
5312 hw
->bus_width
= e1000_bus_width_pciex_1
;
5315 hw
->bus_type
= e1000_bus_type_pci_express
;
5316 hw
->bus_speed
= e1000_bus_speed_2500
;
5317 hw
->bus_width
= e1000_bus_width_pciex_4
;
5320 status
= E1000_READ_REG(hw
, STATUS
);
5321 hw
->bus_type
= (status
& E1000_STATUS_PCIX_MODE
) ?
5322 e1000_bus_type_pcix
: e1000_bus_type_pci
;
5324 if(hw
->device_id
== E1000_DEV_ID_82546EB_QUAD_COPPER
) {
5325 hw
->bus_speed
= (hw
->bus_type
== e1000_bus_type_pci
) ?
5326 e1000_bus_speed_66
: e1000_bus_speed_120
;
5327 } else if(hw
->bus_type
== e1000_bus_type_pci
) {
5328 hw
->bus_speed
= (status
& E1000_STATUS_PCI66
) ?
5329 e1000_bus_speed_66
: e1000_bus_speed_33
;
5331 switch (status
& E1000_STATUS_PCIX_SPEED
) {
5332 case E1000_STATUS_PCIX_SPEED_66
:
5333 hw
->bus_speed
= e1000_bus_speed_66
;
5335 case E1000_STATUS_PCIX_SPEED_100
:
5336 hw
->bus_speed
= e1000_bus_speed_100
;
5338 case E1000_STATUS_PCIX_SPEED_133
:
5339 hw
->bus_speed
= e1000_bus_speed_133
;
5342 hw
->bus_speed
= e1000_bus_speed_reserved
;
5346 hw
->bus_width
= (status
& E1000_STATUS_BUS64
) ?
5347 e1000_bus_width_64
: e1000_bus_width_32
;
5353 /******************************************************************************
5354 * Reads a value from one of the devices registers using port I/O (as opposed
5355 * memory mapped I/O). Only 82544 and newer devices support port I/O.
5357 * hw - Struct containing variables accessed by shared code
5358 * offset - offset to read from
5359 *****************************************************************************/
5361 e1000_read_reg_io(struct e1000_hw
*hw
,
5364 unsigned long io_addr
= hw
->io_base
;
5365 unsigned long io_data
= hw
->io_base
+ 4;
5367 e1000_io_write(hw
, io_addr
, offset
);
5368 return e1000_io_read(hw
, io_data
);
5372 /******************************************************************************
5373 * Writes a value to one of the devices registers using port I/O (as opposed to
5374 * memory mapped I/O). Only 82544 and newer devices support port I/O.
5376 * hw - Struct containing variables accessed by shared code
5377 * offset - offset to write to
5378 * value - value to write
5379 *****************************************************************************/
5381 e1000_write_reg_io(struct e1000_hw
*hw
,
5385 unsigned long io_addr
= hw
->io_base
;
5386 unsigned long io_data
= hw
->io_base
+ 4;
5388 e1000_io_write(hw
, io_addr
, offset
);
5389 e1000_io_write(hw
, io_data
, value
);
5393 /******************************************************************************
5394 * Estimates the cable length.
5396 * hw - Struct containing variables accessed by shared code
5397 * min_length - The estimated minimum length
5398 * max_length - The estimated maximum length
5400 * returns: - E1000_ERR_XXX
5403 * This function always returns a ranged length (minimum & maximum).
5404 * So for M88 phy's, this function interprets the one value returned from the
5405 * register to the minimum and maximum range.
5406 * For IGP phy's, the function calculates the range by the AGC registers.
5407 *****************************************************************************/
5409 e1000_get_cable_length(struct e1000_hw
*hw
,
5410 uint16_t *min_length
,
5411 uint16_t *max_length
)
5414 uint16_t agc_value
= 0;
5415 uint16_t cur_agc
, min_agc
= IGP01E1000_AGC_LENGTH_TABLE_SIZE
;
5416 uint16_t max_agc
= 0;
5417 uint16_t i
, phy_data
;
5418 uint16_t cable_length
;
5420 DEBUGFUNC("e1000_get_cable_length");
5422 *min_length
= *max_length
= 0;
5424 /* Use old method for Phy older than IGP */
5425 if(hw
->phy_type
== e1000_phy_m88
) {
5427 ret_val
= e1000_read_phy_reg(hw
, M88E1000_PHY_SPEC_STATUS
,
5431 cable_length
= (phy_data
& M88E1000_PSSR_CABLE_LENGTH
) >>
5432 M88E1000_PSSR_CABLE_LENGTH_SHIFT
;
5434 /* Convert the enum value to ranged values */
5435 switch (cable_length
) {
5436 case e1000_cable_length_50
:
5438 *max_length
= e1000_igp_cable_length_50
;
5440 case e1000_cable_length_50_80
:
5441 *min_length
= e1000_igp_cable_length_50
;
5442 *max_length
= e1000_igp_cable_length_80
;
5444 case e1000_cable_length_80_110
:
5445 *min_length
= e1000_igp_cable_length_80
;
5446 *max_length
= e1000_igp_cable_length_110
;
5448 case e1000_cable_length_110_140
:
5449 *min_length
= e1000_igp_cable_length_110
;
5450 *max_length
= e1000_igp_cable_length_140
;
5452 case e1000_cable_length_140
:
5453 *min_length
= e1000_igp_cable_length_140
;
5454 *max_length
= e1000_igp_cable_length_170
;
5457 return -E1000_ERR_PHY
;
5460 } else if(hw
->phy_type
== e1000_phy_igp
) { /* For IGP PHY */
5461 uint16_t agc_reg_array
[IGP01E1000_PHY_CHANNEL_NUM
] =
5462 {IGP01E1000_PHY_AGC_A
,
5463 IGP01E1000_PHY_AGC_B
,
5464 IGP01E1000_PHY_AGC_C
,
5465 IGP01E1000_PHY_AGC_D
};
5466 /* Read the AGC registers for all channels */
5467 for(i
= 0; i
< IGP01E1000_PHY_CHANNEL_NUM
; i
++) {
5469 ret_val
= e1000_read_phy_reg(hw
, agc_reg_array
[i
], &phy_data
);
5473 cur_agc
= phy_data
>> IGP01E1000_AGC_LENGTH_SHIFT
;
5475 /* Array bound check. */
5476 if((cur_agc
>= IGP01E1000_AGC_LENGTH_TABLE_SIZE
- 1) ||
5478 return -E1000_ERR_PHY
;
5480 agc_value
+= cur_agc
;
5482 /* Update minimal AGC value. */
5483 if(min_agc
> cur_agc
)
5487 /* Remove the minimal AGC result for length < 50m */
5488 if(agc_value
< IGP01E1000_PHY_CHANNEL_NUM
* e1000_igp_cable_length_50
) {
5489 agc_value
-= min_agc
;
5491 /* Get the average length of the remaining 3 channels */
5492 agc_value
/= (IGP01E1000_PHY_CHANNEL_NUM
- 1);
5494 /* Get the average length of all the 4 channels. */
5495 agc_value
/= IGP01E1000_PHY_CHANNEL_NUM
;
5498 /* Set the range of the calculated length. */
5499 *min_length
= ((e1000_igp_cable_length_table
[agc_value
] -
5500 IGP01E1000_AGC_RANGE
) > 0) ?
5501 (e1000_igp_cable_length_table
[agc_value
] -
5502 IGP01E1000_AGC_RANGE
) : 0;
5503 *max_length
= e1000_igp_cable_length_table
[agc_value
] +
5504 IGP01E1000_AGC_RANGE
;
5505 } else if (hw
->phy_type
== e1000_phy_igp_2
) {
5506 uint16_t agc_reg_array
[IGP02E1000_PHY_CHANNEL_NUM
] =
5507 {IGP02E1000_PHY_AGC_A
,
5508 IGP02E1000_PHY_AGC_B
,
5509 IGP02E1000_PHY_AGC_C
,
5510 IGP02E1000_PHY_AGC_D
};
5511 /* Read the AGC registers for all channels */
5512 for (i
= 0; i
< IGP02E1000_PHY_CHANNEL_NUM
; i
++) {
5513 ret_val
= e1000_read_phy_reg(hw
, agc_reg_array
[i
], &phy_data
);
5517 /* Getting bits 15:9, which represent the combination of course and
5518 * fine gain values. The result is a number that can be put into
5519 * the lookup table to obtain the approximate cable length. */
5520 cur_agc
= (phy_data
>> IGP02E1000_AGC_LENGTH_SHIFT
) &
5521 IGP02E1000_AGC_LENGTH_MASK
;
5523 /* Remove min & max AGC values from calculation. */
5524 if (e1000_igp_2_cable_length_table
[min_agc
] > e1000_igp_2_cable_length_table
[cur_agc
])
5526 if (e1000_igp_2_cable_length_table
[max_agc
] < e1000_igp_2_cable_length_table
[cur_agc
])
5529 agc_value
+= e1000_igp_2_cable_length_table
[cur_agc
];
5532 agc_value
-= (e1000_igp_2_cable_length_table
[min_agc
] + e1000_igp_2_cable_length_table
[max_agc
]);
5533 agc_value
/= (IGP02E1000_PHY_CHANNEL_NUM
- 2);
5535 /* Calculate cable length with the error range of +/- 10 meters. */
5536 *min_length
= ((agc_value
- IGP02E1000_AGC_RANGE
) > 0) ?
5537 (agc_value
- IGP02E1000_AGC_RANGE
) : 0;
5538 *max_length
= agc_value
+ IGP02E1000_AGC_RANGE
;
5541 return E1000_SUCCESS
;
5544 /******************************************************************************
5545 * Check the cable polarity
5547 * hw - Struct containing variables accessed by shared code
5548 * polarity - output parameter : 0 - Polarity is not reversed
5549 * 1 - Polarity is reversed.
5551 * returns: - E1000_ERR_XXX
5554 * For phy's older then IGP, this function simply reads the polarity bit in the
5555 * Phy Status register. For IGP phy's, this bit is valid only if link speed is
5556 * 10 Mbps. If the link speed is 100 Mbps there is no polarity so this bit will
5557 * return 0. If the link speed is 1000 Mbps the polarity status is in the
5558 * IGP01E1000_PHY_PCS_INIT_REG.
5559 *****************************************************************************/
5561 e1000_check_polarity(struct e1000_hw
*hw
,
5567 DEBUGFUNC("e1000_check_polarity");
5569 if(hw
->phy_type
== e1000_phy_m88
) {
5570 /* return the Polarity bit in the Status register. */
5571 ret_val
= e1000_read_phy_reg(hw
, M88E1000_PHY_SPEC_STATUS
,
5575 *polarity
= (phy_data
& M88E1000_PSSR_REV_POLARITY
) >>
5576 M88E1000_PSSR_REV_POLARITY_SHIFT
;
5577 } else if(hw
->phy_type
== e1000_phy_igp
||
5578 hw
->phy_type
== e1000_phy_igp_2
) {
5579 /* Read the Status register to check the speed */
5580 ret_val
= e1000_read_phy_reg(hw
, IGP01E1000_PHY_PORT_STATUS
,
5585 /* If speed is 1000 Mbps, must read the IGP01E1000_PHY_PCS_INIT_REG to
5586 * find the polarity status */
5587 if((phy_data
& IGP01E1000_PSSR_SPEED_MASK
) ==
5588 IGP01E1000_PSSR_SPEED_1000MBPS
) {
5590 /* Read the GIG initialization PCS register (0x00B4) */
5591 ret_val
= e1000_read_phy_reg(hw
, IGP01E1000_PHY_PCS_INIT_REG
,
5596 /* Check the polarity bits */
5597 *polarity
= (phy_data
& IGP01E1000_PHY_POLARITY_MASK
) ? 1 : 0;
5599 /* For 10 Mbps, read the polarity bit in the status register. (for
5600 * 100 Mbps this bit is always 0) */
5601 *polarity
= phy_data
& IGP01E1000_PSSR_POLARITY_REVERSED
;
5604 return E1000_SUCCESS
;
5607 /******************************************************************************
5608 * Check if Downshift occured
5610 * hw - Struct containing variables accessed by shared code
5611 * downshift - output parameter : 0 - No Downshift ocured.
5612 * 1 - Downshift ocured.
5614 * returns: - E1000_ERR_XXX
5617 * For phy's older then IGP, this function reads the Downshift bit in the Phy
5618 * Specific Status register. For IGP phy's, it reads the Downgrade bit in the
5619 * Link Health register. In IGP this bit is latched high, so the driver must
5620 * read it immediately after link is established.
5621 *****************************************************************************/
5623 e1000_check_downshift(struct e1000_hw
*hw
)
5628 DEBUGFUNC("e1000_check_downshift");
5630 if(hw
->phy_type
== e1000_phy_igp
||
5631 hw
->phy_type
== e1000_phy_igp_2
) {
5632 ret_val
= e1000_read_phy_reg(hw
, IGP01E1000_PHY_LINK_HEALTH
,
5637 hw
->speed_downgraded
= (phy_data
& IGP01E1000_PLHR_SS_DOWNGRADE
) ? 1 : 0;
5638 } else if(hw
->phy_type
== e1000_phy_m88
) {
5639 ret_val
= e1000_read_phy_reg(hw
, M88E1000_PHY_SPEC_STATUS
,
5644 hw
->speed_downgraded
= (phy_data
& M88E1000_PSSR_DOWNSHIFT
) >>
5645 M88E1000_PSSR_DOWNSHIFT_SHIFT
;
5648 return E1000_SUCCESS
;
5651 /*****************************************************************************
5653 * 82541_rev_2 & 82547_rev_2 have the capability to configure the DSP when a
5654 * gigabit link is achieved to improve link quality.
5656 * hw: Struct containing variables accessed by shared code
5658 * returns: - E1000_ERR_PHY if fail to read/write the PHY
5659 * E1000_SUCCESS at any other case.
5661 ****************************************************************************/
5664 e1000_config_dsp_after_link_change(struct e1000_hw
*hw
,
5668 uint16_t phy_data
, phy_saved_data
, speed
, duplex
, i
;
5669 uint16_t dsp_reg_array
[IGP01E1000_PHY_CHANNEL_NUM
] =
5670 {IGP01E1000_PHY_AGC_PARAM_A
,
5671 IGP01E1000_PHY_AGC_PARAM_B
,
5672 IGP01E1000_PHY_AGC_PARAM_C
,
5673 IGP01E1000_PHY_AGC_PARAM_D
};
5674 uint16_t min_length
, max_length
;
5676 DEBUGFUNC("e1000_config_dsp_after_link_change");
5678 if(hw
->phy_type
!= e1000_phy_igp
)
5679 return E1000_SUCCESS
;
5682 ret_val
= e1000_get_speed_and_duplex(hw
, &speed
, &duplex
);
5684 DEBUGOUT("Error getting link speed and duplex\n");
5688 if(speed
== SPEED_1000
) {
5690 e1000_get_cable_length(hw
, &min_length
, &max_length
);
5692 if((hw
->dsp_config_state
== e1000_dsp_config_enabled
) &&
5693 min_length
>= e1000_igp_cable_length_50
) {
5695 for(i
= 0; i
< IGP01E1000_PHY_CHANNEL_NUM
; i
++) {
5696 ret_val
= e1000_read_phy_reg(hw
, dsp_reg_array
[i
],
5701 phy_data
&= ~IGP01E1000_PHY_EDAC_MU_INDEX
;
5703 ret_val
= e1000_write_phy_reg(hw
, dsp_reg_array
[i
],
5708 hw
->dsp_config_state
= e1000_dsp_config_activated
;
5711 if((hw
->ffe_config_state
== e1000_ffe_config_enabled
) &&
5712 (min_length
< e1000_igp_cable_length_50
)) {
5714 uint16_t ffe_idle_err_timeout
= FFE_IDLE_ERR_COUNT_TIMEOUT_20
;
5715 uint32_t idle_errs
= 0;
5717 /* clear previous idle error counts */
5718 ret_val
= e1000_read_phy_reg(hw
, PHY_1000T_STATUS
,
5723 for(i
= 0; i
< ffe_idle_err_timeout
; i
++) {
5725 ret_val
= e1000_read_phy_reg(hw
, PHY_1000T_STATUS
,
5730 idle_errs
+= (phy_data
& SR_1000T_IDLE_ERROR_CNT
);
5731 if(idle_errs
> SR_1000T_PHY_EXCESSIVE_IDLE_ERR_COUNT
) {
5732 hw
->ffe_config_state
= e1000_ffe_config_active
;
5734 ret_val
= e1000_write_phy_reg(hw
,
5735 IGP01E1000_PHY_DSP_FFE
,
5736 IGP01E1000_PHY_DSP_FFE_CM_CP
);
5743 ffe_idle_err_timeout
= FFE_IDLE_ERR_COUNT_TIMEOUT_100
;
5748 if(hw
->dsp_config_state
== e1000_dsp_config_activated
) {
5749 /* Save off the current value of register 0x2F5B to be restored at
5750 * the end of the routines. */
5751 ret_val
= e1000_read_phy_reg(hw
, 0x2F5B, &phy_saved_data
);
5756 /* Disable the PHY transmitter */
5757 ret_val
= e1000_write_phy_reg(hw
, 0x2F5B, 0x0003);
5764 ret_val
= e1000_write_phy_reg(hw
, 0x0000,
5765 IGP01E1000_IEEE_FORCE_GIGA
);
5768 for(i
= 0; i
< IGP01E1000_PHY_CHANNEL_NUM
; i
++) {
5769 ret_val
= e1000_read_phy_reg(hw
, dsp_reg_array
[i
], &phy_data
);
5773 phy_data
&= ~IGP01E1000_PHY_EDAC_MU_INDEX
;
5774 phy_data
|= IGP01E1000_PHY_EDAC_SIGN_EXT_9_BITS
;
5776 ret_val
= e1000_write_phy_reg(hw
,dsp_reg_array
[i
], phy_data
);
5781 ret_val
= e1000_write_phy_reg(hw
, 0x0000,
5782 IGP01E1000_IEEE_RESTART_AUTONEG
);
5788 /* Now enable the transmitter */
5789 ret_val
= e1000_write_phy_reg(hw
, 0x2F5B, phy_saved_data
);
5794 hw
->dsp_config_state
= e1000_dsp_config_enabled
;
5797 if(hw
->ffe_config_state
== e1000_ffe_config_active
) {
5798 /* Save off the current value of register 0x2F5B to be restored at
5799 * the end of the routines. */
5800 ret_val
= e1000_read_phy_reg(hw
, 0x2F5B, &phy_saved_data
);
5805 /* Disable the PHY transmitter */
5806 ret_val
= e1000_write_phy_reg(hw
, 0x2F5B, 0x0003);
5813 ret_val
= e1000_write_phy_reg(hw
, 0x0000,
5814 IGP01E1000_IEEE_FORCE_GIGA
);
5817 ret_val
= e1000_write_phy_reg(hw
, IGP01E1000_PHY_DSP_FFE
,
5818 IGP01E1000_PHY_DSP_FFE_DEFAULT
);
5822 ret_val
= e1000_write_phy_reg(hw
, 0x0000,
5823 IGP01E1000_IEEE_RESTART_AUTONEG
);
5829 /* Now enable the transmitter */
5830 ret_val
= e1000_write_phy_reg(hw
, 0x2F5B, phy_saved_data
);
5835 hw
->ffe_config_state
= e1000_ffe_config_enabled
;
5838 return E1000_SUCCESS
;
5841 /*****************************************************************************
5842 * Set PHY to class A mode
5843 * Assumes the following operations will follow to enable the new class mode.
5844 * 1. Do a PHY soft reset
5845 * 2. Restart auto-negotiation or force link.
5847 * hw - Struct containing variables accessed by shared code
5848 ****************************************************************************/
5850 e1000_set_phy_mode(struct e1000_hw
*hw
)
5853 uint16_t eeprom_data
;
5855 DEBUGFUNC("e1000_set_phy_mode");
5857 if((hw
->mac_type
== e1000_82545_rev_3
) &&
5858 (hw
->media_type
== e1000_media_type_copper
)) {
5859 ret_val
= e1000_read_eeprom(hw
, EEPROM_PHY_CLASS_WORD
, 1, &eeprom_data
);
5864 if((eeprom_data
!= EEPROM_RESERVED_WORD
) &&
5865 (eeprom_data
& EEPROM_PHY_CLASS_A
)) {
5866 ret_val
= e1000_write_phy_reg(hw
, M88E1000_PHY_PAGE_SELECT
, 0x000B);
5869 ret_val
= e1000_write_phy_reg(hw
, M88E1000_PHY_GEN_CONTROL
, 0x8104);
5873 hw
->phy_reset_disable
= FALSE
;
5877 return E1000_SUCCESS
;
5880 /*****************************************************************************
5882 * This function sets the lplu state according to the active flag. When
5883 * activating lplu this function also disables smart speed and vise versa.
5884 * lplu will not be activated unless the device autonegotiation advertisment
5885 * meets standards of either 10 or 10/100 or 10/100/1000 at all duplexes.
5886 * hw: Struct containing variables accessed by shared code
5887 * active - true to enable lplu false to disable lplu.
5889 * returns: - E1000_ERR_PHY if fail to read/write the PHY
5890 * E1000_SUCCESS at any other case.
5892 ****************************************************************************/
5895 e1000_set_d3_lplu_state(struct e1000_hw
*hw
,
5900 DEBUGFUNC("e1000_set_d3_lplu_state");
5902 if(hw
->phy_type
!= e1000_phy_igp
&& hw
->phy_type
!= e1000_phy_igp_2
)
5903 return E1000_SUCCESS
;
5905 /* During driver activity LPLU should not be used or it will attain link
5906 * from the lowest speeds starting from 10Mbps. The capability is used for
5907 * Dx transitions and states */
5908 if(hw
->mac_type
== e1000_82541_rev_2
|| hw
->mac_type
== e1000_82547_rev_2
) {
5909 ret_val
= e1000_read_phy_reg(hw
, IGP01E1000_GMII_FIFO
, &phy_data
);
5913 ret_val
= e1000_read_phy_reg(hw
, IGP02E1000_PHY_POWER_MGMT
, &phy_data
);
5919 if(hw
->mac_type
== e1000_82541_rev_2
||
5920 hw
->mac_type
== e1000_82547_rev_2
) {
5921 phy_data
&= ~IGP01E1000_GMII_FLEX_SPD
;
5922 ret_val
= e1000_write_phy_reg(hw
, IGP01E1000_GMII_FIFO
, phy_data
);
5926 phy_data
&= ~IGP02E1000_PM_D3_LPLU
;
5927 ret_val
= e1000_write_phy_reg(hw
, IGP02E1000_PHY_POWER_MGMT
,
5933 /* LPLU and SmartSpeed are mutually exclusive. LPLU is used during
5934 * Dx states where the power conservation is most important. During
5935 * driver activity we should enable SmartSpeed, so performance is
5937 if (hw
->smart_speed
== e1000_smart_speed_on
) {
5938 ret_val
= e1000_read_phy_reg(hw
, IGP01E1000_PHY_PORT_CONFIG
,
5943 phy_data
|= IGP01E1000_PSCFR_SMART_SPEED
;
5944 ret_val
= e1000_write_phy_reg(hw
, IGP01E1000_PHY_PORT_CONFIG
,
5948 } else if (hw
->smart_speed
== e1000_smart_speed_off
) {
5949 ret_val
= e1000_read_phy_reg(hw
, IGP01E1000_PHY_PORT_CONFIG
,
5954 phy_data
&= ~IGP01E1000_PSCFR_SMART_SPEED
;
5955 ret_val
= e1000_write_phy_reg(hw
, IGP01E1000_PHY_PORT_CONFIG
,
5961 } else if((hw
->autoneg_advertised
== AUTONEG_ADVERTISE_SPEED_DEFAULT
) ||
5962 (hw
->autoneg_advertised
== AUTONEG_ADVERTISE_10_ALL
) ||
5963 (hw
->autoneg_advertised
== AUTONEG_ADVERTISE_10_100_ALL
)) {
5965 if(hw
->mac_type
== e1000_82541_rev_2
||
5966 hw
->mac_type
== e1000_82547_rev_2
) {
5967 phy_data
|= IGP01E1000_GMII_FLEX_SPD
;
5968 ret_val
= e1000_write_phy_reg(hw
, IGP01E1000_GMII_FIFO
, phy_data
);
5972 phy_data
|= IGP02E1000_PM_D3_LPLU
;
5973 ret_val
= e1000_write_phy_reg(hw
, IGP02E1000_PHY_POWER_MGMT
,
5979 /* When LPLU is enabled we should disable SmartSpeed */
5980 ret_val
= e1000_read_phy_reg(hw
, IGP01E1000_PHY_PORT_CONFIG
, &phy_data
);
5984 phy_data
&= ~IGP01E1000_PSCFR_SMART_SPEED
;
5985 ret_val
= e1000_write_phy_reg(hw
, IGP01E1000_PHY_PORT_CONFIG
, phy_data
);
5990 return E1000_SUCCESS
;
5993 /*****************************************************************************
5995 * This function sets the lplu d0 state according to the active flag. When
5996 * activating lplu this function also disables smart speed and vise versa.
5997 * lplu will not be activated unless the device autonegotiation advertisment
5998 * meets standards of either 10 or 10/100 or 10/100/1000 at all duplexes.
5999 * hw: Struct containing variables accessed by shared code
6000 * active - true to enable lplu false to disable lplu.
6002 * returns: - E1000_ERR_PHY if fail to read/write the PHY
6003 * E1000_SUCCESS at any other case.
6005 ****************************************************************************/
6008 e1000_set_d0_lplu_state(struct e1000_hw
*hw
,
6013 DEBUGFUNC("e1000_set_d0_lplu_state");
6015 if(hw
->mac_type
<= e1000_82547_rev_2
)
6016 return E1000_SUCCESS
;
6018 ret_val
= e1000_read_phy_reg(hw
, IGP02E1000_PHY_POWER_MGMT
, &phy_data
);
6023 phy_data
&= ~IGP02E1000_PM_D0_LPLU
;
6024 ret_val
= e1000_write_phy_reg(hw
, IGP02E1000_PHY_POWER_MGMT
, phy_data
);
6028 /* LPLU and SmartSpeed are mutually exclusive. LPLU is used during
6029 * Dx states where the power conservation is most important. During
6030 * driver activity we should enable SmartSpeed, so performance is
6032 if (hw
->smart_speed
== e1000_smart_speed_on
) {
6033 ret_val
= e1000_read_phy_reg(hw
, IGP01E1000_PHY_PORT_CONFIG
,
6038 phy_data
|= IGP01E1000_PSCFR_SMART_SPEED
;
6039 ret_val
= e1000_write_phy_reg(hw
, IGP01E1000_PHY_PORT_CONFIG
,
6043 } else if (hw
->smart_speed
== e1000_smart_speed_off
) {
6044 ret_val
= e1000_read_phy_reg(hw
, IGP01E1000_PHY_PORT_CONFIG
,
6049 phy_data
&= ~IGP01E1000_PSCFR_SMART_SPEED
;
6050 ret_val
= e1000_write_phy_reg(hw
, IGP01E1000_PHY_PORT_CONFIG
,
6059 phy_data
|= IGP02E1000_PM_D0_LPLU
;
6060 ret_val
= e1000_write_phy_reg(hw
, IGP02E1000_PHY_POWER_MGMT
, phy_data
);
6064 /* When LPLU is enabled we should disable SmartSpeed */
6065 ret_val
= e1000_read_phy_reg(hw
, IGP01E1000_PHY_PORT_CONFIG
, &phy_data
);
6069 phy_data
&= ~IGP01E1000_PSCFR_SMART_SPEED
;
6070 ret_val
= e1000_write_phy_reg(hw
, IGP01E1000_PHY_PORT_CONFIG
, phy_data
);
6075 return E1000_SUCCESS
;
6078 /******************************************************************************
6079 * Change VCO speed register to improve Bit Error Rate performance of SERDES.
6081 * hw - Struct containing variables accessed by shared code
6082 *****************************************************************************/
6084 e1000_set_vco_speed(struct e1000_hw
*hw
)
6087 uint16_t default_page
= 0;
6090 DEBUGFUNC("e1000_set_vco_speed");
6092 switch(hw
->mac_type
) {
6093 case e1000_82545_rev_3
:
6094 case e1000_82546_rev_3
:
6097 return E1000_SUCCESS
;
6100 /* Set PHY register 30, page 5, bit 8 to 0 */
6102 ret_val
= e1000_read_phy_reg(hw
, M88E1000_PHY_PAGE_SELECT
, &default_page
);
6106 ret_val
= e1000_write_phy_reg(hw
, M88E1000_PHY_PAGE_SELECT
, 0x0005);
6110 ret_val
= e1000_read_phy_reg(hw
, M88E1000_PHY_GEN_CONTROL
, &phy_data
);
6114 phy_data
&= ~M88E1000_PHY_VCO_REG_BIT8
;
6115 ret_val
= e1000_write_phy_reg(hw
, M88E1000_PHY_GEN_CONTROL
, phy_data
);
6119 /* Set PHY register 30, page 4, bit 11 to 1 */
6121 ret_val
= e1000_write_phy_reg(hw
, M88E1000_PHY_PAGE_SELECT
, 0x0004);
6125 ret_val
= e1000_read_phy_reg(hw
, M88E1000_PHY_GEN_CONTROL
, &phy_data
);
6129 phy_data
|= M88E1000_PHY_VCO_REG_BIT11
;
6130 ret_val
= e1000_write_phy_reg(hw
, M88E1000_PHY_GEN_CONTROL
, phy_data
);
6134 ret_val
= e1000_write_phy_reg(hw
, M88E1000_PHY_PAGE_SELECT
, default_page
);
6138 return E1000_SUCCESS
;
6142 /*****************************************************************************
6143 * This function reads the cookie from ARC ram.
6145 * returns: - E1000_SUCCESS .
6146 ****************************************************************************/
6148 e1000_host_if_read_cookie(struct e1000_hw
* hw
, uint8_t *buffer
)
6151 uint32_t offset
= E1000_MNG_DHCP_COOKIE_OFFSET
;
6152 uint8_t length
= E1000_MNG_DHCP_COOKIE_LENGTH
;
6154 length
= (length
>> 2);
6155 offset
= (offset
>> 2);
6157 for (i
= 0; i
< length
; i
++) {
6158 *((uint32_t *) buffer
+ i
) =
6159 E1000_READ_REG_ARRAY_DWORD(hw
, HOST_IF
, offset
+ i
);
6161 return E1000_SUCCESS
;
6165 /*****************************************************************************
6166 * This function checks whether the HOST IF is enabled for command operaton
6167 * and also checks whether the previous command is completed.
6168 * It busy waits in case of previous command is not completed.
6170 * returns: - E1000_ERR_HOST_INTERFACE_COMMAND in case if is not ready or
6172 * - E1000_SUCCESS for success.
6173 ****************************************************************************/
6175 e1000_mng_enable_host_if(struct e1000_hw
* hw
)
6180 /* Check that the host interface is enabled. */
6181 hicr
= E1000_READ_REG(hw
, HICR
);
6182 if ((hicr
& E1000_HICR_EN
) == 0) {
6183 DEBUGOUT("E1000_HOST_EN bit disabled.\n");
6184 return -E1000_ERR_HOST_INTERFACE_COMMAND
;
6186 /* check the previous command is completed */
6187 for (i
= 0; i
< E1000_MNG_DHCP_COMMAND_TIMEOUT
; i
++) {
6188 hicr
= E1000_READ_REG(hw
, HICR
);
6189 if (!(hicr
& E1000_HICR_C
))
6194 if (i
== E1000_MNG_DHCP_COMMAND_TIMEOUT
) {
6195 DEBUGOUT("Previous command timeout failed .\n");
6196 return -E1000_ERR_HOST_INTERFACE_COMMAND
;
6198 return E1000_SUCCESS
;
6201 /*****************************************************************************
6202 * This function writes the buffer content at the offset given on the host if.
6203 * It also does alignment considerations to do the writes in most efficient way.
6204 * Also fills up the sum of the buffer in *buffer parameter.
6206 * returns - E1000_SUCCESS for success.
6207 ****************************************************************************/
6209 e1000_mng_host_if_write(struct e1000_hw
* hw
, uint8_t *buffer
,
6210 uint16_t length
, uint16_t offset
, uint8_t *sum
)
6213 uint8_t *bufptr
= buffer
;
6215 uint16_t remaining
, i
, j
, prev_bytes
;
6217 /* sum = only sum of the data and it is not checksum */
6219 if (length
== 0 || offset
+ length
> E1000_HI_MAX_MNG_DATA_LENGTH
) {
6220 return -E1000_ERR_PARAM
;
6223 tmp
= (uint8_t *)&data
;
6224 prev_bytes
= offset
& 0x3;
6229 data
= E1000_READ_REG_ARRAY_DWORD(hw
, HOST_IF
, offset
);
6230 for (j
= prev_bytes
; j
< sizeof(uint32_t); j
++) {
6231 *(tmp
+ j
) = *bufptr
++;
6234 E1000_WRITE_REG_ARRAY_DWORD(hw
, HOST_IF
, offset
, data
);
6235 length
-= j
- prev_bytes
;
6239 remaining
= length
& 0x3;
6240 length
-= remaining
;
6242 /* Calculate length in DWORDs */
6245 /* The device driver writes the relevant command block into the
6247 for (i
= 0; i
< length
; i
++) {
6248 for (j
= 0; j
< sizeof(uint32_t); j
++) {
6249 *(tmp
+ j
) = *bufptr
++;
6253 E1000_WRITE_REG_ARRAY_DWORD(hw
, HOST_IF
, offset
+ i
, data
);
6256 for (j
= 0; j
< sizeof(uint32_t); j
++) {
6258 *(tmp
+ j
) = *bufptr
++;
6264 E1000_WRITE_REG_ARRAY_DWORD(hw
, HOST_IF
, offset
+ i
, data
);
6267 return E1000_SUCCESS
;
6271 /*****************************************************************************
6272 * This function writes the command header after does the checksum calculation.
6274 * returns - E1000_SUCCESS for success.
6275 ****************************************************************************/
6277 e1000_mng_write_cmd_header(struct e1000_hw
* hw
,
6278 struct e1000_host_mng_command_header
* hdr
)
6284 /* Write the whole command header structure which includes sum of
6287 uint16_t length
= sizeof(struct e1000_host_mng_command_header
);
6289 sum
= hdr
->checksum
;
6292 buffer
= (uint8_t *) hdr
;
6297 hdr
->checksum
= 0 - sum
;
6300 /* The device driver writes the relevant command block into the ram area. */
6301 for (i
= 0; i
< length
; i
++)
6302 E1000_WRITE_REG_ARRAY_DWORD(hw
, HOST_IF
, i
, *((uint32_t *) hdr
+ i
));
6304 return E1000_SUCCESS
;
6308 /*****************************************************************************
6309 * This function indicates to ARC that a new command is pending which completes
6310 * one write operation by the driver.
6312 * returns - E1000_SUCCESS for success.
6313 ****************************************************************************/
6315 e1000_mng_write_commit(
6316 struct e1000_hw
* hw
)
6320 hicr
= E1000_READ_REG(hw
, HICR
);
6321 /* Setting this bit tells the ARC that a new command is pending. */
6322 E1000_WRITE_REG(hw
, HICR
, hicr
| E1000_HICR_C
);
6324 return E1000_SUCCESS
;
6328 /*****************************************************************************
6329 * This function checks the mode of the firmware.
6331 * returns - TRUE when the mode is IAMT or FALSE.
6332 ****************************************************************************/
6334 e1000_check_mng_mode(
6335 struct e1000_hw
*hw
)
6339 fwsm
= E1000_READ_REG(hw
, FWSM
);
6341 if((fwsm
& E1000_FWSM_MODE_MASK
) ==
6342 (E1000_MNG_IAMT_MODE
<< E1000_FWSM_MODE_SHIFT
))
6349 /*****************************************************************************
6350 * This function writes the dhcp info .
6351 ****************************************************************************/
6353 e1000_mng_write_dhcp_info(struct e1000_hw
* hw
, uint8_t *buffer
,
6357 struct e1000_host_mng_command_header hdr
;
6359 hdr
.command_id
= E1000_MNG_DHCP_TX_PAYLOAD_CMD
;
6360 hdr
.command_length
= length
;
6365 ret_val
= e1000_mng_enable_host_if(hw
);
6366 if (ret_val
== E1000_SUCCESS
) {
6367 ret_val
= e1000_mng_host_if_write(hw
, buffer
, length
, sizeof(hdr
),
6369 if (ret_val
== E1000_SUCCESS
) {
6370 ret_val
= e1000_mng_write_cmd_header(hw
, &hdr
);
6371 if (ret_val
== E1000_SUCCESS
)
6372 ret_val
= e1000_mng_write_commit(hw
);
6379 /*****************************************************************************
6380 * This function calculates the checksum.
6382 * returns - checksum of buffer contents.
6383 ****************************************************************************/
6385 e1000_calculate_mng_checksum(char *buffer
, uint32_t length
)
6393 for (i
=0; i
< length
; i
++)
6396 return (uint8_t) (0 - sum
);
6399 /*****************************************************************************
6400 * This function checks whether tx pkt filtering needs to be enabled or not.
6402 * returns - TRUE for packet filtering or FALSE.
6403 ****************************************************************************/
6405 e1000_enable_tx_pkt_filtering(struct e1000_hw
*hw
)
6407 /* called in init as well as watchdog timer functions */
6409 int32_t ret_val
, checksum
;
6410 boolean_t tx_filter
= FALSE
;
6411 struct e1000_host_mng_dhcp_cookie
*hdr
= &(hw
->mng_cookie
);
6412 uint8_t *buffer
= (uint8_t *) &(hw
->mng_cookie
);
6414 if (e1000_check_mng_mode(hw
)) {
6415 ret_val
= e1000_mng_enable_host_if(hw
);
6416 if (ret_val
== E1000_SUCCESS
) {
6417 ret_val
= e1000_host_if_read_cookie(hw
, buffer
);
6418 if (ret_val
== E1000_SUCCESS
) {
6419 checksum
= hdr
->checksum
;
6421 if ((hdr
->signature
== E1000_IAMT_SIGNATURE
) &&
6422 checksum
== e1000_calculate_mng_checksum((char *)buffer
,
6423 E1000_MNG_DHCP_COOKIE_LENGTH
)) {
6425 E1000_MNG_DHCP_COOKIE_STATUS_PARSING_SUPPORT
)
6434 hw
->tx_pkt_filtering
= tx_filter
;
6438 /******************************************************************************
6439 * Verifies the hardware needs to allow ARPs to be processed by the host
6441 * hw - Struct containing variables accessed by shared code
6443 * returns: - TRUE/FALSE
6445 *****************************************************************************/
6447 e1000_enable_mng_pass_thru(struct e1000_hw
*hw
)
6450 uint32_t fwsm
, factps
;
6452 if (hw
->asf_firmware_present
) {
6453 manc
= E1000_READ_REG(hw
, MANC
);
6455 if (!(manc
& E1000_MANC_RCV_TCO_EN
) ||
6456 !(manc
& E1000_MANC_EN_MAC_ADDR_FILTER
))
6458 if (e1000_arc_subsystem_valid(hw
) == TRUE
) {
6459 fwsm
= E1000_READ_REG(hw
, FWSM
);
6460 factps
= E1000_READ_REG(hw
, FACTPS
);
6462 if (((fwsm
& E1000_FWSM_MODE_MASK
) ==
6463 (e1000_mng_mode_pt
<< E1000_FWSM_MODE_SHIFT
)) &&
6464 (factps
& E1000_FACTPS_MNGCG
))
6467 if ((manc
& E1000_MANC_SMBUS_EN
) && !(manc
& E1000_MANC_ASF_EN
))
6474 e1000_polarity_reversal_workaround(struct e1000_hw
*hw
)
6477 uint16_t mii_status_reg
;
6480 /* Polarity reversal workaround for forced 10F/10H links. */
6482 /* Disable the transmitter on the PHY */
6484 ret_val
= e1000_write_phy_reg(hw
, M88E1000_PHY_PAGE_SELECT
, 0x0019);
6487 ret_val
= e1000_write_phy_reg(hw
, M88E1000_PHY_GEN_CONTROL
, 0xFFFF);
6491 ret_val
= e1000_write_phy_reg(hw
, M88E1000_PHY_PAGE_SELECT
, 0x0000);
6495 /* This loop will early-out if the NO link condition has been met. */
6496 for(i
= PHY_FORCE_TIME
; i
> 0; i
--) {
6497 /* Read the MII Status Register and wait for Link Status bit
6501 ret_val
= e1000_read_phy_reg(hw
, PHY_STATUS
, &mii_status_reg
);
6505 ret_val
= e1000_read_phy_reg(hw
, PHY_STATUS
, &mii_status_reg
);
6509 if((mii_status_reg
& ~MII_SR_LINK_STATUS
) == 0) break;
6510 msec_delay_irq(100);
6513 /* Recommended delay time after link has been lost */
6514 msec_delay_irq(1000);
6516 /* Now we will re-enable th transmitter on the PHY */
6518 ret_val
= e1000_write_phy_reg(hw
, M88E1000_PHY_PAGE_SELECT
, 0x0019);
6522 ret_val
= e1000_write_phy_reg(hw
, M88E1000_PHY_GEN_CONTROL
, 0xFFF0);
6526 ret_val
= e1000_write_phy_reg(hw
, M88E1000_PHY_GEN_CONTROL
, 0xFF00);
6530 ret_val
= e1000_write_phy_reg(hw
, M88E1000_PHY_GEN_CONTROL
, 0x0000);
6534 ret_val
= e1000_write_phy_reg(hw
, M88E1000_PHY_PAGE_SELECT
, 0x0000);
6538 /* This loop will early-out if the link condition has been met. */
6539 for(i
= PHY_FORCE_TIME
; i
> 0; i
--) {
6540 /* Read the MII Status Register and wait for Link Status bit
6544 ret_val
= e1000_read_phy_reg(hw
, PHY_STATUS
, &mii_status_reg
);
6548 ret_val
= e1000_read_phy_reg(hw
, PHY_STATUS
, &mii_status_reg
);
6552 if(mii_status_reg
& MII_SR_LINK_STATUS
) break;
6553 msec_delay_irq(100);
6555 return E1000_SUCCESS
;
6558 /***************************************************************************
6560 * Disables PCI-Express master access.
6562 * hw: Struct containing variables accessed by shared code
6566 ***************************************************************************/
6568 e1000_set_pci_express_master_disable(struct e1000_hw
*hw
)
6572 DEBUGFUNC("e1000_set_pci_express_master_disable");
6574 if (hw
->bus_type
!= e1000_bus_type_pci_express
)
6577 ctrl
= E1000_READ_REG(hw
, CTRL
);
6578 ctrl
|= E1000_CTRL_GIO_MASTER_DISABLE
;
6579 E1000_WRITE_REG(hw
, CTRL
, ctrl
);
6583 /***************************************************************************
6585 * Enables PCI-Express master access.
6587 * hw: Struct containing variables accessed by shared code
6591 ***************************************************************************/
6593 e1000_enable_pciex_master(struct e1000_hw
*hw
)
6597 DEBUGFUNC("e1000_enable_pciex_master");
6599 if (hw
->bus_type
!= e1000_bus_type_pci_express
)
6602 ctrl
= E1000_READ_REG(hw
, CTRL
);
6603 ctrl
&= ~E1000_CTRL_GIO_MASTER_DISABLE
;
6604 E1000_WRITE_REG(hw
, CTRL
, ctrl
);
6608 /*******************************************************************************
6610 * Disables PCI-Express master access and verifies there are no pending requests
6612 * hw: Struct containing variables accessed by shared code
6614 * returns: - E1000_ERR_MASTER_REQUESTS_PENDING if master disable bit hasn't
6615 * caused the master requests to be disabled.
6616 * E1000_SUCCESS master requests disabled.
6618 ******************************************************************************/
6620 e1000_disable_pciex_master(struct e1000_hw
*hw
)
6622 int32_t timeout
= MASTER_DISABLE_TIMEOUT
; /* 80ms */
6624 DEBUGFUNC("e1000_disable_pciex_master");
6626 if (hw
->bus_type
!= e1000_bus_type_pci_express
)
6627 return E1000_SUCCESS
;
6629 e1000_set_pci_express_master_disable(hw
);
6632 if(!(E1000_READ_REG(hw
, STATUS
) & E1000_STATUS_GIO_MASTER_ENABLE
))
6640 DEBUGOUT("Master requests are pending.\n");
6641 return -E1000_ERR_MASTER_REQUESTS_PENDING
;
6644 return E1000_SUCCESS
;
6647 /*******************************************************************************
6649 * Check for EEPROM Auto Read bit done.
6651 * hw: Struct containing variables accessed by shared code
6653 * returns: - E1000_ERR_RESET if fail to reset MAC
6654 * E1000_SUCCESS at any other case.
6656 ******************************************************************************/
6658 e1000_get_auto_rd_done(struct e1000_hw
*hw
)
6660 int32_t timeout
= AUTO_READ_DONE_TIMEOUT
;
6662 DEBUGFUNC("e1000_get_auto_rd_done");
6664 switch (hw
->mac_type
) {
6672 if (E1000_READ_REG(hw
, EECD
) & E1000_EECD_AUTO_RD
) break;
6678 DEBUGOUT("Auto read by HW from EEPROM has not completed.\n");
6679 return -E1000_ERR_RESET
;
6684 /* PHY configuration from NVM just starts after EECD_AUTO_RD sets to high.
6685 * Need to wait for PHY configuration completion before accessing NVM
6687 if (hw
->mac_type
== e1000_82573
)
6690 return E1000_SUCCESS
;
6693 /***************************************************************************
6694 * Checks if the PHY configuration is done
6696 * hw: Struct containing variables accessed by shared code
6698 * returns: - E1000_ERR_RESET if fail to reset MAC
6699 * E1000_SUCCESS at any other case.
6701 ***************************************************************************/
6703 e1000_get_phy_cfg_done(struct e1000_hw
*hw
)
6705 int32_t timeout
= PHY_CFG_TIMEOUT
;
6706 uint32_t cfg_mask
= E1000_EEPROM_CFG_DONE
;
6708 DEBUGFUNC("e1000_get_phy_cfg_done");
6710 switch (hw
->mac_type
) {
6717 if (E1000_READ_REG(hw
, EEMNGCTL
) & cfg_mask
)
6725 DEBUGOUT("MNG configuration cycle has not completed.\n");
6726 return -E1000_ERR_RESET
;
6731 /* PHY configuration from NVM just starts after EECD_AUTO_RD sets to high.
6732 * Need to wait for PHY configuration completion before accessing NVM
6734 if (hw
->mac_type
== e1000_82573
)
6737 return E1000_SUCCESS
;
6740 /***************************************************************************
6742 * Using the combination of SMBI and SWESMBI semaphore bits when resetting
6743 * adapter or Eeprom access.
6745 * hw: Struct containing variables accessed by shared code
6747 * returns: - E1000_ERR_EEPROM if fail to access EEPROM.
6748 * E1000_SUCCESS at any other case.
6750 ***************************************************************************/
6752 e1000_get_hw_eeprom_semaphore(struct e1000_hw
*hw
)
6757 DEBUGFUNC("e1000_get_hw_eeprom_semaphore");
6759 if(!hw
->eeprom_semaphore_present
)
6760 return E1000_SUCCESS
;
6763 /* Get the FW semaphore. */
6764 timeout
= hw
->eeprom
.word_size
+ 1;
6766 swsm
= E1000_READ_REG(hw
, SWSM
);
6767 swsm
|= E1000_SWSM_SWESMBI
;
6768 E1000_WRITE_REG(hw
, SWSM
, swsm
);
6769 /* if we managed to set the bit we got the semaphore. */
6770 swsm
= E1000_READ_REG(hw
, SWSM
);
6771 if(swsm
& E1000_SWSM_SWESMBI
)
6779 /* Release semaphores */
6780 e1000_put_hw_eeprom_semaphore(hw
);
6781 DEBUGOUT("Driver can't access the Eeprom - SWESMBI bit is set.\n");
6782 return -E1000_ERR_EEPROM
;
6785 return E1000_SUCCESS
;
6788 /***************************************************************************
6789 * This function clears HW semaphore bits.
6791 * hw: Struct containing variables accessed by shared code
6795 ***************************************************************************/
6797 e1000_put_hw_eeprom_semaphore(struct e1000_hw
*hw
)
6801 DEBUGFUNC("e1000_put_hw_eeprom_semaphore");
6803 if(!hw
->eeprom_semaphore_present
)
6806 swsm
= E1000_READ_REG(hw
, SWSM
);
6807 swsm
&= ~(E1000_SWSM_SWESMBI
);
6808 E1000_WRITE_REG(hw
, SWSM
, swsm
);
6811 /******************************************************************************
6812 * Checks if PHY reset is blocked due to SOL/IDER session, for example.
6813 * Returning E1000_BLK_PHY_RESET isn't necessarily an error. But it's up to
6814 * the caller to figure out how to deal with it.
6816 * hw - Struct containing variables accessed by shared code
6818 * returns: - E1000_BLK_PHY_RESET
6821 *****************************************************************************/
6823 e1000_check_phy_reset_block(struct e1000_hw
*hw
)
6826 if(hw
->mac_type
> e1000_82547_rev_2
)
6827 manc
= E1000_READ_REG(hw
, MANC
);
6828 return (manc
& E1000_MANC_BLK_PHY_RST_ON_IDE
) ?
6829 E1000_BLK_PHY_RESET
: E1000_SUCCESS
;
6833 e1000_arc_subsystem_valid(struct e1000_hw
*hw
)
6837 /* On 8257x silicon, registers in the range of 0x8800 - 0x8FFC
6838 * may not be provided a DMA clock when no manageability features are
6839 * enabled. We do not want to perform any reads/writes to these registers
6840 * if this is the case. We read FWSM to determine the manageability mode.
6842 switch (hw
->mac_type
) {
6846 fwsm
= E1000_READ_REG(hw
, FWSM
);
6847 if((fwsm
& E1000_FWSM_MODE_MASK
) != 0)