arch/arm/mach-davinci/board-dm365-evm.c

   1 /*
   2  * TI DaVinci DM365 EVM board support
   3  *
   4  * Copyright (C) 2009 Texas Instruments Incorporated
   5  *
   6  * This program is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU General Public License as
   8  * published by the Free Software Foundation version 2.
   9  *
  10  * This program is distributed "as is" WITHOUT ANY WARRANTY of any
  11  * kind, whether express or implied; without even the implied warranty
  12  * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  */
  15 #include <linux/kernel.h>
  16 #include <linux/init.h>
  17 #include <linux/err.h>
  18 #include <linux/i2c.h>
  19 #include <linux/io.h>
  20 #include <linux/clk.h>
  21 #include <linux/i2c/at24.h>
  22 #include <linux/leds.h>
  23 #include <linux/mtd/mtd.h>
  24 #include <linux/mtd/partitions.h>
  25 #include <linux/mtd/nand.h>
  26
  27 #include <asm/mach-types.h>
  28 #include <asm/mach/arch.h>
  29
  30 #include <mach/mux.h>
  31 #include <mach/dm365.h>
  32 #include <mach/common.h>
  33 #include <mach/i2c.h>
  34 #include <mach/serial.h>
  35 #include <mach/mmc.h>
  36 #include <mach/nand.h>
  37
  38 static inline int have_imager(void)
  39 {
  40         /* REVISIT when it's supported, trigger via Kconfig */
  41         return 0;
  42 }
  43
  44 static inline int have_tvp7002(void)
  45 {
  46         /* REVISIT when it's supported, trigger via Kconfig */
  47         return 0;
  48 }
  49
  50
  51 #define DM365_ASYNC_EMIF_CONTROL_BASE   0x01d10000
  52 #define DM365_ASYNC_EMIF_DATA_CE0_BASE  0x02000000
  53 #define DM365_ASYNC_EMIF_DATA_CE1_BASE  0x04000000
  54
  55 #define DM365_EVM_PHY_MASK              (0x2)
  56 #define DM365_EVM_MDIO_FREQUENCY        (2200000) /* PHY bus frequency */
  57
  58 /*
  59  * A MAX-II CPLD is used for various board control functions.
  60  */
  61 #define CPLD_OFFSET(a13a8,a2a1)         (((a13a8) << 10) + ((a2a1) << 3))
  62
  63 #define CPLD_VERSION    CPLD_OFFSET(0,0)        /* r/o */
  64 #define CPLD_TEST       CPLD_OFFSET(0,1)
  65 #define CPLD_LEDS       CPLD_OFFSET(0,2)
  66 #define CPLD_MUX        CPLD_OFFSET(0,3)
  67 #define CPLD_SWITCH     CPLD_OFFSET(1,0)        /* r/o */
  68 #define CPLD_POWER      CPLD_OFFSET(1,1)
  69 #define CPLD_VIDEO      CPLD_OFFSET(1,2)
  70 #define CPLD_CARDSTAT   CPLD_OFFSET(1,3)        /* r/o */
  71
  72 #define CPLD_DILC_OUT   CPLD_OFFSET(2,0)
  73 #define CPLD_DILC_IN    CPLD_OFFSET(2,1)        /* r/o */
  74
  75 #define CPLD_IMG_DIR0   CPLD_OFFSET(2,2)
  76 #define CPLD_IMG_MUX0   CPLD_OFFSET(2,3)
  77 #define CPLD_IMG_MUX1   CPLD_OFFSET(3,0)
  78 #define CPLD_IMG_DIR1   CPLD_OFFSET(3,1)
  79 #define CPLD_IMG_MUX2   CPLD_OFFSET(3,2)
  80 #define CPLD_IMG_MUX3   CPLD_OFFSET(3,3)
  81 #define CPLD_IMG_DIR2   CPLD_OFFSET(4,0)
  82 #define CPLD_IMG_MUX4   CPLD_OFFSET(4,1)
  83 #define CPLD_IMG_MUX5   CPLD_OFFSET(4,2)
  84
  85 #define CPLD_RESETS     CPLD_OFFSET(4,3)
  86
  87 #define CPLD_CCD_DIR1   CPLD_OFFSET(0x3e,0)
  88 #define CPLD_CCD_IO1    CPLD_OFFSET(0x3e,1)
  89 #define CPLD_CCD_DIR2   CPLD_OFFSET(0x3e,2)
  90 #define CPLD_CCD_IO2    CPLD_OFFSET(0x3e,3)
  91 #define CPLD_CCD_DIR3   CPLD_OFFSET(0x3f,0)
  92 #define CPLD_CCD_IO3    CPLD_OFFSET(0x3f,1)
  93
  94 static void __iomem *cpld;
  95
  96
  97 /* NOTE:  this is geared for the standard config, with a socketed
  98  * 2 GByte Micron NAND (MT29F16G08FAA) using 128KB sectors.  If you
  99  * swap chips with a different block size, partitioning will
 100  * need to be changed. This NAND chip MT29F16G08FAA is the default
 101  * NAND shipped with the Spectrum Digital DM365 EVM
 102  */
 103 #define NAND_BLOCK_SIZE         SZ_128K
 104
 105 static struct mtd_partition davinci_nand_partitions[] = {
 106         {
 107                 /* UBL (a few copies) plus U-Boot */
 108                 .name           = "bootloader",
 109                 .offset         = 0,
 110                 .size           = 28 * NAND_BLOCK_SIZE,
 111                 .mask_flags     = MTD_WRITEABLE, /* force read-only */
 112         }, {
 113                 /* U-Boot environment */
 114                 .name           = "params",
 115                 .offset         = MTDPART_OFS_APPEND,
 116                 .size           = 2 * NAND_BLOCK_SIZE,
 117                 .mask_flags     = 0,
 118         }, {
 119                 .name           = "kernel",
 120                 .offset         = MTDPART_OFS_APPEND,
 121                 .size           = SZ_4M,
 122                 .mask_flags     = 0,
 123         }, {
 124                 .name           = "filesystem1",
 125                 .offset         = MTDPART_OFS_APPEND,
 126                 .size           = SZ_512M,
 127                 .mask_flags     = 0,
 128         }, {
 129                 .name           = "filesystem2",
 130                 .offset         = MTDPART_OFS_APPEND,
 131                 .size           = MTDPART_SIZ_FULL,
 132                 .mask_flags     = 0,
 133         }
 134         /* two blocks with bad block table (and mirror) at the end */
 135 };
 136
 137 static struct davinci_nand_pdata davinci_nand_data = {
 138         .mask_chipsel           = BIT(14),
 139         .parts                  = davinci_nand_partitions,
 140         .nr_parts               = ARRAY_SIZE(davinci_nand_partitions),
 141         .ecc_mode               = NAND_ECC_HW,
 142         .options                = NAND_USE_FLASH_BBT,
 143         .ecc_bits               = 4,
 144 };
 145
 146 static struct resource davinci_nand_resources[] = {
 147         {
 148                 .start          = DM365_ASYNC_EMIF_DATA_CE0_BASE,
 149                 .end            = DM365_ASYNC_EMIF_DATA_CE0_BASE + SZ_32M - 1,
 150                 .flags          = IORESOURCE_MEM,
 151         }, {
 152                 .start          = DM365_ASYNC_EMIF_CONTROL_BASE,
 153                 .end            = DM365_ASYNC_EMIF_CONTROL_BASE + SZ_4K - 1,
 154                 .flags          = IORESOURCE_MEM,
 155         },
 156 };
 157
 158 static struct platform_device davinci_nand_device = {
 159         .name                   = "davinci_nand",
 160         .id                     = 0,
 161         .num_resources          = ARRAY_SIZE(davinci_nand_resources),
 162         .resource               = davinci_nand_resources,
 163         .dev                    = {
 164                 .platform_data  = &davinci_nand_data,
 165         },
 166 };
 167
 168 static struct at24_platform_data eeprom_info = {
 169         .byte_len       = (256*1024) / 8,
 170         .page_size      = 64,
 171         .flags          = AT24_FLAG_ADDR16,
 172         .setup          = davinci_get_mac_addr,
 173         .context        = (void *)0x7f00,
 174 };
 175
 176 static struct snd_platform_data dm365_evm_snd_data;
 177
 178 static struct i2c_board_info i2c_info[] = {
 179         {
 180                 I2C_BOARD_INFO("24c256", 0x50),
 181                 .platform_data  = &eeprom_info,
 182         },
 183         {
 184                 I2C_BOARD_INFO("tlv320aic3x", 0x18),
 185         },
 186 };
 187
 188 static struct davinci_i2c_platform_data i2c_pdata = {
 189         .bus_freq       = 400   /* kHz */,
 190         .bus_delay      = 0     /* usec */,
 191 };
 192
 193 static int cpld_mmc_get_cd(int module)
 194 {
 195         if (!cpld)
 196                 return -ENXIO;
 197
 198         /* low == card present */
 199         return !(__raw_readb(cpld + CPLD_CARDSTAT) & BIT(module ? 4 : 0));
 200 }
 201
 202 static int cpld_mmc_get_ro(int module)
 203 {
 204         if (!cpld)
 205                 return -ENXIO;
 206
 207         /* high == card's write protect switch active */
 208         return !!(__raw_readb(cpld + CPLD_CARDSTAT) & BIT(module ? 5 : 1));
 209 }
 210
 211 static struct davinci_mmc_config dm365evm_mmc_config = {
 212         .get_cd         = cpld_mmc_get_cd,
 213         .get_ro         = cpld_mmc_get_ro,
 214         .wires          = 4,
 215         .max_freq       = 50000000,
 216         .caps           = MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED,
 217         .version        = MMC_CTLR_VERSION_2,
 218 };
 219
 220 static void dm365evm_emac_configure(void)
 221 {
 222         /*
 223          * EMAC pins are multiplexed with GPIO and UART
 224          * Further details are available at the DM365 ARM
 225          * Subsystem Users Guide(sprufg5.pdf) pages 125 - 127
 226          */
 227         davinci_cfg_reg(DM365_EMAC_TX_EN);
 228         davinci_cfg_reg(DM365_EMAC_TX_CLK);
 229         davinci_cfg_reg(DM365_EMAC_COL);
 230         davinci_cfg_reg(DM365_EMAC_TXD3);
 231         davinci_cfg_reg(DM365_EMAC_TXD2);
 232         davinci_cfg_reg(DM365_EMAC_TXD1);
 233         davinci_cfg_reg(DM365_EMAC_TXD0);
 234         davinci_cfg_reg(DM365_EMAC_RXD3);
 235         davinci_cfg_reg(DM365_EMAC_RXD2);
 236         davinci_cfg_reg(DM365_EMAC_RXD1);
 237         davinci_cfg_reg(DM365_EMAC_RXD0);
 238         davinci_cfg_reg(DM365_EMAC_RX_CLK);
 239         davinci_cfg_reg(DM365_EMAC_RX_DV);
 240         davinci_cfg_reg(DM365_EMAC_RX_ER);
 241         davinci_cfg_reg(DM365_EMAC_CRS);
 242         davinci_cfg_reg(DM365_EMAC_MDIO);
 243         davinci_cfg_reg(DM365_EMAC_MDCLK);
 244
 245         /*
 246          * EMAC interrupts are multiplexed with GPIO interrupts
 247          * Details are available at the DM365 ARM
 248          * Subsystem Users Guide(sprufg5.pdf) pages 133 - 134
 249          */
 250         davinci_cfg_reg(DM365_INT_EMAC_RXTHRESH);
 251         davinci_cfg_reg(DM365_INT_EMAC_RXPULSE);
 252         davinci_cfg_reg(DM365_INT_EMAC_TXPULSE);
 253         davinci_cfg_reg(DM365_INT_EMAC_MISCPULSE);
 254 }
 255
 256 static void dm365evm_mmc_configure(void)
 257 {
 258         /*
 259          * MMC/SD pins are multiplexed with GPIO and EMIF
 260          * Further details are available at the DM365 ARM
 261          * Subsystem Users Guide(sprufg5.pdf) pages 118, 128 - 131
 262          */
 263         davinci_cfg_reg(DM365_SD1_CLK);
 264         davinci_cfg_reg(DM365_SD1_CMD);
 265         davinci_cfg_reg(DM365_SD1_DATA3);
 266         davinci_cfg_reg(DM365_SD1_DATA2);
 267         davinci_cfg_reg(DM365_SD1_DATA1);
 268         davinci_cfg_reg(DM365_SD1_DATA0);
 269 }
 270
 271 static void __init evm_init_i2c(void)
 272 {
 273         davinci_init_i2c(&i2c_pdata);
 274         i2c_register_board_info(1, i2c_info, ARRAY_SIZE(i2c_info));
 275 }
 276
 277 static struct platform_device *dm365_evm_nand_devices[] __initdata = {
 278         &davinci_nand_device,
 279 };
 280
 281 static inline int have_leds(void)
 282 {
 283 #ifdef CONFIG_LEDS_CLASS
 284         return 1;
 285 #else
 286         return 0;
 287 #endif
 288 }
 289
 290 struct cpld_led {
 291         struct led_classdev     cdev;
 292         u8                      mask;
 293 };
 294
 295 static const struct {
 296         const char *name;
 297         const char *trigger;
 298 } cpld_leds[] = {
 299         { "dm365evm::ds2", },
 300         { "dm365evm::ds3", },
 301         { "dm365evm::ds4", },
 302         { "dm365evm::ds5", },
 303         { "dm365evm::ds6", "nand-disk", },
 304         { "dm365evm::ds7", "mmc1", },
 305         { "dm365evm::ds8", "mmc0", },
 306         { "dm365evm::ds9", "heartbeat", },
 307 };
 308
 309 static void cpld_led_set(struct led_classdev *cdev, enum led_brightness b)
 310 {
 311         struct cpld_led *led = container_of(cdev, struct cpld_led, cdev);
 312         u8 reg = __raw_readb(cpld + CPLD_LEDS);
 313
 314         if (b != LED_OFF)
 315                 reg &= ~led->mask;
 316         else
 317                 reg |= led->mask;
 318         __raw_writeb(reg, cpld + CPLD_LEDS);
 319 }
 320
 321 static enum led_brightness cpld_led_get(struct led_classdev *cdev)
 322 {
 323         struct cpld_led *led = container_of(cdev, struct cpld_led, cdev);
 324         u8 reg = __raw_readb(cpld + CPLD_LEDS);
 325
 326         return (reg & led->mask) ? LED_OFF : LED_FULL;
 327 }
 328
 329 static int __init cpld_leds_init(void)
 330 {
 331         int     i;
 332
 333         if (!have_leds() ||  !cpld)
 334                 return 0;
 335
 336         /* setup LEDs */
 337         __raw_writeb(0xff, cpld + CPLD_LEDS);
 338         for (i = 0; i < ARRAY_SIZE(cpld_leds); i++) {
 339                 struct cpld_led *led;
 340
 341                 led = kzalloc(sizeof(*led), GFP_KERNEL);
 342                 if (!led)
 343                         break;
 344
 345                 led->cdev.name = cpld_leds[i].name;
 346                 led->cdev.brightness_set = cpld_led_set;
 347                 led->cdev.brightness_get = cpld_led_get;
 348                 led->cdev.default_trigger = cpld_leds[i].trigger;
 349                 led->mask = BIT(i);
 350
 351                 if (led_classdev_register(NULL, &led->cdev) < 0) {
 352                         kfree(led);
 353                         break;
 354                 }
 355         }
 356
 357         return 0;
 358 }
 359 /* run after subsys_initcall() for LEDs */
 360 fs_initcall(cpld_leds_init);
 361
 362
 363 static void __init evm_init_cpld(void)
 364 {
 365         u8 mux, resets;
 366         const char *label;
 367         struct clk *aemif_clk;
 368
 369         /* Make sure we can configure the CPLD through CS1.  Then
 370          * leave it on for later access to MMC and LED registers.
 371          */
 372         aemif_clk = clk_get(NULL, "aemif");
 373         if (IS_ERR(aemif_clk))
 374                 return;
 375         clk_enable(aemif_clk);
 376
 377         if (request_mem_region(DM365_ASYNC_EMIF_DATA_CE1_BASE, SECTION_SIZE,
 378                         "cpld") == NULL)
 379                 goto fail;
 380         cpld = ioremap(DM365_ASYNC_EMIF_DATA_CE1_BASE, SECTION_SIZE);
 381         if (!cpld) {
 382                 release_mem_region(DM365_ASYNC_EMIF_DATA_CE1_BASE,
 383                                 SECTION_SIZE);
 384 fail:
 385                 pr_err("ERROR: can't map CPLD\n");
 386                 clk_disable(aemif_clk);
 387                 return;
 388         }
 389
 390         /* External muxing for some signals */
 391         mux = 0;
 392
 393         /* Read SW5 to set up NAND + keypad _or_ OneNAND (sync read).
 394          * NOTE:  SW4 bus width setting must match!
 395          */
 396         if ((__raw_readb(cpld + CPLD_SWITCH) & BIT(5)) == 0) {
 397                 /* external keypad mux */
 398                 mux |= BIT(7);
 399
 400                 platform_add_devices(dm365_evm_nand_devices,
 401                                 ARRAY_SIZE(dm365_evm_nand_devices));
 402         } else {
 403                 /* no OneNAND support yet */
 404         }
 405
 406         /* Leave external chips in reset when unused. */
 407         resets = BIT(3) | BIT(2) | BIT(1) | BIT(0);
 408
 409         /* Static video input config with SN74CBT16214 1-of-3 mux:
 410          *  - port b1 == tvp7002 (mux lowbits == 1 or 6)
 411          *  - port b2 == imager (mux lowbits == 2 or 7)
 412          *  - port b3 == tvp5146 (mux lowbits == 5)
 413          *
 414          * Runtime switching could work too, with limitations.
 415          */
 416         if (have_imager()) {
 417                 label = "HD imager";
 418                 mux |= 1;
 419
 420                 /* externally mux MMC1/ENET/AIC33 to imager */
 421                 mux |= BIT(6) | BIT(5) | BIT(3);
 422         } else {
 423                 struct davinci_soc_info *soc_info = &davinci_soc_info;
 424
 425                 /* we can use MMC1 ... */
 426                 dm365evm_mmc_configure();
 427                 davinci_setup_mmc(1, &dm365evm_mmc_config);
 428
 429                 /* ... and ENET ... */
 430                 dm365evm_emac_configure();
 431                 soc_info->emac_pdata->phy_mask = DM365_EVM_PHY_MASK;
 432                 soc_info->emac_pdata->mdio_max_freq = DM365_EVM_MDIO_FREQUENCY;
 433                 resets &= ~BIT(3);
 434
 435                 /* ... and AIC33 */
 436                 resets &= ~BIT(1);
 437
 438                 if (have_tvp7002()) {
 439                         mux |= 2;
 440                         resets &= ~BIT(2);
 441                         label = "tvp7002 HD";
 442                 } else {
 443                         /* default to tvp5146 */
 444                         mux |= 5;
 445                         resets &= ~BIT(0);
 446                         label = "tvp5146 SD";
 447                 }
 448         }
 449         __raw_writeb(mux, cpld + CPLD_MUX);
 450         __raw_writeb(resets, cpld + CPLD_RESETS);
 451         pr_info("EVM: %s video input\n", label);
 452
 453         /* REVISIT export switches: NTSC/PAL (SW5.6), EXTRA1 (SW5.2), etc */
 454 }
 455
 456 static struct davinci_uart_config uart_config __initdata = {
 457         .enabled_uarts = (1 << 0),
 458 };
 459
 460 static void __init dm365_evm_map_io(void)
 461 {
 462         dm365_init();
 463 }
 464
 465 static __init void dm365_evm_init(void)
 466 {
 467         evm_init_i2c();
 468         davinci_serial_init(&uart_config);
 469
 470         dm365evm_emac_configure();
 471         dm365evm_mmc_configure();
 472
 473         davinci_setup_mmc(0, &dm365evm_mmc_config);
 474
 475         /* maybe setup mmc1/etc ... _after_ mmc0 */
 476         evm_init_cpld();
 477
 478         dm365_init_asp(&dm365_evm_snd_data);
 479 }
 480
 481 static __init void dm365_evm_irq_init(void)
 482 {
 483         davinci_irq_init();
 484 }
 485
 486 MACHINE_START(DAVINCI_DM365_EVM, "DaVinci DM365 EVM")
 487         .phys_io        = IO_PHYS,
 488         .io_pg_offst    = (__IO_ADDRESS(IO_PHYS) >> 18) & 0xfffc,
 489         .boot_params    = (0x80000100),
 490         .map_io         = dm365_evm_map_io,
 491         .init_irq       = dm365_evm_irq_init,
 492         .timer          = &davinci_timer,
 493         .init_machine   = dm365_evm_init,
 494 MACHINE_END
 495