| blob | 499a065f4e6019544c957d72a8c5168fa6461803 |
1 //
2 // assembly portion of the IA64 MCA handling
3 //
4 // Mods by cfleck to integrate into kernel build
5 // 00/03/15 davidm Added various stop bits to get a clean compile
6 //
7 // 00/03/29 cfleck Added code to save INIT handoff state in pt_regs format, switch to temp
8 // kstack, switch modes, jump to C INIT handler
9 //
10 // 02/01/04 J.Hall <jenna.s.hall@intel.com>
11 // Before entering virtual mode code:
12 // 1. Check for TLB CPU error
13 // 2. Restore current thread pointer to kr6
14 // 3. Move stack ptr 16 bytes to conform to C calling convention
15 //
16 // 04/11/12 Russ Anderson <rja@sgi.com>
17 // Added per cpu MCA/INIT stack save areas.
18 //
19 // 12/08/05 Keith Owens <kaos@sgi.com>
20 // Use per cpu MCA/INIT stacks for all data.
21 //
22 #include <linux/config.h>
23 #include <linux/threads.h>
25 #include <asm/asmmacro.h>
26 #include <asm/pgtable.h>
27 #include <asm/processor.h>
28 #include <asm/mca_asm.h>
29 #include <asm/mca.h>
31 #include "entry.h"
33 #define GET_IA64_MCA_DATA(reg) \
34 GET_THIS_PADDR(reg, ia64_mca_data) \
35 ;; \
36 ld8 reg=[reg]
38 .global ia64_do_tlb_purge
39 .global ia64_os_mca_dispatch
40 .global ia64_os_init_dispatch_monarch
41 .global ia64_os_init_dispatch_slave
43 .text
44 .align 16
46 //StartMain////////////////////////////////////////////////////////////////////
48 /*
49 * Just the TLB purge part is moved to a separate function
50 * so we can re-use the code for cpu hotplug code as well
51 * Caller should now setup b1, so we can branch once the
52 * tlb flush is complete.
53 */
55 ia64_do_tlb_purge:
56 #define O(member) IA64_CPUINFO_##member##_OFFSET
58 GET_THIS_PADDR(r2, cpu_info) // load phys addr of cpu_info into r2
59 ;;
60 addl r17=O(PTCE_STRIDE),r2
61 addl r2=O(PTCE_BASE),r2
62 ;;
63 ld8 r18=[r2],(O(PTCE_COUNT)-O(PTCE_BASE));; // r18=ptce_base
64 ld4 r19=[r2],4 // r19=ptce_count[0]
65 ld4 r21=[r17],4 // r21=ptce_stride[0]
66 ;;
67 ld4 r20=[r2] // r20=ptce_count[1]
68 ld4 r22=[r17] // r22=ptce_stride[1]
69 mov r24=0
70 ;;
71 adds r20=-1,r20
72 ;;
73 #undef O
75 2:
76 cmp.ltu p6,p7=r24,r19
77 (p7) br.cond.dpnt.few 4f
78 mov ar.lc=r20
79 3:
80 ptc.e r18
81 ;;
82 add r18=r22,r18
83 br.cloop.sptk.few 3b
84 ;;
85 add r18=r21,r18
86 add r24=1,r24
87 ;;
88 br.sptk.few 2b
89 4:
90 srlz.i // srlz.i implies srlz.d
91 ;;
93 // Now purge addresses formerly mapped by TR registers
94 // 1. Purge ITR&DTR for kernel.
95 movl r16=KERNEL_START
96 mov r18=KERNEL_TR_PAGE_SHIFT<<2
97 ;;
98 ptr.i r16, r18
99 ptr.d r16, r18
100 ;;
101 srlz.i
102 ;;
103 srlz.d
104 ;;
105 // 2. Purge DTR for PERCPU data.
106 movl r16=PERCPU_ADDR
107 mov r18=PERCPU_PAGE_SHIFT<<2
108 ;;
109 ptr.d r16,r18
110 ;;
111 srlz.d
112 ;;
113 // 3. Purge ITR for PAL code.
114 GET_THIS_PADDR(r2, ia64_mca_pal_base)
115 ;;
116 ld8 r16=[r2]
117 mov r18=IA64_GRANULE_SHIFT<<2
118 ;;
119 ptr.i r16,r18
120 ;;
121 srlz.i
122 ;;
123 // 4. Purge DTR for stack.
124 mov r16=IA64_KR(CURRENT_STACK)
125 ;;
126 shl r16=r16,IA64_GRANULE_SHIFT
127 movl r19=PAGE_OFFSET
128 ;;
129 add r16=r19,r16
130 mov r18=IA64_GRANULE_SHIFT<<2
131 ;;
132 ptr.d r16,r18
133 ;;
134 srlz.i
135 ;;
136 // Now branch away to caller.
137 br.sptk.many b1
138 ;;
140 //EndMain//////////////////////////////////////////////////////////////////////
142 //StartMain////////////////////////////////////////////////////////////////////
144 ia64_os_mca_dispatch:
145 // Serialize all MCA processing
146 mov r3=1;;
147 LOAD_PHYSICAL(p0,r2,ia64_mca_serialize);;
148 ia64_os_mca_spin:
149 xchg4 r4=[r2],r3;;
150 cmp.ne p6,p0=r4,r0
151 (p6) br ia64_os_mca_spin
153 mov r3=IA64_MCA_CPU_MCA_STACK_OFFSET // use the MCA stack
154 LOAD_PHYSICAL(p0,r2,1f) // return address
155 mov r19=1 // All MCA events are treated as monarch (for now)
156 br.sptk ia64_state_save // save the state that is not in minstate
157 1:
159 GET_IA64_MCA_DATA(r2)
160 // Using MCA stack, struct ia64_sal_os_state, variable proc_state_param
161 ;;
162 add r3=IA64_MCA_CPU_MCA_STACK_OFFSET+MCA_SOS_OFFSET+IA64_SAL_OS_STATE_PROC_STATE_PARAM_OFFSET, r2
163 ;;
164 ld8 r18=[r3] // Get processor state parameter on existing PALE_CHECK.
165 ;;
166 tbit.nz p6,p7=r18,60
167 (p7) br.spnt done_tlb_purge_and_reload
169 // The following code purges TC and TR entries. Then reload all TC entries.
170 // Purge percpu data TC entries.
171 begin_tlb_purge_and_reload:
172 movl r18=ia64_reload_tr;;
173 LOAD_PHYSICAL(p0,r18,ia64_reload_tr);;
174 mov b1=r18;;
175 br.sptk.many ia64_do_tlb_purge;;
177 ia64_reload_tr:
178 // Finally reload the TR registers.
179 // 1. Reload DTR/ITR registers for kernel.
180 mov r18=KERNEL_TR_PAGE_SHIFT<<2
181 movl r17=KERNEL_START
182 ;;
183 mov cr.itir=r18
184 mov cr.ifa=r17
185 mov r16=IA64_TR_KERNEL
186 mov r19=ip
187 movl r18=PAGE_KERNEL
188 ;;
189 dep r17=0,r19,0, KERNEL_TR_PAGE_SHIFT
190 ;;
191 or r18=r17,r18
192 ;;
193 itr.i itr[r16]=r18
194 ;;
195 itr.d dtr[r16]=r18
196 ;;
197 srlz.i
198 srlz.d
199 ;;
200 // 2. Reload DTR register for PERCPU data.
201 GET_THIS_PADDR(r2, ia64_mca_per_cpu_pte)
202 ;;
203 movl r16=PERCPU_ADDR // vaddr
204 movl r18=PERCPU_PAGE_SHIFT<<2
205 ;;
206 mov cr.itir=r18
207 mov cr.ifa=r16
208 ;;
209 ld8 r18=[r2] // load per-CPU PTE
210 mov r16=IA64_TR_PERCPU_DATA;
211 ;;
212 itr.d dtr[r16]=r18
213 ;;
214 srlz.d
215 ;;
216 // 3. Reload ITR for PAL code.
217 GET_THIS_PADDR(r2, ia64_mca_pal_pte)
218 ;;
219 ld8 r18=[r2] // load PAL PTE
220 ;;
221 GET_THIS_PADDR(r2, ia64_mca_pal_base)
222 ;;
223 ld8 r16=[r2] // load PAL vaddr
224 mov r19=IA64_GRANULE_SHIFT<<2
225 ;;
226 mov cr.itir=r19
227 mov cr.ifa=r16
228 mov r20=IA64_TR_PALCODE
229 ;;
230 itr.i itr[r20]=r18
231 ;;
232 srlz.i
233 ;;
234 // 4. Reload DTR for stack.
235 mov r16=IA64_KR(CURRENT_STACK)
236 ;;
237 shl r16=r16,IA64_GRANULE_SHIFT
238 movl r19=PAGE_OFFSET
239 ;;
240 add r18=r19,r16
241 movl r20=PAGE_KERNEL
242 ;;
243 add r16=r20,r16
244 mov r19=IA64_GRANULE_SHIFT<<2
245 ;;
246 mov cr.itir=r19
247 mov cr.ifa=r18
248 mov r20=IA64_TR_CURRENT_STACK
249 ;;
250 itr.d dtr[r20]=r16
251 ;;
252 srlz.d
254 done_tlb_purge_and_reload:
256 // switch to per cpu MCA stack
257 mov r3=IA64_MCA_CPU_MCA_STACK_OFFSET // use the MCA stack
258 LOAD_PHYSICAL(p0,r2,1f) // return address
259 br.sptk ia64_new_stack
260 1:
262 // everything saved, now we can set the kernel registers
263 mov r3=IA64_MCA_CPU_MCA_STACK_OFFSET // use the MCA stack
264 LOAD_PHYSICAL(p0,r2,1f) // return address
265 br.sptk ia64_set_kernel_registers
266 1:
268 // This must be done in physical mode
269 GET_IA64_MCA_DATA(r2)
270 ;;
271 mov r7=r2
273 // Enter virtual mode from physical mode
274 VIRTUAL_MODE_ENTER(r2, r3, ia64_os_mca_virtual_begin, r4)
276 // This code returns to SAL via SOS r2, in general SAL has no unwind
277 // data. To get a clean termination when backtracing the C MCA/INIT
278 // handler, set a dummy return address of 0 in this routine. That
279 // requires that ia64_os_mca_virtual_begin be a global function.
280 ENTRY(ia64_os_mca_virtual_begin)
281 .prologue
282 .save rp,r0
283 .body
285 mov ar.rsc=3 // set eager mode for C handler
286 mov r2=r7 // see GET_IA64_MCA_DATA above
287 ;;
289 // Call virtual mode handler
290 alloc r14=ar.pfs,0,0,3,0
291 ;;
292 DATA_PA_TO_VA(r2,r7)
293 ;;
294 add out0=IA64_MCA_CPU_MCA_STACK_OFFSET+MCA_PT_REGS_OFFSET, r2
295 add out1=IA64_MCA_CPU_MCA_STACK_OFFSET+MCA_SWITCH_STACK_OFFSET, r2
296 add out2=IA64_MCA_CPU_MCA_STACK_OFFSET+MCA_SOS_OFFSET, r2
297 br.call.sptk.many b0=ia64_mca_handler
299 // Revert back to physical mode before going back to SAL
300 PHYSICAL_MODE_ENTER(r2, r3, ia64_os_mca_virtual_end, r4)
301 ia64_os_mca_virtual_end:
303 END(ia64_os_mca_virtual_begin)
305 // switch back to previous stack
306 alloc r14=ar.pfs,0,0,0,0 // remove the MCA handler frame
307 mov r3=IA64_MCA_CPU_MCA_STACK_OFFSET // use the MCA stack
308 LOAD_PHYSICAL(p0,r2,1f) // return address
309 br.sptk ia64_old_stack
310 1:
312 mov r3=IA64_MCA_CPU_MCA_STACK_OFFSET // use the MCA stack
313 LOAD_PHYSICAL(p0,r2,1f) // return address
314 br.sptk ia64_state_restore // restore the SAL state
315 1:
317 mov b0=r12 // SAL_CHECK return address
319 // release lock
320 LOAD_PHYSICAL(p0,r3,ia64_mca_serialize);;
321 st4.rel [r3]=r0
323 br b0
325 //EndMain//////////////////////////////////////////////////////////////////////
327 //StartMain////////////////////////////////////////////////////////////////////
329 //
330 // SAL to OS entry point for INIT on all processors. This has been defined for
331 // registration purposes with SAL as a part of ia64_mca_init. Monarch and
332 // slave INIT have identical processing, except for the value of the
333 // sos->monarch flag in r19.
334 //
336 ia64_os_init_dispatch_monarch:
337 mov r19=1 // Bow, bow, ye lower middle classes!
338 br.sptk ia64_os_init_dispatch
340 ia64_os_init_dispatch_slave:
341 mov r19=0 // <igor>yeth, mathter</igor>
343 ia64_os_init_dispatch:
345 mov r3=IA64_MCA_CPU_INIT_STACK_OFFSET // use the INIT stack
346 LOAD_PHYSICAL(p0,r2,1f) // return address
347 br.sptk ia64_state_save // save the state that is not in minstate
348 1:
350 // switch to per cpu INIT stack
351 mov r3=IA64_MCA_CPU_INIT_STACK_OFFSET // use the INIT stack
352 LOAD_PHYSICAL(p0,r2,1f) // return address
353 br.sptk ia64_new_stack
354 1:
356 // everything saved, now we can set the kernel registers
357 mov r3=IA64_MCA_CPU_INIT_STACK_OFFSET // use the INIT stack
358 LOAD_PHYSICAL(p0,r2,1f) // return address
359 br.sptk ia64_set_kernel_registers
360 1:
362 // This must be done in physical mode
363 GET_IA64_MCA_DATA(r2)
364 ;;
365 mov r7=r2
367 // Enter virtual mode from physical mode
368 VIRTUAL_MODE_ENTER(r2, r3, ia64_os_init_virtual_begin, r4)
370 // This code returns to SAL via SOS r2, in general SAL has no unwind
371 // data. To get a clean termination when backtracing the C MCA/INIT
372 // handler, set a dummy return address of 0 in this routine. That
373 // requires that ia64_os_init_virtual_begin be a global function.
374 ENTRY(ia64_os_init_virtual_begin)
375 .prologue
376 .save rp,r0
377 .body
379 mov ar.rsc=3 // set eager mode for C handler
380 mov r2=r7 // see GET_IA64_MCA_DATA above
381 ;;
383 // Call virtual mode handler
384 alloc r14=ar.pfs,0,0,3,0
385 ;;
386 DATA_PA_TO_VA(r2,r7)
387 ;;
388 add out0=IA64_MCA_CPU_INIT_STACK_OFFSET+MCA_PT_REGS_OFFSET, r2
389 add out1=IA64_MCA_CPU_INIT_STACK_OFFSET+MCA_SWITCH_STACK_OFFSET, r2
390 add out2=IA64_MCA_CPU_INIT_STACK_OFFSET+MCA_SOS_OFFSET, r2
391 br.call.sptk.many b0=ia64_init_handler
393 // Revert back to physical mode before going back to SAL
394 PHYSICAL_MODE_ENTER(r2, r3, ia64_os_init_virtual_end, r4)
395 ia64_os_init_virtual_end:
397 END(ia64_os_init_virtual_begin)
399 mov r3=IA64_MCA_CPU_INIT_STACK_OFFSET // use the INIT stack
400 LOAD_PHYSICAL(p0,r2,1f) // return address
401 br.sptk ia64_state_restore // restore the SAL state
402 1:
404 // switch back to previous stack
405 alloc r14=ar.pfs,0,0,0,0 // remove the INIT handler frame
406 mov r3=IA64_MCA_CPU_INIT_STACK_OFFSET // use the INIT stack
407 LOAD_PHYSICAL(p0,r2,1f) // return address
408 br.sptk ia64_old_stack
409 1:
411 mov b0=r12 // SAL_CHECK return address
412 br b0
414 //EndMain//////////////////////////////////////////////////////////////////////
416 // common defines for the stubs
417 #define ms r4
418 #define regs r5
419 #define temp1 r2 /* careful, it overlaps with input registers */
420 #define temp2 r3 /* careful, it overlaps with input registers */
421 #define temp3 r7
422 #define temp4 r14
425 //++
426 // Name:
427 // ia64_state_save()
428 //
429 // Stub Description:
430 //
431 // Save the state that is not in minstate. This is sensitive to the layout of
432 // struct ia64_sal_os_state in mca.h.
433 //
434 // r2 contains the return address, r3 contains either
435 // IA64_MCA_CPU_MCA_STACK_OFFSET or IA64_MCA_CPU_INIT_STACK_OFFSET.
436 //
437 // The OS to SAL section of struct ia64_sal_os_state is set to a default
438 // value of cold boot (MCA) or warm boot (INIT) and return to the same
439 // context. ia64_sal_os_state is also used to hold some registers that
440 // need to be saved and restored across the stack switches.
441 //
442 // Most input registers to this stub come from PAL/SAL
443 // r1 os gp, physical
444 // r8 pal_proc entry point
445 // r9 sal_proc entry point
446 // r10 sal gp
447 // r11 MCA - rendevzous state, INIT - reason code
448 // r12 sal return address
449 // r17 pal min_state
450 // r18 processor state parameter
451 // r19 monarch flag, set by the caller of this routine
452 //
453 // In addition to the SAL to OS state, this routine saves all the
454 // registers that appear in struct pt_regs and struct switch_stack,
455 // excluding those that are already in the PAL minstate area. This
456 // results in a partial pt_regs and switch_stack, the C code copies the
457 // remaining registers from PAL minstate to pt_regs and switch_stack. The
458 // resulting structures contain all the state of the original process when
459 // MCA/INIT occurred.
460 //
461 //--
463 ia64_state_save:
464 add regs=MCA_SOS_OFFSET, r3
465 add ms=MCA_SOS_OFFSET+8, r3
466 mov b0=r2 // save return address
467 cmp.eq p1,p2=IA64_MCA_CPU_MCA_STACK_OFFSET, r3
468 ;;
469 GET_IA64_MCA_DATA(temp2)
470 ;;
471 add temp1=temp2, regs // struct ia64_sal_os_state on MCA or INIT stack
472 add temp2=temp2, ms // struct ia64_sal_os_state+8 on MCA or INIT stack
473 ;;
474 mov regs=temp1 // save the start of sos
475 st8 [temp1]=r1,16 // os_gp
476 st8 [temp2]=r8,16 // pal_proc
477 ;;
478 st8 [temp1]=r9,16 // sal_proc
479 st8 [temp2]=r11,16 // rv_rc
480 mov r11=cr.iipa
481 ;;
482 st8 [temp1]=r18,16 // proc_state_param
483 st8 [temp2]=r19,16 // monarch
484 mov r6=IA64_KR(CURRENT)
485 ;;
486 st8 [temp1]=r12,16 // sal_ra
487 st8 [temp2]=r10,16 // sal_gp
488 mov r12=cr.isr
489 ;;
490 st8 [temp1]=r17,16 // pal_min_state
491 st8 [temp2]=r6,16 // prev_IA64_KR_CURRENT
492 mov r6=cr.ifa
493 ;;
494 st8 [temp1]=r0,16 // prev_task, starts off as NULL
495 st8 [temp2]=r12,16 // cr.isr
496 mov r12=cr.itir
497 ;;
498 st8 [temp1]=r6,16 // cr.ifa
499 st8 [temp2]=r12,16 // cr.itir
500 mov r12=cr.iim
501 ;;
502 st8 [temp1]=r11,16 // cr.iipa
503 st8 [temp2]=r12,16 // cr.iim
504 mov r6=cr.iha
505 (p1) mov r12=IA64_MCA_COLD_BOOT
506 (p2) mov r12=IA64_INIT_WARM_BOOT
507 ;;
508 st8 [temp1]=r6,16 // cr.iha
509 st8 [temp2]=r12 // os_status, default is cold boot
510 mov r6=IA64_MCA_SAME_CONTEXT
511 ;;
512 st8 [temp1]=r6 // context, default is same context
514 // Save the pt_regs data that is not in minstate. The previous code
515 // left regs at sos.
516 add regs=MCA_PT_REGS_OFFSET-MCA_SOS_OFFSET, regs
517 ;;
518 add temp1=PT(B6), regs
519 mov temp3=b6
520 mov temp4=b7
521 add temp2=PT(B7), regs
522 ;;
523 st8 [temp1]=temp3,PT(AR_CSD)-PT(B6) // save b6
524 st8 [temp2]=temp4,PT(AR_SSD)-PT(B7) // save b7
525 mov temp3=ar.csd
526 mov temp4=ar.ssd
527 cover // must be last in group
528 ;;
529 st8 [temp1]=temp3,PT(AR_UNAT)-PT(AR_CSD) // save ar.csd
530 st8 [temp2]=temp4,PT(AR_PFS)-PT(AR_SSD) // save ar.ssd
531 mov temp3=ar.unat
532 mov temp4=ar.pfs
533 ;;
534 st8 [temp1]=temp3,PT(AR_RNAT)-PT(AR_UNAT) // save ar.unat
535 st8 [temp2]=temp4,PT(AR_BSPSTORE)-PT(AR_PFS) // save ar.pfs
536 mov temp3=ar.rnat
537 mov temp4=ar.bspstore
538 ;;
539 st8 [temp1]=temp3,PT(LOADRS)-PT(AR_RNAT) // save ar.rnat
540 st8 [temp2]=temp4,PT(AR_FPSR)-PT(AR_BSPSTORE) // save ar.bspstore
541 mov temp3=ar.bsp
542 ;;
543 sub temp3=temp3, temp4 // ar.bsp - ar.bspstore
544 mov temp4=ar.fpsr
545 ;;
546 shl temp3=temp3,16 // compute ar.rsc to be used for "loadrs"
547 ;;
548 st8 [temp1]=temp3,PT(AR_CCV)-PT(LOADRS) // save loadrs
549 st8 [temp2]=temp4,PT(F6)-PT(AR_FPSR) // save ar.fpsr
550 mov temp3=ar.ccv
551 ;;
552 st8 [temp1]=temp3,PT(F7)-PT(AR_CCV) // save ar.ccv
553 stf.spill [temp2]=f6,PT(F8)-PT(F6)
554 ;;
555 stf.spill [temp1]=f7,PT(F9)-PT(F7)
556 stf.spill [temp2]=f8,PT(F10)-PT(F8)
557 ;;
558 stf.spill [temp1]=f9,PT(F11)-PT(F9)
559 stf.spill [temp2]=f10
560 ;;
561 stf.spill [temp1]=f11
563 // Save the switch_stack data that is not in minstate nor pt_regs. The
564 // previous code left regs at pt_regs.
565 add regs=MCA_SWITCH_STACK_OFFSET-MCA_PT_REGS_OFFSET, regs
566 ;;
567 add temp1=SW(F2), regs
568 add temp2=SW(F3), regs
569 ;;
570 stf.spill [temp1]=f2,32
571 stf.spill [temp2]=f3,32
572 ;;
573 stf.spill [temp1]=f4,32
574 stf.spill [temp2]=f5,32
575 ;;
576 stf.spill [temp1]=f12,32
577 stf.spill [temp2]=f13,32
578 ;;
579 stf.spill [temp1]=f14,32
580 stf.spill [temp2]=f15,32
581 ;;
582 stf.spill [temp1]=f16,32
583 stf.spill [temp2]=f17,32
584 ;;
585 stf.spill [temp1]=f18,32
586 stf.spill [temp2]=f19,32
587 ;;
588 stf.spill [temp1]=f20,32
589 stf.spill [temp2]=f21,32
590 ;;
591 stf.spill [temp1]=f22,32
592 stf.spill [temp2]=f23,32
593 ;;
594 stf.spill [temp1]=f24,32
595 stf.spill [temp2]=f25,32
596 ;;
597 stf.spill [temp1]=f26,32
598 stf.spill [temp2]=f27,32
599 ;;
600 stf.spill [temp1]=f28,32
601 stf.spill [temp2]=f29,32
602 ;;
603 stf.spill [temp1]=f30,SW(B2)-SW(F30)
604 stf.spill [temp2]=f31,SW(B3)-SW(F31)
605 mov temp3=b2
606 mov temp4=b3
607 ;;
608 st8 [temp1]=temp3,16 // save b2
609 st8 [temp2]=temp4,16 // save b3
610 mov temp3=b4
611 mov temp4=b5
612 ;;
613 st8 [temp1]=temp3,SW(AR_LC)-SW(B4) // save b4
614 st8 [temp2]=temp4 // save b5
615 mov temp3=ar.lc
616 ;;
617 st8 [temp1]=temp3 // save ar.lc
619 // FIXME: Some proms are incorrectly accessing the minstate area as
620 // cached data. The C code uses region 6, uncached virtual. Ensure
621 // that there is no cache data lying around for the first 1K of the
622 // minstate area.
623 // Remove this code in September 2006, that gives platforms a year to
624 // fix their proms and get their customers updated.
626 add r1=32*1,r17
627 add r2=32*2,r17
628 add r3=32*3,r17
629 add r4=32*4,r17
630 add r5=32*5,r17
631 add r6=32*6,r17
632 add r7=32*7,r17
633 ;;
634 fc r17
635 fc r1
636 fc r2
637 fc r3
638 fc r4
639 fc r5
640 fc r6
641 fc r7
642 add r17=32*8,r17
643 add r1=32*8,r1
644 add r2=32*8,r2
645 add r3=32*8,r3
646 add r4=32*8,r4
647 add r5=32*8,r5
648 add r6=32*8,r6
649 add r7=32*8,r7
650 ;;
651 fc r17
652 fc r1
653 fc r2
654 fc r3
655 fc r4
656 fc r5
657 fc r6
658 fc r7
659 add r17=32*8,r17
660 add r1=32*8,r1
661 add r2=32*8,r2
662 add r3=32*8,r3
663 add r4=32*8,r4
664 add r5=32*8,r5
665 add r6=32*8,r6
666 add r7=32*8,r7
667 ;;
668 fc r17
669 fc r1
670 fc r2
671 fc r3
672 fc r4
673 fc r5
674 fc r6
675 fc r7
676 add r17=32*8,r17
677 add r1=32*8,r1
678 add r2=32*8,r2
679 add r3=32*8,r3
680 add r4=32*8,r4
681 add r5=32*8,r5
682 add r6=32*8,r6
683 add r7=32*8,r7
684 ;;
685 fc r17
686 fc r1
687 fc r2
688 fc r3
689 fc r4
690 fc r5
691 fc r6
692 fc r7
694 br.sptk b0
696 //EndStub//////////////////////////////////////////////////////////////////////
699 //++
700 // Name:
701 // ia64_state_restore()
702 //
703 // Stub Description:
704 //
705 // Restore the SAL/OS state. This is sensitive to the layout of struct
706 // ia64_sal_os_state in mca.h.
707 //
708 // r2 contains the return address, r3 contains either
709 // IA64_MCA_CPU_MCA_STACK_OFFSET or IA64_MCA_CPU_INIT_STACK_OFFSET.
710 //
711 // In addition to the SAL to OS state, this routine restores all the
712 // registers that appear in struct pt_regs and struct switch_stack,
713 // excluding those in the PAL minstate area.
714 //
715 //--
717 ia64_state_restore:
718 // Restore the switch_stack data that is not in minstate nor pt_regs.
719 add regs=MCA_SWITCH_STACK_OFFSET, r3
720 mov b0=r2 // save return address
721 ;;
722 GET_IA64_MCA_DATA(temp2)
723 ;;
724 add regs=temp2, regs
725 ;;
726 add temp1=SW(F2), regs
727 add temp2=SW(F3), regs
728 ;;
729 ldf.fill f2=[temp1],32
730 ldf.fill f3=[temp2],32
731 ;;
732 ldf.fill f4=[temp1],32
733 ldf.fill f5=[temp2],32
734 ;;
735 ldf.fill f12=[temp1],32
736 ldf.fill f13=[temp2],32
737 ;;
738 ldf.fill f14=[temp1],32
739 ldf.fill f15=[temp2],32
740 ;;
741 ldf.fill f16=[temp1],32
742 ldf.fill f17=[temp2],32
743 ;;
744 ldf.fill f18=[temp1],32
745 ldf.fill f19=[temp2],32
746 ;;
747 ldf.fill f20=[temp1],32
748 ldf.fill f21=[temp2],32
749 ;;
750 ldf.fill f22=[temp1],32
751 ldf.fill f23=[temp2],32
752 ;;
753 ldf.fill f24=[temp1],32
754 ldf.fill f25=[temp2],32
755 ;;
756 ldf.fill f26=[temp1],32
757 ldf.fill f27=[temp2],32
758 ;;
759 ldf.fill f28=[temp1],32
760 ldf.fill f29=[temp2],32
761 ;;
762 ldf.fill f30=[temp1],SW(B2)-SW(F30)
763 ldf.fill f31=[temp2],SW(B3)-SW(F31)
764 ;;
765 ld8 temp3=[temp1],16 // restore b2
766 ld8 temp4=[temp2],16 // restore b3
767 ;;
768 mov b2=temp3
769 mov b3=temp4
770 ld8 temp3=[temp1],SW(AR_LC)-SW(B4) // restore b4
771 ld8 temp4=[temp2] // restore b5
772 ;;
773 mov b4=temp3
774 mov b5=temp4
775 ld8 temp3=[temp1] // restore ar.lc
776 ;;
777 mov ar.lc=temp3
779 // Restore the pt_regs data that is not in minstate. The previous code
780 // left regs at switch_stack.
781 add regs=MCA_PT_REGS_OFFSET-MCA_SWITCH_STACK_OFFSET, regs
782 ;;
783 add temp1=PT(B6), regs
784 add temp2=PT(B7), regs
785 ;;
786 ld8 temp3=[temp1],PT(AR_CSD)-PT(B6) // restore b6
787 ld8 temp4=[temp2],PT(AR_SSD)-PT(B7) // restore b7
788 ;;
789 mov b6=temp3
790 mov b7=temp4
791 ld8 temp3=[temp1],PT(AR_UNAT)-PT(AR_CSD) // restore ar.csd
792 ld8 temp4=[temp2],PT(AR_PFS)-PT(AR_SSD) // restore ar.ssd
793 ;;
794 mov ar.csd=temp3
795 mov ar.ssd=temp4
796 ld8 temp3=[temp1] // restore ar.unat
797 add temp1=PT(AR_CCV)-PT(AR_UNAT), temp1
798 ld8 temp4=[temp2],PT(AR_FPSR)-PT(AR_PFS) // restore ar.pfs
799 ;;
800 mov ar.unat=temp3
801 mov ar.pfs=temp4
802 // ar.rnat, ar.bspstore, loadrs are restore in ia64_old_stack.
803 ld8 temp3=[temp1],PT(F6)-PT(AR_CCV) // restore ar.ccv
804 ld8 temp4=[temp2],PT(F7)-PT(AR_FPSR) // restore ar.fpsr
805 ;;
806 mov ar.ccv=temp3
807 mov ar.fpsr=temp4
808 ldf.fill f6=[temp1],PT(F8)-PT(F6)
809 ldf.fill f7=[temp2],PT(F9)-PT(F7)
810 ;;
811 ldf.fill f8=[temp1],PT(F10)-PT(F8)
812 ldf.fill f9=[temp2],PT(F11)-PT(F9)
813 ;;
814 ldf.fill f10=[temp1]
815 ldf.fill f11=[temp2]
817 // Restore the SAL to OS state. The previous code left regs at pt_regs.
818 add regs=MCA_SOS_OFFSET-MCA_PT_REGS_OFFSET, regs
819 ;;
820 add temp1=IA64_SAL_OS_STATE_COMMON_OFFSET, regs
821 add temp2=IA64_SAL_OS_STATE_COMMON_OFFSET+8, regs
822 ;;
823 ld8 r12=[temp1],16 // sal_ra
824 ld8 r9=[temp2],16 // sal_gp
825 ;;
826 ld8 r22=[temp1],24 // pal_min_state, virtual. skip prev_task
827 ld8 r21=[temp2],16 // prev_IA64_KR_CURRENT
828 ;;
829 ld8 temp3=[temp1],16 // cr.isr
830 ld8 temp4=[temp2],16 // cr.ifa
831 ;;
832 mov cr.isr=temp3
833 mov cr.ifa=temp4
834 ld8 temp3=[temp1],16 // cr.itir
835 ld8 temp4=[temp2],16 // cr.iipa
836 ;;
837 mov cr.itir=temp3
838 mov cr.iipa=temp4
839 ld8 temp3=[temp1],16 // cr.iim
840 ld8 temp4=[temp2],16 // cr.iha
841 ;;
842 mov cr.iim=temp3
843 mov cr.iha=temp4
844 dep r22=0,r22,62,2 // pal_min_state, physical, uncached
845 mov IA64_KR(CURRENT)=r21
846 ld8 r8=[temp1] // os_status
847 ld8 r10=[temp2] // context
849 br.sptk b0
851 //EndStub//////////////////////////////////////////////////////////////////////
854 //++
855 // Name:
856 // ia64_new_stack()
857 //
858 // Stub Description:
859 //
860 // Switch to the MCA/INIT stack.
861 //
862 // r2 contains the return address, r3 contains either
863 // IA64_MCA_CPU_MCA_STACK_OFFSET or IA64_MCA_CPU_INIT_STACK_OFFSET.
864 //
865 // On entry RBS is still on the original stack, this routine switches RBS
866 // to use the MCA/INIT stack.
867 //
868 // On entry, sos->pal_min_state is physical, on exit it is virtual.
869 //
870 //--
872 ia64_new_stack:
873 add regs=MCA_PT_REGS_OFFSET, r3
874 add temp2=MCA_SOS_OFFSET+IA64_SAL_OS_STATE_PAL_MIN_STATE_OFFSET, r3
875 mov b0=r2 // save return address
876 GET_IA64_MCA_DATA(temp1)
877 invala
878 ;;
879 add temp2=temp2, temp1 // struct ia64_sal_os_state.pal_min_state on MCA or INIT stack
880 add regs=regs, temp1 // struct pt_regs on MCA or INIT stack
881 ;;
882 // Address of minstate area provided by PAL is physical, uncacheable.
883 // Convert to Linux virtual address in region 6 for C code.
884 ld8 ms=[temp2] // pal_min_state, physical
885 ;;
886 dep temp1=-1,ms,62,2 // set region 6
887 mov temp3=IA64_RBS_OFFSET-MCA_PT_REGS_OFFSET
888 ;;
889 st8 [temp2]=temp1 // pal_min_state, virtual
891 add temp4=temp3, regs // start of bspstore on new stack
892 ;;
893 mov ar.bspstore=temp4 // switch RBS to MCA/INIT stack
894 ;;
895 flushrs // must be first in group
896 br.sptk b0
898 //EndStub//////////////////////////////////////////////////////////////////////
901 //++
902 // Name:
903 // ia64_old_stack()
904 //
905 // Stub Description:
906 //
907 // Switch to the old stack.
908 //
909 // r2 contains the return address, r3 contains either
910 // IA64_MCA_CPU_MCA_STACK_OFFSET or IA64_MCA_CPU_INIT_STACK_OFFSET.
911 //
912 // On entry, pal_min_state is virtual, on exit it is physical.
913 //
914 // On entry RBS is on the MCA/INIT stack, this routine switches RBS
915 // back to the previous stack.
916 //
917 // The psr is set to all zeroes. SAL return requires either all zeroes or
918 // just psr.mc set. Leaving psr.mc off allows INIT to be issued if this
919 // code does not perform correctly.
920 //
921 // The dirty registers at the time of the event were flushed to the
922 // MCA/INIT stack in ia64_pt_regs_save(). Restore the dirty registers
923 // before reverting to the previous bspstore.
924 //--
926 ia64_old_stack:
927 add regs=MCA_PT_REGS_OFFSET, r3
928 mov b0=r2 // save return address
929 GET_IA64_MCA_DATA(temp2)
930 LOAD_PHYSICAL(p0,temp1,1f)
931 ;;
932 mov cr.ipsr=r0
933 mov cr.ifs=r0
934 mov cr.iip=temp1
935 ;;
936 invala
937 rfi
938 1:
940 add regs=regs, temp2 // struct pt_regs on MCA or INIT stack
941 ;;
942 add temp1=PT(LOADRS), regs
943 ;;
944 ld8 temp2=[temp1],PT(AR_BSPSTORE)-PT(LOADRS) // restore loadrs
945 ;;
946 ld8 temp3=[temp1],PT(AR_RNAT)-PT(AR_BSPSTORE) // restore ar.bspstore
947 mov ar.rsc=temp2
948 ;;
949 loadrs
950 ld8 temp4=[temp1] // restore ar.rnat
951 ;;
952 mov ar.bspstore=temp3 // back to old stack
953 ;;
954 mov ar.rnat=temp4
955 ;;
957 br.sptk b0
959 //EndStub//////////////////////////////////////////////////////////////////////
962 //++
963 // Name:
964 // ia64_set_kernel_registers()
965 //
966 // Stub Description:
967 //
968 // Set the registers that are required by the C code in order to run on an
969 // MCA/INIT stack.
970 //
971 // r2 contains the return address, r3 contains either
972 // IA64_MCA_CPU_MCA_STACK_OFFSET or IA64_MCA_CPU_INIT_STACK_OFFSET.
973 //
974 //--
976 ia64_set_kernel_registers:
977 add temp3=MCA_SP_OFFSET, r3
978 add temp4=MCA_SOS_OFFSET+IA64_SAL_OS_STATE_OS_GP_OFFSET, r3
979 mov b0=r2 // save return address
980 GET_IA64_MCA_DATA(temp1)
981 ;;
982 add temp4=temp4, temp1 // &struct ia64_sal_os_state.os_gp
983 add r12=temp1, temp3 // kernel stack pointer on MCA/INIT stack
984 add r13=temp1, r3 // set current to start of MCA/INIT stack
985 ;;
986 ld8 r1=[temp4] // OS GP from SAL OS state
987 ;;
988 DATA_PA_TO_VA(r1,temp1)
989 DATA_PA_TO_VA(r12,temp2)
990 DATA_PA_TO_VA(r13,temp3)
991 ;;
992 mov IA64_KR(CURRENT)=r13
994 // FIXME: do I need to wire IA64_KR_CURRENT_STACK and IA64_TR_CURRENT_STACK?
996 br.sptk b0
998 //EndStub//////////////////////////////////////////////////////////////////////
1000 #undef ms
1001 #undef regs
1002 #undef temp1
1003 #undef temp2
1004 #undef temp3
1005 #undef temp4
1008 // Support function for mca.c, it is here to avoid using inline asm. Given the
1009 // address of an rnat slot, if that address is below the current ar.bspstore
1010 // then return the contents of that slot, otherwise return the contents of
1011 // ar.rnat.
1012 GLOBAL_ENTRY(ia64_get_rnat)
1013 alloc r14=ar.pfs,1,0,0,0
1014 mov ar.rsc=0
1015 ;;
1016 mov r14=ar.bspstore
1017 ;;
1018 cmp.lt p6,p7=in0,r14
1019 ;;
1020 (p6) ld8 r8=[in0]
1021 (p7) mov r8=ar.rnat
1022 mov ar.rsc=3
1023 br.ret.sptk.many rp
1024 END(ia64_get_rnat)