arch/arm/mach-pxa/pxa3xx.c

   1 /*
   2  * linux/arch/arm/mach-pxa/pxa3xx.c
   3  *
   4  * code specific to pxa3xx aka Monahans
   5  *
   6  * Copyright (C) 2006 Marvell International Ltd.
   7  *
   8  * 2007-09-02: eric miao <eric.miao@marvell.com>
   9  *             initial version
  10  *
  11  * This program is free software; you can redistribute it and/or modify
  12  * it under the terms of the GNU General Public License version 2 as
  13  * published by the Free Software Foundation.
  14  */
  15
  16 #include <linux/module.h>
  17 #include <linux/kernel.h>
  18 #include <linux/init.h>
  19 #include <linux/pm.h>
  20 #include <linux/platform_device.h>
  21 #include <linux/irq.h>
  22 #include <linux/io.h>
  23 #include <linux/sysdev.h>
  24
  25 #include <asm/mach/map.h>
  26 #include <mach/hardware.h>
  27 #include <mach/gpio.h>
  28 #include <mach/pxa3xx-regs.h>
  29 #include <mach/reset.h>
  30 #include <mach/ohci.h>
  31 #include <mach/pm.h>
  32 #include <mach/dma.h>
  33 #include <mach/regs-intc.h>
  34 #include <mach/smemc.h>
  35 #include <plat/i2c.h>
  36
  37 #include "generic.h"
  38 #include "devices.h"
  39 #include "clock.h"
  40
  41 #define PECR_IE(n)      ((1 << ((n) * 2)) << 28)
  42 #define PECR_IS(n)      ((1 << ((n) * 2)) << 29)
  43
  44 void pxa3xx_clear_reset_status(unsigned int mask)
  45 {
  46         /* RESET_STATUS_* has a 1:1 mapping with ARSR */
  47         ARSR = mask;
  48 }
  49
  50 static DEFINE_PXA3_CKEN(pxa3xx_ffuart, FFUART, 14857000, 1);
  51 static DEFINE_PXA3_CKEN(pxa3xx_btuart, BTUART, 14857000, 1);
  52 static DEFINE_PXA3_CKEN(pxa3xx_stuart, STUART, 14857000, 1);
  53 static DEFINE_PXA3_CKEN(pxa3xx_i2c, I2C, 32842000, 0);
  54 static DEFINE_PXA3_CKEN(pxa3xx_udc, UDC, 48000000, 5);
  55 static DEFINE_PXA3_CKEN(pxa3xx_usbh, USBH, 48000000, 0);
  56 static DEFINE_PXA3_CKEN(pxa3xx_u2d, USB2, 48000000, 0);
  57 static DEFINE_PXA3_CKEN(pxa3xx_keypad, KEYPAD, 32768, 0);
  58 static DEFINE_PXA3_CKEN(pxa3xx_ssp1, SSP1, 13000000, 0);
  59 static DEFINE_PXA3_CKEN(pxa3xx_ssp2, SSP2, 13000000, 0);
  60 static DEFINE_PXA3_CKEN(pxa3xx_ssp3, SSP3, 13000000, 0);
  61 static DEFINE_PXA3_CKEN(pxa3xx_ssp4, SSP4, 13000000, 0);
  62 static DEFINE_PXA3_CKEN(pxa3xx_pwm0, PWM0, 13000000, 0);
  63 static DEFINE_PXA3_CKEN(pxa3xx_pwm1, PWM1, 13000000, 0);
  64 static DEFINE_PXA3_CKEN(pxa3xx_mmc1, MMC1, 19500000, 0);
  65 static DEFINE_PXA3_CKEN(pxa3xx_mmc2, MMC2, 19500000, 0);
  66
  67 static DEFINE_CK(pxa3xx_lcd, LCD, &clk_pxa3xx_hsio_ops);
  68 static DEFINE_CK(pxa3xx_camera, CAMERA, &clk_pxa3xx_hsio_ops);
  69 static DEFINE_CK(pxa3xx_ac97, AC97, &clk_pxa3xx_ac97_ops);
  70 static DEFINE_CLK(pxa3xx_pout, &clk_pxa3xx_pout_ops, 13000000, 70);
  71
  72 static struct clk_lookup pxa3xx_clkregs[] = {
  73         INIT_CLKREG(&clk_pxa3xx_pout, NULL, "CLK_POUT"),
  74         /* Power I2C clock is always on */
  75         INIT_CLKREG(&clk_dummy, "pxa3xx-pwri2c.1", NULL),
  76         INIT_CLKREG(&clk_pxa3xx_lcd, "pxa2xx-fb", NULL),
  77         INIT_CLKREG(&clk_pxa3xx_camera, NULL, "CAMCLK"),
  78         INIT_CLKREG(&clk_pxa3xx_ac97, NULL, "AC97CLK"),
  79         INIT_CLKREG(&clk_pxa3xx_ffuart, "pxa2xx-uart.0", NULL),
  80         INIT_CLKREG(&clk_pxa3xx_btuart, "pxa2xx-uart.1", NULL),
  81         INIT_CLKREG(&clk_pxa3xx_stuart, "pxa2xx-uart.2", NULL),
  82         INIT_CLKREG(&clk_pxa3xx_stuart, "pxa2xx-ir", "UARTCLK"),
  83         INIT_CLKREG(&clk_pxa3xx_i2c, "pxa2xx-i2c.0", NULL),
  84         INIT_CLKREG(&clk_pxa3xx_udc, "pxa27x-udc", NULL),
  85         INIT_CLKREG(&clk_pxa3xx_usbh, "pxa27x-ohci", NULL),
  86         INIT_CLKREG(&clk_pxa3xx_u2d, "pxa3xx-u2d", NULL),
  87         INIT_CLKREG(&clk_pxa3xx_keypad, "pxa27x-keypad", NULL),
  88         INIT_CLKREG(&clk_pxa3xx_ssp1, "pxa27x-ssp.0", NULL),
  89         INIT_CLKREG(&clk_pxa3xx_ssp2, "pxa27x-ssp.1", NULL),
  90         INIT_CLKREG(&clk_pxa3xx_ssp3, "pxa27x-ssp.2", NULL),
  91         INIT_CLKREG(&clk_pxa3xx_ssp4, "pxa27x-ssp.3", NULL),
  92         INIT_CLKREG(&clk_pxa3xx_pwm0, "pxa27x-pwm.0", NULL),
  93         INIT_CLKREG(&clk_pxa3xx_pwm1, "pxa27x-pwm.1", NULL),
  94         INIT_CLKREG(&clk_pxa3xx_mmc1, "pxa2xx-mci.0", NULL),
  95         INIT_CLKREG(&clk_pxa3xx_mmc2, "pxa2xx-mci.1", NULL),
  96 };
  97
  98 #ifdef CONFIG_PM
  99
 100 #define ISRAM_START     0x5c000000
 101 #define ISRAM_SIZE      SZ_256K
 102
 103 static void __iomem *sram;
 104 static unsigned long wakeup_src;
 105
 106 #define SAVE(x)         sleep_save[SLEEP_SAVE_##x] = x
 107 #define RESTORE(x)      x = sleep_save[SLEEP_SAVE_##x]
 108
 109 enum {  SLEEP_SAVE_CKENA,
 110         SLEEP_SAVE_CKENB,
 111         SLEEP_SAVE_ACCR,
 112
 113         SLEEP_SAVE_COUNT,
 114 };
 115
 116 static void pxa3xx_cpu_pm_save(unsigned long *sleep_save)
 117 {
 118         SAVE(CKENA);
 119         SAVE(CKENB);
 120         SAVE(ACCR);
 121 }
 122
 123 static void pxa3xx_cpu_pm_restore(unsigned long *sleep_save)
 124 {
 125         RESTORE(ACCR);
 126         RESTORE(CKENA);
 127         RESTORE(CKENB);
 128 }
 129
 130 /*
 131  * Enter a standby mode (S0D1C2 or S0D2C2).  Upon wakeup, the dynamic
 132  * memory controller has to be reinitialised, so we place some code
 133  * in the SRAM to perform this function.
 134  *
 135  * We disable FIQs across the standby - otherwise, we might receive a
 136  * FIQ while the SDRAM is unavailable.
 137  */
 138 static void pxa3xx_cpu_standby(unsigned int pwrmode)
 139 {
 140         extern const char pm_enter_standby_start[], pm_enter_standby_end[];
 141         void (*fn)(unsigned int) = (void __force *)(sram + 0x8000);
 142
 143         memcpy_toio(sram + 0x8000, pm_enter_standby_start,
 144                     pm_enter_standby_end - pm_enter_standby_start);
 145
 146         AD2D0SR = ~0;
 147         AD2D1SR = ~0;
 148         AD2D0ER = wakeup_src;
 149         AD2D1ER = 0;
 150         ASCR = ASCR;
 151         ARSR = ARSR;
 152
 153         local_fiq_disable();
 154         fn(pwrmode);
 155         local_fiq_enable();
 156
 157         AD2D0ER = 0;
 158         AD2D1ER = 0;
 159 }
 160
 161 /*
 162  * NOTE:  currently, the OBM (OEM Boot Module) binary comes along with
 163  * PXA3xx development kits assumes that the resuming process continues
 164  * with the address stored within the first 4 bytes of SDRAM. The PSPR
 165  * register is used privately by BootROM and OBM, and _must_ be set to
 166  * 0x5c014000 for the moment.
 167  */
 168 static void pxa3xx_cpu_pm_suspend(void)
 169 {
 170         volatile unsigned long *p = (volatile void *)0xc0000000;
 171         unsigned long saved_data = *p;
 172
 173         extern void pxa3xx_cpu_suspend(void);
 174         extern void pxa3xx_cpu_resume(void);
 175
 176         /* resuming from D2 requires the HSIO2/BOOT/TPM clocks enabled */
 177         CKENA |= (1 << CKEN_BOOT) | (1 << CKEN_TPM);
 178         CKENB |= 1 << (CKEN_HSIO2 & 0x1f);
 179
 180         /* clear and setup wakeup source */
 181         AD3SR = ~0;
 182         AD3ER = wakeup_src;
 183         ASCR = ASCR;
 184         ARSR = ARSR;
 185
 186         PCFR |= (1u << 13);                     /* L1_DIS */
 187         PCFR &= ~((1u << 12) | (1u << 1));      /* L0_EN | SL_ROD */
 188
 189         PSPR = 0x5c014000;
 190
 191         /* overwrite with the resume address */
 192         *p = virt_to_phys(pxa3xx_cpu_resume);
 193
 194         pxa3xx_cpu_suspend();
 195
 196         *p = saved_data;
 197
 198         AD3ER = 0;
 199 }
 200
 201 static void pxa3xx_cpu_pm_enter(suspend_state_t state)
 202 {
 203         /*
 204          * Don't sleep if no wakeup sources are defined
 205          */
 206         if (wakeup_src == 0) {
 207                 printk(KERN_ERR "Not suspending: no wakeup sources\n");
 208                 return;
 209         }
 210
 211         switch (state) {
 212         case PM_SUSPEND_STANDBY:
 213                 pxa3xx_cpu_standby(PXA3xx_PM_S0D2C2);
 214                 break;
 215
 216         case PM_SUSPEND_MEM:
 217                 pxa3xx_cpu_pm_suspend();
 218                 break;
 219         }
 220 }
 221
 222 static int pxa3xx_cpu_pm_valid(suspend_state_t state)
 223 {
 224         return state == PM_SUSPEND_MEM || state == PM_SUSPEND_STANDBY;
 225 }
 226
 227 static struct pxa_cpu_pm_fns pxa3xx_cpu_pm_fns = {
 228         .save_count     = SLEEP_SAVE_COUNT,
 229         .save           = pxa3xx_cpu_pm_save,
 230         .restore        = pxa3xx_cpu_pm_restore,
 231         .valid          = pxa3xx_cpu_pm_valid,
 232         .enter          = pxa3xx_cpu_pm_enter,
 233 };
 234
 235 static void __init pxa3xx_init_pm(void)
 236 {
 237         sram = ioremap(ISRAM_START, ISRAM_SIZE);
 238         if (!sram) {
 239                 printk(KERN_ERR "Unable to map ISRAM: disabling standby/suspend\n");
 240                 return;
 241         }
 242
 243         /*
 244          * Since we copy wakeup code into the SRAM, we need to ensure
 245          * that it is preserved over the low power modes.  Note: bit 8
 246          * is undocumented in the developer manual, but must be set.
 247          */
 248         AD1R |= ADXR_L2 | ADXR_R0;
 249         AD2R |= ADXR_L2 | ADXR_R0;
 250         AD3R |= ADXR_L2 | ADXR_R0;
 251
 252         /*
 253          * Clear the resume enable registers.
 254          */
 255         AD1D0ER = 0;
 256         AD2D0ER = 0;
 257         AD2D1ER = 0;
 258         AD3ER = 0;
 259
 260         pxa_cpu_pm_fns = &pxa3xx_cpu_pm_fns;
 261 }
 262
 263 static int pxa3xx_set_wake(unsigned int irq, unsigned int on)
 264 {
 265         unsigned long flags, mask = 0;
 266
 267         switch (irq) {
 268         case IRQ_SSP3:
 269                 mask = ADXER_MFP_WSSP3;
 270                 break;
 271         case IRQ_MSL:
 272                 mask = ADXER_WMSL0;
 273                 break;
 274         case IRQ_USBH2:
 275         case IRQ_USBH1:
 276                 mask = ADXER_WUSBH;
 277                 break;
 278         case IRQ_KEYPAD:
 279                 mask = ADXER_WKP;
 280                 break;
 281         case IRQ_AC97:
 282                 mask = ADXER_MFP_WAC97;
 283                 break;
 284         case IRQ_USIM:
 285                 mask = ADXER_WUSIM0;
 286                 break;
 287         case IRQ_SSP2:
 288                 mask = ADXER_MFP_WSSP2;
 289                 break;
 290         case IRQ_I2C:
 291                 mask = ADXER_MFP_WI2C;
 292                 break;
 293         case IRQ_STUART:
 294                 mask = ADXER_MFP_WUART3;
 295                 break;
 296         case IRQ_BTUART:
 297                 mask = ADXER_MFP_WUART2;
 298                 break;
 299         case IRQ_FFUART:
 300                 mask = ADXER_MFP_WUART1;
 301                 break;
 302         case IRQ_MMC:
 303                 mask = ADXER_MFP_WMMC1;
 304                 break;
 305         case IRQ_SSP:
 306                 mask = ADXER_MFP_WSSP1;
 307                 break;
 308         case IRQ_RTCAlrm:
 309                 mask = ADXER_WRTC;
 310                 break;
 311         case IRQ_SSP4:
 312                 mask = ADXER_MFP_WSSP4;
 313                 break;
 314         case IRQ_TSI:
 315                 mask = ADXER_WTSI;
 316                 break;
 317         case IRQ_USIM2:
 318                 mask = ADXER_WUSIM1;
 319                 break;
 320         case IRQ_MMC2:
 321                 mask = ADXER_MFP_WMMC2;
 322                 break;
 323         case IRQ_NAND:
 324                 mask = ADXER_MFP_WFLASH;
 325                 break;
 326         case IRQ_USB2:
 327                 mask = ADXER_WUSB2;
 328                 break;
 329         case IRQ_WAKEUP0:
 330                 mask = ADXER_WEXTWAKE0;
 331                 break;
 332         case IRQ_WAKEUP1:
 333                 mask = ADXER_WEXTWAKE1;
 334                 break;
 335         case IRQ_MMC3:
 336                 mask = ADXER_MFP_GEN12;
 337                 break;
 338         default:
 339                 return -EINVAL;
 340         }
 341
 342         local_irq_save(flags);
 343         if (on)
 344                 wakeup_src |= mask;
 345         else
 346                 wakeup_src &= ~mask;
 347         local_irq_restore(flags);
 348
 349         return 0;
 350 }
 351 #else
 352 static inline void pxa3xx_init_pm(void) {}
 353 #define pxa3xx_set_wake NULL
 354 #endif
 355
 356 static void pxa_ack_ext_wakeup(unsigned int irq)
 357 {
 358         PECR |= PECR_IS(irq - IRQ_WAKEUP0);
 359 }
 360
 361 static void pxa_mask_ext_wakeup(unsigned int irq)
 362 {
 363         ICMR2 &= ~(1 << ((irq - PXA_IRQ(0)) & 0x1f));
 364         PECR &= ~PECR_IE(irq - IRQ_WAKEUP0);
 365 }
 366
 367 static void pxa_unmask_ext_wakeup(unsigned int irq)
 368 {
 369         ICMR2 |= 1 << ((irq - PXA_IRQ(0)) & 0x1f);
 370         PECR |= PECR_IE(irq - IRQ_WAKEUP0);
 371 }
 372
 373 static int pxa_set_ext_wakeup_type(unsigned int irq, unsigned int flow_type)
 374 {
 375         if (flow_type & IRQ_TYPE_EDGE_RISING)
 376                 PWER |= 1 << (irq - IRQ_WAKEUP0);
 377
 378         if (flow_type & IRQ_TYPE_EDGE_FALLING)
 379                 PWER |= 1 << (irq - IRQ_WAKEUP0 + 2);
 380
 381         return 0;
 382 }
 383
 384 static struct irq_chip pxa_ext_wakeup_chip = {
 385         .name           = "WAKEUP",
 386         .ack            = pxa_ack_ext_wakeup,
 387         .mask           = pxa_mask_ext_wakeup,
 388         .unmask         = pxa_unmask_ext_wakeup,
 389         .set_type       = pxa_set_ext_wakeup_type,
 390 };
 391
 392 static void __init pxa_init_ext_wakeup_irq(set_wake_t fn)
 393 {
 394         int irq;
 395
 396         for (irq = IRQ_WAKEUP0; irq <= IRQ_WAKEUP1; irq++) {
 397                 set_irq_chip(irq, &pxa_ext_wakeup_chip);
 398                 set_irq_handler(irq, handle_edge_irq);
 399                 set_irq_flags(irq, IRQF_VALID);
 400         }
 401
 402         pxa_ext_wakeup_chip.set_wake = fn;
 403 }
 404
 405 void __init pxa3xx_init_irq(void)
 406 {
 407         /* enable CP6 access */
 408         u32 value;
 409         __asm__ __volatile__("mrc p15, 0, %0, c15, c1, 0\n": "=r"(value));
 410         value |= (1 << 6);
 411         __asm__ __volatile__("mcr p15, 0, %0, c15, c1, 0\n": :"r"(value));
 412
 413         pxa_init_irq(56, pxa3xx_set_wake);
 414         pxa_init_ext_wakeup_irq(pxa3xx_set_wake);
 415         pxa_init_gpio(IRQ_GPIO_2_x, 2, 127, NULL);
 416 }
 417
 418 static struct map_desc pxa3xx_io_desc[] __initdata = {
 419         {       /* Mem Ctl */
 420                 .virtual        = SMEMC_VIRT,
 421                 .pfn            = __phys_to_pfn(PXA3XX_SMEMC_BASE),
 422                 .length         = 0x00200000,
 423                 .type           = MT_DEVICE
 424         }
 425 };
 426
 427 void __init pxa3xx_map_io(void)
 428 {
 429         pxa_map_io();
 430         iotable_init(ARRAY_AND_SIZE(pxa3xx_io_desc));
 431         pxa3xx_get_clk_frequency_khz(1);
 432 }
 433
 434 /*
 435  * device registration specific to PXA3xx.
 436  */
 437
 438 void __init pxa3xx_set_i2c_power_info(struct i2c_pxa_platform_data *info)
 439 {
 440         pxa_register_device(&pxa3xx_device_i2c_power, info);
 441 }
 442
 443 static struct platform_device *devices[] __initdata = {
 444         &pxa27x_device_udc,
 445         &pxa_device_pmu,
 446         &pxa_device_i2s,
 447         &pxa_device_asoc_ssp1,
 448         &pxa_device_asoc_ssp2,
 449         &pxa_device_asoc_ssp3,
 450         &pxa_device_asoc_ssp4,
 451         &pxa_device_asoc_platform,
 452         &sa1100_device_rtc,
 453         &pxa_device_rtc,
 454         &pxa27x_device_ssp1,
 455         &pxa27x_device_ssp2,
 456         &pxa27x_device_ssp3,
 457         &pxa3xx_device_ssp4,
 458         &pxa27x_device_pwm0,
 459         &pxa27x_device_pwm1,
 460 };
 461
 462 static struct sys_device pxa3xx_sysdev[] = {
 463         {
 464                 .cls    = &pxa_irq_sysclass,
 465         }, {
 466                 .cls    = &pxa3xx_mfp_sysclass,
 467         }, {
 468                 .cls    = &pxa_gpio_sysclass,
 469         },
 470 };
 471
 472 static int __init pxa3xx_init(void)
 473 {
 474         int i, ret = 0;
 475
 476         if (cpu_is_pxa3xx()) {
 477
 478                 reset_status = ARSR;
 479
 480                 /*
 481                  * clear RDH bit every time after reset
 482                  *
 483                  * Note: the last 3 bits DxS are write-1-to-clear so carefully
 484                  * preserve them here in case they will be referenced later
 485                  */
 486                 ASCR &= ~(ASCR_RDH | ASCR_D1S | ASCR_D2S | ASCR_D3S);
 487
 488                 clkdev_add_table(pxa3xx_clkregs, ARRAY_SIZE(pxa3xx_clkregs));
 489
 490                 if ((ret = pxa_init_dma(IRQ_DMA, 32)))
 491                         return ret;
 492
 493                 pxa3xx_init_pm();
 494
 495                 for (i = 0; i < ARRAY_SIZE(pxa3xx_sysdev); i++) {
 496                         ret = sysdev_register(&pxa3xx_sysdev[i]);
 497                         if (ret)
 498                                 pr_err("failed to register sysdev[%d]\n", i);
 499                 }
 500
 501                 ret = platform_add_devices(devices, ARRAY_SIZE(devices));
 502         }
 503
 504         return ret;
 505 }
 506
 507 postcore_initcall(pxa3xx_init);