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Merge tags 'omap-cleanup-for-v3.6', 'omap-devel-dmtimer-for-v3.6' and 'omap-devel...
[linux-2.6.git] / arch / arm / mach-omap2 / omap_hwmod_3xxx_data.c
blob6491e057d9ce72676157fd2f3a06f816c2724a05
1 /*
2 * omap_hwmod_3xxx_data.c - hardware modules present on the OMAP3xxx chips
3 *
4 * Copyright (C) 2009-2011 Nokia Corporation
5 * Copyright (C) 2012 Texas Instruments, Inc.
6 * Paul Walmsley
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 *
12 * The data in this file should be completely autogeneratable from
13 * the TI hardware database or other technical documentation.
14 *
15 * XXX these should be marked initdata for multi-OMAP kernels
16 */
17 #include <plat/omap_hwmod.h>
18 #include <mach/irqs.h>
19 #include <plat/cpu.h>
20 #include <plat/dma.h>
21 #include <plat/serial.h>
22 #include <plat/l3_3xxx.h>
23 #include <plat/l4_3xxx.h>
24 #include <plat/i2c.h>
25 #include <plat/gpio.h>
26 #include <plat/mmc.h>
27 #include <plat/mcbsp.h>
28 #include <plat/mcspi.h>
29 #include <plat/dmtimer.h>
30
31 #include "omap_hwmod_common_data.h"
32
33 #include "smartreflex.h"
34 #include "prm-regbits-34xx.h"
35 #include "cm-regbits-34xx.h"
36 #include "wd_timer.h"
37 #include <mach/am35xx.h>
38
39 /*
40 * OMAP3xxx hardware module integration data
41 *
42 * All of the data in this section should be autogeneratable from the
43 * TI hardware database or other technical documentation. Data that
44 * is driver-specific or driver-kernel integration-specific belongs
45 * elsewhere.
46 */
47
48 /*
49 * IP blocks
50 */
51
52 /* L3 */
53 static struct omap_hwmod_irq_info omap3xxx_l3_main_irqs[] = {
54 { .irq = INT_34XX_L3_DBG_IRQ },
55 { .irq = INT_34XX_L3_APP_IRQ },
56 { .irq = -1 }
57 };
58
59 static struct omap_hwmod omap3xxx_l3_main_hwmod = {
60 .name = "l3_main",
61 .class = &l3_hwmod_class,
62 .mpu_irqs = omap3xxx_l3_main_irqs,
63 .flags = HWMOD_NO_IDLEST,
64 };
65
66 /* L4 CORE */
67 static struct omap_hwmod omap3xxx_l4_core_hwmod = {
68 .name = "l4_core",
69 .class = &l4_hwmod_class,
70 .flags = HWMOD_NO_IDLEST,
71 };
72
73 /* L4 PER */
74 static struct omap_hwmod omap3xxx_l4_per_hwmod = {
75 .name = "l4_per",
76 .class = &l4_hwmod_class,
77 .flags = HWMOD_NO_IDLEST,
78 };
79
80 /* L4 WKUP */
81 static struct omap_hwmod omap3xxx_l4_wkup_hwmod = {
82 .name = "l4_wkup",
83 .class = &l4_hwmod_class,
84 .flags = HWMOD_NO_IDLEST,
85 };
86
87 /* L4 SEC */
88 static struct omap_hwmod omap3xxx_l4_sec_hwmod = {
89 .name = "l4_sec",
90 .class = &l4_hwmod_class,
91 .flags = HWMOD_NO_IDLEST,
92 };
93
94 /* MPU */
95 static struct omap_hwmod omap3xxx_mpu_hwmod = {
96 .name = "mpu",
97 .class = &mpu_hwmod_class,
98 .main_clk = "arm_fck",
99 };
100
101 /* IVA2 (IVA2) */
102 static struct omap_hwmod_rst_info omap3xxx_iva_resets[] = {
103 { .name = "logic", .rst_shift = 0 },
104 { .name = "seq0", .rst_shift = 1 },
105 { .name = "seq1", .rst_shift = 2 },
106 };
107
108 static struct omap_hwmod omap3xxx_iva_hwmod = {
109 .name = "iva",
110 .class = &iva_hwmod_class,
111 .clkdm_name = "iva2_clkdm",
112 .rst_lines = omap3xxx_iva_resets,
113 .rst_lines_cnt = ARRAY_SIZE(omap3xxx_iva_resets),
114 .main_clk = "iva2_ck",
115 };
116
117 /* timer class */
118 static struct omap_hwmod_class_sysconfig omap3xxx_timer_1ms_sysc = {
119 .rev_offs = 0x0000,
120 .sysc_offs = 0x0010,
121 .syss_offs = 0x0014,
122 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_CLOCKACTIVITY |
123 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
124 SYSC_HAS_EMUFREE | SYSC_HAS_AUTOIDLE),
125 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
126 .sysc_fields = &omap_hwmod_sysc_type1,
127 };
128
129 static struct omap_hwmod_class omap3xxx_timer_1ms_hwmod_class = {
130 .name = "timer",
131 .sysc = &omap3xxx_timer_1ms_sysc,
132 };
133
134 static struct omap_hwmod_class_sysconfig omap3xxx_timer_sysc = {
135 .rev_offs = 0x0000,
136 .sysc_offs = 0x0010,
137 .syss_offs = 0x0014,
138 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_ENAWAKEUP |
139 SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
140 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
141 .sysc_fields = &omap_hwmod_sysc_type1,
142 };
143
144 static struct omap_hwmod_class omap3xxx_timer_hwmod_class = {
145 .name = "timer",
146 .sysc = &omap3xxx_timer_sysc,
147 };
148
149 /* secure timers dev attribute */
150 static struct omap_timer_capability_dev_attr capability_secure_dev_attr = {
151 .timer_capability = OMAP_TIMER_ALWON | OMAP_TIMER_SECURE,
152 };
153
154 /* always-on timers dev attribute */
155 static struct omap_timer_capability_dev_attr capability_alwon_dev_attr = {
156 .timer_capability = OMAP_TIMER_ALWON,
157 };
158
159 /* pwm timers dev attribute */
160 static struct omap_timer_capability_dev_attr capability_pwm_dev_attr = {
161 .timer_capability = OMAP_TIMER_HAS_PWM,
162 };
163
164 /* timer1 */
165 static struct omap_hwmod omap3xxx_timer1_hwmod = {
166 .name = "timer1",
167 .mpu_irqs = omap2_timer1_mpu_irqs,
168 .main_clk = "gpt1_fck",
169 .prcm = {
170 .omap2 = {
171 .prcm_reg_id = 1,
172 .module_bit = OMAP3430_EN_GPT1_SHIFT,
173 .module_offs = WKUP_MOD,
174 .idlest_reg_id = 1,
175 .idlest_idle_bit = OMAP3430_ST_GPT1_SHIFT,
176 },
177 },
178 .dev_attr = &capability_alwon_dev_attr,
179 .class = &omap3xxx_timer_1ms_hwmod_class,
180 };
181
182 /* timer2 */
183 static struct omap_hwmod omap3xxx_timer2_hwmod = {
184 .name = "timer2",
185 .mpu_irqs = omap2_timer2_mpu_irqs,
186 .main_clk = "gpt2_fck",
187 .prcm = {
188 .omap2 = {
189 .prcm_reg_id = 1,
190 .module_bit = OMAP3430_EN_GPT2_SHIFT,
191 .module_offs = OMAP3430_PER_MOD,
192 .idlest_reg_id = 1,
193 .idlest_idle_bit = OMAP3430_ST_GPT2_SHIFT,
194 },
195 },
196 .class = &omap3xxx_timer_1ms_hwmod_class,
197 };
198
199 /* timer3 */
200 static struct omap_hwmod omap3xxx_timer3_hwmod = {
201 .name = "timer3",
202 .mpu_irqs = omap2_timer3_mpu_irqs,
203 .main_clk = "gpt3_fck",
204 .prcm = {
205 .omap2 = {
206 .prcm_reg_id = 1,
207 .module_bit = OMAP3430_EN_GPT3_SHIFT,
208 .module_offs = OMAP3430_PER_MOD,
209 .idlest_reg_id = 1,
210 .idlest_idle_bit = OMAP3430_ST_GPT3_SHIFT,
211 },
212 },
213 .class = &omap3xxx_timer_hwmod_class,
214 };
215
216 /* timer4 */
217 static struct omap_hwmod omap3xxx_timer4_hwmod = {
218 .name = "timer4",
219 .mpu_irqs = omap2_timer4_mpu_irqs,
220 .main_clk = "gpt4_fck",
221 .prcm = {
222 .omap2 = {
223 .prcm_reg_id = 1,
224 .module_bit = OMAP3430_EN_GPT4_SHIFT,
225 .module_offs = OMAP3430_PER_MOD,
226 .idlest_reg_id = 1,
227 .idlest_idle_bit = OMAP3430_ST_GPT4_SHIFT,
228 },
229 },
230 .class = &omap3xxx_timer_hwmod_class,
231 };
232
233 /* timer5 */
234 static struct omap_hwmod omap3xxx_timer5_hwmod = {
235 .name = "timer5",
236 .mpu_irqs = omap2_timer5_mpu_irqs,
237 .main_clk = "gpt5_fck",
238 .prcm = {
239 .omap2 = {
240 .prcm_reg_id = 1,
241 .module_bit = OMAP3430_EN_GPT5_SHIFT,
242 .module_offs = OMAP3430_PER_MOD,
243 .idlest_reg_id = 1,
244 .idlest_idle_bit = OMAP3430_ST_GPT5_SHIFT,
245 },
246 },
247 .class = &omap3xxx_timer_hwmod_class,
248 };
249
250 /* timer6 */
251 static struct omap_hwmod omap3xxx_timer6_hwmod = {
252 .name = "timer6",
253 .mpu_irqs = omap2_timer6_mpu_irqs,
254 .main_clk = "gpt6_fck",
255 .prcm = {
256 .omap2 = {
257 .prcm_reg_id = 1,
258 .module_bit = OMAP3430_EN_GPT6_SHIFT,
259 .module_offs = OMAP3430_PER_MOD,
260 .idlest_reg_id = 1,
261 .idlest_idle_bit = OMAP3430_ST_GPT6_SHIFT,
262 },
263 },
264 .class = &omap3xxx_timer_hwmod_class,
265 };
266
267 /* timer7 */
268 static struct omap_hwmod omap3xxx_timer7_hwmod = {
269 .name = "timer7",
270 .mpu_irqs = omap2_timer7_mpu_irqs,
271 .main_clk = "gpt7_fck",
272 .prcm = {
273 .omap2 = {
274 .prcm_reg_id = 1,
275 .module_bit = OMAP3430_EN_GPT7_SHIFT,
276 .module_offs = OMAP3430_PER_MOD,
277 .idlest_reg_id = 1,
278 .idlest_idle_bit = OMAP3430_ST_GPT7_SHIFT,
279 },
280 },
281 .class = &omap3xxx_timer_hwmod_class,
282 };
283
284 /* timer8 */
285 static struct omap_hwmod omap3xxx_timer8_hwmod = {
286 .name = "timer8",
287 .mpu_irqs = omap2_timer8_mpu_irqs,
288 .main_clk = "gpt8_fck",
289 .prcm = {
290 .omap2 = {
291 .prcm_reg_id = 1,
292 .module_bit = OMAP3430_EN_GPT8_SHIFT,
293 .module_offs = OMAP3430_PER_MOD,
294 .idlest_reg_id = 1,
295 .idlest_idle_bit = OMAP3430_ST_GPT8_SHIFT,
296 },
297 },
298 .dev_attr = &capability_pwm_dev_attr,
299 .class = &omap3xxx_timer_hwmod_class,
300 };
301
302 /* timer9 */
303 static struct omap_hwmod omap3xxx_timer9_hwmod = {
304 .name = "timer9",
305 .mpu_irqs = omap2_timer9_mpu_irqs,
306 .main_clk = "gpt9_fck",
307 .prcm = {
308 .omap2 = {
309 .prcm_reg_id = 1,
310 .module_bit = OMAP3430_EN_GPT9_SHIFT,
311 .module_offs = OMAP3430_PER_MOD,
312 .idlest_reg_id = 1,
313 .idlest_idle_bit = OMAP3430_ST_GPT9_SHIFT,
314 },
315 },
316 .dev_attr = &capability_pwm_dev_attr,
317 .class = &omap3xxx_timer_hwmod_class,
318 };
319
320 /* timer10 */
321 static struct omap_hwmod omap3xxx_timer10_hwmod = {
322 .name = "timer10",
323 .mpu_irqs = omap2_timer10_mpu_irqs,
324 .main_clk = "gpt10_fck",
325 .prcm = {
326 .omap2 = {
327 .prcm_reg_id = 1,
328 .module_bit = OMAP3430_EN_GPT10_SHIFT,
329 .module_offs = CORE_MOD,
330 .idlest_reg_id = 1,
331 .idlest_idle_bit = OMAP3430_ST_GPT10_SHIFT,
332 },
333 },
334 .dev_attr = &capability_pwm_dev_attr,
335 .class = &omap3xxx_timer_1ms_hwmod_class,
336 };
337
338 /* timer11 */
339 static struct omap_hwmod omap3xxx_timer11_hwmod = {
340 .name = "timer11",
341 .mpu_irqs = omap2_timer11_mpu_irqs,
342 .main_clk = "gpt11_fck",
343 .prcm = {
344 .omap2 = {
345 .prcm_reg_id = 1,
346 .module_bit = OMAP3430_EN_GPT11_SHIFT,
347 .module_offs = CORE_MOD,
348 .idlest_reg_id = 1,
349 .idlest_idle_bit = OMAP3430_ST_GPT11_SHIFT,
350 },
351 },
352 .dev_attr = &capability_pwm_dev_attr,
353 .class = &omap3xxx_timer_hwmod_class,
354 };
355
356 /* timer12 */
357 static struct omap_hwmod_irq_info omap3xxx_timer12_mpu_irqs[] = {
358 { .irq = 95, },
359 { .irq = -1 }
360 };
361
362 static struct omap_hwmod omap3xxx_timer12_hwmod = {
363 .name = "timer12",
364 .mpu_irqs = omap3xxx_timer12_mpu_irqs,
365 .main_clk = "gpt12_fck",
366 .prcm = {
367 .omap2 = {
368 .prcm_reg_id = 1,
369 .module_bit = OMAP3430_EN_GPT12_SHIFT,
370 .module_offs = WKUP_MOD,
371 .idlest_reg_id = 1,
372 .idlest_idle_bit = OMAP3430_ST_GPT12_SHIFT,
373 },
374 },
375 .dev_attr = &capability_secure_dev_attr,
376 .class = &omap3xxx_timer_hwmod_class,
377 };
378
379 /*
380 * 'wd_timer' class
381 * 32-bit watchdog upward counter that generates a pulse on the reset pin on
382 * overflow condition
383 */
384
385 static struct omap_hwmod_class_sysconfig omap3xxx_wd_timer_sysc = {
386 .rev_offs = 0x0000,
387 .sysc_offs = 0x0010,
388 .syss_offs = 0x0014,
389 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_EMUFREE |
390 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
391 SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
392 SYSS_HAS_RESET_STATUS),
393 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
394 .sysc_fields = &omap_hwmod_sysc_type1,
395 };
396
397 /* I2C common */
398 static struct omap_hwmod_class_sysconfig i2c_sysc = {
399 .rev_offs = 0x00,
400 .sysc_offs = 0x20,
401 .syss_offs = 0x10,
402 .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
403 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
404 SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
405 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
406 .clockact = CLOCKACT_TEST_ICLK,
407 .sysc_fields = &omap_hwmod_sysc_type1,
408 };
409
410 static struct omap_hwmod_class omap3xxx_wd_timer_hwmod_class = {
411 .name = "wd_timer",
412 .sysc = &omap3xxx_wd_timer_sysc,
413 .pre_shutdown = &omap2_wd_timer_disable,
414 .reset = &omap2_wd_timer_reset,
415 };
416
417 static struct omap_hwmod omap3xxx_wd_timer2_hwmod = {
418 .name = "wd_timer2",
419 .class = &omap3xxx_wd_timer_hwmod_class,
420 .main_clk = "wdt2_fck",
421 .prcm = {
422 .omap2 = {
423 .prcm_reg_id = 1,
424 .module_bit = OMAP3430_EN_WDT2_SHIFT,
425 .module_offs = WKUP_MOD,
426 .idlest_reg_id = 1,
427 .idlest_idle_bit = OMAP3430_ST_WDT2_SHIFT,
428 },
429 },
430 /*
431 * XXX: Use software supervised mode, HW supervised smartidle seems to
432 * block CORE power domain idle transitions. Maybe a HW bug in wdt2?
433 */
434 .flags = HWMOD_SWSUP_SIDLE,
435 };
436
437 /* UART1 */
438 static struct omap_hwmod omap3xxx_uart1_hwmod = {
439 .name = "uart1",
440 .mpu_irqs = omap2_uart1_mpu_irqs,
441 .sdma_reqs = omap2_uart1_sdma_reqs,
442 .main_clk = "uart1_fck",
443 .prcm = {
444 .omap2 = {
445 .module_offs = CORE_MOD,
446 .prcm_reg_id = 1,
447 .module_bit = OMAP3430_EN_UART1_SHIFT,
448 .idlest_reg_id = 1,
449 .idlest_idle_bit = OMAP3430_EN_UART1_SHIFT,
450 },
451 },
452 .class = &omap2_uart_class,
453 };
454
455 /* UART2 */
456 static struct omap_hwmod omap3xxx_uart2_hwmod = {
457 .name = "uart2",
458 .mpu_irqs = omap2_uart2_mpu_irqs,
459 .sdma_reqs = omap2_uart2_sdma_reqs,
460 .main_clk = "uart2_fck",
461 .prcm = {
462 .omap2 = {
463 .module_offs = CORE_MOD,
464 .prcm_reg_id = 1,
465 .module_bit = OMAP3430_EN_UART2_SHIFT,
466 .idlest_reg_id = 1,
467 .idlest_idle_bit = OMAP3430_EN_UART2_SHIFT,
468 },
469 },
470 .class = &omap2_uart_class,
471 };
472
473 /* UART3 */
474 static struct omap_hwmod omap3xxx_uart3_hwmod = {
475 .name = "uart3",
476 .mpu_irqs = omap2_uart3_mpu_irqs,
477 .sdma_reqs = omap2_uart3_sdma_reqs,
478 .main_clk = "uart3_fck",
479 .prcm = {
480 .omap2 = {
481 .module_offs = OMAP3430_PER_MOD,
482 .prcm_reg_id = 1,
483 .module_bit = OMAP3430_EN_UART3_SHIFT,
484 .idlest_reg_id = 1,
485 .idlest_idle_bit = OMAP3430_EN_UART3_SHIFT,
486 },
487 },
488 .class = &omap2_uart_class,
489 };
490
491 /* UART4 */
492 static struct omap_hwmod_irq_info uart4_mpu_irqs[] = {
493 { .irq = INT_36XX_UART4_IRQ, },
494 { .irq = -1 }
495 };
496
497 static struct omap_hwmod_dma_info uart4_sdma_reqs[] = {
498 { .name = "rx", .dma_req = OMAP36XX_DMA_UART4_RX, },
499 { .name = "tx", .dma_req = OMAP36XX_DMA_UART4_TX, },
500 { .dma_req = -1 }
501 };
502
503 static struct omap_hwmod omap36xx_uart4_hwmod = {
504 .name = "uart4",
505 .mpu_irqs = uart4_mpu_irqs,
506 .sdma_reqs = uart4_sdma_reqs,
507 .main_clk = "uart4_fck",
508 .prcm = {
509 .omap2 = {
510 .module_offs = OMAP3430_PER_MOD,
511 .prcm_reg_id = 1,
512 .module_bit = OMAP3630_EN_UART4_SHIFT,
513 .idlest_reg_id = 1,
514 .idlest_idle_bit = OMAP3630_EN_UART4_SHIFT,
515 },
516 },
517 .class = &omap2_uart_class,
518 };
519
520 static struct omap_hwmod_irq_info am35xx_uart4_mpu_irqs[] = {
521 { .irq = INT_35XX_UART4_IRQ, },
522 };
523
524 static struct omap_hwmod_dma_info am35xx_uart4_sdma_reqs[] = {
525 { .name = "rx", .dma_req = AM35XX_DMA_UART4_RX, },
526 { .name = "tx", .dma_req = AM35XX_DMA_UART4_TX, },
527 };
528
529 static struct omap_hwmod am35xx_uart4_hwmod = {
530 .name = "uart4",
531 .mpu_irqs = am35xx_uart4_mpu_irqs,
532 .sdma_reqs = am35xx_uart4_sdma_reqs,
533 .main_clk = "uart4_fck",
534 .prcm = {
535 .omap2 = {
536 .module_offs = CORE_MOD,
537 .prcm_reg_id = 1,
538 .module_bit = OMAP3430_EN_UART4_SHIFT,
539 .idlest_reg_id = 1,
540 .idlest_idle_bit = OMAP3430_EN_UART4_SHIFT,
541 },
542 },
543 .class = &omap2_uart_class,
544 };
545
546 static struct omap_hwmod_class i2c_class = {
547 .name = "i2c",
548 .sysc = &i2c_sysc,
549 .rev = OMAP_I2C_IP_VERSION_1,
550 .reset = &omap_i2c_reset,
551 };
552
553 static struct omap_hwmod_dma_info omap3xxx_dss_sdma_chs[] = {
554 { .name = "dispc", .dma_req = 5 },
555 { .name = "dsi1", .dma_req = 74 },
556 { .dma_req = -1 }
557 };
558
559 /* dss */
560 static struct omap_hwmod_opt_clk dss_opt_clks[] = {
561 /*
562 * The DSS HW needs all DSS clocks enabled during reset. The dss_core
563 * driver does not use these clocks.
564 */
565 { .role = "sys_clk", .clk = "dss2_alwon_fck" },
566 { .role = "tv_clk", .clk = "dss_tv_fck" },
567 /* required only on OMAP3430 */
568 { .role = "tv_dac_clk", .clk = "dss_96m_fck" },
569 };
570
571 static struct omap_hwmod omap3430es1_dss_core_hwmod = {
572 .name = "dss_core",
573 .class = &omap2_dss_hwmod_class,
574 .main_clk = "dss1_alwon_fck", /* instead of dss_fck */
575 .sdma_reqs = omap3xxx_dss_sdma_chs,
576 .prcm = {
577 .omap2 = {
578 .prcm_reg_id = 1,
579 .module_bit = OMAP3430_EN_DSS1_SHIFT,
580 .module_offs = OMAP3430_DSS_MOD,
581 .idlest_reg_id = 1,
582 .idlest_stdby_bit = OMAP3430ES1_ST_DSS_SHIFT,
583 },
584 },
585 .opt_clks = dss_opt_clks,
586 .opt_clks_cnt = ARRAY_SIZE(dss_opt_clks),
587 .flags = HWMOD_NO_IDLEST | HWMOD_CONTROL_OPT_CLKS_IN_RESET,
588 };
589
590 static struct omap_hwmod omap3xxx_dss_core_hwmod = {
591 .name = "dss_core",
592 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
593 .class = &omap2_dss_hwmod_class,
594 .main_clk = "dss1_alwon_fck", /* instead of dss_fck */
595 .sdma_reqs = omap3xxx_dss_sdma_chs,
596 .prcm = {
597 .omap2 = {
598 .prcm_reg_id = 1,
599 .module_bit = OMAP3430_EN_DSS1_SHIFT,
600 .module_offs = OMAP3430_DSS_MOD,
601 .idlest_reg_id = 1,
602 .idlest_idle_bit = OMAP3430ES2_ST_DSS_IDLE_SHIFT,
603 .idlest_stdby_bit = OMAP3430ES2_ST_DSS_STDBY_SHIFT,
604 },
605 },
606 .opt_clks = dss_opt_clks,
607 .opt_clks_cnt = ARRAY_SIZE(dss_opt_clks),
608 };
609
610 /*
611 * 'dispc' class
612 * display controller
613 */
614
615 static struct omap_hwmod_class_sysconfig omap3_dispc_sysc = {
616 .rev_offs = 0x0000,
617 .sysc_offs = 0x0010,
618 .syss_offs = 0x0014,
619 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE |
620 SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
621 SYSC_HAS_ENAWAKEUP),
622 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
623 MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
624 .sysc_fields = &omap_hwmod_sysc_type1,
625 };
626
627 static struct omap_hwmod_class omap3_dispc_hwmod_class = {
628 .name = "dispc",
629 .sysc = &omap3_dispc_sysc,
630 };
631
632 static struct omap_hwmod omap3xxx_dss_dispc_hwmod = {
633 .name = "dss_dispc",
634 .class = &omap3_dispc_hwmod_class,
635 .mpu_irqs = omap2_dispc_irqs,
636 .main_clk = "dss1_alwon_fck",
637 .prcm = {
638 .omap2 = {
639 .prcm_reg_id = 1,
640 .module_bit = OMAP3430_EN_DSS1_SHIFT,
641 .module_offs = OMAP3430_DSS_MOD,
642 },
643 },
644 .flags = HWMOD_NO_IDLEST,
645 .dev_attr = &omap2_3_dss_dispc_dev_attr
646 };
647
648 /*
649 * 'dsi' class
650 * display serial interface controller
651 */
652
653 static struct omap_hwmod_class omap3xxx_dsi_hwmod_class = {
654 .name = "dsi",
655 };
656
657 static struct omap_hwmod_irq_info omap3xxx_dsi1_irqs[] = {
658 { .irq = 25 },
659 { .irq = -1 }
660 };
661
662 /* dss_dsi1 */
663 static struct omap_hwmod_opt_clk dss_dsi1_opt_clks[] = {
664 { .role = "sys_clk", .clk = "dss2_alwon_fck" },
665 };
666
667 static struct omap_hwmod omap3xxx_dss_dsi1_hwmod = {
668 .name = "dss_dsi1",
669 .class = &omap3xxx_dsi_hwmod_class,
670 .mpu_irqs = omap3xxx_dsi1_irqs,
671 .main_clk = "dss1_alwon_fck",
672 .prcm = {
673 .omap2 = {
674 .prcm_reg_id = 1,
675 .module_bit = OMAP3430_EN_DSS1_SHIFT,
676 .module_offs = OMAP3430_DSS_MOD,
677 },
678 },
679 .opt_clks = dss_dsi1_opt_clks,
680 .opt_clks_cnt = ARRAY_SIZE(dss_dsi1_opt_clks),
681 .flags = HWMOD_NO_IDLEST,
682 };
683
684 static struct omap_hwmod_opt_clk dss_rfbi_opt_clks[] = {
685 { .role = "ick", .clk = "dss_ick" },
686 };
687
688 static struct omap_hwmod omap3xxx_dss_rfbi_hwmod = {
689 .name = "dss_rfbi",
690 .class = &omap2_rfbi_hwmod_class,
691 .main_clk = "dss1_alwon_fck",
692 .prcm = {
693 .omap2 = {
694 .prcm_reg_id = 1,
695 .module_bit = OMAP3430_EN_DSS1_SHIFT,
696 .module_offs = OMAP3430_DSS_MOD,
697 },
698 },
699 .opt_clks = dss_rfbi_opt_clks,
700 .opt_clks_cnt = ARRAY_SIZE(dss_rfbi_opt_clks),
701 .flags = HWMOD_NO_IDLEST,
702 };
703
704 static struct omap_hwmod_opt_clk dss_venc_opt_clks[] = {
705 /* required only on OMAP3430 */
706 { .role = "tv_dac_clk", .clk = "dss_96m_fck" },
707 };
708
709 static struct omap_hwmod omap3xxx_dss_venc_hwmod = {
710 .name = "dss_venc",
711 .class = &omap2_venc_hwmod_class,
712 .main_clk = "dss_tv_fck",
713 .prcm = {
714 .omap2 = {
715 .prcm_reg_id = 1,
716 .module_bit = OMAP3430_EN_DSS1_SHIFT,
717 .module_offs = OMAP3430_DSS_MOD,
718 },
719 },
720 .opt_clks = dss_venc_opt_clks,
721 .opt_clks_cnt = ARRAY_SIZE(dss_venc_opt_clks),
722 .flags = HWMOD_NO_IDLEST,
723 };
724
725 /* I2C1 */
726 static struct omap_i2c_dev_attr i2c1_dev_attr = {
727 .fifo_depth = 8, /* bytes */
728 .flags = OMAP_I2C_FLAG_APPLY_ERRATA_I207 |
729 OMAP_I2C_FLAG_RESET_REGS_POSTIDLE |
730 OMAP_I2C_FLAG_BUS_SHIFT_2,
731 };
732
733 static struct omap_hwmod omap3xxx_i2c1_hwmod = {
734 .name = "i2c1",
735 .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
736 .mpu_irqs = omap2_i2c1_mpu_irqs,
737 .sdma_reqs = omap2_i2c1_sdma_reqs,
738 .main_clk = "i2c1_fck",
739 .prcm = {
740 .omap2 = {
741 .module_offs = CORE_MOD,
742 .prcm_reg_id = 1,
743 .module_bit = OMAP3430_EN_I2C1_SHIFT,
744 .idlest_reg_id = 1,
745 .idlest_idle_bit = OMAP3430_ST_I2C1_SHIFT,
746 },
747 },
748 .class = &i2c_class,
749 .dev_attr = &i2c1_dev_attr,
750 };
751
752 /* I2C2 */
753 static struct omap_i2c_dev_attr i2c2_dev_attr = {
754 .fifo_depth = 8, /* bytes */
755 .flags = OMAP_I2C_FLAG_APPLY_ERRATA_I207 |
756 OMAP_I2C_FLAG_RESET_REGS_POSTIDLE |
757 OMAP_I2C_FLAG_BUS_SHIFT_2,
758 };
759
760 static struct omap_hwmod omap3xxx_i2c2_hwmod = {
761 .name = "i2c2",
762 .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
763 .mpu_irqs = omap2_i2c2_mpu_irqs,
764 .sdma_reqs = omap2_i2c2_sdma_reqs,
765 .main_clk = "i2c2_fck",
766 .prcm = {
767 .omap2 = {
768 .module_offs = CORE_MOD,
769 .prcm_reg_id = 1,
770 .module_bit = OMAP3430_EN_I2C2_SHIFT,
771 .idlest_reg_id = 1,
772 .idlest_idle_bit = OMAP3430_ST_I2C2_SHIFT,
773 },
774 },
775 .class = &i2c_class,
776 .dev_attr = &i2c2_dev_attr,
777 };
778
779 /* I2C3 */
780 static struct omap_i2c_dev_attr i2c3_dev_attr = {
781 .fifo_depth = 64, /* bytes */
782 .flags = OMAP_I2C_FLAG_APPLY_ERRATA_I207 |
783 OMAP_I2C_FLAG_RESET_REGS_POSTIDLE |
784 OMAP_I2C_FLAG_BUS_SHIFT_2,
785 };
786
787 static struct omap_hwmod_irq_info i2c3_mpu_irqs[] = {
788 { .irq = INT_34XX_I2C3_IRQ, },
789 { .irq = -1 }
790 };
791
792 static struct omap_hwmod_dma_info i2c3_sdma_reqs[] = {
793 { .name = "tx", .dma_req = OMAP34XX_DMA_I2C3_TX },
794 { .name = "rx", .dma_req = OMAP34XX_DMA_I2C3_RX },
795 { .dma_req = -1 }
796 };
797
798 static struct omap_hwmod omap3xxx_i2c3_hwmod = {
799 .name = "i2c3",
800 .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
801 .mpu_irqs = i2c3_mpu_irqs,
802 .sdma_reqs = i2c3_sdma_reqs,
803 .main_clk = "i2c3_fck",
804 .prcm = {
805 .omap2 = {
806 .module_offs = CORE_MOD,
807 .prcm_reg_id = 1,
808 .module_bit = OMAP3430_EN_I2C3_SHIFT,
809 .idlest_reg_id = 1,
810 .idlest_idle_bit = OMAP3430_ST_I2C3_SHIFT,
811 },
812 },
813 .class = &i2c_class,
814 .dev_attr = &i2c3_dev_attr,
815 };
816
817 /*
818 * 'gpio' class
819 * general purpose io module
820 */
821
822 static struct omap_hwmod_class_sysconfig omap3xxx_gpio_sysc = {
823 .rev_offs = 0x0000,
824 .sysc_offs = 0x0010,
825 .syss_offs = 0x0014,
826 .sysc_flags = (SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
827 SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
828 SYSS_HAS_RESET_STATUS),
829 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
830 .sysc_fields = &omap_hwmod_sysc_type1,
831 };
832
833 static struct omap_hwmod_class omap3xxx_gpio_hwmod_class = {
834 .name = "gpio",
835 .sysc = &omap3xxx_gpio_sysc,
836 .rev = 1,
837 };
838
839 /* gpio_dev_attr */
840 static struct omap_gpio_dev_attr gpio_dev_attr = {
841 .bank_width = 32,
842 .dbck_flag = true,
843 };
844
845 /* gpio1 */
846 static struct omap_hwmod_opt_clk gpio1_opt_clks[] = {
847 { .role = "dbclk", .clk = "gpio1_dbck", },
848 };
849
850 static struct omap_hwmod omap3xxx_gpio1_hwmod = {
851 .name = "gpio1",
852 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
853 .mpu_irqs = omap2_gpio1_irqs,
854 .main_clk = "gpio1_ick",
855 .opt_clks = gpio1_opt_clks,
856 .opt_clks_cnt = ARRAY_SIZE(gpio1_opt_clks),
857 .prcm = {
858 .omap2 = {
859 .prcm_reg_id = 1,
860 .module_bit = OMAP3430_EN_GPIO1_SHIFT,
861 .module_offs = WKUP_MOD,
862 .idlest_reg_id = 1,
863 .idlest_idle_bit = OMAP3430_ST_GPIO1_SHIFT,
864 },
865 },
866 .class = &omap3xxx_gpio_hwmod_class,
867 .dev_attr = &gpio_dev_attr,
868 };
869
870 /* gpio2 */
871 static struct omap_hwmod_opt_clk gpio2_opt_clks[] = {
872 { .role = "dbclk", .clk = "gpio2_dbck", },
873 };
874
875 static struct omap_hwmod omap3xxx_gpio2_hwmod = {
876 .name = "gpio2",
877 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
878 .mpu_irqs = omap2_gpio2_irqs,
879 .main_clk = "gpio2_ick",
880 .opt_clks = gpio2_opt_clks,
881 .opt_clks_cnt = ARRAY_SIZE(gpio2_opt_clks),
882 .prcm = {
883 .omap2 = {
884 .prcm_reg_id = 1,
885 .module_bit = OMAP3430_EN_GPIO2_SHIFT,
886 .module_offs = OMAP3430_PER_MOD,
887 .idlest_reg_id = 1,
888 .idlest_idle_bit = OMAP3430_ST_GPIO2_SHIFT,
889 },
890 },
891 .class = &omap3xxx_gpio_hwmod_class,
892 .dev_attr = &gpio_dev_attr,
893 };
894
895 /* gpio3 */
896 static struct omap_hwmod_opt_clk gpio3_opt_clks[] = {
897 { .role = "dbclk", .clk = "gpio3_dbck", },
898 };
899
900 static struct omap_hwmod omap3xxx_gpio3_hwmod = {
901 .name = "gpio3",
902 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
903 .mpu_irqs = omap2_gpio3_irqs,
904 .main_clk = "gpio3_ick",
905 .opt_clks = gpio3_opt_clks,
906 .opt_clks_cnt = ARRAY_SIZE(gpio3_opt_clks),
907 .prcm = {
908 .omap2 = {
909 .prcm_reg_id = 1,
910 .module_bit = OMAP3430_EN_GPIO3_SHIFT,
911 .module_offs = OMAP3430_PER_MOD,
912 .idlest_reg_id = 1,
913 .idlest_idle_bit = OMAP3430_ST_GPIO3_SHIFT,
914 },
915 },
916 .class = &omap3xxx_gpio_hwmod_class,
917 .dev_attr = &gpio_dev_attr,
918 };
919
920 /* gpio4 */
921 static struct omap_hwmod_opt_clk gpio4_opt_clks[] = {
922 { .role = "dbclk", .clk = "gpio4_dbck", },
923 };
924
925 static struct omap_hwmod omap3xxx_gpio4_hwmod = {
926 .name = "gpio4",
927 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
928 .mpu_irqs = omap2_gpio4_irqs,
929 .main_clk = "gpio4_ick",
930 .opt_clks = gpio4_opt_clks,
931 .opt_clks_cnt = ARRAY_SIZE(gpio4_opt_clks),
932 .prcm = {
933 .omap2 = {
934 .prcm_reg_id = 1,
935 .module_bit = OMAP3430_EN_GPIO4_SHIFT,
936 .module_offs = OMAP3430_PER_MOD,
937 .idlest_reg_id = 1,
938 .idlest_idle_bit = OMAP3430_ST_GPIO4_SHIFT,
939 },
940 },
941 .class = &omap3xxx_gpio_hwmod_class,
942 .dev_attr = &gpio_dev_attr,
943 };
944
945 /* gpio5 */
946 static struct omap_hwmod_irq_info omap3xxx_gpio5_irqs[] = {
947 { .irq = 33 }, /* INT_34XX_GPIO_BANK5 */
948 { .irq = -1 }
949 };
950
951 static struct omap_hwmod_opt_clk gpio5_opt_clks[] = {
952 { .role = "dbclk", .clk = "gpio5_dbck", },
953 };
954
955 static struct omap_hwmod omap3xxx_gpio5_hwmod = {
956 .name = "gpio5",
957 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
958 .mpu_irqs = omap3xxx_gpio5_irqs,
959 .main_clk = "gpio5_ick",
960 .opt_clks = gpio5_opt_clks,
961 .opt_clks_cnt = ARRAY_SIZE(gpio5_opt_clks),
962 .prcm = {
963 .omap2 = {
964 .prcm_reg_id = 1,
965 .module_bit = OMAP3430_EN_GPIO5_SHIFT,
966 .module_offs = OMAP3430_PER_MOD,
967 .idlest_reg_id = 1,
968 .idlest_idle_bit = OMAP3430_ST_GPIO5_SHIFT,
969 },
970 },
971 .class = &omap3xxx_gpio_hwmod_class,
972 .dev_attr = &gpio_dev_attr,
973 };
974
975 /* gpio6 */
976 static struct omap_hwmod_irq_info omap3xxx_gpio6_irqs[] = {
977 { .irq = 34 }, /* INT_34XX_GPIO_BANK6 */
978 { .irq = -1 }
979 };
980
981 static struct omap_hwmod_opt_clk gpio6_opt_clks[] = {
982 { .role = "dbclk", .clk = "gpio6_dbck", },
983 };
984
985 static struct omap_hwmod omap3xxx_gpio6_hwmod = {
986 .name = "gpio6",
987 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
988 .mpu_irqs = omap3xxx_gpio6_irqs,
989 .main_clk = "gpio6_ick",
990 .opt_clks = gpio6_opt_clks,
991 .opt_clks_cnt = ARRAY_SIZE(gpio6_opt_clks),
992 .prcm = {
993 .omap2 = {
994 .prcm_reg_id = 1,
995 .module_bit = OMAP3430_EN_GPIO6_SHIFT,
996 .module_offs = OMAP3430_PER_MOD,
997 .idlest_reg_id = 1,
998 .idlest_idle_bit = OMAP3430_ST_GPIO6_SHIFT,
999 },
1000 },
1001 .class = &omap3xxx_gpio_hwmod_class,
1002 .dev_attr = &gpio_dev_attr,
1003 };
1004
1005 /* dma attributes */
1006 static struct omap_dma_dev_attr dma_dev_attr = {
1007 .dev_caps = RESERVE_CHANNEL | DMA_LINKED_LCH | GLOBAL_PRIORITY |
1008 IS_CSSA_32 | IS_CDSA_32 | IS_RW_PRIORITY,
1009 .lch_count = 32,
1010 };
1011
1012 static struct omap_hwmod_class_sysconfig omap3xxx_dma_sysc = {
1013 .rev_offs = 0x0000,
1014 .sysc_offs = 0x002c,
1015 .syss_offs = 0x0028,
1016 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
1017 SYSC_HAS_MIDLEMODE | SYSC_HAS_CLOCKACTIVITY |
1018 SYSC_HAS_EMUFREE | SYSC_HAS_AUTOIDLE |
1019 SYSS_HAS_RESET_STATUS),
1020 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1021 MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
1022 .sysc_fields = &omap_hwmod_sysc_type1,
1023 };
1024
1025 static struct omap_hwmod_class omap3xxx_dma_hwmod_class = {
1026 .name = "dma",
1027 .sysc = &omap3xxx_dma_sysc,
1028 };
1029
1030 /* dma_system */
1031 static struct omap_hwmod omap3xxx_dma_system_hwmod = {
1032 .name = "dma",
1033 .class = &omap3xxx_dma_hwmod_class,
1034 .mpu_irqs = omap2_dma_system_irqs,
1035 .main_clk = "core_l3_ick",
1036 .prcm = {
1037 .omap2 = {
1038 .module_offs = CORE_MOD,
1039 .prcm_reg_id = 1,
1040 .module_bit = OMAP3430_ST_SDMA_SHIFT,
1041 .idlest_reg_id = 1,
1042 .idlest_idle_bit = OMAP3430_ST_SDMA_SHIFT,
1043 },
1044 },
1045 .dev_attr = &dma_dev_attr,
1046 .flags = HWMOD_NO_IDLEST,
1047 };
1048
1049 /*
1050 * 'mcbsp' class
1051 * multi channel buffered serial port controller
1052 */
1053
1054 static struct omap_hwmod_class_sysconfig omap3xxx_mcbsp_sysc = {
1055 .sysc_offs = 0x008c,
1056 .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_ENAWAKEUP |
1057 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
1058 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1059 .sysc_fields = &omap_hwmod_sysc_type1,
1060 .clockact = 0x2,
1061 };
1062
1063 static struct omap_hwmod_class omap3xxx_mcbsp_hwmod_class = {
1064 .name = "mcbsp",
1065 .sysc = &omap3xxx_mcbsp_sysc,
1066 .rev = MCBSP_CONFIG_TYPE3,
1067 };
1068
1069 /* McBSP functional clock mapping */
1070 static struct omap_hwmod_opt_clk mcbsp15_opt_clks[] = {
1071 { .role = "pad_fck", .clk = "mcbsp_clks" },
1072 { .role = "prcm_fck", .clk = "core_96m_fck" },
1073 };
1074
1075 static struct omap_hwmod_opt_clk mcbsp234_opt_clks[] = {
1076 { .role = "pad_fck", .clk = "mcbsp_clks" },
1077 { .role = "prcm_fck", .clk = "per_96m_fck" },
1078 };
1079
1080 /* mcbsp1 */
1081 static struct omap_hwmod_irq_info omap3xxx_mcbsp1_irqs[] = {
1082 { .name = "common", .irq = 16 },
1083 { .name = "tx", .irq = 59 },
1084 { .name = "rx", .irq = 60 },
1085 { .irq = -1 }
1086 };
1087
1088 static struct omap_hwmod omap3xxx_mcbsp1_hwmod = {
1089 .name = "mcbsp1",
1090 .class = &omap3xxx_mcbsp_hwmod_class,
1091 .mpu_irqs = omap3xxx_mcbsp1_irqs,
1092 .sdma_reqs = omap2_mcbsp1_sdma_reqs,
1093 .main_clk = "mcbsp1_fck",
1094 .prcm = {
1095 .omap2 = {
1096 .prcm_reg_id = 1,
1097 .module_bit = OMAP3430_EN_MCBSP1_SHIFT,
1098 .module_offs = CORE_MOD,
1099 .idlest_reg_id = 1,
1100 .idlest_idle_bit = OMAP3430_ST_MCBSP1_SHIFT,
1101 },
1102 },
1103 .opt_clks = mcbsp15_opt_clks,
1104 .opt_clks_cnt = ARRAY_SIZE(mcbsp15_opt_clks),
1105 };
1106
1107 /* mcbsp2 */
1108 static struct omap_hwmod_irq_info omap3xxx_mcbsp2_irqs[] = {
1109 { .name = "common", .irq = 17 },
1110 { .name = "tx", .irq = 62 },
1111 { .name = "rx", .irq = 63 },
1112 { .irq = -1 }
1113 };
1114
1115 static struct omap_mcbsp_dev_attr omap34xx_mcbsp2_dev_attr = {
1116 .sidetone = "mcbsp2_sidetone",
1117 };
1118
1119 static struct omap_hwmod omap3xxx_mcbsp2_hwmod = {
1120 .name = "mcbsp2",
1121 .class = &omap3xxx_mcbsp_hwmod_class,
1122 .mpu_irqs = omap3xxx_mcbsp2_irqs,
1123 .sdma_reqs = omap2_mcbsp2_sdma_reqs,
1124 .main_clk = "mcbsp2_fck",
1125 .prcm = {
1126 .omap2 = {
1127 .prcm_reg_id = 1,
1128 .module_bit = OMAP3430_EN_MCBSP2_SHIFT,
1129 .module_offs = OMAP3430_PER_MOD,
1130 .idlest_reg_id = 1,
1131 .idlest_idle_bit = OMAP3430_ST_MCBSP2_SHIFT,
1132 },
1133 },
1134 .opt_clks = mcbsp234_opt_clks,
1135 .opt_clks_cnt = ARRAY_SIZE(mcbsp234_opt_clks),
1136 .dev_attr = &omap34xx_mcbsp2_dev_attr,
1137 };
1138
1139 /* mcbsp3 */
1140 static struct omap_hwmod_irq_info omap3xxx_mcbsp3_irqs[] = {
1141 { .name = "common", .irq = 22 },
1142 { .name = "tx", .irq = 89 },
1143 { .name = "rx", .irq = 90 },
1144 { .irq = -1 }
1145 };
1146
1147 static struct omap_mcbsp_dev_attr omap34xx_mcbsp3_dev_attr = {
1148 .sidetone = "mcbsp3_sidetone",
1149 };
1150
1151 static struct omap_hwmod omap3xxx_mcbsp3_hwmod = {
1152 .name = "mcbsp3",
1153 .class = &omap3xxx_mcbsp_hwmod_class,
1154 .mpu_irqs = omap3xxx_mcbsp3_irqs,
1155 .sdma_reqs = omap2_mcbsp3_sdma_reqs,
1156 .main_clk = "mcbsp3_fck",
1157 .prcm = {
1158 .omap2 = {
1159 .prcm_reg_id = 1,
1160 .module_bit = OMAP3430_EN_MCBSP3_SHIFT,
1161 .module_offs = OMAP3430_PER_MOD,
1162 .idlest_reg_id = 1,
1163 .idlest_idle_bit = OMAP3430_ST_MCBSP3_SHIFT,
1164 },
1165 },
1166 .opt_clks = mcbsp234_opt_clks,
1167 .opt_clks_cnt = ARRAY_SIZE(mcbsp234_opt_clks),
1168 .dev_attr = &omap34xx_mcbsp3_dev_attr,
1169 };
1170
1171 /* mcbsp4 */
1172 static struct omap_hwmod_irq_info omap3xxx_mcbsp4_irqs[] = {
1173 { .name = "common", .irq = 23 },
1174 { .name = "tx", .irq = 54 },
1175 { .name = "rx", .irq = 55 },
1176 { .irq = -1 }
1177 };
1178
1179 static struct omap_hwmod_dma_info omap3xxx_mcbsp4_sdma_chs[] = {
1180 { .name = "rx", .dma_req = 20 },
1181 { .name = "tx", .dma_req = 19 },
1182 { .dma_req = -1 }
1183 };
1184
1185 static struct omap_hwmod omap3xxx_mcbsp4_hwmod = {
1186 .name = "mcbsp4",
1187 .class = &omap3xxx_mcbsp_hwmod_class,
1188 .mpu_irqs = omap3xxx_mcbsp4_irqs,
1189 .sdma_reqs = omap3xxx_mcbsp4_sdma_chs,
1190 .main_clk = "mcbsp4_fck",
1191 .prcm = {
1192 .omap2 = {
1193 .prcm_reg_id = 1,
1194 .module_bit = OMAP3430_EN_MCBSP4_SHIFT,
1195 .module_offs = OMAP3430_PER_MOD,
1196 .idlest_reg_id = 1,
1197 .idlest_idle_bit = OMAP3430_ST_MCBSP4_SHIFT,
1198 },
1199 },
1200 .opt_clks = mcbsp234_opt_clks,
1201 .opt_clks_cnt = ARRAY_SIZE(mcbsp234_opt_clks),
1202 };
1203
1204 /* mcbsp5 */
1205 static struct omap_hwmod_irq_info omap3xxx_mcbsp5_irqs[] = {
1206 { .name = "common", .irq = 27 },
1207 { .name = "tx", .irq = 81 },
1208 { .name = "rx", .irq = 82 },
1209 { .irq = -1 }
1210 };
1211
1212 static struct omap_hwmod_dma_info omap3xxx_mcbsp5_sdma_chs[] = {
1213 { .name = "rx", .dma_req = 22 },
1214 { .name = "tx", .dma_req = 21 },
1215 { .dma_req = -1 }
1216 };
1217
1218 static struct omap_hwmod omap3xxx_mcbsp5_hwmod = {
1219 .name = "mcbsp5",
1220 .class = &omap3xxx_mcbsp_hwmod_class,
1221 .mpu_irqs = omap3xxx_mcbsp5_irqs,
1222 .sdma_reqs = omap3xxx_mcbsp5_sdma_chs,
1223 .main_clk = "mcbsp5_fck",
1224 .prcm = {
1225 .omap2 = {
1226 .prcm_reg_id = 1,
1227 .module_bit = OMAP3430_EN_MCBSP5_SHIFT,
1228 .module_offs = CORE_MOD,
1229 .idlest_reg_id = 1,
1230 .idlest_idle_bit = OMAP3430_ST_MCBSP5_SHIFT,
1231 },
1232 },
1233 .opt_clks = mcbsp15_opt_clks,
1234 .opt_clks_cnt = ARRAY_SIZE(mcbsp15_opt_clks),
1235 };
1236
1237 /* 'mcbsp sidetone' class */
1238 static struct omap_hwmod_class_sysconfig omap3xxx_mcbsp_sidetone_sysc = {
1239 .sysc_offs = 0x0010,
1240 .sysc_flags = SYSC_HAS_AUTOIDLE,
1241 .sysc_fields = &omap_hwmod_sysc_type1,
1242 };
1243
1244 static struct omap_hwmod_class omap3xxx_mcbsp_sidetone_hwmod_class = {
1245 .name = "mcbsp_sidetone",
1246 .sysc = &omap3xxx_mcbsp_sidetone_sysc,
1247 };
1248
1249 /* mcbsp2_sidetone */
1250 static struct omap_hwmod_irq_info omap3xxx_mcbsp2_sidetone_irqs[] = {
1251 { .name = "irq", .irq = 4 },
1252 { .irq = -1 }
1253 };
1254
1255 static struct omap_hwmod omap3xxx_mcbsp2_sidetone_hwmod = {
1256 .name = "mcbsp2_sidetone",
1257 .class = &omap3xxx_mcbsp_sidetone_hwmod_class,
1258 .mpu_irqs = omap3xxx_mcbsp2_sidetone_irqs,
1259 .main_clk = "mcbsp2_fck",
1260 .prcm = {
1261 .omap2 = {
1262 .prcm_reg_id = 1,
1263 .module_bit = OMAP3430_EN_MCBSP2_SHIFT,
1264 .module_offs = OMAP3430_PER_MOD,
1265 .idlest_reg_id = 1,
1266 .idlest_idle_bit = OMAP3430_ST_MCBSP2_SHIFT,
1267 },
1268 },
1269 };
1270
1271 /* mcbsp3_sidetone */
1272 static struct omap_hwmod_irq_info omap3xxx_mcbsp3_sidetone_irqs[] = {
1273 { .name = "irq", .irq = 5 },
1274 { .irq = -1 }
1275 };
1276
1277 static struct omap_hwmod omap3xxx_mcbsp3_sidetone_hwmod = {
1278 .name = "mcbsp3_sidetone",
1279 .class = &omap3xxx_mcbsp_sidetone_hwmod_class,
1280 .mpu_irqs = omap3xxx_mcbsp3_sidetone_irqs,
1281 .main_clk = "mcbsp3_fck",
1282 .prcm = {
1283 .omap2 = {
1284 .prcm_reg_id = 1,
1285 .module_bit = OMAP3430_EN_MCBSP3_SHIFT,
1286 .module_offs = OMAP3430_PER_MOD,
1287 .idlest_reg_id = 1,
1288 .idlest_idle_bit = OMAP3430_ST_MCBSP3_SHIFT,
1289 },
1290 },
1291 };
1292
1293 /* SR common */
1294 static struct omap_hwmod_sysc_fields omap34xx_sr_sysc_fields = {
1295 .clkact_shift = 20,
1296 };
1297
1298 static struct omap_hwmod_class_sysconfig omap34xx_sr_sysc = {
1299 .sysc_offs = 0x24,
1300 .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_NO_CACHE),
1301 .clockact = CLOCKACT_TEST_ICLK,
1302 .sysc_fields = &omap34xx_sr_sysc_fields,
1303 };
1304
1305 static struct omap_hwmod_class omap34xx_smartreflex_hwmod_class = {
1306 .name = "smartreflex",
1307 .sysc = &omap34xx_sr_sysc,
1308 .rev = 1,
1309 };
1310
1311 static struct omap_hwmod_sysc_fields omap36xx_sr_sysc_fields = {
1312 .sidle_shift = 24,
1313 .enwkup_shift = 26,
1314 };
1315
1316 static struct omap_hwmod_class_sysconfig omap36xx_sr_sysc = {
1317 .sysc_offs = 0x38,
1318 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1319 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_ENAWAKEUP |
1320 SYSC_NO_CACHE),
1321 .sysc_fields = &omap36xx_sr_sysc_fields,
1322 };
1323
1324 static struct omap_hwmod_class omap36xx_smartreflex_hwmod_class = {
1325 .name = "smartreflex",
1326 .sysc = &omap36xx_sr_sysc,
1327 .rev = 2,
1328 };
1329
1330 /* SR1 */
1331 static struct omap_smartreflex_dev_attr sr1_dev_attr = {
1332 .sensor_voltdm_name = "mpu_iva",
1333 };
1334
1335 static struct omap_hwmod_irq_info omap3_smartreflex_mpu_irqs[] = {
1336 { .irq = 18 },
1337 { .irq = -1 }
1338 };
1339
1340 static struct omap_hwmod omap34xx_sr1_hwmod = {
1341 .name = "sr1",
1342 .class = &omap34xx_smartreflex_hwmod_class,
1343 .main_clk = "sr1_fck",
1344 .prcm = {
1345 .omap2 = {
1346 .prcm_reg_id = 1,
1347 .module_bit = OMAP3430_EN_SR1_SHIFT,
1348 .module_offs = WKUP_MOD,
1349 .idlest_reg_id = 1,
1350 .idlest_idle_bit = OMAP3430_EN_SR1_SHIFT,
1351 },
1352 },
1353 .dev_attr = &sr1_dev_attr,
1354 .mpu_irqs = omap3_smartreflex_mpu_irqs,
1355 .flags = HWMOD_SET_DEFAULT_CLOCKACT,
1356 };
1357
1358 static struct omap_hwmod omap36xx_sr1_hwmod = {
1359 .name = "sr1",
1360 .class = &omap36xx_smartreflex_hwmod_class,
1361 .main_clk = "sr1_fck",
1362 .prcm = {
1363 .omap2 = {
1364 .prcm_reg_id = 1,
1365 .module_bit = OMAP3430_EN_SR1_SHIFT,
1366 .module_offs = WKUP_MOD,
1367 .idlest_reg_id = 1,
1368 .idlest_idle_bit = OMAP3430_EN_SR1_SHIFT,
1369 },
1370 },
1371 .dev_attr = &sr1_dev_attr,
1372 .mpu_irqs = omap3_smartreflex_mpu_irqs,
1373 };
1374
1375 /* SR2 */
1376 static struct omap_smartreflex_dev_attr sr2_dev_attr = {
1377 .sensor_voltdm_name = "core",
1378 };
1379
1380 static struct omap_hwmod_irq_info omap3_smartreflex_core_irqs[] = {
1381 { .irq = 19 },
1382 { .irq = -1 }
1383 };
1384
1385 static struct omap_hwmod omap34xx_sr2_hwmod = {
1386 .name = "sr2",
1387 .class = &omap34xx_smartreflex_hwmod_class,
1388 .main_clk = "sr2_fck",
1389 .prcm = {
1390 .omap2 = {
1391 .prcm_reg_id = 1,
1392 .module_bit = OMAP3430_EN_SR2_SHIFT,
1393 .module_offs = WKUP_MOD,
1394 .idlest_reg_id = 1,
1395 .idlest_idle_bit = OMAP3430_EN_SR2_SHIFT,
1396 },
1397 },
1398 .dev_attr = &sr2_dev_attr,
1399 .mpu_irqs = omap3_smartreflex_core_irqs,
1400 .flags = HWMOD_SET_DEFAULT_CLOCKACT,
1401 };
1402
1403 static struct omap_hwmod omap36xx_sr2_hwmod = {
1404 .name = "sr2",
1405 .class = &omap36xx_smartreflex_hwmod_class,
1406 .main_clk = "sr2_fck",
1407 .prcm = {
1408 .omap2 = {
1409 .prcm_reg_id = 1,
1410 .module_bit = OMAP3430_EN_SR2_SHIFT,
1411 .module_offs = WKUP_MOD,
1412 .idlest_reg_id = 1,
1413 .idlest_idle_bit = OMAP3430_EN_SR2_SHIFT,
1414 },
1415 },
1416 .dev_attr = &sr2_dev_attr,
1417 .mpu_irqs = omap3_smartreflex_core_irqs,
1418 };
1419
1420 /*
1421 * 'mailbox' class
1422 * mailbox module allowing communication between the on-chip processors
1423 * using a queued mailbox-interrupt mechanism.
1424 */
1425
1426 static struct omap_hwmod_class_sysconfig omap3xxx_mailbox_sysc = {
1427 .rev_offs = 0x000,
1428 .sysc_offs = 0x010,
1429 .syss_offs = 0x014,
1430 .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
1431 SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
1432 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1433 .sysc_fields = &omap_hwmod_sysc_type1,
1434 };
1435
1436 static struct omap_hwmod_class omap3xxx_mailbox_hwmod_class = {
1437 .name = "mailbox",
1438 .sysc = &omap3xxx_mailbox_sysc,
1439 };
1440
1441 static struct omap_hwmod_irq_info omap3xxx_mailbox_irqs[] = {
1442 { .irq = 26 },
1443 { .irq = -1 }
1444 };
1445
1446 static struct omap_hwmod omap3xxx_mailbox_hwmod = {
1447 .name = "mailbox",
1448 .class = &omap3xxx_mailbox_hwmod_class,
1449 .mpu_irqs = omap3xxx_mailbox_irqs,
1450 .main_clk = "mailboxes_ick",
1451 .prcm = {
1452 .omap2 = {
1453 .prcm_reg_id = 1,
1454 .module_bit = OMAP3430_EN_MAILBOXES_SHIFT,
1455 .module_offs = CORE_MOD,
1456 .idlest_reg_id = 1,
1457 .idlest_idle_bit = OMAP3430_ST_MAILBOXES_SHIFT,
1458 },
1459 },
1460 };
1461
1462 /*
1463 * 'mcspi' class
1464 * multichannel serial port interface (mcspi) / master/slave synchronous serial
1465 * bus
1466 */
1467
1468 static struct omap_hwmod_class_sysconfig omap34xx_mcspi_sysc = {
1469 .rev_offs = 0x0000,
1470 .sysc_offs = 0x0010,
1471 .syss_offs = 0x0014,
1472 .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
1473 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
1474 SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
1475 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1476 .sysc_fields = &omap_hwmod_sysc_type1,
1477 };
1478
1479 static struct omap_hwmod_class omap34xx_mcspi_class = {
1480 .name = "mcspi",
1481 .sysc = &omap34xx_mcspi_sysc,
1482 .rev = OMAP3_MCSPI_REV,
1483 };
1484
1485 /* mcspi1 */
1486 static struct omap2_mcspi_dev_attr omap_mcspi1_dev_attr = {
1487 .num_chipselect = 4,
1488 };
1489
1490 static struct omap_hwmod omap34xx_mcspi1 = {
1491 .name = "mcspi1",
1492 .mpu_irqs = omap2_mcspi1_mpu_irqs,
1493 .sdma_reqs = omap2_mcspi1_sdma_reqs,
1494 .main_clk = "mcspi1_fck",
1495 .prcm = {
1496 .omap2 = {
1497 .module_offs = CORE_MOD,
1498 .prcm_reg_id = 1,
1499 .module_bit = OMAP3430_EN_MCSPI1_SHIFT,
1500 .idlest_reg_id = 1,
1501 .idlest_idle_bit = OMAP3430_ST_MCSPI1_SHIFT,
1502 },
1503 },
1504 .class = &omap34xx_mcspi_class,
1505 .dev_attr = &omap_mcspi1_dev_attr,
1506 };
1507
1508 /* mcspi2 */
1509 static struct omap2_mcspi_dev_attr omap_mcspi2_dev_attr = {
1510 .num_chipselect = 2,
1511 };
1512
1513 static struct omap_hwmod omap34xx_mcspi2 = {
1514 .name = "mcspi2",
1515 .mpu_irqs = omap2_mcspi2_mpu_irqs,
1516 .sdma_reqs = omap2_mcspi2_sdma_reqs,
1517 .main_clk = "mcspi2_fck",
1518 .prcm = {
1519 .omap2 = {
1520 .module_offs = CORE_MOD,
1521 .prcm_reg_id = 1,
1522 .module_bit = OMAP3430_EN_MCSPI2_SHIFT,
1523 .idlest_reg_id = 1,
1524 .idlest_idle_bit = OMAP3430_ST_MCSPI2_SHIFT,
1525 },
1526 },
1527 .class = &omap34xx_mcspi_class,
1528 .dev_attr = &omap_mcspi2_dev_attr,
1529 };
1530
1531 /* mcspi3 */
1532 static struct omap_hwmod_irq_info omap34xx_mcspi3_mpu_irqs[] = {
1533 { .name = "irq", .irq = 91 }, /* 91 */
1534 { .irq = -1 }
1535 };
1536
1537 static struct omap_hwmod_dma_info omap34xx_mcspi3_sdma_reqs[] = {
1538 { .name = "tx0", .dma_req = 15 },
1539 { .name = "rx0", .dma_req = 16 },
1540 { .name = "tx1", .dma_req = 23 },
1541 { .name = "rx1", .dma_req = 24 },
1542 { .dma_req = -1 }
1543 };
1544
1545 static struct omap2_mcspi_dev_attr omap_mcspi3_dev_attr = {
1546 .num_chipselect = 2,
1547 };
1548
1549 static struct omap_hwmod omap34xx_mcspi3 = {
1550 .name = "mcspi3",
1551 .mpu_irqs = omap34xx_mcspi3_mpu_irqs,
1552 .sdma_reqs = omap34xx_mcspi3_sdma_reqs,
1553 .main_clk = "mcspi3_fck",
1554 .prcm = {
1555 .omap2 = {
1556 .module_offs = CORE_MOD,
1557 .prcm_reg_id = 1,
1558 .module_bit = OMAP3430_EN_MCSPI3_SHIFT,
1559 .idlest_reg_id = 1,
1560 .idlest_idle_bit = OMAP3430_ST_MCSPI3_SHIFT,
1561 },
1562 },
1563 .class = &omap34xx_mcspi_class,
1564 .dev_attr = &omap_mcspi3_dev_attr,
1565 };
1566
1567 /* mcspi4 */
1568 static struct omap_hwmod_irq_info omap34xx_mcspi4_mpu_irqs[] = {
1569 { .name = "irq", .irq = INT_34XX_SPI4_IRQ }, /* 48 */
1570 { .irq = -1 }
1571 };
1572
1573 static struct omap_hwmod_dma_info omap34xx_mcspi4_sdma_reqs[] = {
1574 { .name = "tx0", .dma_req = 70 }, /* DMA_SPI4_TX0 */
1575 { .name = "rx0", .dma_req = 71 }, /* DMA_SPI4_RX0 */
1576 { .dma_req = -1 }
1577 };
1578
1579 static struct omap2_mcspi_dev_attr omap_mcspi4_dev_attr = {
1580 .num_chipselect = 1,
1581 };
1582
1583 static struct omap_hwmod omap34xx_mcspi4 = {
1584 .name = "mcspi4",
1585 .mpu_irqs = omap34xx_mcspi4_mpu_irqs,
1586 .sdma_reqs = omap34xx_mcspi4_sdma_reqs,
1587 .main_clk = "mcspi4_fck",
1588 .prcm = {
1589 .omap2 = {
1590 .module_offs = CORE_MOD,
1591 .prcm_reg_id = 1,
1592 .module_bit = OMAP3430_EN_MCSPI4_SHIFT,
1593 .idlest_reg_id = 1,
1594 .idlest_idle_bit = OMAP3430_ST_MCSPI4_SHIFT,
1595 },
1596 },
1597 .class = &omap34xx_mcspi_class,
1598 .dev_attr = &omap_mcspi4_dev_attr,
1599 };
1600
1601 /* usbhsotg */
1602 static struct omap_hwmod_class_sysconfig omap3xxx_usbhsotg_sysc = {
1603 .rev_offs = 0x0400,
1604 .sysc_offs = 0x0404,
1605 .syss_offs = 0x0408,
1606 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE|
1607 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
1608 SYSC_HAS_AUTOIDLE),
1609 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1610 MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
1611 .sysc_fields = &omap_hwmod_sysc_type1,
1612 };
1613
1614 static struct omap_hwmod_class usbotg_class = {
1615 .name = "usbotg",
1616 .sysc = &omap3xxx_usbhsotg_sysc,
1617 };
1618
1619 /* usb_otg_hs */
1620 static struct omap_hwmod_irq_info omap3xxx_usbhsotg_mpu_irqs[] = {
1621
1622 { .name = "mc", .irq = 92 },
1623 { .name = "dma", .irq = 93 },
1624 { .irq = -1 }
1625 };
1626
1627 static struct omap_hwmod omap3xxx_usbhsotg_hwmod = {
1628 .name = "usb_otg_hs",
1629 .mpu_irqs = omap3xxx_usbhsotg_mpu_irqs,
1630 .main_clk = "hsotgusb_ick",
1631 .prcm = {
1632 .omap2 = {
1633 .prcm_reg_id = 1,
1634 .module_bit = OMAP3430_EN_HSOTGUSB_SHIFT,
1635 .module_offs = CORE_MOD,
1636 .idlest_reg_id = 1,
1637 .idlest_idle_bit = OMAP3430ES2_ST_HSOTGUSB_IDLE_SHIFT,
1638 .idlest_stdby_bit = OMAP3430ES2_ST_HSOTGUSB_STDBY_SHIFT
1639 },
1640 },
1641 .class = &usbotg_class,
1642
1643 /*
1644 * Erratum ID: i479 idle_req / idle_ack mechanism potentially
1645 * broken when autoidle is enabled
1646 * workaround is to disable the autoidle bit at module level.
1647 */
1648 .flags = HWMOD_NO_OCP_AUTOIDLE | HWMOD_SWSUP_SIDLE
1649 | HWMOD_SWSUP_MSTANDBY,
1650 };
1651
1652 /* usb_otg_hs */
1653 static struct omap_hwmod_irq_info am35xx_usbhsotg_mpu_irqs[] = {
1654
1655 { .name = "mc", .irq = 71 },
1656 { .irq = -1 }
1657 };
1658
1659 static struct omap_hwmod_class am35xx_usbotg_class = {
1660 .name = "am35xx_usbotg",
1661 .sysc = NULL,
1662 };
1663
1664 static struct omap_hwmod am35xx_usbhsotg_hwmod = {
1665 .name = "am35x_otg_hs",
1666 .mpu_irqs = am35xx_usbhsotg_mpu_irqs,
1667 .main_clk = NULL,
1668 .prcm = {
1669 .omap2 = {
1670 },
1671 },
1672 .class = &am35xx_usbotg_class,
1673 };
1674
1675 /* MMC/SD/SDIO common */
1676 static struct omap_hwmod_class_sysconfig omap34xx_mmc_sysc = {
1677 .rev_offs = 0x1fc,
1678 .sysc_offs = 0x10,
1679 .syss_offs = 0x14,
1680 .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
1681 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
1682 SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
1683 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1684 .sysc_fields = &omap_hwmod_sysc_type1,
1685 };
1686
1687 static struct omap_hwmod_class omap34xx_mmc_class = {
1688 .name = "mmc",
1689 .sysc = &omap34xx_mmc_sysc,
1690 };
1691
1692 /* MMC/SD/SDIO1 */
1693
1694 static struct omap_hwmod_irq_info omap34xx_mmc1_mpu_irqs[] = {
1695 { .irq = 83, },
1696 { .irq = -1 }
1697 };
1698
1699 static struct omap_hwmod_dma_info omap34xx_mmc1_sdma_reqs[] = {
1700 { .name = "tx", .dma_req = 61, },
1701 { .name = "rx", .dma_req = 62, },
1702 { .dma_req = -1 }
1703 };
1704
1705 static struct omap_hwmod_opt_clk omap34xx_mmc1_opt_clks[] = {
1706 { .role = "dbck", .clk = "omap_32k_fck", },
1707 };
1708
1709 static struct omap_mmc_dev_attr mmc1_dev_attr = {
1710 .flags = OMAP_HSMMC_SUPPORTS_DUAL_VOLT,
1711 };
1712
1713 /* See 35xx errata 2.1.1.128 in SPRZ278F */
1714 static struct omap_mmc_dev_attr mmc1_pre_es3_dev_attr = {
1715 .flags = (OMAP_HSMMC_SUPPORTS_DUAL_VOLT |
1716 OMAP_HSMMC_BROKEN_MULTIBLOCK_READ),
1717 };
1718
1719 static struct omap_hwmod omap3xxx_pre_es3_mmc1_hwmod = {
1720 .name = "mmc1",
1721 .mpu_irqs = omap34xx_mmc1_mpu_irqs,
1722 .sdma_reqs = omap34xx_mmc1_sdma_reqs,
1723 .opt_clks = omap34xx_mmc1_opt_clks,
1724 .opt_clks_cnt = ARRAY_SIZE(omap34xx_mmc1_opt_clks),
1725 .main_clk = "mmchs1_fck",
1726 .prcm = {
1727 .omap2 = {
1728 .module_offs = CORE_MOD,
1729 .prcm_reg_id = 1,
1730 .module_bit = OMAP3430_EN_MMC1_SHIFT,
1731 .idlest_reg_id = 1,
1732 .idlest_idle_bit = OMAP3430_ST_MMC1_SHIFT,
1733 },
1734 },
1735 .dev_attr = &mmc1_pre_es3_dev_attr,
1736 .class = &omap34xx_mmc_class,
1737 };
1738
1739 static struct omap_hwmod omap3xxx_es3plus_mmc1_hwmod = {
1740 .name = "mmc1",
1741 .mpu_irqs = omap34xx_mmc1_mpu_irqs,
1742 .sdma_reqs = omap34xx_mmc1_sdma_reqs,
1743 .opt_clks = omap34xx_mmc1_opt_clks,
1744 .opt_clks_cnt = ARRAY_SIZE(omap34xx_mmc1_opt_clks),
1745 .main_clk = "mmchs1_fck",
1746 .prcm = {
1747 .omap2 = {
1748 .module_offs = CORE_MOD,
1749 .prcm_reg_id = 1,
1750 .module_bit = OMAP3430_EN_MMC1_SHIFT,
1751 .idlest_reg_id = 1,
1752 .idlest_idle_bit = OMAP3430_ST_MMC1_SHIFT,
1753 },
1754 },
1755 .dev_attr = &mmc1_dev_attr,
1756 .class = &omap34xx_mmc_class,
1757 };
1758
1759 /* MMC/SD/SDIO2 */
1760
1761 static struct omap_hwmod_irq_info omap34xx_mmc2_mpu_irqs[] = {
1762 { .irq = INT_24XX_MMC2_IRQ, },
1763 { .irq = -1 }
1764 };
1765
1766 static struct omap_hwmod_dma_info omap34xx_mmc2_sdma_reqs[] = {
1767 { .name = "tx", .dma_req = 47, },
1768 { .name = "rx", .dma_req = 48, },
1769 { .dma_req = -1 }
1770 };
1771
1772 static struct omap_hwmod_opt_clk omap34xx_mmc2_opt_clks[] = {
1773 { .role = "dbck", .clk = "omap_32k_fck", },
1774 };
1775
1776 /* See 35xx errata 2.1.1.128 in SPRZ278F */
1777 static struct omap_mmc_dev_attr mmc2_pre_es3_dev_attr = {
1778 .flags = OMAP_HSMMC_BROKEN_MULTIBLOCK_READ,
1779 };
1780
1781 static struct omap_hwmod omap3xxx_pre_es3_mmc2_hwmod = {
1782 .name = "mmc2",
1783 .mpu_irqs = omap34xx_mmc2_mpu_irqs,
1784 .sdma_reqs = omap34xx_mmc2_sdma_reqs,
1785 .opt_clks = omap34xx_mmc2_opt_clks,
1786 .opt_clks_cnt = ARRAY_SIZE(omap34xx_mmc2_opt_clks),
1787 .main_clk = "mmchs2_fck",
1788 .prcm = {
1789 .omap2 = {
1790 .module_offs = CORE_MOD,
1791 .prcm_reg_id = 1,
1792 .module_bit = OMAP3430_EN_MMC2_SHIFT,
1793 .idlest_reg_id = 1,
1794 .idlest_idle_bit = OMAP3430_ST_MMC2_SHIFT,
1795 },
1796 },
1797 .dev_attr = &mmc2_pre_es3_dev_attr,
1798 .class = &omap34xx_mmc_class,
1799 };
1800
1801 static struct omap_hwmod omap3xxx_es3plus_mmc2_hwmod = {
1802 .name = "mmc2",
1803 .mpu_irqs = omap34xx_mmc2_mpu_irqs,
1804 .sdma_reqs = omap34xx_mmc2_sdma_reqs,
1805 .opt_clks = omap34xx_mmc2_opt_clks,
1806 .opt_clks_cnt = ARRAY_SIZE(omap34xx_mmc2_opt_clks),
1807 .main_clk = "mmchs2_fck",
1808 .prcm = {
1809 .omap2 = {
1810 .module_offs = CORE_MOD,
1811 .prcm_reg_id = 1,
1812 .module_bit = OMAP3430_EN_MMC2_SHIFT,
1813 .idlest_reg_id = 1,
1814 .idlest_idle_bit = OMAP3430_ST_MMC2_SHIFT,
1815 },
1816 },
1817 .class = &omap34xx_mmc_class,
1818 };
1819
1820 /* MMC/SD/SDIO3 */
1821
1822 static struct omap_hwmod_irq_info omap34xx_mmc3_mpu_irqs[] = {
1823 { .irq = 94, },
1824 { .irq = -1 }
1825 };
1826
1827 static struct omap_hwmod_dma_info omap34xx_mmc3_sdma_reqs[] = {
1828 { .name = "tx", .dma_req = 77, },
1829 { .name = "rx", .dma_req = 78, },
1830 { .dma_req = -1 }
1831 };
1832
1833 static struct omap_hwmod_opt_clk omap34xx_mmc3_opt_clks[] = {
1834 { .role = "dbck", .clk = "omap_32k_fck", },
1835 };
1836
1837 static struct omap_hwmod omap3xxx_mmc3_hwmod = {
1838 .name = "mmc3",
1839 .mpu_irqs = omap34xx_mmc3_mpu_irqs,
1840 .sdma_reqs = omap34xx_mmc3_sdma_reqs,
1841 .opt_clks = omap34xx_mmc3_opt_clks,
1842 .opt_clks_cnt = ARRAY_SIZE(omap34xx_mmc3_opt_clks),
1843 .main_clk = "mmchs3_fck",
1844 .prcm = {
1845 .omap2 = {
1846 .prcm_reg_id = 1,
1847 .module_bit = OMAP3430_EN_MMC3_SHIFT,
1848 .idlest_reg_id = 1,
1849 .idlest_idle_bit = OMAP3430_ST_MMC3_SHIFT,
1850 },
1851 },
1852 .class = &omap34xx_mmc_class,
1853 };
1854
1855 /*
1856 * 'usb_host_hs' class
1857 * high-speed multi-port usb host controller
1858 */
1859
1860 static struct omap_hwmod_class_sysconfig omap3xxx_usb_host_hs_sysc = {
1861 .rev_offs = 0x0000,
1862 .sysc_offs = 0x0010,
1863 .syss_offs = 0x0014,
1864 .sysc_flags = (SYSC_HAS_MIDLEMODE | SYSC_HAS_CLOCKACTIVITY |
1865 SYSC_HAS_SIDLEMODE | SYSC_HAS_ENAWAKEUP |
1866 SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
1867 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1868 MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
1869 .sysc_fields = &omap_hwmod_sysc_type1,
1870 };
1871
1872 static struct omap_hwmod_class omap3xxx_usb_host_hs_hwmod_class = {
1873 .name = "usb_host_hs",
1874 .sysc = &omap3xxx_usb_host_hs_sysc,
1875 };
1876
1877 static struct omap_hwmod_opt_clk omap3xxx_usb_host_hs_opt_clks[] = {
1878 { .role = "ehci_logic_fck", .clk = "usbhost_120m_fck", },
1879 };
1880
1881 static struct omap_hwmod_irq_info omap3xxx_usb_host_hs_irqs[] = {
1882 { .name = "ohci-irq", .irq = 76 },
1883 { .name = "ehci-irq", .irq = 77 },
1884 { .irq = -1 }
1885 };
1886
1887 static struct omap_hwmod omap3xxx_usb_host_hs_hwmod = {
1888 .name = "usb_host_hs",
1889 .class = &omap3xxx_usb_host_hs_hwmod_class,
1890 .clkdm_name = "l3_init_clkdm",
1891 .mpu_irqs = omap3xxx_usb_host_hs_irqs,
1892 .main_clk = "usbhost_48m_fck",
1893 .prcm = {
1894 .omap2 = {
1895 .module_offs = OMAP3430ES2_USBHOST_MOD,
1896 .prcm_reg_id = 1,
1897 .module_bit = OMAP3430ES2_EN_USBHOST1_SHIFT,
1898 .idlest_reg_id = 1,
1899 .idlest_idle_bit = OMAP3430ES2_ST_USBHOST_IDLE_SHIFT,
1900 .idlest_stdby_bit = OMAP3430ES2_ST_USBHOST_STDBY_SHIFT,
1901 },
1902 },
1903 .opt_clks = omap3xxx_usb_host_hs_opt_clks,
1904 .opt_clks_cnt = ARRAY_SIZE(omap3xxx_usb_host_hs_opt_clks),
1905
1906 /*
1907 * Errata: USBHOST Configured In Smart-Idle Can Lead To a Deadlock
1908 * id: i660
1909 *
1910 * Description:
1911 * In the following configuration :
1912 * - USBHOST module is set to smart-idle mode
1913 * - PRCM asserts idle_req to the USBHOST module ( This typically
1914 * happens when the system is going to a low power mode : all ports
1915 * have been suspended, the master part of the USBHOST module has
1916 * entered the standby state, and SW has cut the functional clocks)
1917 * - an USBHOST interrupt occurs before the module is able to answer
1918 * idle_ack, typically a remote wakeup IRQ.
1919 * Then the USB HOST module will enter a deadlock situation where it
1920 * is no more accessible nor functional.
1921 *
1922 * Workaround:
1923 * Don't use smart idle; use only force idle, hence HWMOD_SWSUP_SIDLE
1924 */
1925
1926 /*
1927 * Errata: USB host EHCI may stall when entering smart-standby mode
1928 * Id: i571
1929 *
1930 * Description:
1931 * When the USBHOST module is set to smart-standby mode, and when it is
1932 * ready to enter the standby state (i.e. all ports are suspended and
1933 * all attached devices are in suspend mode), then it can wrongly assert
1934 * the Mstandby signal too early while there are still some residual OCP
1935 * transactions ongoing. If this condition occurs, the internal state
1936 * machine may go to an undefined state and the USB link may be stuck
1937 * upon the next resume.
1938 *
1939 * Workaround:
1940 * Don't use smart standby; use only force standby,
1941 * hence HWMOD_SWSUP_MSTANDBY
1942 */
1943
1944 /*
1945 * During system boot; If the hwmod framework resets the module
1946 * the module will have smart idle settings; which can lead to deadlock
1947 * (above Errata Id:i660); so, dont reset the module during boot;
1948 * Use HWMOD_INIT_NO_RESET.
1949 */
1950
1951 .flags = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY |
1952 HWMOD_INIT_NO_RESET,
1953 };
1954
1955 /*
1956 * 'usb_tll_hs' class
1957 * usb_tll_hs module is the adapter on the usb_host_hs ports
1958 */
1959 static struct omap_hwmod_class_sysconfig omap3xxx_usb_tll_hs_sysc = {
1960 .rev_offs = 0x0000,
1961 .sysc_offs = 0x0010,
1962 .syss_offs = 0x0014,
1963 .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
1964 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
1965 SYSC_HAS_AUTOIDLE),
1966 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1967 .sysc_fields = &omap_hwmod_sysc_type1,
1968 };
1969
1970 static struct omap_hwmod_class omap3xxx_usb_tll_hs_hwmod_class = {
1971 .name = "usb_tll_hs",
1972 .sysc = &omap3xxx_usb_tll_hs_sysc,
1973 };
1974
1975 static struct omap_hwmod_irq_info omap3xxx_usb_tll_hs_irqs[] = {
1976 { .name = "tll-irq", .irq = 78 },
1977 { .irq = -1 }
1978 };
1979
1980 static struct omap_hwmod omap3xxx_usb_tll_hs_hwmod = {
1981 .name = "usb_tll_hs",
1982 .class = &omap3xxx_usb_tll_hs_hwmod_class,
1983 .clkdm_name = "l3_init_clkdm",
1984 .mpu_irqs = omap3xxx_usb_tll_hs_irqs,
1985 .main_clk = "usbtll_fck",
1986 .prcm = {
1987 .omap2 = {
1988 .module_offs = CORE_MOD,
1989 .prcm_reg_id = 3,
1990 .module_bit = OMAP3430ES2_EN_USBTLL_SHIFT,
1991 .idlest_reg_id = 3,
1992 .idlest_idle_bit = OMAP3430ES2_ST_USBTLL_SHIFT,
1993 },
1994 },
1995 };
1996
1997 static struct omap_hwmod omap3xxx_hdq1w_hwmod = {
1998 .name = "hdq1w",
1999 .mpu_irqs = omap2_hdq1w_mpu_irqs,
2000 .main_clk = "hdq_fck",
2001 .prcm = {
2002 .omap2 = {
2003 .module_offs = CORE_MOD,
2004 .prcm_reg_id = 1,
2005 .module_bit = OMAP3430_EN_HDQ_SHIFT,
2006 .idlest_reg_id = 1,
2007 .idlest_idle_bit = OMAP3430_ST_HDQ_SHIFT,
2008 },
2009 },
2010 .class = &omap2_hdq1w_class,
2011 };
2012
2013 /*
2014 * '32K sync counter' class
2015 * 32-bit ordinary counter, clocked by the falling edge of the 32 khz clock
2016 */
2017 static struct omap_hwmod_class_sysconfig omap3xxx_counter_sysc = {
2018 .rev_offs = 0x0000,
2019 .sysc_offs = 0x0004,
2020 .sysc_flags = SYSC_HAS_SIDLEMODE,
2021 .idlemodes = (SIDLE_FORCE | SIDLE_NO),
2022 .sysc_fields = &omap_hwmod_sysc_type1,
2023 };
2024
2025 static struct omap_hwmod_class omap3xxx_counter_hwmod_class = {
2026 .name = "counter",
2027 .sysc = &omap3xxx_counter_sysc,
2028 };
2029
2030 static struct omap_hwmod omap3xxx_counter_32k_hwmod = {
2031 .name = "counter_32k",
2032 .class = &omap3xxx_counter_hwmod_class,
2033 .clkdm_name = "wkup_clkdm",
2034 .flags = HWMOD_SWSUP_SIDLE,
2035 .main_clk = "wkup_32k_fck",
2036 .prcm = {
2037 .omap2 = {
2038 .module_offs = WKUP_MOD,
2039 .prcm_reg_id = 1,
2040 .module_bit = OMAP3430_ST_32KSYNC_SHIFT,
2041 .idlest_reg_id = 1,
2042 .idlest_idle_bit = OMAP3430_ST_32KSYNC_SHIFT,
2043 },
2044 },
2045 };
2046
2047 /*
2048 * interfaces
2049 */
2050
2051 /* L3 -> L4_CORE interface */
2052 static struct omap_hwmod_ocp_if omap3xxx_l3_main__l4_core = {
2053 .master = &omap3xxx_l3_main_hwmod,
2054 .slave = &omap3xxx_l4_core_hwmod,
2055 .user = OCP_USER_MPU | OCP_USER_SDMA,
2056 };
2057
2058 /* L3 -> L4_PER interface */
2059 static struct omap_hwmod_ocp_if omap3xxx_l3_main__l4_per = {
2060 .master = &omap3xxx_l3_main_hwmod,
2061 .slave = &omap3xxx_l4_per_hwmod,
2062 .user = OCP_USER_MPU | OCP_USER_SDMA,
2063 };
2064
2065 static struct omap_hwmod_addr_space omap3xxx_l3_main_addrs[] = {
2066 {
2067 .pa_start = 0x68000000,
2068 .pa_end = 0x6800ffff,
2069 .flags = ADDR_TYPE_RT,
2070 },
2071 { }
2072 };
2073
2074 /* MPU -> L3 interface */
2075 static struct omap_hwmod_ocp_if omap3xxx_mpu__l3_main = {
2076 .master = &omap3xxx_mpu_hwmod,
2077 .slave = &omap3xxx_l3_main_hwmod,
2078 .addr = omap3xxx_l3_main_addrs,
2079 .user = OCP_USER_MPU,
2080 };
2081
2082 /* DSS -> l3 */
2083 static struct omap_hwmod_ocp_if omap3430es1_dss__l3 = {
2084 .master = &omap3430es1_dss_core_hwmod,
2085 .slave = &omap3xxx_l3_main_hwmod,
2086 .user = OCP_USER_MPU | OCP_USER_SDMA,
2087 };
2088
2089 static struct omap_hwmod_ocp_if omap3xxx_dss__l3 = {
2090 .master = &omap3xxx_dss_core_hwmod,
2091 .slave = &omap3xxx_l3_main_hwmod,
2092 .fw = {
2093 .omap2 = {
2094 .l3_perm_bit = OMAP3_L3_CORE_FW_INIT_ID_DSS,
2095 .flags = OMAP_FIREWALL_L3,
2096 }
2097 },
2098 .user = OCP_USER_MPU | OCP_USER_SDMA,
2099 };
2100
2101 /* l3_core -> usbhsotg interface */
2102 static struct omap_hwmod_ocp_if omap3xxx_usbhsotg__l3 = {
2103 .master = &omap3xxx_usbhsotg_hwmod,
2104 .slave = &omap3xxx_l3_main_hwmod,
2105 .clk = "core_l3_ick",
2106 .user = OCP_USER_MPU,
2107 };
2108
2109 /* l3_core -> am35xx_usbhsotg interface */
2110 static struct omap_hwmod_ocp_if am35xx_usbhsotg__l3 = {
2111 .master = &am35xx_usbhsotg_hwmod,
2112 .slave = &omap3xxx_l3_main_hwmod,
2113 .clk = "core_l3_ick",
2114 .user = OCP_USER_MPU,
2115 };
2116 /* L4_CORE -> L4_WKUP interface */
2117 static struct omap_hwmod_ocp_if omap3xxx_l4_core__l4_wkup = {
2118 .master = &omap3xxx_l4_core_hwmod,
2119 .slave = &omap3xxx_l4_wkup_hwmod,
2120 .user = OCP_USER_MPU | OCP_USER_SDMA,
2121 };
2122
2123 /* L4 CORE -> MMC1 interface */
2124 static struct omap_hwmod_ocp_if omap3xxx_l4_core__pre_es3_mmc1 = {
2125 .master = &omap3xxx_l4_core_hwmod,
2126 .slave = &omap3xxx_pre_es3_mmc1_hwmod,
2127 .clk = "mmchs1_ick",
2128 .addr = omap2430_mmc1_addr_space,
2129 .user = OCP_USER_MPU | OCP_USER_SDMA,
2130 .flags = OMAP_FIREWALL_L4
2131 };
2132
2133 static struct omap_hwmod_ocp_if omap3xxx_l4_core__es3plus_mmc1 = {
2134 .master = &omap3xxx_l4_core_hwmod,
2135 .slave = &omap3xxx_es3plus_mmc1_hwmod,
2136 .clk = "mmchs1_ick",
2137 .addr = omap2430_mmc1_addr_space,
2138 .user = OCP_USER_MPU | OCP_USER_SDMA,
2139 .flags = OMAP_FIREWALL_L4
2140 };
2141
2142 /* L4 CORE -> MMC2 interface */
2143 static struct omap_hwmod_ocp_if omap3xxx_l4_core__pre_es3_mmc2 = {
2144 .master = &omap3xxx_l4_core_hwmod,
2145 .slave = &omap3xxx_pre_es3_mmc2_hwmod,
2146 .clk = "mmchs2_ick",
2147 .addr = omap2430_mmc2_addr_space,
2148 .user = OCP_USER_MPU | OCP_USER_SDMA,
2149 .flags = OMAP_FIREWALL_L4
2150 };
2151
2152 static struct omap_hwmod_ocp_if omap3xxx_l4_core__es3plus_mmc2 = {
2153 .master = &omap3xxx_l4_core_hwmod,
2154 .slave = &omap3xxx_es3plus_mmc2_hwmod,
2155 .clk = "mmchs2_ick",
2156 .addr = omap2430_mmc2_addr_space,
2157 .user = OCP_USER_MPU | OCP_USER_SDMA,
2158 .flags = OMAP_FIREWALL_L4
2159 };
2160
2161 /* L4 CORE -> MMC3 interface */
2162 static struct omap_hwmod_addr_space omap3xxx_mmc3_addr_space[] = {
2163 {
2164 .pa_start = 0x480ad000,
2165 .pa_end = 0x480ad1ff,
2166 .flags = ADDR_TYPE_RT,
2167 },
2168 { }
2169 };
2170
2171 static struct omap_hwmod_ocp_if omap3xxx_l4_core__mmc3 = {
2172 .master = &omap3xxx_l4_core_hwmod,
2173 .slave = &omap3xxx_mmc3_hwmod,
2174 .clk = "mmchs3_ick",
2175 .addr = omap3xxx_mmc3_addr_space,
2176 .user = OCP_USER_MPU | OCP_USER_SDMA,
2177 .flags = OMAP_FIREWALL_L4
2178 };
2179
2180 /* L4 CORE -> UART1 interface */
2181 static struct omap_hwmod_addr_space omap3xxx_uart1_addr_space[] = {
2182 {
2183 .pa_start = OMAP3_UART1_BASE,
2184 .pa_end = OMAP3_UART1_BASE + SZ_8K - 1,
2185 .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
2186 },
2187 { }
2188 };
2189
2190 static struct omap_hwmod_ocp_if omap3_l4_core__uart1 = {
2191 .master = &omap3xxx_l4_core_hwmod,
2192 .slave = &omap3xxx_uart1_hwmod,
2193 .clk = "uart1_ick",
2194 .addr = omap3xxx_uart1_addr_space,
2195 .user = OCP_USER_MPU | OCP_USER_SDMA,
2196 };
2197
2198 /* L4 CORE -> UART2 interface */
2199 static struct omap_hwmod_addr_space omap3xxx_uart2_addr_space[] = {
2200 {
2201 .pa_start = OMAP3_UART2_BASE,
2202 .pa_end = OMAP3_UART2_BASE + SZ_1K - 1,
2203 .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
2204 },
2205 { }
2206 };
2207
2208 static struct omap_hwmod_ocp_if omap3_l4_core__uart2 = {
2209 .master = &omap3xxx_l4_core_hwmod,
2210 .slave = &omap3xxx_uart2_hwmod,
2211 .clk = "uart2_ick",
2212 .addr = omap3xxx_uart2_addr_space,
2213 .user = OCP_USER_MPU | OCP_USER_SDMA,
2214 };
2215
2216 /* L4 PER -> UART3 interface */
2217 static struct omap_hwmod_addr_space omap3xxx_uart3_addr_space[] = {
2218 {
2219 .pa_start = OMAP3_UART3_BASE,
2220 .pa_end = OMAP3_UART3_BASE + SZ_1K - 1,
2221 .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
2222 },
2223 { }
2224 };
2225
2226 static struct omap_hwmod_ocp_if omap3_l4_per__uart3 = {
2227 .master = &omap3xxx_l4_per_hwmod,
2228 .slave = &omap3xxx_uart3_hwmod,
2229 .clk = "uart3_ick",
2230 .addr = omap3xxx_uart3_addr_space,
2231 .user = OCP_USER_MPU | OCP_USER_SDMA,
2232 };
2233
2234 /* L4 PER -> UART4 interface */
2235 static struct omap_hwmod_addr_space omap36xx_uart4_addr_space[] = {
2236 {
2237 .pa_start = OMAP3_UART4_BASE,
2238 .pa_end = OMAP3_UART4_BASE + SZ_1K - 1,
2239 .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
2240 },
2241 { }
2242 };
2243
2244 static struct omap_hwmod_ocp_if omap36xx_l4_per__uart4 = {
2245 .master = &omap3xxx_l4_per_hwmod,
2246 .slave = &omap36xx_uart4_hwmod,
2247 .clk = "uart4_ick",
2248 .addr = omap36xx_uart4_addr_space,
2249 .user = OCP_USER_MPU | OCP_USER_SDMA,
2250 };
2251
2252 /* AM35xx: L4 CORE -> UART4 interface */
2253 static struct omap_hwmod_addr_space am35xx_uart4_addr_space[] = {
2254 {
2255 .pa_start = OMAP3_UART4_AM35XX_BASE,
2256 .pa_end = OMAP3_UART4_AM35XX_BASE + SZ_1K - 1,
2257 .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
2258 },
2259 };
2260
2261 static struct omap_hwmod_ocp_if am35xx_l4_core__uart4 = {
2262 .master = &omap3xxx_l4_core_hwmod,
2263 .slave = &am35xx_uart4_hwmod,
2264 .clk = "uart4_ick",
2265 .addr = am35xx_uart4_addr_space,
2266 .user = OCP_USER_MPU | OCP_USER_SDMA,
2267 };
2268
2269 /* L4 CORE -> I2C1 interface */
2270 static struct omap_hwmod_ocp_if omap3_l4_core__i2c1 = {
2271 .master = &omap3xxx_l4_core_hwmod,
2272 .slave = &omap3xxx_i2c1_hwmod,
2273 .clk = "i2c1_ick",
2274 .addr = omap2_i2c1_addr_space,
2275 .fw = {
2276 .omap2 = {
2277 .l4_fw_region = OMAP3_L4_CORE_FW_I2C1_REGION,
2278 .l4_prot_group = 7,
2279 .flags = OMAP_FIREWALL_L4,
2280 }
2281 },
2282 .user = OCP_USER_MPU | OCP_USER_SDMA,
2283 };
2284
2285 /* L4 CORE -> I2C2 interface */
2286 static struct omap_hwmod_ocp_if omap3_l4_core__i2c2 = {
2287 .master = &omap3xxx_l4_core_hwmod,
2288 .slave = &omap3xxx_i2c2_hwmod,
2289 .clk = "i2c2_ick",
2290 .addr = omap2_i2c2_addr_space,
2291 .fw = {
2292 .omap2 = {
2293 .l4_fw_region = OMAP3_L4_CORE_FW_I2C2_REGION,
2294 .l4_prot_group = 7,
2295 .flags = OMAP_FIREWALL_L4,
2296 }
2297 },
2298 .user = OCP_USER_MPU | OCP_USER_SDMA,
2299 };
2300
2301 /* L4 CORE -> I2C3 interface */
2302 static struct omap_hwmod_addr_space omap3xxx_i2c3_addr_space[] = {
2303 {
2304 .pa_start = 0x48060000,
2305 .pa_end = 0x48060000 + SZ_128 - 1,
2306 .flags = ADDR_TYPE_RT,
2307 },
2308 { }
2309 };
2310
2311 static struct omap_hwmod_ocp_if omap3_l4_core__i2c3 = {
2312 .master = &omap3xxx_l4_core_hwmod,
2313 .slave = &omap3xxx_i2c3_hwmod,
2314 .clk = "i2c3_ick",
2315 .addr = omap3xxx_i2c3_addr_space,
2316 .fw = {
2317 .omap2 = {
2318 .l4_fw_region = OMAP3_L4_CORE_FW_I2C3_REGION,
2319 .l4_prot_group = 7,
2320 .flags = OMAP_FIREWALL_L4,
2321 }
2322 },
2323 .user = OCP_USER_MPU | OCP_USER_SDMA,
2324 };
2325
2326 /* L4 CORE -> SR1 interface */
2327 static struct omap_hwmod_addr_space omap3_sr1_addr_space[] = {
2328 {
2329 .pa_start = OMAP34XX_SR1_BASE,
2330 .pa_end = OMAP34XX_SR1_BASE + SZ_1K - 1,
2331 .flags = ADDR_TYPE_RT,
2332 },
2333 { }
2334 };
2335
2336 static struct omap_hwmod_ocp_if omap34xx_l4_core__sr1 = {
2337 .master = &omap3xxx_l4_core_hwmod,
2338 .slave = &omap34xx_sr1_hwmod,
2339 .clk = "sr_l4_ick",
2340 .addr = omap3_sr1_addr_space,
2341 .user = OCP_USER_MPU,
2342 };
2343
2344 static struct omap_hwmod_ocp_if omap36xx_l4_core__sr1 = {
2345 .master = &omap3xxx_l4_core_hwmod,
2346 .slave = &omap36xx_sr1_hwmod,
2347 .clk = "sr_l4_ick",
2348 .addr = omap3_sr1_addr_space,
2349 .user = OCP_USER_MPU,
2350 };
2351
2352 /* L4 CORE -> SR1 interface */
2353 static struct omap_hwmod_addr_space omap3_sr2_addr_space[] = {
2354 {
2355 .pa_start = OMAP34XX_SR2_BASE,
2356 .pa_end = OMAP34XX_SR2_BASE + SZ_1K - 1,
2357 .flags = ADDR_TYPE_RT,
2358 },
2359 { }
2360 };
2361
2362 static struct omap_hwmod_ocp_if omap34xx_l4_core__sr2 = {
2363 .master = &omap3xxx_l4_core_hwmod,
2364 .slave = &omap34xx_sr2_hwmod,
2365 .clk = "sr_l4_ick",
2366 .addr = omap3_sr2_addr_space,
2367 .user = OCP_USER_MPU,
2368 };
2369
2370 static struct omap_hwmod_ocp_if omap36xx_l4_core__sr2 = {
2371 .master = &omap3xxx_l4_core_hwmod,
2372 .slave = &omap36xx_sr2_hwmod,
2373 .clk = "sr_l4_ick",
2374 .addr = omap3_sr2_addr_space,
2375 .user = OCP_USER_MPU,
2376 };
2377
2378 static struct omap_hwmod_addr_space omap3xxx_usbhsotg_addrs[] = {
2379 {
2380 .pa_start = OMAP34XX_HSUSB_OTG_BASE,
2381 .pa_end = OMAP34XX_HSUSB_OTG_BASE + SZ_4K - 1,
2382 .flags = ADDR_TYPE_RT
2383 },
2384 { }
2385 };
2386
2387 /* l4_core -> usbhsotg */
2388 static struct omap_hwmod_ocp_if omap3xxx_l4_core__usbhsotg = {
2389 .master = &omap3xxx_l4_core_hwmod,
2390 .slave = &omap3xxx_usbhsotg_hwmod,
2391 .clk = "l4_ick",
2392 .addr = omap3xxx_usbhsotg_addrs,
2393 .user = OCP_USER_MPU,
2394 };
2395
2396 static struct omap_hwmod_addr_space am35xx_usbhsotg_addrs[] = {
2397 {
2398 .pa_start = AM35XX_IPSS_USBOTGSS_BASE,
2399 .pa_end = AM35XX_IPSS_USBOTGSS_BASE + SZ_4K - 1,
2400 .flags = ADDR_TYPE_RT
2401 },
2402 { }
2403 };
2404
2405 /* l4_core -> usbhsotg */
2406 static struct omap_hwmod_ocp_if am35xx_l4_core__usbhsotg = {
2407 .master = &omap3xxx_l4_core_hwmod,
2408 .slave = &am35xx_usbhsotg_hwmod,
2409 .clk = "l4_ick",
2410 .addr = am35xx_usbhsotg_addrs,
2411 .user = OCP_USER_MPU,
2412 };
2413
2414 /* L4_WKUP -> L4_SEC interface */
2415 static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__l4_sec = {
2416 .master = &omap3xxx_l4_wkup_hwmod,
2417 .slave = &omap3xxx_l4_sec_hwmod,
2418 .user = OCP_USER_MPU | OCP_USER_SDMA,
2419 };
2420
2421 /* IVA2 <- L3 interface */
2422 static struct omap_hwmod_ocp_if omap3xxx_l3__iva = {
2423 .master = &omap3xxx_l3_main_hwmod,
2424 .slave = &omap3xxx_iva_hwmod,
2425 .clk = "core_l3_ick",
2426 .user = OCP_USER_MPU | OCP_USER_SDMA,
2427 };
2428
2429 static struct omap_hwmod_addr_space omap3xxx_timer1_addrs[] = {
2430 {
2431 .pa_start = 0x48318000,
2432 .pa_end = 0x48318000 + SZ_1K - 1,
2433 .flags = ADDR_TYPE_RT
2434 },
2435 { }
2436 };
2437
2438 /* l4_wkup -> timer1 */
2439 static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__timer1 = {
2440 .master = &omap3xxx_l4_wkup_hwmod,
2441 .slave = &omap3xxx_timer1_hwmod,
2442 .clk = "gpt1_ick",
2443 .addr = omap3xxx_timer1_addrs,
2444 .user = OCP_USER_MPU | OCP_USER_SDMA,
2445 };
2446
2447 static struct omap_hwmod_addr_space omap3xxx_timer2_addrs[] = {
2448 {
2449 .pa_start = 0x49032000,
2450 .pa_end = 0x49032000 + SZ_1K - 1,
2451 .flags = ADDR_TYPE_RT
2452 },
2453 { }
2454 };
2455
2456 /* l4_per -> timer2 */
2457 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer2 = {
2458 .master = &omap3xxx_l4_per_hwmod,
2459 .slave = &omap3xxx_timer2_hwmod,
2460 .clk = "gpt2_ick",
2461 .addr = omap3xxx_timer2_addrs,
2462 .user = OCP_USER_MPU | OCP_USER_SDMA,
2463 };
2464
2465 static struct omap_hwmod_addr_space omap3xxx_timer3_addrs[] = {
2466 {
2467 .pa_start = 0x49034000,
2468 .pa_end = 0x49034000 + SZ_1K - 1,
2469 .flags = ADDR_TYPE_RT
2470 },
2471 { }
2472 };
2473
2474 /* l4_per -> timer3 */
2475 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer3 = {
2476 .master = &omap3xxx_l4_per_hwmod,
2477 .slave = &omap3xxx_timer3_hwmod,
2478 .clk = "gpt3_ick",
2479 .addr = omap3xxx_timer3_addrs,
2480 .user = OCP_USER_MPU | OCP_USER_SDMA,
2481 };
2482
2483 static struct omap_hwmod_addr_space omap3xxx_timer4_addrs[] = {
2484 {
2485 .pa_start = 0x49036000,
2486 .pa_end = 0x49036000 + SZ_1K - 1,
2487 .flags = ADDR_TYPE_RT
2488 },
2489 { }
2490 };
2491
2492 /* l4_per -> timer4 */
2493 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer4 = {
2494 .master = &omap3xxx_l4_per_hwmod,
2495 .slave = &omap3xxx_timer4_hwmod,
2496 .clk = "gpt4_ick",
2497 .addr = omap3xxx_timer4_addrs,
2498 .user = OCP_USER_MPU | OCP_USER_SDMA,
2499 };
2500
2501 static struct omap_hwmod_addr_space omap3xxx_timer5_addrs[] = {
2502 {
2503 .pa_start = 0x49038000,
2504 .pa_end = 0x49038000 + SZ_1K - 1,
2505 .flags = ADDR_TYPE_RT
2506 },
2507 { }
2508 };
2509
2510 /* l4_per -> timer5 */
2511 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer5 = {
2512 .master = &omap3xxx_l4_per_hwmod,
2513 .slave = &omap3xxx_timer5_hwmod,
2514 .clk = "gpt5_ick",
2515 .addr = omap3xxx_timer5_addrs,
2516 .user = OCP_USER_MPU | OCP_USER_SDMA,
2517 };
2518
2519 static struct omap_hwmod_addr_space omap3xxx_timer6_addrs[] = {
2520 {
2521 .pa_start = 0x4903A000,
2522 .pa_end = 0x4903A000 + SZ_1K - 1,
2523 .flags = ADDR_TYPE_RT
2524 },
2525 { }
2526 };
2527
2528 /* l4_per -> timer6 */
2529 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer6 = {
2530 .master = &omap3xxx_l4_per_hwmod,
2531 .slave = &omap3xxx_timer6_hwmod,
2532 .clk = "gpt6_ick",
2533 .addr = omap3xxx_timer6_addrs,
2534 .user = OCP_USER_MPU | OCP_USER_SDMA,
2535 };
2536
2537 static struct omap_hwmod_addr_space omap3xxx_timer7_addrs[] = {
2538 {
2539 .pa_start = 0x4903C000,
2540 .pa_end = 0x4903C000 + SZ_1K - 1,
2541 .flags = ADDR_TYPE_RT
2542 },
2543 { }
2544 };
2545
2546 /* l4_per -> timer7 */
2547 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer7 = {
2548 .master = &omap3xxx_l4_per_hwmod,
2549 .slave = &omap3xxx_timer7_hwmod,
2550 .clk = "gpt7_ick",
2551 .addr = omap3xxx_timer7_addrs,
2552 .user = OCP_USER_MPU | OCP_USER_SDMA,
2553 };
2554
2555 static struct omap_hwmod_addr_space omap3xxx_timer8_addrs[] = {
2556 {
2557 .pa_start = 0x4903E000,
2558 .pa_end = 0x4903E000 + SZ_1K - 1,
2559 .flags = ADDR_TYPE_RT
2560 },
2561 { }
2562 };
2563
2564 /* l4_per -> timer8 */
2565 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer8 = {
2566 .master = &omap3xxx_l4_per_hwmod,
2567 .slave = &omap3xxx_timer8_hwmod,
2568 .clk = "gpt8_ick",
2569 .addr = omap3xxx_timer8_addrs,
2570 .user = OCP_USER_MPU | OCP_USER_SDMA,
2571 };
2572
2573 static struct omap_hwmod_addr_space omap3xxx_timer9_addrs[] = {
2574 {
2575 .pa_start = 0x49040000,
2576 .pa_end = 0x49040000 + SZ_1K - 1,
2577 .flags = ADDR_TYPE_RT
2578 },
2579 { }
2580 };
2581
2582 /* l4_per -> timer9 */
2583 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer9 = {
2584 .master = &omap3xxx_l4_per_hwmod,
2585 .slave = &omap3xxx_timer9_hwmod,
2586 .clk = "gpt9_ick",
2587 .addr = omap3xxx_timer9_addrs,
2588 .user = OCP_USER_MPU | OCP_USER_SDMA,
2589 };
2590
2591 /* l4_core -> timer10 */
2592 static struct omap_hwmod_ocp_if omap3xxx_l4_core__timer10 = {
2593 .master = &omap3xxx_l4_core_hwmod,
2594 .slave = &omap3xxx_timer10_hwmod,
2595 .clk = "gpt10_ick",
2596 .addr = omap2_timer10_addrs,
2597 .user = OCP_USER_MPU | OCP_USER_SDMA,
2598 };
2599
2600 /* l4_core -> timer11 */
2601 static struct omap_hwmod_ocp_if omap3xxx_l4_core__timer11 = {
2602 .master = &omap3xxx_l4_core_hwmod,
2603 .slave = &omap3xxx_timer11_hwmod,
2604 .clk = "gpt11_ick",
2605 .addr = omap2_timer11_addrs,
2606 .user = OCP_USER_MPU | OCP_USER_SDMA,
2607 };
2608
2609 static struct omap_hwmod_addr_space omap3xxx_timer12_addrs[] = {
2610 {
2611 .pa_start = 0x48304000,
2612 .pa_end = 0x48304000 + SZ_1K - 1,
2613 .flags = ADDR_TYPE_RT
2614 },
2615 { }
2616 };
2617
2618 /* l4_core -> timer12 */
2619 static struct omap_hwmod_ocp_if omap3xxx_l4_sec__timer12 = {
2620 .master = &omap3xxx_l4_sec_hwmod,
2621 .slave = &omap3xxx_timer12_hwmod,
2622 .clk = "gpt12_ick",
2623 .addr = omap3xxx_timer12_addrs,
2624 .user = OCP_USER_MPU | OCP_USER_SDMA,
2625 };
2626
2627 /* l4_wkup -> wd_timer2 */
2628 static struct omap_hwmod_addr_space omap3xxx_wd_timer2_addrs[] = {
2629 {
2630 .pa_start = 0x48314000,
2631 .pa_end = 0x4831407f,
2632 .flags = ADDR_TYPE_RT
2633 },
2634 { }
2635 };
2636
2637 static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__wd_timer2 = {
2638 .master = &omap3xxx_l4_wkup_hwmod,
2639 .slave = &omap3xxx_wd_timer2_hwmod,
2640 .clk = "wdt2_ick",
2641 .addr = omap3xxx_wd_timer2_addrs,
2642 .user = OCP_USER_MPU | OCP_USER_SDMA,
2643 };
2644
2645 /* l4_core -> dss */
2646 static struct omap_hwmod_ocp_if omap3430es1_l4_core__dss = {
2647 .master = &omap3xxx_l4_core_hwmod,
2648 .slave = &omap3430es1_dss_core_hwmod,
2649 .clk = "dss_ick",
2650 .addr = omap2_dss_addrs,
2651 .fw = {
2652 .omap2 = {
2653 .l4_fw_region = OMAP3ES1_L4_CORE_FW_DSS_CORE_REGION,
2654 .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP,
2655 .flags = OMAP_FIREWALL_L4,
2656 }
2657 },
2658 .user = OCP_USER_MPU | OCP_USER_SDMA,
2659 };
2660
2661 static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss = {
2662 .master = &omap3xxx_l4_core_hwmod,
2663 .slave = &omap3xxx_dss_core_hwmod,
2664 .clk = "dss_ick",
2665 .addr = omap2_dss_addrs,
2666 .fw = {
2667 .omap2 = {
2668 .l4_fw_region = OMAP3_L4_CORE_FW_DSS_CORE_REGION,
2669 .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP,
2670 .flags = OMAP_FIREWALL_L4,
2671 }
2672 },
2673 .user = OCP_USER_MPU | OCP_USER_SDMA,
2674 };
2675
2676 /* l4_core -> dss_dispc */
2677 static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_dispc = {
2678 .master = &omap3xxx_l4_core_hwmod,
2679 .slave = &omap3xxx_dss_dispc_hwmod,
2680 .clk = "dss_ick",
2681 .addr = omap2_dss_dispc_addrs,
2682 .fw = {
2683 .omap2 = {
2684 .l4_fw_region = OMAP3_L4_CORE_FW_DSS_DISPC_REGION,
2685 .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP,
2686 .flags = OMAP_FIREWALL_L4,
2687 }
2688 },
2689 .user = OCP_USER_MPU | OCP_USER_SDMA,
2690 };
2691
2692 static struct omap_hwmod_addr_space omap3xxx_dss_dsi1_addrs[] = {
2693 {
2694 .pa_start = 0x4804FC00,
2695 .pa_end = 0x4804FFFF,
2696 .flags = ADDR_TYPE_RT
2697 },
2698 { }
2699 };
2700
2701 /* l4_core -> dss_dsi1 */
2702 static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_dsi1 = {
2703 .master = &omap3xxx_l4_core_hwmod,
2704 .slave = &omap3xxx_dss_dsi1_hwmod,
2705 .clk = "dss_ick",
2706 .addr = omap3xxx_dss_dsi1_addrs,
2707 .fw = {
2708 .omap2 = {
2709 .l4_fw_region = OMAP3_L4_CORE_FW_DSS_DSI_REGION,
2710 .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP,
2711 .flags = OMAP_FIREWALL_L4,
2712 }
2713 },
2714 .user = OCP_USER_MPU | OCP_USER_SDMA,
2715 };
2716
2717 /* l4_core -> dss_rfbi */
2718 static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_rfbi = {
2719 .master = &omap3xxx_l4_core_hwmod,
2720 .slave = &omap3xxx_dss_rfbi_hwmod,
2721 .clk = "dss_ick",
2722 .addr = omap2_dss_rfbi_addrs,
2723 .fw = {
2724 .omap2 = {
2725 .l4_fw_region = OMAP3_L4_CORE_FW_DSS_RFBI_REGION,
2726 .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP ,
2727 .flags = OMAP_FIREWALL_L4,
2728 }
2729 },
2730 .user = OCP_USER_MPU | OCP_USER_SDMA,
2731 };
2732
2733 /* l4_core -> dss_venc */
2734 static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_venc = {
2735 .master = &omap3xxx_l4_core_hwmod,
2736 .slave = &omap3xxx_dss_venc_hwmod,
2737 .clk = "dss_ick",
2738 .addr = omap2_dss_venc_addrs,
2739 .fw = {
2740 .omap2 = {
2741 .l4_fw_region = OMAP3_L4_CORE_FW_DSS_VENC_REGION,
2742 .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP,
2743 .flags = OMAP_FIREWALL_L4,
2744 }
2745 },
2746 .flags = OCPIF_SWSUP_IDLE,
2747 .user = OCP_USER_MPU | OCP_USER_SDMA,
2748 };
2749
2750 /* l4_wkup -> gpio1 */
2751 static struct omap_hwmod_addr_space omap3xxx_gpio1_addrs[] = {
2752 {
2753 .pa_start = 0x48310000,
2754 .pa_end = 0x483101ff,
2755 .flags = ADDR_TYPE_RT
2756 },
2757 { }
2758 };
2759
2760 static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__gpio1 = {
2761 .master = &omap3xxx_l4_wkup_hwmod,
2762 .slave = &omap3xxx_gpio1_hwmod,
2763 .addr = omap3xxx_gpio1_addrs,
2764 .user = OCP_USER_MPU | OCP_USER_SDMA,
2765 };
2766
2767 /* l4_per -> gpio2 */
2768 static struct omap_hwmod_addr_space omap3xxx_gpio2_addrs[] = {
2769 {
2770 .pa_start = 0x49050000,
2771 .pa_end = 0x490501ff,
2772 .flags = ADDR_TYPE_RT
2773 },
2774 { }
2775 };
2776
2777 static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio2 = {
2778 .master = &omap3xxx_l4_per_hwmod,
2779 .slave = &omap3xxx_gpio2_hwmod,
2780 .addr = omap3xxx_gpio2_addrs,
2781 .user = OCP_USER_MPU | OCP_USER_SDMA,
2782 };
2783
2784 /* l4_per -> gpio3 */
2785 static struct omap_hwmod_addr_space omap3xxx_gpio3_addrs[] = {
2786 {
2787 .pa_start = 0x49052000,
2788 .pa_end = 0x490521ff,
2789 .flags = ADDR_TYPE_RT
2790 },
2791 { }
2792 };
2793
2794 static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio3 = {
2795 .master = &omap3xxx_l4_per_hwmod,
2796 .slave = &omap3xxx_gpio3_hwmod,
2797 .addr = omap3xxx_gpio3_addrs,
2798 .user = OCP_USER_MPU | OCP_USER_SDMA,
2799 };
2800
2801 /* l4_per -> gpio4 */
2802 static struct omap_hwmod_addr_space omap3xxx_gpio4_addrs[] = {
2803 {
2804 .pa_start = 0x49054000,
2805 .pa_end = 0x490541ff,
2806 .flags = ADDR_TYPE_RT
2807 },
2808 { }
2809 };
2810
2811 static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio4 = {
2812 .master = &omap3xxx_l4_per_hwmod,
2813 .slave = &omap3xxx_gpio4_hwmod,
2814 .addr = omap3xxx_gpio4_addrs,
2815 .user = OCP_USER_MPU | OCP_USER_SDMA,
2816 };
2817
2818 /* l4_per -> gpio5 */
2819 static struct omap_hwmod_addr_space omap3xxx_gpio5_addrs[] = {
2820 {
2821 .pa_start = 0x49056000,
2822 .pa_end = 0x490561ff,
2823 .flags = ADDR_TYPE_RT
2824 },
2825 { }
2826 };
2827
2828 static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio5 = {
2829 .master = &omap3xxx_l4_per_hwmod,
2830 .slave = &omap3xxx_gpio5_hwmod,
2831 .addr = omap3xxx_gpio5_addrs,
2832 .user = OCP_USER_MPU | OCP_USER_SDMA,
2833 };
2834
2835 /* l4_per -> gpio6 */
2836 static struct omap_hwmod_addr_space omap3xxx_gpio6_addrs[] = {
2837 {
2838 .pa_start = 0x49058000,
2839 .pa_end = 0x490581ff,
2840 .flags = ADDR_TYPE_RT
2841 },
2842 { }
2843 };
2844
2845 static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio6 = {
2846 .master = &omap3xxx_l4_per_hwmod,
2847 .slave = &omap3xxx_gpio6_hwmod,
2848 .addr = omap3xxx_gpio6_addrs,
2849 .user = OCP_USER_MPU | OCP_USER_SDMA,
2850 };
2851
2852 /* dma_system -> L3 */
2853 static struct omap_hwmod_ocp_if omap3xxx_dma_system__l3 = {
2854 .master = &omap3xxx_dma_system_hwmod,
2855 .slave = &omap3xxx_l3_main_hwmod,
2856 .clk = "core_l3_ick",
2857 .user = OCP_USER_MPU | OCP_USER_SDMA,
2858 };
2859
2860 static struct omap_hwmod_addr_space omap3xxx_dma_system_addrs[] = {
2861 {
2862 .pa_start = 0x48056000,
2863 .pa_end = 0x48056fff,
2864 .flags = ADDR_TYPE_RT
2865 },
2866 { }
2867 };
2868
2869 /* l4_cfg -> dma_system */
2870 static struct omap_hwmod_ocp_if omap3xxx_l4_core__dma_system = {
2871 .master = &omap3xxx_l4_core_hwmod,
2872 .slave = &omap3xxx_dma_system_hwmod,
2873 .clk = "core_l4_ick",
2874 .addr = omap3xxx_dma_system_addrs,
2875 .user = OCP_USER_MPU | OCP_USER_SDMA,
2876 };
2877
2878 static struct omap_hwmod_addr_space omap3xxx_mcbsp1_addrs[] = {
2879 {
2880 .name = "mpu",
2881 .pa_start = 0x48074000,
2882 .pa_end = 0x480740ff,
2883 .flags = ADDR_TYPE_RT
2884 },
2885 { }
2886 };
2887
2888 /* l4_core -> mcbsp1 */
2889 static struct omap_hwmod_ocp_if omap3xxx_l4_core__mcbsp1 = {
2890 .master = &omap3xxx_l4_core_hwmod,
2891 .slave = &omap3xxx_mcbsp1_hwmod,
2892 .clk = "mcbsp1_ick",
2893 .addr = omap3xxx_mcbsp1_addrs,
2894 .user = OCP_USER_MPU | OCP_USER_SDMA,
2895 };
2896
2897 static struct omap_hwmod_addr_space omap3xxx_mcbsp2_addrs[] = {
2898 {
2899 .name = "mpu",
2900 .pa_start = 0x49022000,
2901 .pa_end = 0x490220ff,
2902 .flags = ADDR_TYPE_RT
2903 },
2904 { }
2905 };
2906
2907 /* l4_per -> mcbsp2 */
2908 static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp2 = {
2909 .master = &omap3xxx_l4_per_hwmod,
2910 .slave = &omap3xxx_mcbsp2_hwmod,
2911 .clk = "mcbsp2_ick",
2912 .addr = omap3xxx_mcbsp2_addrs,
2913 .user = OCP_USER_MPU | OCP_USER_SDMA,
2914 };
2915
2916 static struct omap_hwmod_addr_space omap3xxx_mcbsp3_addrs[] = {
2917 {
2918 .name = "mpu",
2919 .pa_start = 0x49024000,
2920 .pa_end = 0x490240ff,
2921 .flags = ADDR_TYPE_RT
2922 },
2923 { }
2924 };
2925
2926 /* l4_per -> mcbsp3 */
2927 static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp3 = {
2928 .master = &omap3xxx_l4_per_hwmod,
2929 .slave = &omap3xxx_mcbsp3_hwmod,
2930 .clk = "mcbsp3_ick",
2931 .addr = omap3xxx_mcbsp3_addrs,
2932 .user = OCP_USER_MPU | OCP_USER_SDMA,
2933 };
2934
2935 static struct omap_hwmod_addr_space omap3xxx_mcbsp4_addrs[] = {
2936 {
2937 .name = "mpu",
2938 .pa_start = 0x49026000,
2939 .pa_end = 0x490260ff,
2940 .flags = ADDR_TYPE_RT
2941 },
2942 { }
2943 };
2944
2945 /* l4_per -> mcbsp4 */
2946 static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp4 = {
2947 .master = &omap3xxx_l4_per_hwmod,
2948 .slave = &omap3xxx_mcbsp4_hwmod,
2949 .clk = "mcbsp4_ick",
2950 .addr = omap3xxx_mcbsp4_addrs,
2951 .user = OCP_USER_MPU | OCP_USER_SDMA,
2952 };
2953
2954 static struct omap_hwmod_addr_space omap3xxx_mcbsp5_addrs[] = {
2955 {
2956 .name = "mpu",
2957 .pa_start = 0x48096000,
2958 .pa_end = 0x480960ff,
2959 .flags = ADDR_TYPE_RT
2960 },
2961 { }
2962 };
2963
2964 /* l4_core -> mcbsp5 */
2965 static struct omap_hwmod_ocp_if omap3xxx_l4_core__mcbsp5 = {
2966 .master = &omap3xxx_l4_core_hwmod,
2967 .slave = &omap3xxx_mcbsp5_hwmod,
2968 .clk = "mcbsp5_ick",
2969 .addr = omap3xxx_mcbsp5_addrs,
2970 .user = OCP_USER_MPU | OCP_USER_SDMA,
2971 };
2972
2973 static struct omap_hwmod_addr_space omap3xxx_mcbsp2_sidetone_addrs[] = {
2974 {
2975 .name = "sidetone",
2976 .pa_start = 0x49028000,
2977 .pa_end = 0x490280ff,
2978 .flags = ADDR_TYPE_RT
2979 },
2980 { }
2981 };
2982
2983 /* l4_per -> mcbsp2_sidetone */
2984 static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp2_sidetone = {
2985 .master = &omap3xxx_l4_per_hwmod,
2986 .slave = &omap3xxx_mcbsp2_sidetone_hwmod,
2987 .clk = "mcbsp2_ick",
2988 .addr = omap3xxx_mcbsp2_sidetone_addrs,
2989 .user = OCP_USER_MPU,
2990 };
2991
2992 static struct omap_hwmod_addr_space omap3xxx_mcbsp3_sidetone_addrs[] = {
2993 {
2994 .name = "sidetone",
2995 .pa_start = 0x4902A000,
2996 .pa_end = 0x4902A0ff,
2997 .flags = ADDR_TYPE_RT
2998 },
2999 { }
3000 };
3001
3002 /* l4_per -> mcbsp3_sidetone */
3003 static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp3_sidetone = {
3004 .master = &omap3xxx_l4_per_hwmod,
3005 .slave = &omap3xxx_mcbsp3_sidetone_hwmod,
3006 .clk = "mcbsp3_ick",
3007 .addr = omap3xxx_mcbsp3_sidetone_addrs,
3008 .user = OCP_USER_MPU,
3009 };
3010
3011 static struct omap_hwmod_addr_space omap3xxx_mailbox_addrs[] = {
3012 {
3013 .pa_start = 0x48094000,
3014 .pa_end = 0x480941ff,
3015 .flags = ADDR_TYPE_RT,
3016 },
3017 { }
3018 };
3019
3020 /* l4_core -> mailbox */
3021 static struct omap_hwmod_ocp_if omap3xxx_l4_core__mailbox = {
3022 .master = &omap3xxx_l4_core_hwmod,
3023 .slave = &omap3xxx_mailbox_hwmod,
3024 .addr = omap3xxx_mailbox_addrs,
3025 .user = OCP_USER_MPU | OCP_USER_SDMA,
3026 };
3027
3028 /* l4 core -> mcspi1 interface */
3029 static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi1 = {
3030 .master = &omap3xxx_l4_core_hwmod,
3031 .slave = &omap34xx_mcspi1,
3032 .clk = "mcspi1_ick",
3033 .addr = omap2_mcspi1_addr_space,
3034 .user = OCP_USER_MPU | OCP_USER_SDMA,
3035 };
3036
3037 /* l4 core -> mcspi2 interface */
3038 static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi2 = {
3039 .master = &omap3xxx_l4_core_hwmod,
3040 .slave = &omap34xx_mcspi2,
3041 .clk = "mcspi2_ick",
3042 .addr = omap2_mcspi2_addr_space,
3043 .user = OCP_USER_MPU | OCP_USER_SDMA,
3044 };
3045
3046 /* l4 core -> mcspi3 interface */
3047 static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi3 = {
3048 .master = &omap3xxx_l4_core_hwmod,
3049 .slave = &omap34xx_mcspi3,
3050 .clk = "mcspi3_ick",
3051 .addr = omap2430_mcspi3_addr_space,
3052 .user = OCP_USER_MPU | OCP_USER_SDMA,
3053 };
3054
3055 /* l4 core -> mcspi4 interface */
3056 static struct omap_hwmod_addr_space omap34xx_mcspi4_addr_space[] = {
3057 {
3058 .pa_start = 0x480ba000,
3059 .pa_end = 0x480ba0ff,
3060 .flags = ADDR_TYPE_RT,
3061 },
3062 { }
3063 };
3064
3065 static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi4 = {
3066 .master = &omap3xxx_l4_core_hwmod,
3067 .slave = &omap34xx_mcspi4,
3068 .clk = "mcspi4_ick",
3069 .addr = omap34xx_mcspi4_addr_space,
3070 .user = OCP_USER_MPU | OCP_USER_SDMA,
3071 };
3072
3073 static struct omap_hwmod_ocp_if omap3xxx_usb_host_hs__l3_main_2 = {
3074 .master = &omap3xxx_usb_host_hs_hwmod,
3075 .slave = &omap3xxx_l3_main_hwmod,
3076 .clk = "core_l3_ick",
3077 .user = OCP_USER_MPU,
3078 };
3079
3080 static struct omap_hwmod_addr_space omap3xxx_usb_host_hs_addrs[] = {
3081 {
3082 .name = "uhh",
3083 .pa_start = 0x48064000,
3084 .pa_end = 0x480643ff,
3085 .flags = ADDR_TYPE_RT
3086 },
3087 {
3088 .name = "ohci",
3089 .pa_start = 0x48064400,
3090 .pa_end = 0x480647ff,
3091 },
3092 {
3093 .name = "ehci",
3094 .pa_start = 0x48064800,
3095 .pa_end = 0x48064cff,
3096 },
3097 {}
3098 };
3099
3100 static struct omap_hwmod_ocp_if omap3xxx_l4_core__usb_host_hs = {
3101 .master = &omap3xxx_l4_core_hwmod,
3102 .slave = &omap3xxx_usb_host_hs_hwmod,
3103 .clk = "usbhost_ick",
3104 .addr = omap3xxx_usb_host_hs_addrs,
3105 .user = OCP_USER_MPU | OCP_USER_SDMA,
3106 };
3107
3108 static struct omap_hwmod_addr_space omap3xxx_usb_tll_hs_addrs[] = {
3109 {
3110 .name = "tll",
3111 .pa_start = 0x48062000,
3112 .pa_end = 0x48062fff,
3113 .flags = ADDR_TYPE_RT
3114 },
3115 {}
3116 };
3117
3118 static struct omap_hwmod_ocp_if omap3xxx_l4_core__usb_tll_hs = {
3119 .master = &omap3xxx_l4_core_hwmod,
3120 .slave = &omap3xxx_usb_tll_hs_hwmod,
3121 .clk = "usbtll_ick",
3122 .addr = omap3xxx_usb_tll_hs_addrs,
3123 .user = OCP_USER_MPU | OCP_USER_SDMA,
3124 };
3125
3126 /* l4_core -> hdq1w interface */
3127 static struct omap_hwmod_ocp_if omap3xxx_l4_core__hdq1w = {
3128 .master = &omap3xxx_l4_core_hwmod,
3129 .slave = &omap3xxx_hdq1w_hwmod,
3130 .clk = "hdq_ick",
3131 .addr = omap2_hdq1w_addr_space,
3132 .user = OCP_USER_MPU | OCP_USER_SDMA,
3133 .flags = OMAP_FIREWALL_L4 | OCPIF_SWSUP_IDLE,
3134 };
3135
3136 /* l4_wkup -> 32ksync_counter */
3137 static struct omap_hwmod_addr_space omap3xxx_counter_32k_addrs[] = {
3138 {
3139 .pa_start = 0x48320000,
3140 .pa_end = 0x4832001f,
3141 .flags = ADDR_TYPE_RT
3142 },
3143 { }
3144 };
3145
3146 static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__counter_32k = {
3147 .master = &omap3xxx_l4_wkup_hwmod,
3148 .slave = &omap3xxx_counter_32k_hwmod,
3149 .clk = "omap_32ksync_ick",
3150 .addr = omap3xxx_counter_32k_addrs,
3151 .user = OCP_USER_MPU | OCP_USER_SDMA,
3152 };
3153
3154 static struct omap_hwmod_ocp_if *omap3xxx_hwmod_ocp_ifs[] __initdata = {
3155 &omap3xxx_l3_main__l4_core,
3156 &omap3xxx_l3_main__l4_per,
3157 &omap3xxx_mpu__l3_main,
3158 &omap3xxx_l4_core__l4_wkup,
3159 &omap3xxx_l4_core__mmc3,
3160 &omap3_l4_core__uart1,
3161 &omap3_l4_core__uart2,
3162 &omap3_l4_per__uart3,
3163 &omap3_l4_core__i2c1,
3164 &omap3_l4_core__i2c2,
3165 &omap3_l4_core__i2c3,
3166 &omap3xxx_l4_wkup__l4_sec,
3167 &omap3xxx_l4_wkup__timer1,
3168 &omap3xxx_l4_per__timer2,
3169 &omap3xxx_l4_per__timer3,
3170 &omap3xxx_l4_per__timer4,
3171 &omap3xxx_l4_per__timer5,
3172 &omap3xxx_l4_per__timer6,
3173 &omap3xxx_l4_per__timer7,
3174 &omap3xxx_l4_per__timer8,
3175 &omap3xxx_l4_per__timer9,
3176 &omap3xxx_l4_core__timer10,
3177 &omap3xxx_l4_core__timer11,
3178 &omap3xxx_l4_wkup__wd_timer2,
3179 &omap3xxx_l4_wkup__gpio1,
3180 &omap3xxx_l4_per__gpio2,
3181 &omap3xxx_l4_per__gpio3,
3182 &omap3xxx_l4_per__gpio4,
3183 &omap3xxx_l4_per__gpio5,
3184 &omap3xxx_l4_per__gpio6,
3185 &omap3xxx_dma_system__l3,
3186 &omap3xxx_l4_core__dma_system,
3187 &omap3xxx_l4_core__mcbsp1,
3188 &omap3xxx_l4_per__mcbsp2,
3189 &omap3xxx_l4_per__mcbsp3,
3190 &omap3xxx_l4_per__mcbsp4,
3191 &omap3xxx_l4_core__mcbsp5,
3192 &omap3xxx_l4_per__mcbsp2_sidetone,
3193 &omap3xxx_l4_per__mcbsp3_sidetone,
3194 &omap34xx_l4_core__mcspi1,
3195 &omap34xx_l4_core__mcspi2,
3196 &omap34xx_l4_core__mcspi3,
3197 &omap34xx_l4_core__mcspi4,
3198 &omap3xxx_l4_wkup__counter_32k,
3199 NULL,
3200 };
3201
3202 /* GP-only hwmod links */
3203 static struct omap_hwmod_ocp_if *omap3xxx_gp_hwmod_ocp_ifs[] __initdata = {
3204 &omap3xxx_l4_sec__timer12,
3205 NULL
3206 };
3207
3208 /* 3430ES1-only hwmod links */
3209 static struct omap_hwmod_ocp_if *omap3430es1_hwmod_ocp_ifs[] __initdata = {
3210 &omap3430es1_dss__l3,
3211 &omap3430es1_l4_core__dss,
3212 NULL
3213 };
3214
3215 /* 3430ES2+-only hwmod links */
3216 static struct omap_hwmod_ocp_if *omap3430es2plus_hwmod_ocp_ifs[] __initdata = {
3217 &omap3xxx_dss__l3,
3218 &omap3xxx_l4_core__dss,
3219 &omap3xxx_usbhsotg__l3,
3220 &omap3xxx_l4_core__usbhsotg,
3221 &omap3xxx_usb_host_hs__l3_main_2,
3222 &omap3xxx_l4_core__usb_host_hs,
3223 &omap3xxx_l4_core__usb_tll_hs,
3224 NULL
3225 };
3226
3227 /* <= 3430ES3-only hwmod links */
3228 static struct omap_hwmod_ocp_if *omap3430_pre_es3_hwmod_ocp_ifs[] __initdata = {
3229 &omap3xxx_l4_core__pre_es3_mmc1,
3230 &omap3xxx_l4_core__pre_es3_mmc2,
3231 NULL
3232 };
3233
3234 /* 3430ES3+-only hwmod links */
3235 static struct omap_hwmod_ocp_if *omap3430_es3plus_hwmod_ocp_ifs[] __initdata = {
3236 &omap3xxx_l4_core__es3plus_mmc1,
3237 &omap3xxx_l4_core__es3plus_mmc2,
3238 NULL
3239 };
3240
3241 /* 34xx-only hwmod links (all ES revisions) */
3242 static struct omap_hwmod_ocp_if *omap34xx_hwmod_ocp_ifs[] __initdata = {
3243 &omap3xxx_l3__iva,
3244 &omap34xx_l4_core__sr1,
3245 &omap34xx_l4_core__sr2,
3246 &omap3xxx_l4_core__mailbox,
3247 &omap3xxx_l4_core__hdq1w,
3248 NULL
3249 };
3250
3251 /* 36xx-only hwmod links (all ES revisions) */
3252 static struct omap_hwmod_ocp_if *omap36xx_hwmod_ocp_ifs[] __initdata = {
3253 &omap3xxx_l3__iva,
3254 &omap36xx_l4_per__uart4,
3255 &omap3xxx_dss__l3,
3256 &omap3xxx_l4_core__dss,
3257 &omap36xx_l4_core__sr1,
3258 &omap36xx_l4_core__sr2,
3259 &omap3xxx_usbhsotg__l3,
3260 &omap3xxx_l4_core__usbhsotg,
3261 &omap3xxx_l4_core__mailbox,
3262 &omap3xxx_usb_host_hs__l3_main_2,
3263 &omap3xxx_l4_core__usb_host_hs,
3264 &omap3xxx_l4_core__usb_tll_hs,
3265 &omap3xxx_l4_core__es3plus_mmc1,
3266 &omap3xxx_l4_core__es3plus_mmc2,
3267 &omap3xxx_l4_core__hdq1w,
3268 NULL
3269 };
3270
3271 static struct omap_hwmod_ocp_if *am35xx_hwmod_ocp_ifs[] __initdata = {
3272 &omap3xxx_dss__l3,
3273 &omap3xxx_l4_core__dss,
3274 &am35xx_usbhsotg__l3,
3275 &am35xx_l4_core__usbhsotg,
3276 &am35xx_l4_core__uart4,
3277 &omap3xxx_usb_host_hs__l3_main_2,
3278 &omap3xxx_l4_core__usb_host_hs,
3279 &omap3xxx_l4_core__usb_tll_hs,
3280 &omap3xxx_l4_core__es3plus_mmc1,
3281 &omap3xxx_l4_core__es3plus_mmc2,
3282 NULL
3283 };
3284
3285 static struct omap_hwmod_ocp_if *omap3xxx_dss_hwmod_ocp_ifs[] __initdata = {
3286 &omap3xxx_l4_core__dss_dispc,
3287 &omap3xxx_l4_core__dss_dsi1,
3288 &omap3xxx_l4_core__dss_rfbi,
3289 &omap3xxx_l4_core__dss_venc,
3290 NULL
3291 };
3292
3293 int __init omap3xxx_hwmod_init(void)
3294 {
3295 int r;
3296 struct omap_hwmod_ocp_if **h = NULL;
3297 unsigned int rev;
3298
3299 omap_hwmod_init();
3300
3301 /* Register hwmod links common to all OMAP3 */
3302 r = omap_hwmod_register_links(omap3xxx_hwmod_ocp_ifs);
3303 if (r < 0)
3304 return r;
3305
3306 /* Register GP-only hwmod links. */
3307 if (omap_type() == OMAP2_DEVICE_TYPE_GP) {
3308 r = omap_hwmod_register_links(omap3xxx_gp_hwmod_ocp_ifs);
3309 if (r < 0)
3310 return r;
3311 }
3312
3313 rev = omap_rev();
3314
3315 /*
3316 * Register hwmod links common to individual OMAP3 families, all
3317 * silicon revisions (e.g., 34xx, or AM3505/3517, or 36xx)
3318 * All possible revisions should be included in this conditional.
3319 */
3320 if (rev == OMAP3430_REV_ES1_0 || rev == OMAP3430_REV_ES2_0 ||
3321 rev == OMAP3430_REV_ES2_1 || rev == OMAP3430_REV_ES3_0 ||
3322 rev == OMAP3430_REV_ES3_1 || rev == OMAP3430_REV_ES3_1_2) {
3323 h = omap34xx_hwmod_ocp_ifs;
3324 } else if (rev == AM35XX_REV_ES1_0 || rev == AM35XX_REV_ES1_1) {
3325 h = am35xx_hwmod_ocp_ifs;
3326 } else if (rev == OMAP3630_REV_ES1_0 || rev == OMAP3630_REV_ES1_1 ||
3327 rev == OMAP3630_REV_ES1_2) {
3328 h = omap36xx_hwmod_ocp_ifs;
3329 } else {
3330 WARN(1, "OMAP3 hwmod family init: unknown chip type\n");
3331 return -EINVAL;
3332 };
3333
3334 r = omap_hwmod_register_links(h);
3335 if (r < 0)
3336 return r;
3337
3338 /*
3339 * Register hwmod links specific to certain ES levels of a
3340 * particular family of silicon (e.g., 34xx ES1.0)
3341 */
3342 h = NULL;
3343 if (rev == OMAP3430_REV_ES1_0) {
3344 h = omap3430es1_hwmod_ocp_ifs;
3345 } else if (rev == OMAP3430_REV_ES2_0 || rev == OMAP3430_REV_ES2_1 ||
3346 rev == OMAP3430_REV_ES3_0 || rev == OMAP3430_REV_ES3_1 ||
3347 rev == OMAP3430_REV_ES3_1_2) {
3348 h = omap3430es2plus_hwmod_ocp_ifs;
3349 };
3350
3351 if (h) {
3352 r = omap_hwmod_register_links(h);
3353 if (r < 0)
3354 return r;
3355 }
3356
3357 h = NULL;
3358 if (rev == OMAP3430_REV_ES1_0 || rev == OMAP3430_REV_ES2_0 ||
3359 rev == OMAP3430_REV_ES2_1) {
3360 h = omap3430_pre_es3_hwmod_ocp_ifs;
3361 } else if (rev == OMAP3430_REV_ES3_0 || rev == OMAP3430_REV_ES3_1 ||
3362 rev == OMAP3430_REV_ES3_1_2) {
3363 h = omap3430_es3plus_hwmod_ocp_ifs;
3364 };
3365
3366 if (h)
3367 r = omap_hwmod_register_links(h);
3368 if (r < 0)
3369 return r;
3370
3371 /*
3372 * DSS code presumes that dss_core hwmod is handled first,
3373 * _before_ any other DSS related hwmods so register common
3374 * DSS hwmod links last to ensure that dss_core is already
3375 * registered. Otherwise some change things may happen, for
3376 * ex. if dispc is handled before dss_core and DSS is enabled
3377 * in bootloader DISPC will be reset with outputs enabled
3378 * which sometimes leads to unrecoverable L3 error. XXX The
3379 * long-term fix to this is to ensure hwmods are set up in
3380 * dependency order in the hwmod core code.
3381 */
3382 r = omap_hwmod_register_links(omap3xxx_dss_hwmod_ocp_ifs);
3383
3384 return r;
3385 }
Linus' kernel tree