2 * Universal Flash Storage Host controller driver
4 * This code is based on drivers/scsi/ufs/ufshci.h
5 * Copyright (C) 2011-2013 Samsung India Software Operations
8 * Santosh Yaraganavi <santosh.sy@samsung.com>
9 * Vinayak Holikatti <h.vinayak@samsung.com>
11 * This program is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License
13 * as published by the Free Software Foundation; either version 2
14 * of the License, or (at your option) any later version.
15 * See the COPYING file in the top-level directory or visit
16 * <http://www.gnu.org/licenses/gpl-2.0.html>
18 * This program is distributed in the hope that it will be useful,
19 * but WITHOUT ANY WARRANTY; without even the implied warranty of
20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21 * GNU General Public License for more details.
23 * This program is provided "AS IS" and "WITH ALL FAULTS" and
24 * without warranty of any kind. You are solely responsible for
25 * determining the appropriateness of using and distributing
26 * the program and assume all risks associated with your exercise
27 * of rights with respect to the program, including but not limited
28 * to infringement of third party rights, the risks and costs of
29 * program errors, damage to or loss of data, programs or equipment,
30 * and unavailability or interruption of operations. Under no
31 * circumstances will the contributor of this Program be liable for
32 * any damages of any kind arising from your use or distribution of
40 TASK_REQ_UPIU_SIZE_DWORDS
= 8,
41 TASK_RSP_UPIU_SIZE_DWORDS
= 8,
42 ALIGNED_UPIU_SIZE
= 128,
45 /* UFSHCI Registers */
47 REG_CONTROLLER_CAPABILITIES
= 0x00,
48 REG_UFS_VERSION
= 0x08,
49 REG_CONTROLLER_DEV_ID
= 0x10,
50 REG_CONTROLLER_PROD_ID
= 0x14,
51 REG_INTERRUPT_STATUS
= 0x20,
52 REG_INTERRUPT_ENABLE
= 0x24,
53 REG_CONTROLLER_STATUS
= 0x30,
54 REG_CONTROLLER_ENABLE
= 0x34,
55 REG_UIC_ERROR_CODE_PHY_ADAPTER_LAYER
= 0x38,
56 REG_UIC_ERROR_CODE_DATA_LINK_LAYER
= 0x3C,
57 REG_UIC_ERROR_CODE_NETWORK_LAYER
= 0x40,
58 REG_UIC_ERROR_CODE_TRANSPORT_LAYER
= 0x44,
59 REG_UIC_ERROR_CODE_DME
= 0x48,
60 REG_UTP_TRANSFER_REQ_INT_AGG_CONTROL
= 0x4C,
61 REG_UTP_TRANSFER_REQ_LIST_BASE_L
= 0x50,
62 REG_UTP_TRANSFER_REQ_LIST_BASE_H
= 0x54,
63 REG_UTP_TRANSFER_REQ_DOOR_BELL
= 0x58,
64 REG_UTP_TRANSFER_REQ_LIST_CLEAR
= 0x5C,
65 REG_UTP_TRANSFER_REQ_LIST_RUN_STOP
= 0x60,
66 REG_UTP_TASK_REQ_LIST_BASE_L
= 0x70,
67 REG_UTP_TASK_REQ_LIST_BASE_H
= 0x74,
68 REG_UTP_TASK_REQ_DOOR_BELL
= 0x78,
69 REG_UTP_TASK_REQ_LIST_CLEAR
= 0x7C,
70 REG_UTP_TASK_REQ_LIST_RUN_STOP
= 0x80,
71 REG_UIC_COMMAND
= 0x90,
72 REG_UIC_COMMAND_ARG_1
= 0x94,
73 REG_UIC_COMMAND_ARG_2
= 0x98,
74 REG_UIC_COMMAND_ARG_3
= 0x9C,
77 /* Controller capability masks */
79 MASK_TRANSFER_REQUESTS_SLOTS
= 0x0000001F,
80 MASK_TASK_MANAGEMENT_REQUEST_SLOTS
= 0x00070000,
81 MASK_64_ADDRESSING_SUPPORT
= 0x01000000,
82 MASK_OUT_OF_ORDER_DATA_DELIVERY_SUPPORT
= 0x02000000,
83 MASK_UIC_DME_TEST_MODE_SUPPORT
= 0x04000000,
87 #define MINOR_VERSION_NUM_MASK UFS_MASK(0xFFFF, 0)
88 #define MAJOR_VERSION_NUM_MASK UFS_MASK(0xFFFF, 16)
90 /* Controller UFSHCI version */
92 UFSHCI_VERSION_10
= 0x00010000,
93 UFSHCI_VERSION_11
= 0x00010100,
97 * HCDDID - Host Controller Identification Descriptor
98 * - Device ID and Device Class 10h
100 #define DEVICE_CLASS UFS_MASK(0xFFFF, 0)
101 #define DEVICE_ID UFS_MASK(0xFF, 24)
104 * HCPMID - Host Controller Identification Descriptor
105 * - Product/Manufacturer ID 14h
107 #define MANUFACTURE_ID_MASK UFS_MASK(0xFFFF, 0)
108 #define PRODUCT_ID_MASK UFS_MASK(0xFFFF, 16)
110 #define UFS_BIT(x) (1L << (x))
112 #define UTP_TRANSFER_REQ_COMPL UFS_BIT(0)
113 #define UIC_DME_END_PT_RESET UFS_BIT(1)
114 #define UIC_ERROR UFS_BIT(2)
115 #define UIC_TEST_MODE UFS_BIT(3)
116 #define UIC_POWER_MODE UFS_BIT(4)
117 #define UIC_HIBERNATE_EXIT UFS_BIT(5)
118 #define UIC_HIBERNATE_ENTER UFS_BIT(6)
119 #define UIC_LINK_LOST UFS_BIT(7)
120 #define UIC_LINK_STARTUP UFS_BIT(8)
121 #define UTP_TASK_REQ_COMPL UFS_BIT(9)
122 #define UIC_COMMAND_COMPL UFS_BIT(10)
123 #define DEVICE_FATAL_ERROR UFS_BIT(11)
124 #define CONTROLLER_FATAL_ERROR UFS_BIT(16)
125 #define SYSTEM_BUS_FATAL_ERROR UFS_BIT(17)
127 #define UFSHCD_ERROR_MASK (UIC_ERROR |\
128 DEVICE_FATAL_ERROR |\
129 CONTROLLER_FATAL_ERROR |\
130 SYSTEM_BUS_FATAL_ERROR)
132 #define INT_FATAL_ERRORS (DEVICE_FATAL_ERROR |\
133 CONTROLLER_FATAL_ERROR |\
134 SYSTEM_BUS_FATAL_ERROR)
136 /* HCS - Host Controller Status 30h */
137 #define DEVICE_PRESENT UFS_BIT(0)
138 #define UTP_TRANSFER_REQ_LIST_READY UFS_BIT(1)
139 #define UTP_TASK_REQ_LIST_READY UFS_BIT(2)
140 #define UIC_COMMAND_READY UFS_BIT(3)
141 #define HOST_ERROR_INDICATOR UFS_BIT(4)
142 #define DEVICE_ERROR_INDICATOR UFS_BIT(5)
143 #define UIC_POWER_MODE_CHANGE_REQ_STATUS_MASK UFS_MASK(0x7, 8)
145 /* HCE - Host Controller Enable 34h */
146 #define CONTROLLER_ENABLE UFS_BIT(0)
147 #define CONTROLLER_DISABLE 0x0
149 /* UECPA - Host UIC Error Code PHY Adapter Layer 38h */
150 #define UIC_PHY_ADAPTER_LAYER_ERROR UFS_BIT(31)
151 #define UIC_PHY_ADAPTER_LAYER_ERROR_CODE_MASK 0x1F
153 /* UECDL - Host UIC Error Code Data Link Layer 3Ch */
154 #define UIC_DATA_LINK_LAYER_ERROR UFS_BIT(31)
155 #define UIC_DATA_LINK_LAYER_ERROR_CODE_MASK 0x7FFF
156 #define UIC_DATA_LINK_LAYER_ERROR_PA_INIT 0x2000
158 /* UECN - Host UIC Error Code Network Layer 40h */
159 #define UIC_NETWORK_LAYER_ERROR UFS_BIT(31)
160 #define UIC_NETWORK_LAYER_ERROR_CODE_MASK 0x7
162 /* UECT - Host UIC Error Code Transport Layer 44h */
163 #define UIC_TRANSPORT_LAYER_ERROR UFS_BIT(31)
164 #define UIC_TRANSPORT_LAYER_ERROR_CODE_MASK 0x7F
166 /* UECDME - Host UIC Error Code DME 48h */
167 #define UIC_DME_ERROR UFS_BIT(31)
168 #define UIC_DME_ERROR_CODE_MASK 0x1
170 #define INT_AGGR_TIMEOUT_VAL_MASK 0xFF
171 #define INT_AGGR_COUNTER_THRESHOLD_MASK UFS_MASK(0x1F, 8)
172 #define INT_AGGR_COUNTER_AND_TIMER_RESET UFS_BIT(16)
173 #define INT_AGGR_STATUS_BIT UFS_BIT(20)
174 #define INT_AGGR_PARAM_WRITE UFS_BIT(24)
175 #define INT_AGGR_ENABLE UFS_BIT(31)
177 /* UTRLRSR - UTP Transfer Request Run-Stop Register 60h */
178 #define UTP_TRANSFER_REQ_LIST_RUN_STOP_BIT UFS_BIT(0)
180 /* UTMRLRSR - UTP Task Management Request Run-Stop Register 80h */
181 #define UTP_TASK_REQ_LIST_RUN_STOP_BIT UFS_BIT(0)
183 /* UICCMD - UIC Command */
184 #define COMMAND_OPCODE_MASK 0xFF
185 #define GEN_SELECTOR_INDEX_MASK 0xFFFF
187 #define MIB_ATTRIBUTE_MASK UFS_MASK(0xFFFF, 16)
188 #define RESET_LEVEL 0xFF
190 #define ATTR_SET_TYPE_MASK UFS_MASK(0xFF, 16)
191 #define CONFIG_RESULT_CODE_MASK 0xFF
192 #define GENERIC_ERROR_CODE_MASK 0xFF
196 UIC_CMD_DME_GET
= 0x01,
197 UIC_CMD_DME_SET
= 0x02,
198 UIC_CMD_DME_PEER_GET
= 0x03,
199 UIC_CMD_DME_PEER_SET
= 0x04,
200 UIC_CMD_DME_POWERON
= 0x10,
201 UIC_CMD_DME_POWEROFF
= 0x11,
202 UIC_CMD_DME_ENABLE
= 0x12,
203 UIC_CMD_DME_RESET
= 0x14,
204 UIC_CMD_DME_END_PT_RST
= 0x15,
205 UIC_CMD_DME_LINK_STARTUP
= 0x16,
206 UIC_CMD_DME_HIBER_ENTER
= 0x17,
207 UIC_CMD_DME_HIBER_EXIT
= 0x18,
208 UIC_CMD_DME_TEST_MODE
= 0x1A,
211 /* UIC Config result code / Generic error code */
213 UIC_CMD_RESULT_SUCCESS
= 0x00,
214 UIC_CMD_RESULT_INVALID_ATTR
= 0x01,
215 UIC_CMD_RESULT_FAILURE
= 0x01,
216 UIC_CMD_RESULT_INVALID_ATTR_VALUE
= 0x02,
217 UIC_CMD_RESULT_READ_ONLY_ATTR
= 0x03,
218 UIC_CMD_RESULT_WRITE_ONLY_ATTR
= 0x04,
219 UIC_CMD_RESULT_BAD_INDEX
= 0x05,
220 UIC_CMD_RESULT_LOCKED_ATTR
= 0x06,
221 UIC_CMD_RESULT_BAD_TEST_FEATURE_INDEX
= 0x07,
222 UIC_CMD_RESULT_PEER_COMM_FAILURE
= 0x08,
223 UIC_CMD_RESULT_BUSY
= 0x09,
224 UIC_CMD_RESULT_DME_FAILURE
= 0x0A,
227 #define MASK_UIC_COMMAND_RESULT 0xFF
229 #define INT_AGGR_COUNTER_THRESHOLD_VALUE (0x1F << 8)
230 #define INT_AGGR_TIMEOUT_VALUE (0x02)
232 /* Interrupt disable masks */
234 /* Interrupt disable mask for UFSHCI v1.0 */
235 INTERRUPT_MASK_ALL_VER_10
= 0x30FFF,
236 INTERRUPT_MASK_RW_VER_10
= 0x30000,
238 /* Interrupt disable mask for UFSHCI v1.1 */
239 INTERRUPT_MASK_ALL_VER_11
= 0x31FFF,
243 * Request Descriptor Definitions
246 /* Transfer request command type */
248 UTP_CMD_TYPE_SCSI
= 0x0,
249 UTP_CMD_TYPE_UFS
= 0x1,
250 UTP_CMD_TYPE_DEV_MANAGE
= 0x2,
254 UTP_SCSI_COMMAND
= 0x00000000,
255 UTP_NATIVE_UFS_COMMAND
= 0x10000000,
256 UTP_DEVICE_MANAGEMENT_FUNCTION
= 0x20000000,
257 UTP_REQ_DESC_INT_CMD
= 0x01000000,
260 /* UTP Transfer Request Data Direction (DD) */
262 UTP_NO_DATA_TRANSFER
= 0x00000000,
263 UTP_HOST_TO_DEVICE
= 0x02000000,
264 UTP_DEVICE_TO_HOST
= 0x04000000,
267 /* Overall command status values */
270 OCS_INVALID_CMD_TABLE_ATTR
= 0x1,
271 OCS_INVALID_PRDT_ATTR
= 0x2,
272 OCS_MISMATCH_DATA_BUF_SIZE
= 0x3,
273 OCS_MISMATCH_RESP_UPIU_SIZE
= 0x4,
274 OCS_PEER_COMM_FAILURE
= 0x5,
276 OCS_FATAL_ERROR
= 0x7,
277 OCS_INVALID_COMMAND_STATUS
= 0x0F,
282 * struct ufshcd_sg_entry - UFSHCI PRD Entry
283 * @base_addr: Lower 32bit physical address DW-0
284 * @upper_addr: Upper 32bit physical address DW-1
285 * @reserved: Reserved for future use DW-2
286 * @size: size of physical segment DW-3
288 struct ufshcd_sg_entry
{
296 * struct utp_transfer_cmd_desc - UFS Command Descriptor structure
297 * @command_upiu: Command UPIU Frame address
298 * @response_upiu: Response UPIU Frame address
299 * @prd_table: Physical Region Descriptor
301 struct utp_transfer_cmd_desc
{
302 u8 command_upiu
[ALIGNED_UPIU_SIZE
];
303 u8 response_upiu
[ALIGNED_UPIU_SIZE
];
304 struct ufshcd_sg_entry prd_table
[SG_ALL
];
308 * struct request_desc_header - Descriptor Header common to both UTRD and UTMRD
309 * @dword0: Descriptor Header DW0
310 * @dword1: Descriptor Header DW1
311 * @dword2: Descriptor Header DW2
312 * @dword3: Descriptor Header DW3
314 struct request_desc_header
{
322 * struct utp_transfer_req_desc - UTRD structure
323 * @header: UTRD header DW-0 to DW-3
324 * @command_desc_base_addr_lo: UCD base address low DW-4
325 * @command_desc_base_addr_hi: UCD base address high DW-5
326 * @response_upiu_length: response UPIU length DW-6
327 * @response_upiu_offset: response UPIU offset DW-6
328 * @prd_table_length: Physical region descriptor length DW-7
329 * @prd_table_offset: Physical region descriptor offset DW-7
331 struct utp_transfer_req_desc
{
334 struct request_desc_header header
;
337 u32 command_desc_base_addr_lo
;
338 u32 command_desc_base_addr_hi
;
341 u16 response_upiu_length
;
342 u16 response_upiu_offset
;
345 u16 prd_table_length
;
346 u16 prd_table_offset
;
350 * struct utp_task_req_desc - UTMRD structure
351 * @header: UTMRD header DW-0 to DW-3
352 * @task_req_upiu: Pointer to task request UPIU DW-4 to DW-11
353 * @task_rsp_upiu: Pointer to task response UPIU DW12 to DW-19
355 struct utp_task_req_desc
{
358 struct request_desc_header header
;
361 u32 task_req_upiu
[TASK_REQ_UPIU_SIZE_DWORDS
];
364 u32 task_rsp_upiu
[TASK_RSP_UPIU_SIZE_DWORDS
];
367 #endif /* End of Header */