1 /*******************************************************************************
3 Intel 10 Gigabit PCI Express Linux driver
4 Copyright(c) 1999 - 2009 Intel Corporation.
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
26 *******************************************************************************/
28 #include <linux/pci.h>
29 #include <linux/delay.h>
30 #include <linux/sched.h>
32 #include "ixgbe_common.h"
33 #include "ixgbe_phy.h"
35 static bool ixgbe_validate_phy_addr(struct ixgbe_hw
*hw
, u32 phy_addr
);
36 static enum ixgbe_phy_type
ixgbe_get_phy_type_from_id(u32 phy_id
);
37 static s32
ixgbe_get_phy_id(struct ixgbe_hw
*hw
);
40 * ixgbe_identify_phy_generic - Get physical layer module
41 * @hw: pointer to hardware structure
43 * Determines the physical layer module found on the current adapter.
45 s32
ixgbe_identify_phy_generic(struct ixgbe_hw
*hw
)
47 s32 status
= IXGBE_ERR_PHY_ADDR_INVALID
;
50 if (hw
->phy
.type
== ixgbe_phy_unknown
) {
51 for (phy_addr
= 0; phy_addr
< IXGBE_MAX_PHY_ADDR
; phy_addr
++) {
52 if (ixgbe_validate_phy_addr(hw
, phy_addr
)) {
53 hw
->phy
.addr
= phy_addr
;
56 ixgbe_get_phy_type_from_id(hw
->phy
.id
);
69 * ixgbe_validate_phy_addr - Determines phy address is valid
70 * @hw: pointer to hardware structure
73 static bool ixgbe_validate_phy_addr(struct ixgbe_hw
*hw
, u32 phy_addr
)
78 hw
->phy
.addr
= phy_addr
;
79 hw
->phy
.ops
.read_reg(hw
, IXGBE_MDIO_PHY_ID_HIGH
,
80 IXGBE_MDIO_PMA_PMD_DEV_TYPE
, &phy_id
);
82 if (phy_id
!= 0xFFFF && phy_id
!= 0x0)
89 * ixgbe_get_phy_id - Get the phy type
90 * @hw: pointer to hardware structure
93 static s32
ixgbe_get_phy_id(struct ixgbe_hw
*hw
)
99 status
= hw
->phy
.ops
.read_reg(hw
, IXGBE_MDIO_PHY_ID_HIGH
,
100 IXGBE_MDIO_PMA_PMD_DEV_TYPE
,
104 hw
->phy
.id
= (u32
)(phy_id_high
<< 16);
105 status
= hw
->phy
.ops
.read_reg(hw
, IXGBE_MDIO_PHY_ID_LOW
,
106 IXGBE_MDIO_PMA_PMD_DEV_TYPE
,
108 hw
->phy
.id
|= (u32
)(phy_id_low
& IXGBE_PHY_REVISION_MASK
);
109 hw
->phy
.revision
= (u32
)(phy_id_low
& ~IXGBE_PHY_REVISION_MASK
);
115 * ixgbe_get_phy_type_from_id - Get the phy type
116 * @hw: pointer to hardware structure
119 static enum ixgbe_phy_type
ixgbe_get_phy_type_from_id(u32 phy_id
)
121 enum ixgbe_phy_type phy_type
;
125 phy_type
= ixgbe_phy_tn
;
128 phy_type
= ixgbe_phy_qt
;
131 phy_type
= ixgbe_phy_nl
;
134 phy_type
= ixgbe_phy_unknown
;
142 * ixgbe_reset_phy_generic - Performs a PHY reset
143 * @hw: pointer to hardware structure
145 s32
ixgbe_reset_phy_generic(struct ixgbe_hw
*hw
)
148 * Perform soft PHY reset to the PHY_XS.
149 * This will cause a soft reset to the PHY
151 return hw
->phy
.ops
.write_reg(hw
, IXGBE_MDIO_PHY_XS_CONTROL
,
152 IXGBE_MDIO_PHY_XS_DEV_TYPE
,
153 IXGBE_MDIO_PHY_XS_RESET
);
157 * ixgbe_read_phy_reg_generic - Reads a value from a specified PHY register
158 * @hw: pointer to hardware structure
159 * @reg_addr: 32 bit address of PHY register to read
160 * @phy_data: Pointer to read data from PHY register
162 s32
ixgbe_read_phy_reg_generic(struct ixgbe_hw
*hw
, u32 reg_addr
,
163 u32 device_type
, u16
*phy_data
)
171 if (IXGBE_READ_REG(hw
, IXGBE_STATUS
) & IXGBE_STATUS_LAN_ID_1
)
172 gssr
= IXGBE_GSSR_PHY1_SM
;
174 gssr
= IXGBE_GSSR_PHY0_SM
;
176 if (ixgbe_acquire_swfw_sync(hw
, gssr
) != 0)
177 status
= IXGBE_ERR_SWFW_SYNC
;
180 /* Setup and write the address cycle command */
181 command
= ((reg_addr
<< IXGBE_MSCA_NP_ADDR_SHIFT
) |
182 (device_type
<< IXGBE_MSCA_DEV_TYPE_SHIFT
) |
183 (hw
->phy
.addr
<< IXGBE_MSCA_PHY_ADDR_SHIFT
) |
184 (IXGBE_MSCA_ADDR_CYCLE
| IXGBE_MSCA_MDI_COMMAND
));
186 IXGBE_WRITE_REG(hw
, IXGBE_MSCA
, command
);
189 * Check every 10 usec to see if the address cycle completed.
190 * The MDI Command bit will clear when the operation is
193 for (i
= 0; i
< IXGBE_MDIO_COMMAND_TIMEOUT
; i
++) {
196 command
= IXGBE_READ_REG(hw
, IXGBE_MSCA
);
198 if ((command
& IXGBE_MSCA_MDI_COMMAND
) == 0)
202 if ((command
& IXGBE_MSCA_MDI_COMMAND
) != 0) {
203 hw_dbg(hw
, "PHY address command did not complete.\n");
204 status
= IXGBE_ERR_PHY
;
209 * Address cycle complete, setup and write the read
212 command
= ((reg_addr
<< IXGBE_MSCA_NP_ADDR_SHIFT
) |
213 (device_type
<< IXGBE_MSCA_DEV_TYPE_SHIFT
) |
214 (hw
->phy
.addr
<< IXGBE_MSCA_PHY_ADDR_SHIFT
) |
215 (IXGBE_MSCA_READ
| IXGBE_MSCA_MDI_COMMAND
));
217 IXGBE_WRITE_REG(hw
, IXGBE_MSCA
, command
);
220 * Check every 10 usec to see if the address cycle
221 * completed. The MDI Command bit will clear when the
222 * operation is complete
224 for (i
= 0; i
< IXGBE_MDIO_COMMAND_TIMEOUT
; i
++) {
227 command
= IXGBE_READ_REG(hw
, IXGBE_MSCA
);
229 if ((command
& IXGBE_MSCA_MDI_COMMAND
) == 0)
233 if ((command
& IXGBE_MSCA_MDI_COMMAND
) != 0) {
234 hw_dbg(hw
, "PHY read command didn't complete\n");
235 status
= IXGBE_ERR_PHY
;
238 * Read operation is complete. Get the data
241 data
= IXGBE_READ_REG(hw
, IXGBE_MSRWD
);
242 data
>>= IXGBE_MSRWD_READ_DATA_SHIFT
;
243 *phy_data
= (u16
)(data
);
247 ixgbe_release_swfw_sync(hw
, gssr
);
254 * ixgbe_write_phy_reg_generic - Writes a value to specified PHY register
255 * @hw: pointer to hardware structure
256 * @reg_addr: 32 bit PHY register to write
257 * @device_type: 5 bit device type
258 * @phy_data: Data to write to the PHY register
260 s32
ixgbe_write_phy_reg_generic(struct ixgbe_hw
*hw
, u32 reg_addr
,
261 u32 device_type
, u16 phy_data
)
268 if (IXGBE_READ_REG(hw
, IXGBE_STATUS
) & IXGBE_STATUS_LAN_ID_1
)
269 gssr
= IXGBE_GSSR_PHY1_SM
;
271 gssr
= IXGBE_GSSR_PHY0_SM
;
273 if (ixgbe_acquire_swfw_sync(hw
, gssr
) != 0)
274 status
= IXGBE_ERR_SWFW_SYNC
;
277 /* Put the data in the MDI single read and write data register*/
278 IXGBE_WRITE_REG(hw
, IXGBE_MSRWD
, (u32
)phy_data
);
280 /* Setup and write the address cycle command */
281 command
= ((reg_addr
<< IXGBE_MSCA_NP_ADDR_SHIFT
) |
282 (device_type
<< IXGBE_MSCA_DEV_TYPE_SHIFT
) |
283 (hw
->phy
.addr
<< IXGBE_MSCA_PHY_ADDR_SHIFT
) |
284 (IXGBE_MSCA_ADDR_CYCLE
| IXGBE_MSCA_MDI_COMMAND
));
286 IXGBE_WRITE_REG(hw
, IXGBE_MSCA
, command
);
289 * Check every 10 usec to see if the address cycle completed.
290 * The MDI Command bit will clear when the operation is
293 for (i
= 0; i
< IXGBE_MDIO_COMMAND_TIMEOUT
; i
++) {
296 command
= IXGBE_READ_REG(hw
, IXGBE_MSCA
);
298 if ((command
& IXGBE_MSCA_MDI_COMMAND
) == 0)
302 if ((command
& IXGBE_MSCA_MDI_COMMAND
) != 0) {
303 hw_dbg(hw
, "PHY address cmd didn't complete\n");
304 status
= IXGBE_ERR_PHY
;
309 * Address cycle complete, setup and write the write
312 command
= ((reg_addr
<< IXGBE_MSCA_NP_ADDR_SHIFT
) |
313 (device_type
<< IXGBE_MSCA_DEV_TYPE_SHIFT
) |
314 (hw
->phy
.addr
<< IXGBE_MSCA_PHY_ADDR_SHIFT
) |
315 (IXGBE_MSCA_WRITE
| IXGBE_MSCA_MDI_COMMAND
));
317 IXGBE_WRITE_REG(hw
, IXGBE_MSCA
, command
);
320 * Check every 10 usec to see if the address cycle
321 * completed. The MDI Command bit will clear when the
322 * operation is complete
324 for (i
= 0; i
< IXGBE_MDIO_COMMAND_TIMEOUT
; i
++) {
327 command
= IXGBE_READ_REG(hw
, IXGBE_MSCA
);
329 if ((command
& IXGBE_MSCA_MDI_COMMAND
) == 0)
333 if ((command
& IXGBE_MSCA_MDI_COMMAND
) != 0) {
334 hw_dbg(hw
, "PHY address cmd didn't complete\n");
335 status
= IXGBE_ERR_PHY
;
339 ixgbe_release_swfw_sync(hw
, gssr
);
346 * ixgbe_setup_phy_link_generic - Set and restart autoneg
347 * @hw: pointer to hardware structure
349 * Restart autonegotiation and PHY and waits for completion.
351 s32
ixgbe_setup_phy_link_generic(struct ixgbe_hw
*hw
)
353 s32 status
= IXGBE_NOT_IMPLEMENTED
;
355 u32 max_time_out
= 10;
356 u16 autoneg_reg
= IXGBE_MII_AUTONEG_REG
;
359 * Set advertisement settings in PHY based on autoneg_advertised
360 * settings. If autoneg_advertised = 0, then advertise default values
361 * tnx devices cannot be "forced" to a autoneg 10G and fail. But can
364 hw
->phy
.ops
.read_reg(hw
, IXGBE_MII_SPEED_SELECTION_REG
,
365 IXGBE_MDIO_AUTO_NEG_DEV_TYPE
, &autoneg_reg
);
367 if (hw
->phy
.autoneg_advertised
== IXGBE_LINK_SPEED_1GB_FULL
)
368 autoneg_reg
&= 0xEFFF; /* 0 in bit 12 is 1G operation */
370 autoneg_reg
|= 0x1000; /* 1 in bit 12 is 10G/1G operation */
372 hw
->phy
.ops
.write_reg(hw
, IXGBE_MII_SPEED_SELECTION_REG
,
373 IXGBE_MDIO_AUTO_NEG_DEV_TYPE
, autoneg_reg
);
375 /* Restart PHY autonegotiation and wait for completion */
376 hw
->phy
.ops
.read_reg(hw
, IXGBE_MDIO_AUTO_NEG_CONTROL
,
377 IXGBE_MDIO_AUTO_NEG_DEV_TYPE
, &autoneg_reg
);
379 autoneg_reg
|= IXGBE_MII_RESTART
;
381 hw
->phy
.ops
.write_reg(hw
, IXGBE_MDIO_AUTO_NEG_CONTROL
,
382 IXGBE_MDIO_AUTO_NEG_DEV_TYPE
, autoneg_reg
);
384 /* Wait for autonegotiation to finish */
385 for (time_out
= 0; time_out
< max_time_out
; time_out
++) {
387 /* Restart PHY autonegotiation and wait for completion */
388 status
= hw
->phy
.ops
.read_reg(hw
, IXGBE_MDIO_AUTO_NEG_STATUS
,
389 IXGBE_MDIO_AUTO_NEG_DEV_TYPE
,
392 autoneg_reg
&= IXGBE_MII_AUTONEG_COMPLETE
;
393 if (autoneg_reg
== IXGBE_MII_AUTONEG_COMPLETE
) {
399 if (time_out
== max_time_out
)
400 status
= IXGBE_ERR_LINK_SETUP
;
406 * ixgbe_setup_phy_link_speed_generic - Sets the auto advertised capabilities
407 * @hw: pointer to hardware structure
408 * @speed: new link speed
409 * @autoneg: true if autonegotiation enabled
411 s32
ixgbe_setup_phy_link_speed_generic(struct ixgbe_hw
*hw
,
412 ixgbe_link_speed speed
,
414 bool autoneg_wait_to_complete
)
418 * Clear autoneg_advertised and set new values based on input link
421 hw
->phy
.autoneg_advertised
= 0;
423 if (speed
& IXGBE_LINK_SPEED_10GB_FULL
)
424 hw
->phy
.autoneg_advertised
|= IXGBE_LINK_SPEED_10GB_FULL
;
426 if (speed
& IXGBE_LINK_SPEED_1GB_FULL
)
427 hw
->phy
.autoneg_advertised
|= IXGBE_LINK_SPEED_1GB_FULL
;
429 /* Setup link based on the new speed settings */
430 hw
->phy
.ops
.setup_link(hw
);
436 * ixgbe_reset_phy_nl - Performs a PHY reset
437 * @hw: pointer to hardware structure
439 s32
ixgbe_reset_phy_nl(struct ixgbe_hw
*hw
)
441 u16 phy_offset
, control
, eword
, edata
, block_crc
;
442 bool end_data
= false;
443 u16 list_offset
, data_offset
;
448 hw
->phy
.ops
.read_reg(hw
, IXGBE_MDIO_PHY_XS_CONTROL
,
449 IXGBE_MDIO_PHY_XS_DEV_TYPE
, &phy_data
);
451 /* reset the PHY and poll for completion */
452 hw
->phy
.ops
.write_reg(hw
, IXGBE_MDIO_PHY_XS_CONTROL
,
453 IXGBE_MDIO_PHY_XS_DEV_TYPE
,
454 (phy_data
| IXGBE_MDIO_PHY_XS_RESET
));
456 for (i
= 0; i
< 100; i
++) {
457 hw
->phy
.ops
.read_reg(hw
, IXGBE_MDIO_PHY_XS_CONTROL
,
458 IXGBE_MDIO_PHY_XS_DEV_TYPE
, &phy_data
);
459 if ((phy_data
& IXGBE_MDIO_PHY_XS_RESET
) == 0)
464 if ((phy_data
& IXGBE_MDIO_PHY_XS_RESET
) != 0) {
465 hw_dbg(hw
, "PHY reset did not complete.\n");
466 ret_val
= IXGBE_ERR_PHY
;
470 /* Get init offsets */
471 ret_val
= ixgbe_get_sfp_init_sequence_offsets(hw
, &list_offset
,
476 ret_val
= hw
->eeprom
.ops
.read(hw
, data_offset
, &block_crc
);
480 * Read control word from PHY init contents offset
482 ret_val
= hw
->eeprom
.ops
.read(hw
, data_offset
, &eword
);
483 control
= (eword
& IXGBE_CONTROL_MASK_NL
) >>
484 IXGBE_CONTROL_SHIFT_NL
;
485 edata
= eword
& IXGBE_DATA_MASK_NL
;
489 hw_dbg(hw
, "DELAY: %d MS\n", edata
);
493 hw_dbg(hw
, "DATA: \n");
495 hw
->eeprom
.ops
.read(hw
, data_offset
++,
497 for (i
= 0; i
< edata
; i
++) {
498 hw
->eeprom
.ops
.read(hw
, data_offset
, &eword
);
499 hw
->phy
.ops
.write_reg(hw
, phy_offset
,
500 IXGBE_TWINAX_DEV
, eword
);
501 hw_dbg(hw
, "Wrote %4.4x to %4.4x\n", eword
,
507 case IXGBE_CONTROL_NL
:
509 hw_dbg(hw
, "CONTROL: \n");
510 if (edata
== IXGBE_CONTROL_EOL_NL
) {
513 } else if (edata
== IXGBE_CONTROL_SOL_NL
) {
516 hw_dbg(hw
, "Bad control value\n");
517 ret_val
= IXGBE_ERR_PHY
;
522 hw_dbg(hw
, "Bad control type\n");
523 ret_val
= IXGBE_ERR_PHY
;
533 * ixgbe_identify_sfp_module_generic - Identifies SFP module and assigns
535 * @hw: pointer to hardware structure
537 * Searches for and indentifies the SFP module. Assings appropriate PHY type.
539 s32
ixgbe_identify_sfp_module_generic(struct ixgbe_hw
*hw
)
541 s32 status
= IXGBE_ERR_PHY_ADDR_INVALID
;
544 u8 comp_codes_1g
= 0;
545 u8 comp_codes_10g
= 0;
546 u8 oui_bytes
[4] = {0, 0, 0, 0};
547 u8 transmission_media
= 0;
549 status
= hw
->phy
.ops
.read_i2c_eeprom(hw
, IXGBE_SFF_IDENTIFIER
,
552 if (status
== IXGBE_ERR_SFP_NOT_PRESENT
) {
553 hw
->phy
.sfp_type
= ixgbe_sfp_type_not_present
;
557 if (identifier
== IXGBE_SFF_IDENTIFIER_SFP
) {
558 hw
->phy
.ops
.read_i2c_eeprom(hw
, IXGBE_SFF_1GBE_COMP_CODES
,
560 hw
->phy
.ops
.read_i2c_eeprom(hw
, IXGBE_SFF_10GBE_COMP_CODES
,
562 hw
->phy
.ops
.read_i2c_eeprom(hw
, IXGBE_SFF_TRANSMISSION_MEDIA
,
563 &transmission_media
);
571 if (transmission_media
& IXGBE_SFF_TWIN_AX_CAPABLE
)
572 hw
->phy
.sfp_type
= ixgbe_sfp_type_da_cu
;
573 else if (comp_codes_10g
& IXGBE_SFF_10GBASESR_CAPABLE
)
574 hw
->phy
.sfp_type
= ixgbe_sfp_type_sr
;
575 else if (comp_codes_10g
& IXGBE_SFF_10GBASELR_CAPABLE
)
576 hw
->phy
.sfp_type
= ixgbe_sfp_type_lr
;
578 hw
->phy
.sfp_type
= ixgbe_sfp_type_unknown
;
580 /* Determine PHY vendor */
581 if (hw
->phy
.type
== ixgbe_phy_unknown
) {
582 hw
->phy
.id
= identifier
;
583 hw
->phy
.ops
.read_i2c_eeprom(hw
,
584 IXGBE_SFF_VENDOR_OUI_BYTE0
,
586 hw
->phy
.ops
.read_i2c_eeprom(hw
,
587 IXGBE_SFF_VENDOR_OUI_BYTE1
,
589 hw
->phy
.ops
.read_i2c_eeprom(hw
,
590 IXGBE_SFF_VENDOR_OUI_BYTE2
,
594 ((oui_bytes
[0] << IXGBE_SFF_VENDOR_OUI_BYTE0_SHIFT
) |
595 (oui_bytes
[1] << IXGBE_SFF_VENDOR_OUI_BYTE1_SHIFT
) |
596 (oui_bytes
[2] << IXGBE_SFF_VENDOR_OUI_BYTE2_SHIFT
));
598 switch (vendor_oui
) {
599 case IXGBE_SFF_VENDOR_OUI_TYCO
:
600 if (transmission_media
&
601 IXGBE_SFF_TWIN_AX_CAPABLE
)
602 hw
->phy
.type
= ixgbe_phy_tw_tyco
;
604 case IXGBE_SFF_VENDOR_OUI_FTL
:
605 hw
->phy
.type
= ixgbe_phy_sfp_ftl
;
607 case IXGBE_SFF_VENDOR_OUI_AVAGO
:
608 hw
->phy
.type
= ixgbe_phy_sfp_avago
;
611 if (transmission_media
&
612 IXGBE_SFF_TWIN_AX_CAPABLE
)
613 hw
->phy
.type
= ixgbe_phy_tw_unknown
;
615 hw
->phy
.type
= ixgbe_phy_sfp_unknown
;
627 * ixgbe_get_sfp_init_sequence_offsets - Checks the MAC's EEPROM to see
628 * if it supports a given SFP+ module type, if so it returns the offsets to the
629 * phy init sequence block.
630 * @hw: pointer to hardware structure
631 * @list_offset: offset to the SFP ID list
632 * @data_offset: offset to the SFP data block
634 s32
ixgbe_get_sfp_init_sequence_offsets(struct ixgbe_hw
*hw
,
640 if (hw
->phy
.sfp_type
== ixgbe_sfp_type_unknown
)
641 return IXGBE_ERR_SFP_NOT_SUPPORTED
;
643 if (hw
->phy
.sfp_type
== ixgbe_sfp_type_not_present
)
644 return IXGBE_ERR_SFP_NOT_PRESENT
;
646 if ((hw
->device_id
== IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM
) &&
647 (hw
->phy
.sfp_type
== ixgbe_sfp_type_da_cu
))
648 return IXGBE_ERR_SFP_NOT_SUPPORTED
;
650 /* Read offset to PHY init contents */
651 hw
->eeprom
.ops
.read(hw
, IXGBE_PHY_INIT_OFFSET_NL
, list_offset
);
653 if ((!*list_offset
) || (*list_offset
== 0xFFFF))
654 return IXGBE_ERR_PHY
;
656 /* Shift offset to first ID word */
660 * Find the matching SFP ID in the EEPROM
661 * and program the init sequence
663 hw
->eeprom
.ops
.read(hw
, *list_offset
, &sfp_id
);
665 while (sfp_id
!= IXGBE_PHY_INIT_END_NL
) {
666 if (sfp_id
== hw
->phy
.sfp_type
) {
668 hw
->eeprom
.ops
.read(hw
, *list_offset
, data_offset
);
669 if ((!*data_offset
) || (*data_offset
== 0xFFFF)) {
670 hw_dbg(hw
, "SFP+ module not supported\n");
671 return IXGBE_ERR_SFP_NOT_SUPPORTED
;
677 if (hw
->eeprom
.ops
.read(hw
, *list_offset
, &sfp_id
))
678 return IXGBE_ERR_PHY
;
682 if (sfp_id
== IXGBE_PHY_INIT_END_NL
) {
683 hw_dbg(hw
, "No matching SFP+ module found\n");
684 return IXGBE_ERR_SFP_NOT_SUPPORTED
;
691 * ixgbe_check_phy_link_tnx - Determine link and speed status
692 * @hw: pointer to hardware structure
694 * Reads the VS1 register to determine if link is up and the current speed for
697 s32
ixgbe_check_phy_link_tnx(struct ixgbe_hw
*hw
, ixgbe_link_speed
*speed
,
702 u32 max_time_out
= 10;
707 /* Initialize speed and link to default case */
709 *speed
= IXGBE_LINK_SPEED_10GB_FULL
;
712 * Check current speed and link status of the PHY register.
713 * This is a vendor specific register and may have to
714 * be changed for other copper PHYs.
716 for (time_out
= 0; time_out
< max_time_out
; time_out
++) {
718 status
= hw
->phy
.ops
.read_reg(hw
,
719 IXGBE_MDIO_VENDOR_SPECIFIC_1_STATUS
,
720 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE
,
722 phy_link
= phy_data
&
723 IXGBE_MDIO_VENDOR_SPECIFIC_1_LINK_STATUS
;
724 phy_speed
= phy_data
&
725 IXGBE_MDIO_VENDOR_SPECIFIC_1_SPEED_STATUS
;
726 if (phy_link
== IXGBE_MDIO_VENDOR_SPECIFIC_1_LINK_STATUS
) {
729 IXGBE_MDIO_VENDOR_SPECIFIC_1_SPEED_STATUS
)
730 *speed
= IXGBE_LINK_SPEED_1GB_FULL
;
739 * ixgbe_get_phy_firmware_version_tnx - Gets the PHY Firmware Version
740 * @hw: pointer to hardware structure
741 * @firmware_version: pointer to the PHY Firmware Version
743 s32
ixgbe_get_phy_firmware_version_tnx(struct ixgbe_hw
*hw
,
744 u16
*firmware_version
)
748 status
= hw
->phy
.ops
.read_reg(hw
, TNX_FW_REV
,
749 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE
,