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ixgbe: Update copyright dates, bump the driver version number
[linux-2.6.git] / drivers / net / ixgbe / ixgbe_82598.c
blob8e7315e0a7fae5d1661f61d8c61ec541713d55d0
1 /*******************************************************************************
2
3 Intel 10 Gigabit PCI Express Linux driver
4 Copyright(c) 1999 - 2009 Intel Corporation.
5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
25
26 *******************************************************************************/
27
28 #include <linux/pci.h>
29 #include <linux/delay.h>
30 #include <linux/sched.h>
31
32 #include "ixgbe.h"
33 #include "ixgbe_phy.h"
34
35 #define IXGBE_82598_MAX_TX_QUEUES 32
36 #define IXGBE_82598_MAX_RX_QUEUES 64
37 #define IXGBE_82598_RAR_ENTRIES 16
38 #define IXGBE_82598_MC_TBL_SIZE 128
39 #define IXGBE_82598_VFT_TBL_SIZE 128
40
41 static s32 ixgbe_get_copper_link_capabilities_82598(struct ixgbe_hw *hw,
42 ixgbe_link_speed *speed,
43 bool *autoneg);
44 static s32 ixgbe_setup_copper_link_82598(struct ixgbe_hw *hw);
45 static s32 ixgbe_setup_copper_link_speed_82598(struct ixgbe_hw *hw,
46 ixgbe_link_speed speed,
47 bool autoneg,
48 bool autoneg_wait_to_complete);
49 static s32 ixgbe_read_i2c_eeprom_82598(struct ixgbe_hw *hw, u8 byte_offset,
50 u8 *eeprom_data);
51
52 /**
53 * ixgbe_get_pcie_msix_count_82598 - Gets MSI-X vector count
54 * @hw: pointer to hardware structure
55 *
56 * Read PCIe configuration space, and get the MSI-X vector count from
57 * the capabilities table.
58 **/
59 u16 ixgbe_get_pcie_msix_count_82598(struct ixgbe_hw *hw)
60 {
61 struct ixgbe_adapter *adapter = hw->back;
62 u16 msix_count;
63 pci_read_config_word(adapter->pdev, IXGBE_PCIE_MSIX_82598_CAPS,
64 &msix_count);
65 msix_count &= IXGBE_PCIE_MSIX_TBL_SZ_MASK;
66
67 /* MSI-X count is zero-based in HW, so increment to give proper value */
68 msix_count++;
69
70 return msix_count;
71 }
72
73 /**
74 */
75 static s32 ixgbe_get_invariants_82598(struct ixgbe_hw *hw)
76 {
77 struct ixgbe_mac_info *mac = &hw->mac;
78 struct ixgbe_phy_info *phy = &hw->phy;
79 s32 ret_val = 0;
80 u16 list_offset, data_offset;
81
82 /* Call PHY identify routine to get the phy type */
83 ixgbe_identify_phy_generic(hw);
84
85 /* PHY Init */
86 switch (phy->type) {
87 case ixgbe_phy_tn:
88 phy->ops.check_link = &ixgbe_check_phy_link_tnx;
89 phy->ops.get_firmware_version =
90 &ixgbe_get_phy_firmware_version_tnx;
91 break;
92 case ixgbe_phy_nl:
93 phy->ops.reset = &ixgbe_reset_phy_nl;
94
95 /* Call SFP+ identify routine to get the SFP+ module type */
96 ret_val = phy->ops.identify_sfp(hw);
97 if (ret_val != 0)
98 goto out;
99 else if (hw->phy.sfp_type == ixgbe_sfp_type_unknown) {
100 ret_val = IXGBE_ERR_SFP_NOT_SUPPORTED;
101 goto out;
102 }
103
104 /* Check to see if SFP+ module is supported */
105 ret_val = ixgbe_get_sfp_init_sequence_offsets(hw,
106 &list_offset,
107 &data_offset);
108 if (ret_val != 0) {
109 ret_val = IXGBE_ERR_SFP_NOT_SUPPORTED;
110 goto out;
111 }
112 break;
113 default:
114 break;
115 }
116
117 if (mac->ops.get_media_type(hw) == ixgbe_media_type_copper) {
118 mac->ops.setup_link = &ixgbe_setup_copper_link_82598;
119 mac->ops.setup_link_speed =
120 &ixgbe_setup_copper_link_speed_82598;
121 mac->ops.get_link_capabilities =
122 &ixgbe_get_copper_link_capabilities_82598;
123 }
124
125 mac->mcft_size = IXGBE_82598_MC_TBL_SIZE;
126 mac->vft_size = IXGBE_82598_VFT_TBL_SIZE;
127 mac->num_rar_entries = IXGBE_82598_RAR_ENTRIES;
128 mac->max_rx_queues = IXGBE_82598_MAX_RX_QUEUES;
129 mac->max_tx_queues = IXGBE_82598_MAX_TX_QUEUES;
130 mac->max_msix_vectors = ixgbe_get_pcie_msix_count_82598(hw);
131
132 out:
133 return ret_val;
134 }
135
136 /**
137 * ixgbe_get_link_capabilities_82598 - Determines link capabilities
138 * @hw: pointer to hardware structure
139 * @speed: pointer to link speed
140 * @autoneg: boolean auto-negotiation value
141 *
142 * Determines the link capabilities by reading the AUTOC register.
143 **/
144 static s32 ixgbe_get_link_capabilities_82598(struct ixgbe_hw *hw,
145 ixgbe_link_speed *speed,
146 bool *autoneg)
147 {
148 s32 status = 0;
149 s32 autoc_reg;
150
151 autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC);
152
153 if (hw->mac.link_settings_loaded) {
154 autoc_reg &= ~IXGBE_AUTOC_LMS_ATTACH_TYPE;
155 autoc_reg &= ~IXGBE_AUTOC_LMS_MASK;
156 autoc_reg |= hw->mac.link_attach_type;
157 autoc_reg |= hw->mac.link_mode_select;
158 }
159
160 switch (autoc_reg & IXGBE_AUTOC_LMS_MASK) {
161 case IXGBE_AUTOC_LMS_1G_LINK_NO_AN:
162 *speed = IXGBE_LINK_SPEED_1GB_FULL;
163 *autoneg = false;
164 break;
165
166 case IXGBE_AUTOC_LMS_10G_LINK_NO_AN:
167 *speed = IXGBE_LINK_SPEED_10GB_FULL;
168 *autoneg = false;
169 break;
170
171 case IXGBE_AUTOC_LMS_1G_AN:
172 *speed = IXGBE_LINK_SPEED_1GB_FULL;
173 *autoneg = true;
174 break;
175
176 case IXGBE_AUTOC_LMS_KX4_AN:
177 case IXGBE_AUTOC_LMS_KX4_AN_1G_AN:
178 *speed = IXGBE_LINK_SPEED_UNKNOWN;
179 if (autoc_reg & IXGBE_AUTOC_KX4_SUPP)
180 *speed |= IXGBE_LINK_SPEED_10GB_FULL;
181 if (autoc_reg & IXGBE_AUTOC_KX_SUPP)
182 *speed |= IXGBE_LINK_SPEED_1GB_FULL;
183 *autoneg = true;
184 break;
185
186 default:
187 status = IXGBE_ERR_LINK_SETUP;
188 break;
189 }
190
191 return status;
192 }
193
194 /**
195 * ixgbe_get_copper_link_capabilities_82598 - Determines link capabilities
196 * @hw: pointer to hardware structure
197 * @speed: pointer to link speed
198 * @autoneg: boolean auto-negotiation value
199 *
200 * Determines the link capabilities by reading the AUTOC register.
201 **/
202 static s32 ixgbe_get_copper_link_capabilities_82598(struct ixgbe_hw *hw,
203 ixgbe_link_speed *speed,
204 bool *autoneg)
205 {
206 s32 status = IXGBE_ERR_LINK_SETUP;
207 u16 speed_ability;
208
209 *speed = 0;
210 *autoneg = true;
211
212 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_SPEED_ABILITY,
213 IXGBE_MDIO_PMA_PMD_DEV_TYPE,
214 &speed_ability);
215
216 if (status == 0) {
217 if (speed_ability & IXGBE_MDIO_PHY_SPEED_10G)
218 *speed |= IXGBE_LINK_SPEED_10GB_FULL;
219 if (speed_ability & IXGBE_MDIO_PHY_SPEED_1G)
220 *speed |= IXGBE_LINK_SPEED_1GB_FULL;
221 }
222
223 return status;
224 }
225
226 /**
227 * ixgbe_get_media_type_82598 - Determines media type
228 * @hw: pointer to hardware structure
229 *
230 * Returns the media type (fiber, copper, backplane)
231 **/
232 static enum ixgbe_media_type ixgbe_get_media_type_82598(struct ixgbe_hw *hw)
233 {
234 enum ixgbe_media_type media_type;
235
236 /* Media type for I82598 is based on device ID */
237 switch (hw->device_id) {
238 case IXGBE_DEV_ID_82598:
239 case IXGBE_DEV_ID_82598_BX:
240 media_type = ixgbe_media_type_backplane;
241 break;
242 case IXGBE_DEV_ID_82598AF_DUAL_PORT:
243 case IXGBE_DEV_ID_82598AF_SINGLE_PORT:
244 case IXGBE_DEV_ID_82598EB_CX4:
245 case IXGBE_DEV_ID_82598_CX4_DUAL_PORT:
246 case IXGBE_DEV_ID_82598_DA_DUAL_PORT:
247 case IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM:
248 case IXGBE_DEV_ID_82598EB_XF_LR:
249 case IXGBE_DEV_ID_82598EB_SFP_LOM:
250 media_type = ixgbe_media_type_fiber;
251 break;
252 case IXGBE_DEV_ID_82598AT:
253 media_type = ixgbe_media_type_copper;
254 break;
255 default:
256 media_type = ixgbe_media_type_unknown;
257 break;
258 }
259
260 return media_type;
261 }
262
263 /**
264 * ixgbe_setup_fc_82598 - Configure flow control settings
265 * @hw: pointer to hardware structure
266 * @packetbuf_num: packet buffer number (0-7)
267 *
268 * Configures the flow control settings based on SW configuration. This
269 * function is used for 802.3x flow control configuration only.
270 **/
271 static s32 ixgbe_setup_fc_82598(struct ixgbe_hw *hw, s32 packetbuf_num)
272 {
273 u32 frctl_reg;
274 u32 rmcs_reg;
275
276 if (packetbuf_num < 0 || packetbuf_num > 7) {
277 hw_dbg(hw, "Invalid packet buffer number [%d], expected range is"
278 " 0-7\n", packetbuf_num);
279 }
280
281 frctl_reg = IXGBE_READ_REG(hw, IXGBE_FCTRL);
282 frctl_reg &= ~(IXGBE_FCTRL_RFCE | IXGBE_FCTRL_RPFCE);
283
284 rmcs_reg = IXGBE_READ_REG(hw, IXGBE_RMCS);
285 rmcs_reg &= ~(IXGBE_RMCS_TFCE_PRIORITY | IXGBE_RMCS_TFCE_802_3X);
286
287 /*
288 * 10 gig parts do not have a word in the EEPROM to determine the
289 * default flow control setting, so we explicitly set it to full.
290 */
291 if (hw->fc.type == ixgbe_fc_default)
292 hw->fc.type = ixgbe_fc_full;
293
294 /*
295 * We want to save off the original Flow Control configuration just in
296 * case we get disconnected and then reconnected into a different hub
297 * or switch with different Flow Control capabilities.
298 */
299 hw->fc.original_type = hw->fc.type;
300
301 /*
302 * The possible values of the "flow_control" parameter are:
303 * 0: Flow control is completely disabled
304 * 1: Rx flow control is enabled (we can receive pause frames but not
305 * send pause frames).
306 * 2: Tx flow control is enabled (we can send pause frames but we do not
307 * support receiving pause frames)
308 * 3: Both Rx and Tx flow control (symmetric) are enabled.
309 * other: Invalid.
310 */
311 switch (hw->fc.type) {
312 case ixgbe_fc_none:
313 break;
314 case ixgbe_fc_rx_pause:
315 /*
316 * Rx Flow control is enabled,
317 * and Tx Flow control is disabled.
318 */
319 frctl_reg |= IXGBE_FCTRL_RFCE;
320 break;
321 case ixgbe_fc_tx_pause:
322 /*
323 * Tx Flow control is enabled, and Rx Flow control is disabled,
324 * by a software over-ride.
325 */
326 rmcs_reg |= IXGBE_RMCS_TFCE_802_3X;
327 break;
328 case ixgbe_fc_full:
329 /*
330 * Flow control (both Rx and Tx) is enabled by a software
331 * over-ride.
332 */
333 frctl_reg |= IXGBE_FCTRL_RFCE;
334 rmcs_reg |= IXGBE_RMCS_TFCE_802_3X;
335 break;
336 default:
337 /* We should never get here. The value should be 0-3. */
338 hw_dbg(hw, "Flow control param set incorrectly\n");
339 break;
340 }
341
342 /* Enable 802.3x based flow control settings. */
343 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, frctl_reg);
344 IXGBE_WRITE_REG(hw, IXGBE_RMCS, rmcs_reg);
345
346 /*
347 * Check for invalid software configuration, zeros are completely
348 * invalid for all parameters used past this point, and if we enable
349 * flow control with zero water marks, we blast flow control packets.
350 */
351 if (!hw->fc.low_water || !hw->fc.high_water || !hw->fc.pause_time) {
352 hw_dbg(hw, "Flow control structure initialized incorrectly\n");
353 return IXGBE_ERR_INVALID_LINK_SETTINGS;
354 }
355
356 /*
357 * We need to set up the Receive Threshold high and low water
358 * marks as well as (optionally) enabling the transmission of
359 * XON frames.
360 */
361 if (hw->fc.type & ixgbe_fc_tx_pause) {
362 if (hw->fc.send_xon) {
363 IXGBE_WRITE_REG(hw, IXGBE_FCRTL(packetbuf_num),
364 (hw->fc.low_water | IXGBE_FCRTL_XONE));
365 } else {
366 IXGBE_WRITE_REG(hw, IXGBE_FCRTL(packetbuf_num),
367 hw->fc.low_water);
368 }
369 IXGBE_WRITE_REG(hw, IXGBE_FCRTH(packetbuf_num),
370 (hw->fc.high_water)|IXGBE_FCRTH_FCEN);
371 }
372
373 IXGBE_WRITE_REG(hw, IXGBE_FCTTV(0), hw->fc.pause_time);
374 IXGBE_WRITE_REG(hw, IXGBE_FCRTV, (hw->fc.pause_time >> 1));
375
376 return 0;
377 }
378
379 /**
380 * ixgbe_setup_mac_link_82598 - Configures MAC link settings
381 * @hw: pointer to hardware structure
382 *
383 * Configures link settings based on values in the ixgbe_hw struct.
384 * Restarts the link. Performs autonegotiation if needed.
385 **/
386 static s32 ixgbe_setup_mac_link_82598(struct ixgbe_hw *hw)
387 {
388 u32 autoc_reg;
389 u32 links_reg;
390 u32 i;
391 s32 status = 0;
392
393 autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC);
394
395 if (hw->mac.link_settings_loaded) {
396 autoc_reg &= ~IXGBE_AUTOC_LMS_ATTACH_TYPE;
397 autoc_reg &= ~IXGBE_AUTOC_LMS_MASK;
398 autoc_reg |= hw->mac.link_attach_type;
399 autoc_reg |= hw->mac.link_mode_select;
400
401 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc_reg);
402 IXGBE_WRITE_FLUSH(hw);
403 msleep(50);
404 }
405
406 /* Restart link */
407 autoc_reg |= IXGBE_AUTOC_AN_RESTART;
408 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc_reg);
409
410 /* Only poll for autoneg to complete if specified to do so */
411 if (hw->phy.autoneg_wait_to_complete) {
412 if (hw->mac.link_mode_select == IXGBE_AUTOC_LMS_KX4_AN ||
413 hw->mac.link_mode_select == IXGBE_AUTOC_LMS_KX4_AN_1G_AN) {
414 links_reg = 0; /* Just in case Autoneg time = 0 */
415 for (i = 0; i < IXGBE_AUTO_NEG_TIME; i++) {
416 links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS);
417 if (links_reg & IXGBE_LINKS_KX_AN_COMP)
418 break;
419 msleep(100);
420 }
421 if (!(links_reg & IXGBE_LINKS_KX_AN_COMP)) {
422 status = IXGBE_ERR_AUTONEG_NOT_COMPLETE;
423 hw_dbg(hw, "Autonegotiation did not complete.\n");
424 }
425 }
426 }
427
428 /*
429 * We want to save off the original Flow Control configuration just in
430 * case we get disconnected and then reconnected into a different hub
431 * or switch with different Flow Control capabilities.
432 */
433 hw->fc.original_type = hw->fc.type;
434 ixgbe_setup_fc_82598(hw, 0);
435
436 /* Add delay to filter out noises during initial link setup */
437 msleep(50);
438
439 return status;
440 }
441
442 /**
443 * ixgbe_check_mac_link_82598 - Get link/speed status
444 * @hw: pointer to hardware structure
445 * @speed: pointer to link speed
446 * @link_up: true is link is up, false otherwise
447 * @link_up_wait_to_complete: bool used to wait for link up or not
448 *
449 * Reads the links register to determine if link is up and the current speed
450 **/
451 static s32 ixgbe_check_mac_link_82598(struct ixgbe_hw *hw,
452 ixgbe_link_speed *speed, bool *link_up,
453 bool link_up_wait_to_complete)
454 {
455 u32 links_reg;
456 u32 i;
457 u16 link_reg, adapt_comp_reg;
458
459 /*
460 * SERDES PHY requires us to read link status from register 0xC79F.
461 * Bit 0 set indicates link is up/ready; clear indicates link down.
462 * 0xC00C is read to check that the XAUI lanes are active. Bit 0
463 * clear indicates active; set indicates inactive.
464 */
465 if (hw->phy.type == ixgbe_phy_nl) {
466 hw->phy.ops.read_reg(hw, 0xC79F, IXGBE_TWINAX_DEV, &link_reg);
467 hw->phy.ops.read_reg(hw, 0xC79F, IXGBE_TWINAX_DEV, &link_reg);
468 hw->phy.ops.read_reg(hw, 0xC00C, IXGBE_TWINAX_DEV,
469 &adapt_comp_reg);
470 if (link_up_wait_to_complete) {
471 for (i = 0; i < IXGBE_LINK_UP_TIME; i++) {
472 if ((link_reg & 1) &&
473 ((adapt_comp_reg & 1) == 0)) {
474 *link_up = true;
475 break;
476 } else {
477 *link_up = false;
478 }
479 msleep(100);
480 hw->phy.ops.read_reg(hw, 0xC79F,
481 IXGBE_TWINAX_DEV,
482 &link_reg);
483 hw->phy.ops.read_reg(hw, 0xC00C,
484 IXGBE_TWINAX_DEV,
485 &adapt_comp_reg);
486 }
487 } else {
488 if ((link_reg & 1) && ((adapt_comp_reg & 1) == 0))
489 *link_up = true;
490 else
491 *link_up = false;
492 }
493
494 if (*link_up == false)
495 goto out;
496 }
497
498 links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS);
499 if (link_up_wait_to_complete) {
500 for (i = 0; i < IXGBE_LINK_UP_TIME; i++) {
501 if (links_reg & IXGBE_LINKS_UP) {
502 *link_up = true;
503 break;
504 } else {
505 *link_up = false;
506 }
507 msleep(100);
508 links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS);
509 }
510 } else {
511 if (links_reg & IXGBE_LINKS_UP)
512 *link_up = true;
513 else
514 *link_up = false;
515 }
516
517 if (links_reg & IXGBE_LINKS_SPEED)
518 *speed = IXGBE_LINK_SPEED_10GB_FULL;
519 else
520 *speed = IXGBE_LINK_SPEED_1GB_FULL;
521
522 out:
523 return 0;
524 }
525
526
527 /**
528 * ixgbe_setup_mac_link_speed_82598 - Set MAC link speed
529 * @hw: pointer to hardware structure
530 * @speed: new link speed
531 * @autoneg: true if auto-negotiation enabled
532 * @autoneg_wait_to_complete: true if waiting is needed to complete
533 *
534 * Set the link speed in the AUTOC register and restarts link.
535 **/
536 static s32 ixgbe_setup_mac_link_speed_82598(struct ixgbe_hw *hw,
537 ixgbe_link_speed speed, bool autoneg,
538 bool autoneg_wait_to_complete)
539 {
540 s32 status = 0;
541
542 /* If speed is 10G, then check for CX4 or XAUI. */
543 if ((speed == IXGBE_LINK_SPEED_10GB_FULL) &&
544 (!(hw->mac.link_attach_type & IXGBE_AUTOC_10G_KX4))) {
545 hw->mac.link_mode_select = IXGBE_AUTOC_LMS_10G_LINK_NO_AN;
546 } else if ((speed == IXGBE_LINK_SPEED_1GB_FULL) && (!autoneg)) {
547 hw->mac.link_mode_select = IXGBE_AUTOC_LMS_1G_LINK_NO_AN;
548 } else if (autoneg) {
549 /* BX mode - Autonegotiate 1G */
550 if (!(hw->mac.link_attach_type & IXGBE_AUTOC_1G_PMA_PMD))
551 hw->mac.link_mode_select = IXGBE_AUTOC_LMS_1G_AN;
552 else /* KX/KX4 mode */
553 hw->mac.link_mode_select = IXGBE_AUTOC_LMS_KX4_AN_1G_AN;
554 } else {
555 status = IXGBE_ERR_LINK_SETUP;
556 }
557
558 if (status == 0) {
559 hw->phy.autoneg_wait_to_complete = autoneg_wait_to_complete;
560
561 hw->mac.link_settings_loaded = true;
562 /*
563 * Setup and restart the link based on the new values in
564 * ixgbe_hw This will write the AUTOC register based on the new
565 * stored values
566 */
567 ixgbe_setup_mac_link_82598(hw);
568 }
569
570 return status;
571 }
572
573
574 /**
575 * ixgbe_setup_copper_link_82598 - Setup copper link settings
576 * @hw: pointer to hardware structure
577 *
578 * Configures link settings based on values in the ixgbe_hw struct.
579 * Restarts the link. Performs autonegotiation if needed. Restart
580 * phy and wait for autonegotiate to finish. Then synchronize the
581 * MAC and PHY.
582 **/
583 static s32 ixgbe_setup_copper_link_82598(struct ixgbe_hw *hw)
584 {
585 s32 status;
586
587 /* Restart autonegotiation on PHY */
588 status = hw->phy.ops.setup_link(hw);
589
590 /* Set MAC to KX/KX4 autoneg, which defaults to Parallel detection */
591 hw->mac.link_attach_type = (IXGBE_AUTOC_10G_KX4 | IXGBE_AUTOC_1G_KX);
592 hw->mac.link_mode_select = IXGBE_AUTOC_LMS_KX4_AN;
593
594 /* Set up MAC */
595 ixgbe_setup_mac_link_82598(hw);
596
597 return status;
598 }
599
600 /**
601 * ixgbe_setup_copper_link_speed_82598 - Set the PHY autoneg advertised field
602 * @hw: pointer to hardware structure
603 * @speed: new link speed
604 * @autoneg: true if autonegotiation enabled
605 * @autoneg_wait_to_complete: true if waiting is needed to complete
606 *
607 * Sets the link speed in the AUTOC register in the MAC and restarts link.
608 **/
609 static s32 ixgbe_setup_copper_link_speed_82598(struct ixgbe_hw *hw,
610 ixgbe_link_speed speed,
611 bool autoneg,
612 bool autoneg_wait_to_complete)
613 {
614 s32 status;
615
616 /* Setup the PHY according to input speed */
617 status = hw->phy.ops.setup_link_speed(hw, speed, autoneg,
618 autoneg_wait_to_complete);
619
620 /* Set MAC to KX/KX4 autoneg, which defaults to Parallel detection */
621 hw->mac.link_attach_type = (IXGBE_AUTOC_10G_KX4 | IXGBE_AUTOC_1G_KX);
622 hw->mac.link_mode_select = IXGBE_AUTOC_LMS_KX4_AN;
623
624 /* Set up MAC */
625 ixgbe_setup_mac_link_82598(hw);
626
627 return status;
628 }
629
630 /**
631 * ixgbe_reset_hw_82598 - Performs hardware reset
632 * @hw: pointer to hardware structure
633 *
634 * Resets the hardware by resetting the transmit and receive units, masks and
635 * clears all interrupts, performing a PHY reset, and performing a link (MAC)
636 * reset.
637 **/
638 static s32 ixgbe_reset_hw_82598(struct ixgbe_hw *hw)
639 {
640 s32 status = 0;
641 u32 ctrl;
642 u32 gheccr;
643 u32 i;
644 u32 autoc;
645 u8 analog_val;
646
647 /* Call adapter stop to disable tx/rx and clear interrupts */
648 hw->mac.ops.stop_adapter(hw);
649
650 /*
651 * Power up the Atlas Tx lanes if they are currently powered down.
652 * Atlas Tx lanes are powered down for MAC loopback tests, but
653 * they are not automatically restored on reset.
654 */
655 hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_LPBK, &analog_val);
656 if (analog_val & IXGBE_ATLAS_PDN_TX_REG_EN) {
657 /* Enable Tx Atlas so packets can be transmitted again */
658 hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_LPBK,
659 &analog_val);
660 analog_val &= ~IXGBE_ATLAS_PDN_TX_REG_EN;
661 hw->mac.ops.write_analog_reg8(hw, IXGBE_ATLAS_PDN_LPBK,
662 analog_val);
663
664 hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_10G,
665 &analog_val);
666 analog_val &= ~IXGBE_ATLAS_PDN_TX_10G_QL_ALL;
667 hw->mac.ops.write_analog_reg8(hw, IXGBE_ATLAS_PDN_10G,
668 analog_val);
669
670 hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_1G,
671 &analog_val);
672 analog_val &= ~IXGBE_ATLAS_PDN_TX_1G_QL_ALL;
673 hw->mac.ops.write_analog_reg8(hw, IXGBE_ATLAS_PDN_1G,
674 analog_val);
675
676 hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_AN,
677 &analog_val);
678 analog_val &= ~IXGBE_ATLAS_PDN_TX_AN_QL_ALL;
679 hw->mac.ops.write_analog_reg8(hw, IXGBE_ATLAS_PDN_AN,
680 analog_val);
681 }
682
683 /* Reset PHY */
684 if (hw->phy.reset_disable == false)
685 hw->phy.ops.reset(hw);
686
687 /*
688 * Prevent the PCI-E bus from from hanging by disabling PCI-E master
689 * access and verify no pending requests before reset
690 */
691 if (ixgbe_disable_pcie_master(hw) != 0) {
692 status = IXGBE_ERR_MASTER_REQUESTS_PENDING;
693 hw_dbg(hw, "PCI-E Master disable polling has failed.\n");
694 }
695
696 /*
697 * Issue global reset to the MAC. This needs to be a SW reset.
698 * If link reset is used, it might reset the MAC when mng is using it
699 */
700 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
701 IXGBE_WRITE_REG(hw, IXGBE_CTRL, (ctrl | IXGBE_CTRL_RST));
702 IXGBE_WRITE_FLUSH(hw);
703
704 /* Poll for reset bit to self-clear indicating reset is complete */
705 for (i = 0; i < 10; i++) {
706 udelay(1);
707 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
708 if (!(ctrl & IXGBE_CTRL_RST))
709 break;
710 }
711 if (ctrl & IXGBE_CTRL_RST) {
712 status = IXGBE_ERR_RESET_FAILED;
713 hw_dbg(hw, "Reset polling failed to complete.\n");
714 }
715
716 msleep(50);
717
718 gheccr = IXGBE_READ_REG(hw, IXGBE_GHECCR);
719 gheccr &= ~((1 << 21) | (1 << 18) | (1 << 9) | (1 << 6));
720 IXGBE_WRITE_REG(hw, IXGBE_GHECCR, gheccr);
721
722 /*
723 * AUTOC register which stores link settings gets cleared
724 * and reloaded from EEPROM after reset. We need to restore
725 * our stored value from init in case SW changed the attach
726 * type or speed. If this is the first time and link settings
727 * have not been stored, store default settings from AUTOC.
728 */
729 autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC);
730 if (hw->mac.link_settings_loaded) {
731 autoc &= ~(IXGBE_AUTOC_LMS_ATTACH_TYPE);
732 autoc &= ~(IXGBE_AUTOC_LMS_MASK);
733 autoc |= hw->mac.link_attach_type;
734 autoc |= hw->mac.link_mode_select;
735 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc);
736 } else {
737 hw->mac.link_attach_type =
738 (autoc & IXGBE_AUTOC_LMS_ATTACH_TYPE);
739 hw->mac.link_mode_select = (autoc & IXGBE_AUTOC_LMS_MASK);
740 hw->mac.link_settings_loaded = true;
741 }
742
743 /* Store the permanent mac address */
744 hw->mac.ops.get_mac_addr(hw, hw->mac.perm_addr);
745
746 return status;
747 }
748
749 /**
750 * ixgbe_set_vmdq_82598 - Associate a VMDq set index with a rx address
751 * @hw: pointer to hardware struct
752 * @rar: receive address register index to associate with a VMDq index
753 * @vmdq: VMDq set index
754 **/
755 static s32 ixgbe_set_vmdq_82598(struct ixgbe_hw *hw, u32 rar, u32 vmdq)
756 {
757 u32 rar_high;
758
759 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(rar));
760 rar_high &= ~IXGBE_RAH_VIND_MASK;
761 rar_high |= ((vmdq << IXGBE_RAH_VIND_SHIFT) & IXGBE_RAH_VIND_MASK);
762 IXGBE_WRITE_REG(hw, IXGBE_RAH(rar), rar_high);
763 return 0;
764 }
765
766 /**
767 * ixgbe_clear_vmdq_82598 - Disassociate a VMDq set index from an rx address
768 * @hw: pointer to hardware struct
769 * @rar: receive address register index to associate with a VMDq index
770 * @vmdq: VMDq clear index (not used in 82598, but elsewhere)
771 **/
772 static s32 ixgbe_clear_vmdq_82598(struct ixgbe_hw *hw, u32 rar, u32 vmdq)
773 {
774 u32 rar_high;
775 u32 rar_entries = hw->mac.num_rar_entries;
776
777 if (rar < rar_entries) {
778 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(rar));
779 if (rar_high & IXGBE_RAH_VIND_MASK) {
780 rar_high &= ~IXGBE_RAH_VIND_MASK;
781 IXGBE_WRITE_REG(hw, IXGBE_RAH(rar), rar_high);
782 }
783 } else {
784 hw_dbg(hw, "RAR index %d is out of range.\n", rar);
785 }
786
787 return 0;
788 }
789
790 /**
791 * ixgbe_set_vfta_82598 - Set VLAN filter table
792 * @hw: pointer to hardware structure
793 * @vlan: VLAN id to write to VLAN filter
794 * @vind: VMDq output index that maps queue to VLAN id in VFTA
795 * @vlan_on: boolean flag to turn on/off VLAN in VFTA
796 *
797 * Turn on/off specified VLAN in the VLAN filter table.
798 **/
799 static s32 ixgbe_set_vfta_82598(struct ixgbe_hw *hw, u32 vlan, u32 vind,
800 bool vlan_on)
801 {
802 u32 regindex;
803 u32 bitindex;
804 u32 bits;
805 u32 vftabyte;
806
807 if (vlan > 4095)
808 return IXGBE_ERR_PARAM;
809
810 /* Determine 32-bit word position in array */
811 regindex = (vlan >> 5) & 0x7F; /* upper seven bits */
812
813 /* Determine the location of the (VMD) queue index */
814 vftabyte = ((vlan >> 3) & 0x03); /* bits (4:3) indicating byte array */
815 bitindex = (vlan & 0x7) << 2; /* lower 3 bits indicate nibble */
816
817 /* Set the nibble for VMD queue index */
818 bits = IXGBE_READ_REG(hw, IXGBE_VFTAVIND(vftabyte, regindex));
819 bits &= (~(0x0F << bitindex));
820 bits |= (vind << bitindex);
821 IXGBE_WRITE_REG(hw, IXGBE_VFTAVIND(vftabyte, regindex), bits);
822
823 /* Determine the location of the bit for this VLAN id */
824 bitindex = vlan & 0x1F; /* lower five bits */
825
826 bits = IXGBE_READ_REG(hw, IXGBE_VFTA(regindex));
827 if (vlan_on)
828 /* Turn on this VLAN id */
829 bits |= (1 << bitindex);
830 else
831 /* Turn off this VLAN id */
832 bits &= ~(1 << bitindex);
833 IXGBE_WRITE_REG(hw, IXGBE_VFTA(regindex), bits);
834
835 return 0;
836 }
837
838 /**
839 * ixgbe_clear_vfta_82598 - Clear VLAN filter table
840 * @hw: pointer to hardware structure
841 *
842 * Clears the VLAN filer table, and the VMDq index associated with the filter
843 **/
844 static s32 ixgbe_clear_vfta_82598(struct ixgbe_hw *hw)
845 {
846 u32 offset;
847 u32 vlanbyte;
848
849 for (offset = 0; offset < hw->mac.vft_size; offset++)
850 IXGBE_WRITE_REG(hw, IXGBE_VFTA(offset), 0);
851
852 for (vlanbyte = 0; vlanbyte < 4; vlanbyte++)
853 for (offset = 0; offset < hw->mac.vft_size; offset++)
854 IXGBE_WRITE_REG(hw, IXGBE_VFTAVIND(vlanbyte, offset),
855 0);
856
857 return 0;
858 }
859
860 /**
861 * ixgbe_blink_led_start_82598 - Blink LED based on index.
862 * @hw: pointer to hardware structure
863 * @index: led number to blink
864 **/
865 static s32 ixgbe_blink_led_start_82598(struct ixgbe_hw *hw, u32 index)
866 {
867 ixgbe_link_speed speed = 0;
868 bool link_up = 0;
869 u32 autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC);
870 u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
871
872 /*
873 * Link must be up to auto-blink the LEDs on the 82598EB MAC;
874 * force it if link is down.
875 */
876 hw->mac.ops.check_link(hw, &speed, &link_up, false);
877
878 if (!link_up) {
879 autoc_reg |= IXGBE_AUTOC_FLU;
880 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc_reg);
881 msleep(10);
882 }
883
884 led_reg &= ~IXGBE_LED_MODE_MASK(index);
885 led_reg |= IXGBE_LED_BLINK(index);
886 IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, led_reg);
887 IXGBE_WRITE_FLUSH(hw);
888
889 return 0;
890 }
891
892 /**
893 * ixgbe_blink_led_stop_82598 - Stop blinking LED based on index.
894 * @hw: pointer to hardware structure
895 * @index: led number to stop blinking
896 **/
897 static s32 ixgbe_blink_led_stop_82598(struct ixgbe_hw *hw, u32 index)
898 {
899 u32 autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC);
900 u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
901
902 autoc_reg &= ~IXGBE_AUTOC_FLU;
903 autoc_reg |= IXGBE_AUTOC_AN_RESTART;
904 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc_reg);
905
906 led_reg &= ~IXGBE_LED_MODE_MASK(index);
907 led_reg &= ~IXGBE_LED_BLINK(index);
908 led_reg |= IXGBE_LED_LINK_ACTIVE << IXGBE_LED_MODE_SHIFT(index);
909 IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, led_reg);
910 IXGBE_WRITE_FLUSH(hw);
911
912 return 0;
913 }
914
915 /**
916 * ixgbe_read_analog_reg8_82598 - Reads 8 bit Atlas analog register
917 * @hw: pointer to hardware structure
918 * @reg: analog register to read
919 * @val: read value
920 *
921 * Performs read operation to Atlas analog register specified.
922 **/
923 static s32 ixgbe_read_analog_reg8_82598(struct ixgbe_hw *hw, u32 reg, u8 *val)
924 {
925 u32 atlas_ctl;
926
927 IXGBE_WRITE_REG(hw, IXGBE_ATLASCTL,
928 IXGBE_ATLASCTL_WRITE_CMD | (reg << 8));
929 IXGBE_WRITE_FLUSH(hw);
930 udelay(10);
931 atlas_ctl = IXGBE_READ_REG(hw, IXGBE_ATLASCTL);
932 *val = (u8)atlas_ctl;
933
934 return 0;
935 }
936
937 /**
938 * ixgbe_write_analog_reg8_82598 - Writes 8 bit Atlas analog register
939 * @hw: pointer to hardware structure
940 * @reg: atlas register to write
941 * @val: value to write
942 *
943 * Performs write operation to Atlas analog register specified.
944 **/
945 static s32 ixgbe_write_analog_reg8_82598(struct ixgbe_hw *hw, u32 reg, u8 val)
946 {
947 u32 atlas_ctl;
948
949 atlas_ctl = (reg << 8) | val;
950 IXGBE_WRITE_REG(hw, IXGBE_ATLASCTL, atlas_ctl);
951 IXGBE_WRITE_FLUSH(hw);
952 udelay(10);
953
954 return 0;
955 }
956
957 /**
958 * ixgbe_read_i2c_eeprom_82598 - Read 8 bit EEPROM word of an SFP+ module
959 * over I2C interface through an intermediate phy.
960 * @hw: pointer to hardware structure
961 * @byte_offset: EEPROM byte offset to read
962 * @eeprom_data: value read
963 *
964 * Performs byte read operation to SFP module's EEPROM over I2C interface.
965 **/
966 static s32 ixgbe_read_i2c_eeprom_82598(struct ixgbe_hw *hw, u8 byte_offset,
967 u8 *eeprom_data)
968 {
969 s32 status = 0;
970 u16 sfp_addr = 0;
971 u16 sfp_data = 0;
972 u16 sfp_stat = 0;
973 u32 i;
974
975 if (hw->phy.type == ixgbe_phy_nl) {
976 /*
977 * phy SDA/SCL registers are at addresses 0xC30A to
978 * 0xC30D. These registers are used to talk to the SFP+
979 * module's EEPROM through the SDA/SCL (I2C) interface.
980 */
981 sfp_addr = (IXGBE_I2C_EEPROM_DEV_ADDR << 8) + byte_offset;
982 sfp_addr = (sfp_addr | IXGBE_I2C_EEPROM_READ_MASK);
983 hw->phy.ops.write_reg(hw,
984 IXGBE_MDIO_PMA_PMD_SDA_SCL_ADDR,
985 IXGBE_MDIO_PMA_PMD_DEV_TYPE,
986 sfp_addr);
987
988 /* Poll status */
989 for (i = 0; i < 100; i++) {
990 hw->phy.ops.read_reg(hw,
991 IXGBE_MDIO_PMA_PMD_SDA_SCL_STAT,
992 IXGBE_MDIO_PMA_PMD_DEV_TYPE,
993 &sfp_stat);
994 sfp_stat = sfp_stat & IXGBE_I2C_EEPROM_STATUS_MASK;
995 if (sfp_stat != IXGBE_I2C_EEPROM_STATUS_IN_PROGRESS)
996 break;
997 msleep(10);
998 }
999
1000 if (sfp_stat != IXGBE_I2C_EEPROM_STATUS_PASS) {
1001 hw_dbg(hw, "EEPROM read did not pass.\n");
1002 status = IXGBE_ERR_SFP_NOT_PRESENT;
1003 goto out;
1004 }
1005
1006 /* Read data */
1007 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PMA_PMD_SDA_SCL_DATA,
1008 IXGBE_MDIO_PMA_PMD_DEV_TYPE, &sfp_data);
1009
1010 *eeprom_data = (u8)(sfp_data >> 8);
1011 } else {
1012 status = IXGBE_ERR_PHY;
1013 goto out;
1014 }
1015
1016 out:
1017 return status;
1018 }
1019
1020 /**
1021 * ixgbe_get_supported_physical_layer_82598 - Returns physical layer type
1022 * @hw: pointer to hardware structure
1023 *
1024 * Determines physical layer capabilities of the current configuration.
1025 **/
1026 static s32 ixgbe_get_supported_physical_layer_82598(struct ixgbe_hw *hw)
1027 {
1028 s32 physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN;
1029
1030 switch (hw->device_id) {
1031 case IXGBE_DEV_ID_82598:
1032 /* Default device ID is mezzanine card KX/KX4 */
1033 physical_layer = (IXGBE_PHYSICAL_LAYER_10GBASE_KX4 |
1034 IXGBE_PHYSICAL_LAYER_1000BASE_KX);
1035 break;
1036 case IXGBE_DEV_ID_82598_BX:
1037 physical_layer = IXGBE_PHYSICAL_LAYER_1000BASE_BX;
1038 case IXGBE_DEV_ID_82598EB_CX4:
1039 case IXGBE_DEV_ID_82598_CX4_DUAL_PORT:
1040 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_CX4;
1041 break;
1042 case IXGBE_DEV_ID_82598_DA_DUAL_PORT:
1043 physical_layer = IXGBE_PHYSICAL_LAYER_SFP_PLUS_CU;
1044 break;
1045 case IXGBE_DEV_ID_82598AF_DUAL_PORT:
1046 case IXGBE_DEV_ID_82598AF_SINGLE_PORT:
1047 case IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM:
1048 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_SR;
1049 break;
1050 case IXGBE_DEV_ID_82598EB_XF_LR:
1051 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_LR;
1052 break;
1053 case IXGBE_DEV_ID_82598AT:
1054 physical_layer = (IXGBE_PHYSICAL_LAYER_10GBASE_T |
1055 IXGBE_PHYSICAL_LAYER_1000BASE_T);
1056 break;
1057 case IXGBE_DEV_ID_82598EB_SFP_LOM:
1058 hw->phy.ops.identify_sfp(hw);
1059
1060 switch (hw->phy.sfp_type) {
1061 case ixgbe_sfp_type_da_cu:
1062 physical_layer = IXGBE_PHYSICAL_LAYER_SFP_PLUS_CU;
1063 break;
1064 case ixgbe_sfp_type_sr:
1065 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_SR;
1066 break;
1067 case ixgbe_sfp_type_lr:
1068 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_LR;
1069 break;
1070 default:
1071 physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN;
1072 break;
1073 }
1074 break;
1075
1076 default:
1077 physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN;
1078 break;
1079 }
1080
1081 return physical_layer;
1082 }
1083
1084 static struct ixgbe_mac_operations mac_ops_82598 = {
1085 .init_hw = &ixgbe_init_hw_generic,
1086 .reset_hw = &ixgbe_reset_hw_82598,
1087 .start_hw = &ixgbe_start_hw_generic,
1088 .clear_hw_cntrs = &ixgbe_clear_hw_cntrs_generic,
1089 .get_media_type = &ixgbe_get_media_type_82598,
1090 .get_supported_physical_layer = &ixgbe_get_supported_physical_layer_82598,
1091 .get_mac_addr = &ixgbe_get_mac_addr_generic,
1092 .stop_adapter = &ixgbe_stop_adapter_generic,
1093 .read_analog_reg8 = &ixgbe_read_analog_reg8_82598,
1094 .write_analog_reg8 = &ixgbe_write_analog_reg8_82598,
1095 .setup_link = &ixgbe_setup_mac_link_82598,
1096 .setup_link_speed = &ixgbe_setup_mac_link_speed_82598,
1097 .check_link = &ixgbe_check_mac_link_82598,
1098 .get_link_capabilities = &ixgbe_get_link_capabilities_82598,
1099 .led_on = &ixgbe_led_on_generic,
1100 .led_off = &ixgbe_led_off_generic,
1101 .blink_led_start = &ixgbe_blink_led_start_82598,
1102 .blink_led_stop = &ixgbe_blink_led_stop_82598,
1103 .set_rar = &ixgbe_set_rar_generic,
1104 .clear_rar = &ixgbe_clear_rar_generic,
1105 .set_vmdq = &ixgbe_set_vmdq_82598,
1106 .clear_vmdq = &ixgbe_clear_vmdq_82598,
1107 .init_rx_addrs = &ixgbe_init_rx_addrs_generic,
1108 .update_uc_addr_list = &ixgbe_update_uc_addr_list_generic,
1109 .update_mc_addr_list = &ixgbe_update_mc_addr_list_generic,
1110 .enable_mc = &ixgbe_enable_mc_generic,
1111 .disable_mc = &ixgbe_disable_mc_generic,
1112 .clear_vfta = &ixgbe_clear_vfta_82598,
1113 .set_vfta = &ixgbe_set_vfta_82598,
1114 .setup_fc = &ixgbe_setup_fc_82598,
1115 };
1116
1117 static struct ixgbe_eeprom_operations eeprom_ops_82598 = {
1118 .init_params = &ixgbe_init_eeprom_params_generic,
1119 .read = &ixgbe_read_eeprom_generic,
1120 .validate_checksum = &ixgbe_validate_eeprom_checksum_generic,
1121 .update_checksum = &ixgbe_update_eeprom_checksum_generic,
1122 };
1123
1124 static struct ixgbe_phy_operations phy_ops_82598 = {
1125 .identify = &ixgbe_identify_phy_generic,
1126 .identify_sfp = &ixgbe_identify_sfp_module_generic,
1127 .reset = &ixgbe_reset_phy_generic,
1128 .read_reg = &ixgbe_read_phy_reg_generic,
1129 .write_reg = &ixgbe_write_phy_reg_generic,
1130 .setup_link = &ixgbe_setup_phy_link_generic,
1131 .setup_link_speed = &ixgbe_setup_phy_link_speed_generic,
1132 .read_i2c_eeprom = &ixgbe_read_i2c_eeprom_82598,
1133 };
1134
1135 struct ixgbe_info ixgbe_82598_info = {
1136 .mac = ixgbe_mac_82598EB,
1137 .get_invariants = &ixgbe_get_invariants_82598,
1138 .mac_ops = &mac_ops_82598,
1139 .eeprom_ops = &eeprom_ops_82598,
1140 .phy_ops = &phy_ops_82598,
1141 };
1142
Linus' kernel tree