1 /*******************************************************************************
3 Intel 10 Gigabit PCI Express Linux driver
4 Copyright(c) 1999 - 2009 Intel Corporation.
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
26 *******************************************************************************/
31 #include <linux/types.h>
32 #include <linux/pci.h>
33 #include <linux/netdevice.h>
34 #include <linux/aer.h>
36 #include "ixgbe_type.h"
37 #include "ixgbe_common.h"
38 #include "ixgbe_dcb.h"
39 #ifdef CONFIG_IXGBE_DCA
40 #include <linux/dca.h>
44 #define DPRINTK(nlevel, klevel, fmt, args...) \
45 ((void)((NETIF_MSG_##nlevel & adapter->msg_enable) && \
46 printk(KERN_##klevel PFX "%s: %s: " fmt, adapter->netdev->name, \
49 /* TX/RX descriptor defines */
50 #define IXGBE_DEFAULT_TXD 1024
51 #define IXGBE_MAX_TXD 4096
52 #define IXGBE_MIN_TXD 64
54 #define IXGBE_DEFAULT_RXD 1024
55 #define IXGBE_MAX_RXD 4096
56 #define IXGBE_MIN_RXD 64
59 #define IXGBE_DEFAULT_FCRTL 0x10000
60 #define IXGBE_MIN_FCRTL 0x40
61 #define IXGBE_MAX_FCRTL 0x7FF80
62 #define IXGBE_DEFAULT_FCRTH 0x20000
63 #define IXGBE_MIN_FCRTH 0x600
64 #define IXGBE_MAX_FCRTH 0x7FFF0
65 #define IXGBE_DEFAULT_FCPAUSE 0xFFFF
66 #define IXGBE_MIN_FCPAUSE 0
67 #define IXGBE_MAX_FCPAUSE 0xFFFF
69 /* Supported Rx Buffer Sizes */
70 #define IXGBE_RXBUFFER_64 64 /* Used for packet split */
71 #define IXGBE_RXBUFFER_128 128 /* Used for packet split */
72 #define IXGBE_RXBUFFER_256 256 /* Used for packet split */
73 #define IXGBE_RXBUFFER_2048 2048
75 #define IXGBE_RX_HDR_SIZE IXGBE_RXBUFFER_256
77 #define MAXIMUM_ETHERNET_VLAN_SIZE (ETH_FRAME_LEN + ETH_FCS_LEN + VLAN_HLEN)
79 /* How many Rx Buffers do we bundle into one write to the hardware ? */
80 #define IXGBE_RX_BUFFER_WRITE 16 /* Must be power of 2 */
82 #define IXGBE_TX_FLAGS_CSUM (u32)(1)
83 #define IXGBE_TX_FLAGS_VLAN (u32)(1 << 1)
84 #define IXGBE_TX_FLAGS_TSO (u32)(1 << 2)
85 #define IXGBE_TX_FLAGS_IPV4 (u32)(1 << 3)
86 #define IXGBE_TX_FLAGS_VLAN_MASK 0xffff0000
87 #define IXGBE_TX_FLAGS_VLAN_PRIO_MASK 0x0000e000
88 #define IXGBE_TX_FLAGS_VLAN_SHIFT 16
90 /* wrapper around a pointer to a socket buffer,
91 * so a DMA handle can be stored along with the buffer */
92 struct ixgbe_tx_buffer
{
95 unsigned long time_stamp
;
100 struct ixgbe_rx_buffer
{
105 unsigned int page_offset
;
108 struct ixgbe_queue_stats
{
114 void *desc
; /* descriptor ring memory */
115 dma_addr_t dma
; /* phys. address of descriptor ring */
116 unsigned int size
; /* length in bytes */
117 unsigned int count
; /* amount of descriptors */
118 unsigned int next_to_use
;
119 unsigned int next_to_clean
;
121 int queue_index
; /* needed for multiqueue queue management */
123 struct ixgbe_tx_buffer
*tx_buffer_info
;
124 struct ixgbe_rx_buffer
*rx_buffer_info
;
130 unsigned int total_bytes
;
131 unsigned int total_packets
;
133 u16 reg_idx
; /* holds the special value that gets the hardware register
134 * offset associated with this ring, which is different
135 * for DCB and RSS modes */
137 #ifdef CONFIG_IXGBE_DCA
138 /* cpu for tx queue */
141 struct ixgbe_queue_stats stats
;
142 u16 v_idx
; /* maps directly to the index for this ring in the hardware
143 * vector array, can also be used for finding the bit in EICR
144 * and friends that represents the vector for this ring */
147 u16 work_limit
; /* max work per interrupt */
152 #define RING_F_VMDQ 1
154 #define IXGBE_MAX_DCB_INDICES 8
155 #define IXGBE_MAX_RSS_INDICES 16
156 #define IXGBE_MAX_VMDQ_INDICES 16
157 struct ixgbe_ring_feature
{
162 #define MAX_RX_QUEUES 64
163 #define MAX_TX_QUEUES 32
165 #define MAX_RX_PACKET_BUFFERS ((adapter->flags & IXGBE_FLAG_DCB_ENABLED) \
167 #define MAX_TX_PACKET_BUFFERS MAX_RX_PACKET_BUFFERS
169 /* MAX_MSIX_Q_VECTORS of these are allocated,
170 * but we only use one per queue-specific vector.
172 struct ixgbe_q_vector
{
173 struct ixgbe_adapter
*adapter
;
174 struct napi_struct napi
;
175 DECLARE_BITMAP(rxr_idx
, MAX_RX_QUEUES
); /* Rx ring indices */
176 DECLARE_BITMAP(txr_idx
, MAX_TX_QUEUES
); /* Tx ring indices */
177 u8 rxr_count
; /* Rx ring count assigned to this vector */
178 u8 txr_count
; /* Tx ring count assigned to this vector */
184 /* Helper macros to switch between ints/sec and what the register uses.
185 * And yes, it's the same math going both ways.
187 #define EITR_INTS_PER_SEC_TO_REG(_eitr) \
188 ((_eitr) ? (1000000000 / ((_eitr) * 256)) : 0)
189 #define EITR_REG_TO_INTS_PER_SEC EITR_INTS_PER_SEC_TO_REG
191 #define IXGBE_DESC_UNUSED(R) \
192 ((((R)->next_to_clean > (R)->next_to_use) ? 0 : (R)->count) + \
193 (R)->next_to_clean - (R)->next_to_use - 1)
195 #define IXGBE_RX_DESC_ADV(R, i) \
196 (&(((union ixgbe_adv_rx_desc *)((R).desc))[i]))
197 #define IXGBE_TX_DESC_ADV(R, i) \
198 (&(((union ixgbe_adv_tx_desc *)((R).desc))[i]))
199 #define IXGBE_TX_CTXTDESC_ADV(R, i) \
200 (&(((struct ixgbe_adv_tx_context_desc *)((R).desc))[i]))
202 #define IXGBE_MAX_JUMBO_FRAME_SIZE 16128
204 #define OTHER_VECTOR 1
205 #define NON_Q_VECTORS (OTHER_VECTOR)
207 #define MAX_MSIX_VECTORS_82598 18
208 #define MAX_MSIX_Q_VECTORS_82598 16
210 #define MAX_MSIX_Q_VECTORS MAX_MSIX_Q_VECTORS_82598
211 #define MAX_MSIX_COUNT MAX_MSIX_VECTORS_82598
213 #define MIN_MSIX_Q_VECTORS 2
214 #define MIN_MSIX_COUNT (MIN_MSIX_Q_VECTORS + NON_Q_VECTORS)
216 /* board specific private data structure */
217 struct ixgbe_adapter
{
218 struct timer_list watchdog_timer
;
219 struct vlan_group
*vlgrp
;
221 struct work_struct reset_task
;
222 struct ixgbe_q_vector q_vector
[MAX_MSIX_Q_VECTORS
];
223 char name
[MAX_MSIX_COUNT
][IFNAMSIZ
+ 5];
224 struct ixgbe_dcb_config dcb_cfg
;
225 struct ixgbe_dcb_config temp_dcb_cfg
;
228 /* Interrupt Throttle Rate */
234 struct ixgbe_ring
*tx_ring
; /* One per active queue */
241 u32 tx_timeout_count
;
245 struct ixgbe_ring
*rx_ring
; /* One per active queue */
247 u64 hw_csum_rx_error
;
250 int num_msix_vectors
;
251 int max_msix_q_vectors
; /* true count of q_vectors for device */
252 struct ixgbe_ring_feature ring_feature
[3];
253 struct msix_entry
*msix_entries
;
256 u32 alloc_rx_page_failed
;
257 u32 alloc_rx_buff_failed
;
259 /* Some features need tri-state capability,
260 * thus the additional *_CAPABLE flags.
263 #define IXGBE_FLAG_RX_CSUM_ENABLED (u32)(1)
264 #define IXGBE_FLAG_MSI_CAPABLE (u32)(1 << 1)
265 #define IXGBE_FLAG_MSI_ENABLED (u32)(1 << 2)
266 #define IXGBE_FLAG_MSIX_CAPABLE (u32)(1 << 3)
267 #define IXGBE_FLAG_MSIX_ENABLED (u32)(1 << 4)
268 #define IXGBE_FLAG_RX_1BUF_CAPABLE (u32)(1 << 6)
269 #define IXGBE_FLAG_RX_PS_CAPABLE (u32)(1 << 7)
270 #define IXGBE_FLAG_RX_PS_ENABLED (u32)(1 << 8)
271 #define IXGBE_FLAG_IN_NETPOLL (u32)(1 << 9)
272 #define IXGBE_FLAG_DCA_ENABLED (u32)(1 << 10)
273 #define IXGBE_FLAG_DCA_CAPABLE (u32)(1 << 11)
274 #define IXGBE_FLAG_IMIR_ENABLED (u32)(1 << 12)
275 #define IXGBE_FLAG_MQ_CAPABLE (u32)(1 << 13)
276 #define IXGBE_FLAG_RSS_ENABLED (u32)(1 << 16)
277 #define IXGBE_FLAG_RSS_CAPABLE (u32)(1 << 17)
278 #define IXGBE_FLAG_VMDQ_CAPABLE (u32)(1 << 18)
279 #define IXGBE_FLAG_VMDQ_ENABLED (u32)(1 << 19)
280 #define IXGBE_FLAG_FAN_FAIL_CAPABLE (u32)(1 << 20)
281 #define IXGBE_FLAG_NEED_LINK_UPDATE (u32)(1 << 22)
282 #define IXGBE_FLAG_IN_WATCHDOG_TASK (u32)(1 << 23)
283 #define IXGBE_FLAG_DCB_ENABLED (u32)(1 << 24)
285 /* default to trying for four seconds */
286 #define IXGBE_TRY_LINK_TIMEOUT (4 * HZ)
288 /* OS defined structs */
289 struct net_device
*netdev
;
290 struct pci_dev
*pdev
;
291 struct net_device_stats net_stats
;
293 /* structs defined in ixgbe_hw.h */
296 struct ixgbe_hw_stats stats
;
298 /* Interrupt Throttle Rate */
303 unsigned int tx_ring_count
;
304 unsigned int rx_ring_count
;
308 unsigned long link_check_timeout
;
310 struct work_struct watchdog_task
;
311 struct work_struct sfp_task
;
312 struct timer_list sfp_timer
;
319 __IXGBE_SFP_MODULE_NOT_FOUND
326 extern struct ixgbe_info ixgbe_82598_info
;
327 #ifdef CONFIG_IXGBE_DCB
328 extern struct dcbnl_rtnl_ops dcbnl_ops
;
329 extern int ixgbe_copy_dcb_cfg(struct ixgbe_dcb_config
*src_dcb_cfg
,
330 struct ixgbe_dcb_config
*dst_dcb_cfg
,
334 extern char ixgbe_driver_name
[];
335 extern const char ixgbe_driver_version
[];
337 extern int ixgbe_up(struct ixgbe_adapter
*adapter
);
338 extern void ixgbe_down(struct ixgbe_adapter
*adapter
);
339 extern void ixgbe_reinit_locked(struct ixgbe_adapter
*adapter
);
340 extern void ixgbe_reset(struct ixgbe_adapter
*adapter
);
341 extern void ixgbe_set_ethtool_ops(struct net_device
*netdev
);
342 extern int ixgbe_setup_rx_resources(struct ixgbe_adapter
*, struct ixgbe_ring
*);
343 extern int ixgbe_setup_tx_resources(struct ixgbe_adapter
*, struct ixgbe_ring
*);
344 extern void ixgbe_free_rx_resources(struct ixgbe_adapter
*, struct ixgbe_ring
*);
345 extern void ixgbe_free_tx_resources(struct ixgbe_adapter
*, struct ixgbe_ring
*);
346 extern void ixgbe_update_stats(struct ixgbe_adapter
*adapter
);
347 extern void ixgbe_reset_interrupt_capability(struct ixgbe_adapter
*adapter
);
348 extern int ixgbe_init_interrupt_scheme(struct ixgbe_adapter
*adapter
);
349 void ixgbe_napi_add_all(struct ixgbe_adapter
*adapter
);
350 void ixgbe_napi_del_all(struct ixgbe_adapter
*adapter
);
352 #endif /* _IXGBE_H_ */