| blob | dbd2cb19924a34cca065bcb0c4d3cf2d0765ca07 |
1 config ARM
2 bool
3 default y
4 select HAVE_AOUT
5 select HAVE_DMA_API_DEBUG
6 select HAVE_IDE if PCI || ISA || PCMCIA
7 select HAVE_MEMBLOCK
8 select RTC_LIB
9 select SYS_SUPPORTS_APM_EMULATION
10 select GENERIC_ATOMIC64 if (CPU_V6 || !CPU_32v6K || !AEABI)
11 select HAVE_OPROFILE if (HAVE_PERF_EVENTS)
12 select HAVE_ARCH_KGDB
13 select HAVE_KPROBES if !XIP_KERNEL
14 select HAVE_KRETPROBES if (HAVE_KPROBES)
15 select HAVE_FUNCTION_TRACER if (!XIP_KERNEL)
16 select HAVE_FTRACE_MCOUNT_RECORD if (!XIP_KERNEL)
17 select HAVE_DYNAMIC_FTRACE if (!XIP_KERNEL)
18 select HAVE_FUNCTION_GRAPH_TRACER if (!THUMB2_KERNEL)
19 select HAVE_GENERIC_DMA_COHERENT
20 select HAVE_KERNEL_GZIP
21 select HAVE_KERNEL_LZO
22 select HAVE_KERNEL_LZMA
23 select HAVE_IRQ_WORK
24 select HAVE_PERF_EVENTS
25 select PERF_USE_VMALLOC
26 select HAVE_REGS_AND_STACK_ACCESS_API
27 select HAVE_HW_BREAKPOINT if (PERF_EVENTS && (CPU_V6 || CPU_V6K || CPU_V7))
28 select HAVE_C_RECORDMCOUNT
29 select HAVE_GENERIC_HARDIRQS
30 select HAVE_SPARSE_IRQ
31 select GENERIC_IRQ_SHOW
32 select CPU_PM if (SUSPEND || CPU_IDLE)
33 help
34 The ARM series is a line of low-power-consumption RISC chip designs
35 licensed by ARM Ltd and targeted at embedded applications and
36 handhelds such as the Compaq IPAQ. ARM-based PCs are no longer
37 manufactured, but legacy ARM-based PC hardware remains popular in
38 Europe. There is an ARM Linux project with a web page at
39 <http://www.arm.linux.org.uk/>.
41 config ARM_HAS_SG_CHAIN
42 bool
44 config HAVE_PWM
45 bool
47 config MIGHT_HAVE_PCI
48 bool
50 config SYS_SUPPORTS_APM_EMULATION
51 bool
53 config HAVE_SCHED_CLOCK
54 bool
56 config GENERIC_GPIO
57 bool
59 config ARCH_USES_GETTIMEOFFSET
60 bool
61 default n
63 config GENERIC_CLOCKEVENTS
64 bool
66 config GENERIC_CLOCKEVENTS_BROADCAST
67 bool
68 depends on GENERIC_CLOCKEVENTS
69 default y if SMP
71 config KTIME_SCALAR
72 bool
73 default y
75 config HAVE_TCM
76 bool
77 select GENERIC_ALLOCATOR
79 config HAVE_PROC_CPU
80 bool
82 config NO_IOPORT
83 bool
85 config EISA
86 bool
87 ---help---
88 The Extended Industry Standard Architecture (EISA) bus was
89 developed as an open alternative to the IBM MicroChannel bus.
91 The EISA bus provided some of the features of the IBM MicroChannel
92 bus while maintaining backward compatibility with cards made for
93 the older ISA bus. The EISA bus saw limited use between 1988 and
94 1995 when it was made obsolete by the PCI bus.
96 Say Y here if you are building a kernel for an EISA-based machine.
98 Otherwise, say N.
100 config SBUS
101 bool
103 config MCA
104 bool
105 help
106 MicroChannel Architecture is found in some IBM PS/2 machines and
107 laptops. It is a bus system similar to PCI or ISA. See
108 <file:Documentation/mca.txt> (and especially the web page given
109 there) before attempting to build an MCA bus kernel.
111 config STACKTRACE_SUPPORT
112 bool
113 default y
115 config HAVE_LATENCYTOP_SUPPORT
116 bool
117 depends on !SMP
118 default y
120 config LOCKDEP_SUPPORT
121 bool
122 default y
124 config TRACE_IRQFLAGS_SUPPORT
125 bool
126 default y
128 config HARDIRQS_SW_RESEND
129 bool
130 default y
132 config GENERIC_IRQ_PROBE
133 bool
134 default y
136 config GENERIC_LOCKBREAK
137 bool
138 default y
139 depends on SMP && PREEMPT
141 config RWSEM_GENERIC_SPINLOCK
142 bool
143 default y
145 config RWSEM_XCHGADD_ALGORITHM
146 bool
148 config ARCH_HAS_ILOG2_U32
149 bool
151 config ARCH_HAS_ILOG2_U64
152 bool
154 config ARCH_HAS_CPUFREQ
155 bool
156 help
157 Internal node to signify that the ARCH has CPUFREQ support
158 and that the relevant menu configurations are displayed for
159 it.
161 config ARCH_HAS_CPU_IDLE_WAIT
162 def_bool y
164 config GENERIC_HWEIGHT
165 bool
166 default y
168 config GENERIC_CALIBRATE_DELAY
169 bool
170 default y
172 config ARCH_MAY_HAVE_PC_FDC
173 bool
175 config ZONE_DMA
176 bool
178 config NEED_DMA_MAP_STATE
179 def_bool y
181 config GENERIC_ISA_DMA
182 bool
184 config FIQ
185 bool
187 config ARCH_MTD_XIP
188 bool
190 config VECTORS_BASE
191 hex
192 default 0xffff0000 if MMU || CPU_HIGH_VECTOR
193 default DRAM_BASE if REMAP_VECTORS_TO_RAM
194 default 0x00000000
195 help
196 The base address of exception vectors.
198 config ARM_PATCH_PHYS_VIRT
199 bool "Patch physical to virtual translations at runtime" if EMBEDDED
200 default y
201 depends on !XIP_KERNEL && MMU
202 depends on !ARCH_REALVIEW || !SPARSEMEM
203 help
204 Patch phys-to-virt and virt-to-phys translation functions at
205 boot and module load time according to the position of the
206 kernel in system memory.
208 This can only be used with non-XIP MMU kernels where the base
209 of physical memory is at a 16MB boundary.
211 Only disable this option if you know that you do not require
212 this feature (eg, building a kernel for a single machine) and
213 you need to shrink the kernel to the minimal size.
215 config NEED_MACH_MEMORY_H
216 bool
217 help
218 Select this when mach/memory.h is required to provide special
219 definitions for this platform. The need for mach/memory.h should
220 be avoided when possible.
222 config PHYS_OFFSET
223 hex "Physical address of main memory"
224 depends on !ARM_PATCH_PHYS_VIRT && !NEED_MACH_MEMORY_H
225 help
226 Please provide the physical address corresponding to the
227 location of main memory in your system.
229 config GENERIC_BUG
230 def_bool y
231 depends on BUG
233 source "init/Kconfig"
235 source "kernel/Kconfig.freezer"
237 menu "System Type"
239 config MMU
240 bool "MMU-based Paged Memory Management Support"
241 default y
242 help
243 Select if you want MMU-based virtualised addressing space
244 support by paged memory management. If unsure, say 'Y'.
246 #
247 # The "ARM system type" choice list is ordered alphabetically by option
248 # text. Please add new entries in the option alphabetic order.
249 #
250 choice
251 prompt "ARM system type"
252 default ARCH_VERSATILE
254 config ARCH_INTEGRATOR
255 bool "ARM Ltd. Integrator family"
256 select ARM_AMBA
257 select ARCH_HAS_CPUFREQ
258 select CLKDEV_LOOKUP
259 select HAVE_MACH_CLKDEV
260 select HAVE_TCM
261 select ICST
262 select GENERIC_CLOCKEVENTS
263 select PLAT_VERSATILE
264 select PLAT_VERSATILE_FPGA_IRQ
265 select NEED_MACH_MEMORY_H
266 help
267 Support for ARM's Integrator platform.
269 config ARCH_REALVIEW
270 bool "ARM Ltd. RealView family"
271 select ARM_AMBA
272 select CLKDEV_LOOKUP
273 select HAVE_MACH_CLKDEV
274 select ICST
275 select GENERIC_CLOCKEVENTS
276 select ARCH_WANT_OPTIONAL_GPIOLIB
277 select PLAT_VERSATILE
278 select PLAT_VERSATILE_CLCD
279 select ARM_TIMER_SP804
280 select GPIO_PL061 if GPIOLIB
281 select NEED_MACH_MEMORY_H
282 help
283 This enables support for ARM Ltd RealView boards.
285 config ARCH_VERSATILE
286 bool "ARM Ltd. Versatile family"
287 select ARM_AMBA
288 select ARM_VIC
289 select CLKDEV_LOOKUP
290 select HAVE_MACH_CLKDEV
291 select ICST
292 select GENERIC_CLOCKEVENTS
293 select ARCH_WANT_OPTIONAL_GPIOLIB
294 select PLAT_VERSATILE
295 select PLAT_VERSATILE_CLCD
296 select PLAT_VERSATILE_FPGA_IRQ
297 select ARM_TIMER_SP804
298 help
299 This enables support for ARM Ltd Versatile board.
301 config ARCH_VEXPRESS
302 bool "ARM Ltd. Versatile Express family"
303 select ARCH_WANT_OPTIONAL_GPIOLIB
304 select ARM_AMBA
305 select ARM_TIMER_SP804
306 select CLKDEV_LOOKUP
307 select HAVE_MACH_CLKDEV
308 select GENERIC_CLOCKEVENTS
309 select HAVE_CLK
310 select HAVE_PATA_PLATFORM
311 select ICST
312 select PLAT_VERSATILE
313 select PLAT_VERSATILE_CLCD
314 help
315 This enables support for the ARM Ltd Versatile Express boards.
317 config ARCH_AT91
318 bool "Atmel AT91"
319 select ARCH_REQUIRE_GPIOLIB
320 select HAVE_CLK
321 select CLKDEV_LOOKUP
322 help
323 This enables support for systems based on the Atmel AT91RM9200,
324 AT91SAM9 and AT91CAP9 processors.
326 config ARCH_BCMRING
327 bool "Broadcom BCMRING"
328 depends on MMU
329 select CPU_V6
330 select ARM_AMBA
331 select ARM_TIMER_SP804
332 select CLKDEV_LOOKUP
333 select GENERIC_CLOCKEVENTS
334 select ARCH_WANT_OPTIONAL_GPIOLIB
335 help
336 Support for Broadcom's BCMRing platform.
338 config ARCH_HIGHBANK
339 bool "Calxeda Highbank-based"
340 select ARCH_WANT_OPTIONAL_GPIOLIB
341 select ARM_AMBA
342 select ARM_GIC
343 select ARM_TIMER_SP804
344 select CLKDEV_LOOKUP
345 select CPU_V7
346 select GENERIC_CLOCKEVENTS
347 select HAVE_ARM_SCU
348 select USE_OF
349 help
350 Support for the Calxeda Highbank SoC based boards.
352 config ARCH_CLPS711X
353 bool "Cirrus Logic CLPS711x/EP721x-based"
354 select CPU_ARM720T
355 select ARCH_USES_GETTIMEOFFSET
356 select NEED_MACH_MEMORY_H
357 help
358 Support for Cirrus Logic 711x/721x based boards.
360 config ARCH_CNS3XXX
361 bool "Cavium Networks CNS3XXX family"
362 select CPU_V6K
363 select GENERIC_CLOCKEVENTS
364 select ARM_GIC
365 select MIGHT_HAVE_PCI
366 select PCI_DOMAINS if PCI
367 help
368 Support for Cavium Networks CNS3XXX platform.
370 config ARCH_GEMINI
371 bool "Cortina Systems Gemini"
372 select CPU_FA526
373 select ARCH_REQUIRE_GPIOLIB
374 select ARCH_USES_GETTIMEOFFSET
375 help
376 Support for the Cortina Systems Gemini family SoCs
378 config ARCH_PRIMA2
379 bool "CSR SiRFSoC PRIMA2 ARM Cortex A9 Platform"
380 select CPU_V7
381 select NO_IOPORT
382 select GENERIC_CLOCKEVENTS
383 select CLKDEV_LOOKUP
384 select GENERIC_IRQ_CHIP
385 select USE_OF
386 select ZONE_DMA
387 help
388 Support for CSR SiRFSoC ARM Cortex A9 Platform
390 config ARCH_EBSA110
391 bool "EBSA-110"
392 select CPU_SA110
393 select ISA
394 select NO_IOPORT
395 select ARCH_USES_GETTIMEOFFSET
396 select NEED_MACH_MEMORY_H
397 help
398 This is an evaluation board for the StrongARM processor available
399 from Digital. It has limited hardware on-board, including an
400 Ethernet interface, two PCMCIA sockets, two serial ports and a
401 parallel port.
403 config ARCH_EP93XX
404 bool "EP93xx-based"
405 select CPU_ARM920T
406 select ARM_AMBA
407 select ARM_VIC
408 select CLKDEV_LOOKUP
409 select ARCH_REQUIRE_GPIOLIB
410 select ARCH_HAS_HOLES_MEMORYMODEL
411 select ARCH_USES_GETTIMEOFFSET
412 select NEED_MACH_MEMORY_H
413 help
414 This enables support for the Cirrus EP93xx series of CPUs.
416 config ARCH_FOOTBRIDGE
417 bool "FootBridge"
418 select CPU_SA110
419 select FOOTBRIDGE
420 select GENERIC_CLOCKEVENTS
421 select HAVE_IDE
422 select NEED_MACH_MEMORY_H
423 help
424 Support for systems based on the DC21285 companion chip
425 ("FootBridge"), such as the Simtec CATS and the Rebel NetWinder.
427 config ARCH_MXC
428 bool "Freescale MXC/iMX-based"
429 select GENERIC_CLOCKEVENTS
430 select ARCH_REQUIRE_GPIOLIB
431 select CLKDEV_LOOKUP
432 select CLKSRC_MMIO
433 select GENERIC_IRQ_CHIP
434 select HAVE_SCHED_CLOCK
435 select MULTI_IRQ_HANDLER
436 help
437 Support for Freescale MXC/iMX-based family of processors
439 config ARCH_MXS
440 bool "Freescale MXS-based"
441 select GENERIC_CLOCKEVENTS
442 select ARCH_REQUIRE_GPIOLIB
443 select CLKDEV_LOOKUP
444 select CLKSRC_MMIO
445 help
446 Support for Freescale MXS-based family of processors
448 config ARCH_NETX
449 bool "Hilscher NetX based"
450 select CLKSRC_MMIO
451 select CPU_ARM926T
452 select ARM_VIC
453 select GENERIC_CLOCKEVENTS
454 help
455 This enables support for systems based on the Hilscher NetX Soc
457 config ARCH_H720X
458 bool "Hynix HMS720x-based"
459 select CPU_ARM720T
460 select ISA_DMA_API
461 select ARCH_USES_GETTIMEOFFSET
462 help
463 This enables support for systems based on the Hynix HMS720x
465 config ARCH_IOP13XX
466 bool "IOP13xx-based"
467 depends on MMU
468 select CPU_XSC3
469 select PLAT_IOP
470 select PCI
471 select ARCH_SUPPORTS_MSI
472 select VMSPLIT_1G
473 select NEED_MACH_MEMORY_H
474 help
475 Support for Intel's IOP13XX (XScale) family of processors.
477 config ARCH_IOP32X
478 bool "IOP32x-based"
479 depends on MMU
480 select CPU_XSCALE
481 select PLAT_IOP
482 select PCI
483 select ARCH_REQUIRE_GPIOLIB
484 help
485 Support for Intel's 80219 and IOP32X (XScale) family of
486 processors.
488 config ARCH_IOP33X
489 bool "IOP33x-based"
490 depends on MMU
491 select CPU_XSCALE
492 select PLAT_IOP
493 select PCI
494 select ARCH_REQUIRE_GPIOLIB
495 help
496 Support for Intel's IOP33X (XScale) family of processors.
498 config ARCH_IXP23XX
499 bool "IXP23XX-based"
500 depends on MMU
501 select CPU_XSC3
502 select PCI
503 select ARCH_USES_GETTIMEOFFSET
504 select NEED_MACH_MEMORY_H
505 help
506 Support for Intel's IXP23xx (XScale) family of processors.
508 config ARCH_IXP2000
509 bool "IXP2400/2800-based"
510 depends on MMU
511 select CPU_XSCALE
512 select PCI
513 select ARCH_USES_GETTIMEOFFSET
514 select NEED_MACH_MEMORY_H
515 help
516 Support for Intel's IXP2400/2800 (XScale) family of processors.
518 config ARCH_IXP4XX
519 bool "IXP4xx-based"
520 depends on MMU
521 select CLKSRC_MMIO
522 select CPU_XSCALE
523 select GENERIC_GPIO
524 select GENERIC_CLOCKEVENTS
525 select HAVE_SCHED_CLOCK
526 select MIGHT_HAVE_PCI
527 select DMABOUNCE if PCI
528 help
529 Support for Intel's IXP4XX (XScale) family of processors.
531 config ARCH_DOVE
532 bool "Marvell Dove"
533 select CPU_V7
534 select PCI
535 select ARCH_REQUIRE_GPIOLIB
536 select GENERIC_CLOCKEVENTS
537 select PLAT_ORION
538 help
539 Support for the Marvell Dove SoC 88AP510
541 config ARCH_KIRKWOOD
542 bool "Marvell Kirkwood"
543 select CPU_FEROCEON
544 select PCI
545 select ARCH_REQUIRE_GPIOLIB
546 select GENERIC_CLOCKEVENTS
547 select PLAT_ORION
548 help
549 Support for the following Marvell Kirkwood series SoCs:
550 88F6180, 88F6192 and 88F6281.
552 config ARCH_LPC32XX
553 bool "NXP LPC32XX"
554 select CLKSRC_MMIO
555 select CPU_ARM926T
556 select ARCH_REQUIRE_GPIOLIB
557 select HAVE_IDE
558 select ARM_AMBA
559 select USB_ARCH_HAS_OHCI
560 select CLKDEV_LOOKUP
561 select GENERIC_CLOCKEVENTS
562 help
563 Support for the NXP LPC32XX family of processors
565 config ARCH_MV78XX0
566 bool "Marvell MV78xx0"
567 select CPU_FEROCEON
568 select PCI
569 select ARCH_REQUIRE_GPIOLIB
570 select GENERIC_CLOCKEVENTS
571 select PLAT_ORION
572 help
573 Support for the following Marvell MV78xx0 series SoCs:
574 MV781x0, MV782x0.
576 config ARCH_ORION5X
577 bool "Marvell Orion"
578 depends on MMU
579 select CPU_FEROCEON
580 select PCI
581 select ARCH_REQUIRE_GPIOLIB
582 select GENERIC_CLOCKEVENTS
583 select PLAT_ORION
584 help
585 Support for the following Marvell Orion 5x series SoCs:
586 Orion-1 (5181), Orion-VoIP (5181L), Orion-NAS (5182),
587 Orion-2 (5281), Orion-1-90 (6183).
589 config ARCH_MMP
590 bool "Marvell PXA168/910/MMP2"
591 depends on MMU
592 select ARCH_REQUIRE_GPIOLIB
593 select CLKDEV_LOOKUP
594 select GENERIC_CLOCKEVENTS
595 select HAVE_SCHED_CLOCK
596 select TICK_ONESHOT
597 select PLAT_PXA
598 select SPARSE_IRQ
599 select GENERIC_ALLOCATOR
600 help
601 Support for Marvell's PXA168/PXA910(MMP) and MMP2 processor line.
603 config ARCH_KS8695
604 bool "Micrel/Kendin KS8695"
605 select CPU_ARM922T
606 select ARCH_REQUIRE_GPIOLIB
607 select ARCH_USES_GETTIMEOFFSET
608 select NEED_MACH_MEMORY_H
609 help
610 Support for Micrel/Kendin KS8695 "Centaur" (ARM922T) based
611 System-on-Chip devices.
613 config ARCH_W90X900
614 bool "Nuvoton W90X900 CPU"
615 select CPU_ARM926T
616 select ARCH_REQUIRE_GPIOLIB
617 select CLKDEV_LOOKUP
618 select CLKSRC_MMIO
619 select GENERIC_CLOCKEVENTS
620 help
621 Support for Nuvoton (Winbond logic dept.) ARM9 processor,
622 At present, the w90x900 has been renamed nuc900, regarding
623 the ARM series product line, you can login the following
624 link address to know more.
626 <http://www.nuvoton.com/hq/enu/ProductAndSales/ProductLines/
627 ConsumerElectronicsIC/ARMMicrocontroller/ARMMicrocontroller>
629 config ARCH_TEGRA
630 bool "NVIDIA Tegra"
631 select CLKDEV_LOOKUP
632 select CLKSRC_MMIO
633 select GENERIC_CLOCKEVENTS
634 select GENERIC_GPIO
635 select HAVE_CLK
636 select HAVE_SCHED_CLOCK
637 select ARCH_HAS_CPUFREQ
638 help
639 This enables support for NVIDIA Tegra based systems (Tegra APX,
640 Tegra 6xx and Tegra 2 series).
642 config ARCH_PICOXCELL
643 bool "Picochip picoXcell"
644 select ARCH_REQUIRE_GPIOLIB
645 select ARM_PATCH_PHYS_VIRT
646 select ARM_VIC
647 select CPU_V6K
648 select DW_APB_TIMER
649 select GENERIC_CLOCKEVENTS
650 select GENERIC_GPIO
651 select HAVE_SCHED_CLOCK
652 select HAVE_TCM
653 select NO_IOPORT
654 select USE_OF
655 help
656 This enables support for systems based on the Picochip picoXcell
657 family of Femtocell devices. The picoxcell support requires device tree
658 for all boards.
660 config ARCH_PNX4008
661 bool "Philips Nexperia PNX4008 Mobile"
662 select CPU_ARM926T
663 select CLKDEV_LOOKUP
664 select ARCH_USES_GETTIMEOFFSET
665 help
666 This enables support for Philips PNX4008 mobile platform.
668 config ARCH_PXA
669 bool "PXA2xx/PXA3xx-based"
670 depends on MMU
671 select ARCH_MTD_XIP
672 select ARCH_HAS_CPUFREQ
673 select CLKDEV_LOOKUP
674 select CLKSRC_MMIO
675 select ARCH_REQUIRE_GPIOLIB
676 select GENERIC_CLOCKEVENTS
677 select HAVE_SCHED_CLOCK
678 select TICK_ONESHOT
679 select PLAT_PXA
680 select SPARSE_IRQ
681 select AUTO_ZRELADDR
682 select MULTI_IRQ_HANDLER
683 select ARM_CPU_SUSPEND if PM
684 select HAVE_IDE
685 help
686 Support for Intel/Marvell's PXA2xx/PXA3xx processor line.
688 config ARCH_MSM
689 bool "Qualcomm MSM"
690 select HAVE_CLK
691 select GENERIC_CLOCKEVENTS
692 select ARCH_REQUIRE_GPIOLIB
693 select CLKDEV_LOOKUP
694 help
695 Support for Qualcomm MSM/QSD based systems. This runs on the
696 apps processor of the MSM/QSD and depends on a shared memory
697 interface to the modem processor which runs the baseband
698 stack and controls some vital subsystems
699 (clock and power control, etc).
701 config ARCH_SHMOBILE
702 bool "Renesas SH-Mobile / R-Mobile"
703 select HAVE_CLK
704 select CLKDEV_LOOKUP
705 select HAVE_MACH_CLKDEV
706 select GENERIC_CLOCKEVENTS
707 select NO_IOPORT
708 select SPARSE_IRQ
709 select MULTI_IRQ_HANDLER
710 select PM_GENERIC_DOMAINS if PM
711 select NEED_MACH_MEMORY_H
712 help
713 Support for Renesas's SH-Mobile and R-Mobile ARM platforms.
715 config ARCH_RPC
716 bool "RiscPC"
717 select ARCH_ACORN
718 select FIQ
719 select TIMER_ACORN
720 select ARCH_MAY_HAVE_PC_FDC
721 select HAVE_PATA_PLATFORM
722 select ISA_DMA_API
723 select NO_IOPORT
724 select ARCH_SPARSEMEM_ENABLE
725 select ARCH_USES_GETTIMEOFFSET
726 select HAVE_IDE
727 select NEED_MACH_MEMORY_H
728 help
729 On the Acorn Risc-PC, Linux can support the internal IDE disk and
730 CD-ROM interface, serial and parallel port, and the floppy drive.
732 config ARCH_SA1100
733 bool "SA1100-based"
734 select CLKSRC_MMIO
735 select CPU_SA1100
736 select ISA
737 select ARCH_SPARSEMEM_ENABLE
738 select ARCH_MTD_XIP
739 select ARCH_HAS_CPUFREQ
740 select CPU_FREQ
741 select GENERIC_CLOCKEVENTS
742 select HAVE_CLK
743 select HAVE_SCHED_CLOCK
744 select TICK_ONESHOT
745 select ARCH_REQUIRE_GPIOLIB
746 select HAVE_IDE
747 select NEED_MACH_MEMORY_H
748 help
749 Support for StrongARM 11x0 based boards.
751 config ARCH_S3C2410
752 bool "Samsung S3C2410, S3C2412, S3C2413, S3C2416, S3C2440, S3C2442, S3C2443, S3C2450"
753 select GENERIC_GPIO
754 select ARCH_HAS_CPUFREQ
755 select HAVE_CLK
756 select CLKDEV_LOOKUP
757 select ARCH_USES_GETTIMEOFFSET
758 select HAVE_S3C2410_I2C if I2C
759 help
760 Samsung S3C2410X CPU based systems, such as the Simtec Electronics
761 BAST (<http://www.simtec.co.uk/products/EB110ITX/>), the IPAQ 1940 or
762 the Samsung SMDK2410 development board (and derivatives).
764 Note, the S3C2416 and the S3C2450 are so close that they even share
765 the same SoC ID code. This means that there is no separate machine
766 directory (no arch/arm/mach-s3c2450) as the S3C2416 was first.
768 config ARCH_S3C64XX
769 bool "Samsung S3C64XX"
770 select PLAT_SAMSUNG
771 select CPU_V6
772 select ARM_VIC
773 select HAVE_CLK
774 select HAVE_TCM
775 select CLKDEV_LOOKUP
776 select NO_IOPORT
777 select ARCH_USES_GETTIMEOFFSET
778 select ARCH_HAS_CPUFREQ
779 select ARCH_REQUIRE_GPIOLIB
780 select SAMSUNG_CLKSRC
781 select SAMSUNG_IRQ_VIC_TIMER
782 select S3C_GPIO_TRACK
783 select S3C_DEV_NAND
784 select USB_ARCH_HAS_OHCI
785 select SAMSUNG_GPIOLIB_4BIT
786 select HAVE_S3C2410_I2C if I2C
787 select HAVE_S3C2410_WATCHDOG if WATCHDOG
788 help
789 Samsung S3C64XX series based systems
791 config ARCH_S5P64X0
792 bool "Samsung S5P6440 S5P6450"
793 select CPU_V6
794 select GENERIC_GPIO
795 select HAVE_CLK
796 select CLKDEV_LOOKUP
797 select CLKSRC_MMIO
798 select HAVE_S3C2410_WATCHDOG if WATCHDOG
799 select GENERIC_CLOCKEVENTS
800 select HAVE_SCHED_CLOCK
801 select HAVE_S3C2410_I2C if I2C
802 select HAVE_S3C_RTC if RTC_CLASS
803 help
804 Samsung S5P64X0 CPU based systems, such as the Samsung SMDK6440,
805 SMDK6450.
807 config ARCH_S5PC100
808 bool "Samsung S5PC100"
809 select GENERIC_GPIO
810 select HAVE_CLK
811 select CLKDEV_LOOKUP
812 select CPU_V7
813 select ARM_L1_CACHE_SHIFT_6
814 select ARCH_USES_GETTIMEOFFSET
815 select HAVE_S3C2410_I2C if I2C
816 select HAVE_S3C_RTC if RTC_CLASS
817 select HAVE_S3C2410_WATCHDOG if WATCHDOG
818 help
819 Samsung S5PC100 series based systems
821 config ARCH_S5PV210
822 bool "Samsung S5PV210/S5PC110"
823 select CPU_V7
824 select ARCH_SPARSEMEM_ENABLE
825 select ARCH_HAS_HOLES_MEMORYMODEL
826 select GENERIC_GPIO
827 select HAVE_CLK
828 select CLKDEV_LOOKUP
829 select CLKSRC_MMIO
830 select ARM_L1_CACHE_SHIFT_6
831 select ARCH_HAS_CPUFREQ
832 select GENERIC_CLOCKEVENTS
833 select HAVE_SCHED_CLOCK
834 select HAVE_S3C2410_I2C if I2C
835 select HAVE_S3C_RTC if RTC_CLASS
836 select HAVE_S3C2410_WATCHDOG if WATCHDOG
837 select NEED_MACH_MEMORY_H
838 help
839 Samsung S5PV210/S5PC110 series based systems
841 config ARCH_EXYNOS
842 bool "SAMSUNG EXYNOS"
843 select CPU_V7
844 select ARCH_SPARSEMEM_ENABLE
845 select ARCH_HAS_HOLES_MEMORYMODEL
846 select GENERIC_GPIO
847 select HAVE_CLK
848 select CLKDEV_LOOKUP
849 select ARCH_HAS_CPUFREQ
850 select GENERIC_CLOCKEVENTS
851 select HAVE_S3C_RTC if RTC_CLASS
852 select HAVE_S3C2410_I2C if I2C
853 select HAVE_S3C2410_WATCHDOG if WATCHDOG
854 select NEED_MACH_MEMORY_H
855 help
856 Support for SAMSUNG's EXYNOS SoCs (EXYNOS4/5)
858 config ARCH_SHARK
859 bool "Shark"
860 select CPU_SA110
861 select ISA
862 select ISA_DMA
863 select ZONE_DMA
864 select PCI
865 select ARCH_USES_GETTIMEOFFSET
866 select NEED_MACH_MEMORY_H
867 help
868 Support for the StrongARM based Digital DNARD machine, also known
869 as "Shark" (<http://www.shark-linux.de/shark.html>).
871 config ARCH_TCC_926
872 bool "Telechips TCC ARM926-based systems"
873 select CLKSRC_MMIO
874 select CPU_ARM926T
875 select HAVE_CLK
876 select CLKDEV_LOOKUP
877 select GENERIC_CLOCKEVENTS
878 help
879 Support for Telechips TCC ARM926-based systems.
881 config ARCH_U300
882 bool "ST-Ericsson U300 Series"
883 depends on MMU
884 select CLKSRC_MMIO
885 select CPU_ARM926T
886 select HAVE_SCHED_CLOCK
887 select HAVE_TCM
888 select ARM_AMBA
889 select ARM_PATCH_PHYS_VIRT
890 select ARM_VIC
891 select GENERIC_CLOCKEVENTS
892 select CLKDEV_LOOKUP
893 select HAVE_MACH_CLKDEV
894 select GENERIC_GPIO
895 select ARCH_REQUIRE_GPIOLIB
896 select NEED_MACH_MEMORY_H
897 help
898 Support for ST-Ericsson U300 series mobile platforms.
900 config ARCH_U8500
901 bool "ST-Ericsson U8500 Series"
902 select CPU_V7
903 select ARM_AMBA
904 select GENERIC_CLOCKEVENTS
905 select CLKDEV_LOOKUP
906 select ARCH_REQUIRE_GPIOLIB
907 select ARCH_HAS_CPUFREQ
908 help
909 Support for ST-Ericsson's Ux500 architecture
911 config ARCH_NOMADIK
912 bool "STMicroelectronics Nomadik"
913 select ARM_AMBA
914 select ARM_VIC
915 select CPU_ARM926T
916 select CLKDEV_LOOKUP
917 select GENERIC_CLOCKEVENTS
918 select ARCH_REQUIRE_GPIOLIB
919 help
920 Support for the Nomadik platform by ST-Ericsson
922 config ARCH_DAVINCI
923 bool "TI DaVinci"
924 select GENERIC_CLOCKEVENTS
925 select ARCH_REQUIRE_GPIOLIB
926 select ZONE_DMA
927 select HAVE_IDE
928 select CLKDEV_LOOKUP
929 select GENERIC_ALLOCATOR
930 select GENERIC_IRQ_CHIP
931 select ARCH_HAS_HOLES_MEMORYMODEL
932 help
933 Support for TI's DaVinci platform.
935 config ARCH_OMAP
936 bool "TI OMAP"
937 select HAVE_CLK
938 select ARCH_REQUIRE_GPIOLIB
939 select ARCH_HAS_CPUFREQ
940 select CLKSRC_MMIO
941 select GENERIC_CLOCKEVENTS
942 select HAVE_SCHED_CLOCK
943 select ARCH_HAS_HOLES_MEMORYMODEL
944 help
945 Support for TI's OMAP platform (OMAP1/2/3/4).
947 config PLAT_SPEAR
948 bool "ST SPEAr"
949 select ARM_AMBA
950 select ARCH_REQUIRE_GPIOLIB
951 select CLKDEV_LOOKUP
952 select CLKSRC_MMIO
953 select GENERIC_CLOCKEVENTS
954 select HAVE_CLK
955 help
956 Support for ST's SPEAr platform (SPEAr3xx, SPEAr6xx and SPEAr13xx).
958 config ARCH_VT8500
959 bool "VIA/WonderMedia 85xx"
960 select CPU_ARM926T
961 select GENERIC_GPIO
962 select ARCH_HAS_CPUFREQ
963 select GENERIC_CLOCKEVENTS
964 select ARCH_REQUIRE_GPIOLIB
965 select HAVE_PWM
966 help
967 Support for VIA/WonderMedia VT8500/WM85xx System-on-Chip.
969 config ARCH_ZYNQ
970 bool "Xilinx Zynq ARM Cortex A9 Platform"
971 select CPU_V7
972 select GENERIC_CLOCKEVENTS
973 select CLKDEV_LOOKUP
974 select ARM_GIC
975 select ARM_AMBA
976 select ICST
977 select USE_OF
978 help
979 Support for Xilinx Zynq ARM Cortex A9 Platform
980 endchoice
982 #
983 # This is sorted alphabetically by mach-* pathname. However, plat-*
984 # Kconfigs may be included either alphabetically (according to the
985 # plat- suffix) or along side the corresponding mach-* source.
986 #
987 source "arch/arm/mach-at91/Kconfig"
989 source "arch/arm/mach-bcmring/Kconfig"
991 source "arch/arm/mach-clps711x/Kconfig"
993 source "arch/arm/mach-cns3xxx/Kconfig"
995 source "arch/arm/mach-davinci/Kconfig"
997 source "arch/arm/mach-dove/Kconfig"
999 source "arch/arm/mach-ep93xx/Kconfig"
1001 source "arch/arm/mach-footbridge/Kconfig"
1003 source "arch/arm/mach-gemini/Kconfig"
1005 source "arch/arm/mach-h720x/Kconfig"
1007 source "arch/arm/mach-integrator/Kconfig"
1009 source "arch/arm/mach-iop32x/Kconfig"
1011 source "arch/arm/mach-iop33x/Kconfig"
1013 source "arch/arm/mach-iop13xx/Kconfig"
1015 source "arch/arm/mach-ixp4xx/Kconfig"
1017 source "arch/arm/mach-ixp2000/Kconfig"
1019 source "arch/arm/mach-ixp23xx/Kconfig"
1021 source "arch/arm/mach-kirkwood/Kconfig"
1023 source "arch/arm/mach-ks8695/Kconfig"
1025 source "arch/arm/mach-lpc32xx/Kconfig"
1027 source "arch/arm/mach-msm/Kconfig"
1029 source "arch/arm/mach-mv78xx0/Kconfig"
1031 source "arch/arm/plat-mxc/Kconfig"
1033 source "arch/arm/mach-mxs/Kconfig"
1035 source "arch/arm/mach-netx/Kconfig"
1037 source "arch/arm/mach-nomadik/Kconfig"
1038 source "arch/arm/plat-nomadik/Kconfig"
1040 source "arch/arm/plat-omap/Kconfig"
1042 source "arch/arm/mach-omap1/Kconfig"
1044 source "arch/arm/mach-omap2/Kconfig"
1046 source "arch/arm/mach-orion5x/Kconfig"
1048 source "arch/arm/mach-pxa/Kconfig"
1049 source "arch/arm/plat-pxa/Kconfig"
1051 source "arch/arm/mach-mmp/Kconfig"
1053 source "arch/arm/mach-realview/Kconfig"
1055 source "arch/arm/mach-sa1100/Kconfig"
1057 source "arch/arm/plat-samsung/Kconfig"
1058 source "arch/arm/plat-s3c24xx/Kconfig"
1059 source "arch/arm/plat-s5p/Kconfig"
1061 source "arch/arm/plat-spear/Kconfig"
1063 source "arch/arm/plat-tcc/Kconfig"
1065 if ARCH_S3C2410
1066 source "arch/arm/mach-s3c2410/Kconfig"
1067 source "arch/arm/mach-s3c2412/Kconfig"
1068 source "arch/arm/mach-s3c2416/Kconfig"
1069 source "arch/arm/mach-s3c2440/Kconfig"
1070 source "arch/arm/mach-s3c2443/Kconfig"
1071 endif
1073 if ARCH_S3C64XX
1074 source "arch/arm/mach-s3c64xx/Kconfig"
1075 endif
1077 source "arch/arm/mach-s5p64x0/Kconfig"
1079 source "arch/arm/mach-s5pc100/Kconfig"
1081 source "arch/arm/mach-s5pv210/Kconfig"
1083 source "arch/arm/mach-exynos/Kconfig"
1085 source "arch/arm/mach-shmobile/Kconfig"
1087 source "arch/arm/mach-tegra/Kconfig"
1089 source "arch/arm/mach-u300/Kconfig"
1091 source "arch/arm/mach-ux500/Kconfig"
1093 source "arch/arm/mach-versatile/Kconfig"
1095 source "arch/arm/mach-vexpress/Kconfig"
1096 source "arch/arm/plat-versatile/Kconfig"
1098 source "arch/arm/mach-vt8500/Kconfig"
1100 source "arch/arm/mach-w90x900/Kconfig"
1102 # Definitions to make life easier
1103 config ARCH_ACORN
1104 bool
1106 config PLAT_IOP
1107 bool
1108 select GENERIC_CLOCKEVENTS
1109 select HAVE_SCHED_CLOCK
1111 config PLAT_ORION
1112 bool
1113 select CLKSRC_MMIO
1114 select GENERIC_IRQ_CHIP
1115 select HAVE_SCHED_CLOCK
1117 config PLAT_PXA
1118 bool
1120 config PLAT_VERSATILE
1121 bool
1123 config ARM_TIMER_SP804
1124 bool
1125 select CLKSRC_MMIO
1127 source arch/arm/mm/Kconfig
1129 config ARM_NR_BANKS
1130 int
1131 default 16 if ARCH_EP93XX
1132 default 8
1134 config IWMMXT
1135 bool "Enable iWMMXt support"
1136 depends on CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_PJ4
1137 default y if PXA27x || PXA3xx || PXA95x || ARCH_MMP
1138 help
1139 Enable support for iWMMXt context switching at run time if
1140 running on a CPU that supports it.
1142 # bool 'Use XScale PMU as timer source' CONFIG_XSCALE_PMU_TIMER
1143 config XSCALE_PMU
1144 bool
1145 depends on CPU_XSCALE && !XSCALE_PMU_TIMER
1146 default y
1148 config CPU_HAS_PMU
1149 depends on (CPU_V6 || CPU_V6K || CPU_V7 || XSCALE_PMU) && \
1150 (!ARCH_OMAP3 || OMAP3_EMU)
1151 default y
1152 bool
1154 config MULTI_IRQ_HANDLER
1155 bool
1156 help
1157 Allow each machine to specify it's own IRQ handler at run time.
1159 if !MMU
1160 source "arch/arm/Kconfig-nommu"
1161 endif
1163 config ARM_ERRATA_411920
1164 bool "ARM errata: Invalidation of the Instruction Cache operation can fail"
1165 depends on CPU_V6 || CPU_V6K
1166 help
1167 Invalidation of the Instruction Cache operation can
1168 fail. This erratum is present in 1136 (before r1p4), 1156 and 1176.
1169 It does not affect the MPCore. This option enables the ARM Ltd.
1170 recommended workaround.
1172 config ARM_ERRATA_430973
1173 bool "ARM errata: Stale prediction on replaced interworking branch"
1174 depends on CPU_V7
1175 help
1176 This option enables the workaround for the 430973 Cortex-A8
1177 (r1p0..r1p2) erratum. If a code sequence containing an ARM/Thumb
1178 interworking branch is replaced with another code sequence at the
1179 same virtual address, whether due to self-modifying code or virtual
1180 to physical address re-mapping, Cortex-A8 does not recover from the
1181 stale interworking branch prediction. This results in Cortex-A8
1182 executing the new code sequence in the incorrect ARM or Thumb state.
1183 The workaround enables the BTB/BTAC operations by setting ACTLR.IBE
1184 and also flushes the branch target cache at every context switch.
1185 Note that setting specific bits in the ACTLR register may not be
1186 available in non-secure mode.
1188 config ARM_ERRATA_458693
1189 bool "ARM errata: Processor deadlock when a false hazard is created"
1190 depends on CPU_V7
1191 help
1192 This option enables the workaround for the 458693 Cortex-A8 (r2p0)
1193 erratum. For very specific sequences of memory operations, it is
1194 possible for a hazard condition intended for a cache line to instead
1195 be incorrectly associated with a different cache line. This false
1196 hazard might then cause a processor deadlock. The workaround enables
1197 the L1 caching of the NEON accesses and disables the PLD instruction
1198 in the ACTLR register. Note that setting specific bits in the ACTLR
1199 register may not be available in non-secure mode.
1201 config ARM_ERRATA_460075
1202 bool "ARM errata: Data written to the L2 cache can be overwritten with stale data"
1203 depends on CPU_V7
1204 help
1205 This option enables the workaround for the 460075 Cortex-A8 (r2p0)
1206 erratum. Any asynchronous access to the L2 cache may encounter a
1207 situation in which recent store transactions to the L2 cache are lost
1208 and overwritten with stale memory contents from external memory. The
1209 workaround disables the write-allocate mode for the L2 cache via the
1210 ACTLR register. Note that setting specific bits in the ACTLR register
1211 may not be available in non-secure mode.
1213 config ARM_ERRATA_742230
1214 bool "ARM errata: DMB operation may be faulty"
1215 depends on CPU_V7 && SMP
1216 help
1217 This option enables the workaround for the 742230 Cortex-A9
1218 (r1p0..r2p2) erratum. Under rare circumstances, a DMB instruction
1219 between two write operations may not ensure the correct visibility
1220 ordering of the two writes. This workaround sets a specific bit in
1221 the diagnostic register of the Cortex-A9 which causes the DMB
1222 instruction to behave as a DSB, ensuring the correct behaviour of
1223 the two writes.
1225 config ARM_ERRATA_742231
1226 bool "ARM errata: Incorrect hazard handling in the SCU may lead to data corruption"
1227 depends on CPU_V7 && SMP
1228 help
1229 This option enables the workaround for the 742231 Cortex-A9
1230 (r2p0..r2p2) erratum. Under certain conditions, specific to the
1231 Cortex-A9 MPCore micro-architecture, two CPUs working in SMP mode,
1232 accessing some data located in the same cache line, may get corrupted
1233 data due to bad handling of the address hazard when the line gets
1234 replaced from one of the CPUs at the same time as another CPU is
1235 accessing it. This workaround sets specific bits in the diagnostic
1236 register of the Cortex-A9 which reduces the linefill issuing
1237 capabilities of the processor.
1239 config PL310_ERRATA_588369
1240 bool "PL310 errata: Clean & Invalidate maintenance operations do not invalidate clean lines"
1241 depends on CACHE_L2X0
1242 help
1243 The PL310 L2 cache controller implements three types of Clean &
1244 Invalidate maintenance operations: by Physical Address
1245 (offset 0x7F0), by Index/Way (0x7F8) and by Way (0x7FC).
1246 They are architecturally defined to behave as the execution of a
1247 clean operation followed immediately by an invalidate operation,
1248 both performing to the same memory location. This functionality
1249 is not correctly implemented in PL310 as clean lines are not
1250 invalidated as a result of these operations.
1252 config ARM_ERRATA_720789
1253 bool "ARM errata: TLBIASIDIS and TLBIMVAIS operations can broadcast a faulty ASID"
1254 depends on CPU_V7 && SMP
1255 help
1256 This option enables the workaround for the 720789 Cortex-A9 (prior to
1257 r2p0) erratum. A faulty ASID can be sent to the other CPUs for the
1258 broadcasted CP15 TLB maintenance operations TLBIASIDIS and TLBIMVAIS.
1259 As a consequence of this erratum, some TLB entries which should be
1260 invalidated are not, resulting in an incoherency in the system page
1261 tables. The workaround changes the TLB flushing routines to invalidate
1262 entries regardless of the ASID.
1264 config PL310_ERRATA_727915
1265 bool "PL310 errata: Background Clean & Invalidate by Way operation can cause data corruption"
1266 depends on CACHE_L2X0
1267 help
1268 PL310 implements the Clean & Invalidate by Way L2 cache maintenance
1269 operation (offset 0x7FC). This operation runs in background so that
1270 PL310 can handle normal accesses while it is in progress. Under very
1271 rare circumstances, due to this erratum, write data can be lost when
1272 PL310 treats a cacheable write transaction during a Clean &
1273 Invalidate by Way operation.
1275 config ARM_ERRATA_743622
1276 bool "ARM errata: Faulty hazard checking in the Store Buffer may lead to data corruption"
1277 depends on CPU_V7
1278 help
1279 This option enables the workaround for the 743622 Cortex-A9
1280 (r2p0..r2p2) erratum. Under very rare conditions, a faulty
1281 optimisation in the Cortex-A9 Store Buffer may lead to data
1282 corruption. This workaround sets a specific bit in the diagnostic
1283 register of the Cortex-A9 which disables the Store Buffer
1284 optimisation, preventing the defect from occurring. This has no
1285 visible impact on the overall performance or power consumption of the
1286 processor.
1288 config ARM_ERRATA_751472
1289 bool "ARM errata: Interrupted ICIALLUIS may prevent completion of broadcasted operation"
1290 depends on CPU_V7 && SMP
1291 help
1292 This option enables the workaround for the 751472 Cortex-A9 (prior
1293 to r3p0) erratum. An interrupted ICIALLUIS operation may prevent the
1294 completion of a following broadcasted operation if the second
1295 operation is received by a CPU before the ICIALLUIS has completed,
1296 potentially leading to corrupted entries in the cache or TLB.
1298 config PL310_ERRATA_753970
1299 bool "PL310 errata: cache sync operation may be faulty"
1300 depends on CACHE_PL310
1301 help
1302 This option enables the workaround for the 753970 PL310 (r3p0) erratum.
1304 Under some condition the effect of cache sync operation on
1305 the store buffer still remains when the operation completes.
1306 This means that the store buffer is always asked to drain and
1307 this prevents it from merging any further writes. The workaround
1308 is to replace the normal offset of cache sync operation (0x730)
1309 by another offset targeting an unmapped PL310 register 0x740.
1310 This has the same effect as the cache sync operation: store buffer
1311 drain and waiting for all buffers empty.
1313 config ARM_ERRATA_754322
1314 bool "ARM errata: possible faulty MMU translations following an ASID switch"
1315 depends on CPU_V7
1316 help
1317 This option enables the workaround for the 754322 Cortex-A9 (r2p*,
1318 r3p*) erratum. A speculative memory access may cause a page table walk
1319 which starts prior to an ASID switch but completes afterwards. This
1320 can populate the micro-TLB with a stale entry which may be hit with
1321 the new ASID. This workaround places two dsb instructions in the mm
1322 switching code so that no page table walks can cross the ASID switch.
1324 config ARM_ERRATA_754327
1325 bool "ARM errata: no automatic Store Buffer drain"
1326 depends on CPU_V7 && SMP
1327 help
1328 This option enables the workaround for the 754327 Cortex-A9 (prior to
1329 r2p0) erratum. The Store Buffer does not have any automatic draining
1330 mechanism and therefore a livelock may occur if an external agent
1331 continuously polls a memory location waiting to observe an update.
1332 This workaround defines cpu_relax() as smp_mb(), preventing correctly
1333 written polling loops from denying visibility of updates to memory.
1335 config ARM_ERRATA_364296
1336 bool "ARM errata: Possible cache data corruption with hit-under-miss enabled"
1337 depends on CPU_V6 && !SMP
1338 help
1339 This options enables the workaround for the 364296 ARM1136
1340 r0p2 erratum (possible cache data corruption with
1341 hit-under-miss enabled). It sets the undocumented bit 31 in
1342 the auxiliary control register and the FI bit in the control
1343 register, thus disabling hit-under-miss without putting the
1344 processor into full low interrupt latency mode. ARM11MPCore
1345 is not affected.
1347 config ARM_ERRATA_764369
1348 bool "ARM errata: Data cache line maintenance operation by MVA may not succeed"
1349 depends on CPU_V7 && SMP
1350 help
1351 This option enables the workaround for erratum 764369
1352 affecting Cortex-A9 MPCore with two or more processors (all
1353 current revisions). Under certain timing circumstances, a data
1354 cache line maintenance operation by MVA targeting an Inner
1355 Shareable memory region may fail to proceed up to either the
1356 Point of Coherency or to the Point of Unification of the
1357 system. This workaround adds a DSB instruction before the
1358 relevant cache maintenance functions and sets a specific bit
1359 in the diagnostic control register of the SCU.
1361 config PL310_ERRATA_769419
1362 bool "PL310 errata: no automatic Store Buffer drain"
1363 depends on CACHE_L2X0
1364 help
1365 On revisions of the PL310 prior to r3p2, the Store Buffer does
1366 not automatically drain. This can cause normal, non-cacheable
1367 writes to be retained when the memory system is idle, leading
1368 to suboptimal I/O performance for drivers using coherent DMA.
1369 This option adds a write barrier to the cpu_idle loop so that,
1370 on systems with an outer cache, the store buffer is drained
1371 explicitly.
1373 endmenu
1375 source "arch/arm/common/Kconfig"
1377 menu "Bus support"
1379 config ARM_AMBA
1380 bool
1382 config ISA
1383 bool
1384 help
1385 Find out whether you have ISA slots on your motherboard. ISA is the
1386 name of a bus system, i.e. the way the CPU talks to the other stuff
1387 inside your box. Other bus systems are PCI, EISA, MicroChannel
1388 (MCA) or VESA. ISA is an older system, now being displaced by PCI;
1389 newer boards don't support it. If you have ISA, say Y, otherwise N.
1391 # Select ISA DMA controller support
1392 config ISA_DMA
1393 bool
1394 select ISA_DMA_API
1396 # Select ISA DMA interface
1397 config ISA_DMA_API
1398 bool
1400 config PCI
1401 bool "PCI support" if MIGHT_HAVE_PCI
1402 help
1403 Find out whether you have a PCI motherboard. PCI is the name of a
1404 bus system, i.e. the way the CPU talks to the other stuff inside
1405 your box. Other bus systems are ISA, EISA, MicroChannel (MCA) or
1406 VESA. If you have PCI, say Y, otherwise N.
1408 config PCI_DOMAINS
1409 bool
1410 depends on PCI
1412 config PCI_NANOENGINE
1413 bool "BSE nanoEngine PCI support"
1414 depends on SA1100_NANOENGINE
1415 help
1416 Enable PCI on the BSE nanoEngine board.
1418 config PCI_SYSCALL
1419 def_bool PCI
1421 # Select the host bridge type
1422 config PCI_HOST_VIA82C505
1423 bool
1424 depends on PCI && ARCH_SHARK
1425 default y
1427 config PCI_HOST_ITE8152
1428 bool
1429 depends on PCI && MACH_ARMCORE
1430 default y
1431 select DMABOUNCE
1433 source "drivers/pci/Kconfig"
1435 source "drivers/pcmcia/Kconfig"
1437 endmenu
1439 menu "Kernel Features"
1441 source "kernel/time/Kconfig"
1443 config SMP
1444 bool "Symmetric Multi-Processing"
1445 depends on CPU_V6K || CPU_V7
1446 depends on GENERIC_CLOCKEVENTS
1447 depends on REALVIEW_EB_ARM11MP || REALVIEW_EB_A9MP || \
1448 MACH_REALVIEW_PB11MP || MACH_REALVIEW_PBX || ARCH_OMAP4 || \
1449 ARCH_EXYNOS4 || ARCH_TEGRA || ARCH_U8500 || ARCH_VEXPRESS_CA9X4 || \
1450 ARCH_MSM_SCORPIONMP || ARCH_SHMOBILE || ARCH_HIGHBANK || SOC_IMX6Q
1451 depends on MMU
1452 select USE_GENERIC_SMP_HELPERS
1453 select HAVE_ARM_SCU if !ARCH_MSM_SCORPIONMP
1454 help
1455 This enables support for systems with more than one CPU. If you have
1456 a system with only one CPU, like most personal computers, say N. If
1457 you have a system with more than one CPU, say Y.
1459 If you say N here, the kernel will run on single and multiprocessor
1460 machines, but will use only one CPU of a multiprocessor machine. If
1461 you say Y here, the kernel will run on many, but not all, single
1462 processor machines. On a single processor machine, the kernel will
1463 run faster if you say N here.
1465 See also <file:Documentation/x86/i386/IO-APIC.txt>,
1466 <file:Documentation/nmi_watchdog.txt> and the SMP-HOWTO available at
1467 <http://tldp.org/HOWTO/SMP-HOWTO.html>.
1469 If you don't know what to do here, say N.
1471 config SMP_ON_UP
1472 bool "Allow booting SMP kernel on uniprocessor systems (EXPERIMENTAL)"
1473 depends on EXPERIMENTAL
1474 depends on SMP && !XIP_KERNEL
1475 default y
1476 help
1477 SMP kernels contain instructions which fail on non-SMP processors.
1478 Enabling this option allows the kernel to modify itself to make
1479 these instructions safe. Disabling it allows about 1K of space
1480 savings.
1482 If you don't know what to do here, say Y.
1484 config ARM_CPU_TOPOLOGY
1485 bool "Support cpu topology definition"
1486 depends on SMP && CPU_V7
1487 default y
1488 help
1489 Support ARM cpu topology definition. The MPIDR register defines
1490 affinity between processors which is then used to describe the cpu
1491 topology of an ARM System.
1493 config SCHED_MC
1494 bool "Multi-core scheduler support"
1495 depends on ARM_CPU_TOPOLOGY
1496 help
1497 Multi-core scheduler support improves the CPU scheduler's decision
1498 making when dealing with multi-core CPU chips at a cost of slightly
1499 increased overhead in some places. If unsure say N here.
1501 config SCHED_SMT
1502 bool "SMT scheduler support"
1503 depends on ARM_CPU_TOPOLOGY
1504 help
1505 Improves the CPU scheduler's decision making when dealing with
1506 MultiThreading at a cost of slightly increased overhead in some
1507 places. If unsure say N here.
1509 config HAVE_ARM_SCU
1510 bool
1511 help
1512 This option enables support for the ARM system coherency unit
1514 config HAVE_ARM_TWD
1515 bool
1516 depends on SMP
1517 select TICK_ONESHOT
1518 help
1519 This options enables support for the ARM timer and watchdog unit
1521 choice
1522 prompt "Memory split"
1523 default VMSPLIT_3G
1524 help
1525 Select the desired split between kernel and user memory.
1527 If you are not absolutely sure what you are doing, leave this
1528 option alone!
1530 config VMSPLIT_3G
1531 bool "3G/1G user/kernel split"
1532 config VMSPLIT_2G
1533 bool "2G/2G user/kernel split"
1534 config VMSPLIT_1G
1535 bool "1G/3G user/kernel split"
1536 endchoice
1538 config PAGE_OFFSET
1539 hex
1540 default 0x40000000 if VMSPLIT_1G
1541 default 0x80000000 if VMSPLIT_2G
1542 default 0xC0000000
1544 config NR_CPUS
1545 int "Maximum number of CPUs (2-32)"
1546 range 2 32
1547 depends on SMP
1548 default "4"
1550 config HOTPLUG_CPU
1551 bool "Support for hot-pluggable CPUs (EXPERIMENTAL)"
1552 depends on SMP && HOTPLUG && EXPERIMENTAL
1553 help
1554 Say Y here to experiment with turning CPUs off and on. CPUs
1555 can be controlled through /sys/devices/system/cpu.
1557 config LOCAL_TIMERS
1558 bool "Use local timer interrupts"
1559 depends on SMP
1560 default y
1561 select HAVE_ARM_TWD if (!ARCH_MSM_SCORPIONMP && !EXYNOS4_MCT)
1562 help
1563 Enable support for local timers on SMP platforms, rather then the
1564 legacy IPI broadcast method. Local timers allows the system
1565 accounting to be spread across the timer interval, preventing a
1566 "thundering herd" at every timer tick.
1568 config ARCH_NR_GPIO
1569 int
1570 default 1024 if ARCH_SHMOBILE || ARCH_TEGRA
1571 default 0
1572 help
1573 Maximum number of GPIOs in the system.
1575 If unsure, leave the default value.
1577 source kernel/Kconfig.preempt
1579 config HZ
1580 int
1581 default 200 if ARCH_EBSA110 || ARCH_S3C2410 || ARCH_S5P64X0 || \
1582 ARCH_S5PV210 || ARCH_EXYNOS4
1583 default OMAP_32K_TIMER_HZ if ARCH_OMAP && OMAP_32K_TIMER
1584 default AT91_TIMER_HZ if ARCH_AT91
1585 default SHMOBILE_TIMER_HZ if ARCH_SHMOBILE
1586 default 100
1588 config THUMB2_KERNEL
1589 bool "Compile the kernel in Thumb-2 mode (EXPERIMENTAL)"
1590 depends on CPU_V7 && !CPU_V6 && !CPU_V6K && EXPERIMENTAL
1591 select AEABI
1592 select ARM_ASM_UNIFIED
1593 select ARM_UNWIND
1594 help
1595 By enabling this option, the kernel will be compiled in
1596 Thumb-2 mode. A compiler/assembler that understand the unified
1597 ARM-Thumb syntax is needed.
1599 If unsure, say N.
1601 config THUMB2_AVOID_R_ARM_THM_JUMP11
1602 bool "Work around buggy Thumb-2 short branch relocations in gas"
1603 depends on THUMB2_KERNEL && MODULES
1604 default y
1605 help
1606 Various binutils versions can resolve Thumb-2 branches to
1607 locally-defined, preemptible global symbols as short-range "b.n"
1608 branch instructions.
1610 This is a problem, because there's no guarantee the final
1611 destination of the symbol, or any candidate locations for a
1612 trampoline, are within range of the branch. For this reason, the
1613 kernel does not support fixing up the R_ARM_THM_JUMP11 (102)
1614 relocation in modules at all, and it makes little sense to add
1615 support.
1617 The symptom is that the kernel fails with an "unsupported
1618 relocation" error when loading some modules.
1620 Until fixed tools are available, passing
1621 -fno-optimize-sibling-calls to gcc should prevent gcc generating
1622 code which hits this problem, at the cost of a bit of extra runtime
1623 stack usage in some cases.
1625 The problem is described in more detail at:
1626 https://bugs.launchpad.net/binutils-linaro/+bug/725126
1628 Only Thumb-2 kernels are affected.
1630 Unless you are sure your tools don't have this problem, say Y.
1632 config ARM_ASM_UNIFIED
1633 bool
1635 config AEABI
1636 bool "Use the ARM EABI to compile the kernel"
1637 help
1638 This option allows for the kernel to be compiled using the latest
1639 ARM ABI (aka EABI). This is only useful if you are using a user
1640 space environment that is also compiled with EABI.
1642 Since there are major incompatibilities between the legacy ABI and
1643 EABI, especially with regard to structure member alignment, this
1644 option also changes the kernel syscall calling convention to
1645 disambiguate both ABIs and allow for backward compatibility support
1646 (selected with CONFIG_OABI_COMPAT).
1648 To use this you need GCC version 4.0.0 or later.
1650 config OABI_COMPAT
1651 bool "Allow old ABI binaries to run with this kernel (EXPERIMENTAL)"
1652 depends on AEABI && EXPERIMENTAL && !THUMB2_KERNEL
1653 default y
1654 help
1655 This option preserves the old syscall interface along with the
1656 new (ARM EABI) one. It also provides a compatibility layer to
1657 intercept syscalls that have structure arguments which layout
1658 in memory differs between the legacy ABI and the new ARM EABI
1659 (only for non "thumb" binaries). This option adds a tiny
1660 overhead to all syscalls and produces a slightly larger kernel.
1661 If you know you'll be using only pure EABI user space then you
1662 can say N here. If this option is not selected and you attempt
1663 to execute a legacy ABI binary then the result will be
1664 UNPREDICTABLE (in fact it can be predicted that it won't work
1665 at all). If in doubt say Y.
1667 config ARCH_HAS_HOLES_MEMORYMODEL
1668 bool
1670 config ARCH_SPARSEMEM_ENABLE
1671 bool
1673 config ARCH_SPARSEMEM_DEFAULT
1674 def_bool ARCH_SPARSEMEM_ENABLE
1676 config ARCH_SELECT_MEMORY_MODEL
1677 def_bool ARCH_SPARSEMEM_ENABLE
1679 config HAVE_ARCH_PFN_VALID
1680 def_bool ARCH_HAS_HOLES_MEMORYMODEL || !SPARSEMEM
1682 config HIGHMEM
1683 bool "High Memory Support"
1684 depends on MMU
1685 help
1686 The address space of ARM processors is only 4 Gigabytes large
1687 and it has to accommodate user address space, kernel address
1688 space as well as some memory mapped IO. That means that, if you
1689 have a large amount of physical memory and/or IO, not all of the
1690 memory can be "permanently mapped" by the kernel. The physical
1691 memory that is not permanently mapped is called "high memory".
1693 Depending on the selected kernel/user memory split, minimum
1694 vmalloc space and actual amount of RAM, you may not need this
1695 option which should result in a slightly faster kernel.
1697 If unsure, say n.
1699 config HIGHPTE
1700 bool "Allocate 2nd-level pagetables from highmem"
1701 depends on HIGHMEM
1703 config HW_PERF_EVENTS
1704 bool "Enable hardware performance counter support for perf events"
1705 depends on PERF_EVENTS && CPU_HAS_PMU
1706 default y
1707 help
1708 Enable hardware performance counter support for perf events. If
1709 disabled, perf events will use software events only.
1711 source "mm/Kconfig"
1713 config FORCE_MAX_ZONEORDER
1714 int "Maximum zone order" if ARCH_SHMOBILE
1715 range 11 64 if ARCH_SHMOBILE
1716 default "9" if SA1111
1717 default "11"
1718 help
1719 The kernel memory allocator divides physically contiguous memory
1720 blocks into "zones", where each zone is a power of two number of
1721 pages. This option selects the largest power of two that the kernel
1722 keeps in the memory allocator. If you need to allocate very large
1723 blocks of physically contiguous memory, then you may need to
1724 increase this value.
1726 This config option is actually maximum order plus one. For example,
1727 a value of 11 means that the largest free memory block is 2^10 pages.
1729 config LEDS
1730 bool "Timer and CPU usage LEDs"
1731 depends on ARCH_CDB89712 || ARCH_EBSA110 || \
1732 ARCH_EBSA285 || ARCH_INTEGRATOR || \
1733 ARCH_LUBBOCK || MACH_MAINSTONE || ARCH_NETWINDER || \
1734 ARCH_OMAP || ARCH_P720T || ARCH_PXA_IDP || \
1735 ARCH_SA1100 || ARCH_SHARK || ARCH_VERSATILE || \
1736 ARCH_AT91 || ARCH_DAVINCI || \
1737 ARCH_KS8695 || MACH_RD88F5182 || ARCH_REALVIEW
1738 help
1739 If you say Y here, the LEDs on your machine will be used
1740 to provide useful information about your current system status.
1742 If you are compiling a kernel for a NetWinder or EBSA-285, you will
1743 be able to select which LEDs are active using the options below. If
1744 you are compiling a kernel for the EBSA-110 or the LART however, the
1745 red LED will simply flash regularly to indicate that the system is
1746 still functional. It is safe to say Y here if you have a CATS
1747 system, but the driver will do nothing.
1749 config LEDS_TIMER
1750 bool "Timer LED" if (!ARCH_CDB89712 && !ARCH_OMAP) || \
1751 OMAP_OSK_MISTRAL || MACH_OMAP_H2 \
1752 || MACH_OMAP_PERSEUS2
1753 depends on LEDS
1754 depends on !GENERIC_CLOCKEVENTS
1755 default y if ARCH_EBSA110
1756 help
1757 If you say Y here, one of the system LEDs (the green one on the
1758 NetWinder, the amber one on the EBSA285, or the red one on the LART)
1759 will flash regularly to indicate that the system is still
1760 operational. This is mainly useful to kernel hackers who are
1761 debugging unstable kernels.
1763 The LART uses the same LED for both Timer LED and CPU usage LED
1764 functions. You may choose to use both, but the Timer LED function
1765 will overrule the CPU usage LED.
1767 config LEDS_CPU
1768 bool "CPU usage LED" if (!ARCH_CDB89712 && !ARCH_EBSA110 && \
1769 !ARCH_OMAP) \
1770 || OMAP_OSK_MISTRAL || MACH_OMAP_H2 \
1771 || MACH_OMAP_PERSEUS2
1772 depends on LEDS
1773 help
1774 If you say Y here, the red LED will be used to give a good real
1775 time indication of CPU usage, by lighting whenever the idle task
1776 is not currently executing.
1778 The LART uses the same LED for both Timer LED and CPU usage LED
1779 functions. You may choose to use both, but the Timer LED function
1780 will overrule the CPU usage LED.
1782 config ALIGNMENT_TRAP
1783 bool
1784 depends on CPU_CP15_MMU
1785 default y if !ARCH_EBSA110
1786 select HAVE_PROC_CPU if PROC_FS
1787 help
1788 ARM processors cannot fetch/store information which is not
1789 naturally aligned on the bus, i.e., a 4 byte fetch must start at an
1790 address divisible by 4. On 32-bit ARM processors, these non-aligned
1791 fetch/store instructions will be emulated in software if you say
1792 here, which has a severe performance impact. This is necessary for
1793 correct operation of some network protocols. With an IP-only
1794 configuration it is safe to say N, otherwise say Y.
1796 config UACCESS_WITH_MEMCPY
1797 bool "Use kernel mem{cpy,set}() for {copy_to,clear}_user() (EXPERIMENTAL)"
1798 depends on MMU && EXPERIMENTAL
1799 default y if CPU_FEROCEON
1800 help
1801 Implement faster copy_to_user and clear_user methods for CPU
1802 cores where a 8-word STM instruction give significantly higher
1803 memory write throughput than a sequence of individual 32bit stores.
1805 A possible side effect is a slight increase in scheduling latency
1806 between threads sharing the same address space if they invoke
1807 such copy operations with large buffers.
1809 However, if the CPU data cache is using a write-allocate mode,
1810 this option is unlikely to provide any performance gain.
1812 config SECCOMP
1813 bool
1814 prompt "Enable seccomp to safely compute untrusted bytecode"
1815 ---help---
1816 This kernel feature is useful for number crunching applications
1817 that may need to compute untrusted bytecode during their
1818 execution. By using pipes or other transports made available to
1819 the process as file descriptors supporting the read/write
1820 syscalls, it's possible to isolate those applications in
1821 their own address space using seccomp. Once seccomp is
1822 enabled via prctl(PR_SET_SECCOMP), it cannot be disabled
1823 and the task is only allowed to execute a few safe syscalls
1824 defined by each seccomp mode.
1826 config CC_STACKPROTECTOR
1827 bool "Enable -fstack-protector buffer overflow detection (EXPERIMENTAL)"
1828 depends on EXPERIMENTAL
1829 help
1830 This option turns on the -fstack-protector GCC feature. This
1831 feature puts, at the beginning of functions, a canary value on
1832 the stack just before the return address, and validates
1833 the value just before actually returning. Stack based buffer
1834 overflows (that need to overwrite this return address) now also
1835 overwrite the canary, which gets detected and the attack is then
1836 neutralized via a kernel panic.
1837 This feature requires gcc version 4.2 or above.
1839 config DEPRECATED_PARAM_STRUCT
1840 bool "Provide old way to pass kernel parameters"
1841 help
1842 This was deprecated in 2001 and announced to live on for 5 years.
1843 Some old boot loaders still use this way.
1845 endmenu
1847 menu "Boot options"
1849 config USE_OF
1850 bool "Flattened Device Tree support"
1851 select OF
1852 select OF_EARLY_FLATTREE
1853 select IRQ_DOMAIN
1854 help
1855 Include support for flattened device tree machine descriptions.
1857 # Compressed boot loader in ROM. Yes, we really want to ask about
1858 # TEXT and BSS so we preserve their values in the config files.
1859 config ZBOOT_ROM_TEXT
1860 hex "Compressed ROM boot loader base address"
1861 default "0"
1862 help
1863 The physical address at which the ROM-able zImage is to be
1864 placed in the target. Platforms which normally make use of
1865 ROM-able zImage formats normally set this to a suitable
1866 value in their defconfig file.
1868 If ZBOOT_ROM is not enabled, this has no effect.
1870 config ZBOOT_ROM_BSS
1871 hex "Compressed ROM boot loader BSS address"
1872 default "0"
1873 help
1874 The base address of an area of read/write memory in the target
1875 for the ROM-able zImage which must be available while the
1876 decompressor is running. It must be large enough to hold the
1877 entire decompressed kernel plus an additional 128 KiB.
1878 Platforms which normally make use of ROM-able zImage formats
1879 normally set this to a suitable value in their defconfig file.
1881 If ZBOOT_ROM is not enabled, this has no effect.
1883 config ZBOOT_ROM
1884 bool "Compressed boot loader in ROM/flash"
1885 depends on ZBOOT_ROM_TEXT != ZBOOT_ROM_BSS
1886 help
1887 Say Y here if you intend to execute your compressed kernel image
1888 (zImage) directly from ROM or flash. If unsure, say N.
1890 choice
1891 prompt "Include SD/MMC loader in zImage (EXPERIMENTAL)"
1892 depends on ZBOOT_ROM && ARCH_SH7372 && EXPERIMENTAL
1893 default ZBOOT_ROM_NONE
1894 help
1895 Include experimental SD/MMC loading code in the ROM-able zImage.
1896 With this enabled it is possible to write the the ROM-able zImage
1897 kernel image to an MMC or SD card and boot the kernel straight
1898 from the reset vector. At reset the processor Mask ROM will load
1899 the first part of the the ROM-able zImage which in turn loads the
1900 rest the kernel image to RAM.
1902 config ZBOOT_ROM_NONE
1903 bool "No SD/MMC loader in zImage (EXPERIMENTAL)"
1904 help
1905 Do not load image from SD or MMC
1907 config ZBOOT_ROM_MMCIF
1908 bool "Include MMCIF loader in zImage (EXPERIMENTAL)"
1909 help
1910 Load image from MMCIF hardware block.
1912 config ZBOOT_ROM_SH_MOBILE_SDHI
1913 bool "Include SuperH Mobile SDHI loader in zImage (EXPERIMENTAL)"
1914 help
1915 Load image from SDHI hardware block
1917 endchoice
1919 config ARM_APPENDED_DTB
1920 bool "Use appended device tree blob to zImage (EXPERIMENTAL)"
1921 depends on OF && !ZBOOT_ROM && EXPERIMENTAL
1922 help
1923 With this option, the boot code will look for a device tree binary
1924 (DTB) appended to zImage
1925 (e.g. cat zImage <filename>.dtb > zImage_w_dtb).
1927 This is meant as a backward compatibility convenience for those
1928 systems with a bootloader that can't be upgraded to accommodate
1929 the documented boot protocol using a device tree.
1931 Beware that there is very little in terms of protection against
1932 this option being confused by leftover garbage in memory that might
1933 look like a DTB header after a reboot if no actual DTB is appended
1934 to zImage. Do not leave this option active in a production kernel
1935 if you don't intend to always append a DTB. Proper passing of the
1936 location into r2 of a bootloader provided DTB is always preferable
1937 to this option.
1939 config ARM_ATAG_DTB_COMPAT
1940 bool "Supplement the appended DTB with traditional ATAG information"
1941 depends on ARM_APPENDED_DTB
1942 help
1943 Some old bootloaders can't be updated to a DTB capable one, yet
1944 they provide ATAGs with memory configuration, the ramdisk address,
1945 the kernel cmdline string, etc. Such information is dynamically
1946 provided by the bootloader and can't always be stored in a static
1947 DTB. To allow a device tree enabled kernel to be used with such
1948 bootloaders, this option allows zImage to extract the information
1949 from the ATAG list and store it at run time into the appended DTB.
1951 config CMDLINE
1952 string "Default kernel command string"
1953 default ""
1954 help
1955 On some architectures (EBSA110 and CATS), there is currently no way
1956 for the boot loader to pass arguments to the kernel. For these
1957 architectures, you should supply some command-line options at build
1958 time by entering them here. As a minimum, you should specify the
1959 memory size and the root device (e.g., mem=64M root=/dev/nfs).
1961 choice
1962 prompt "Kernel command line type" if CMDLINE != ""
1963 default CMDLINE_FROM_BOOTLOADER
1965 config CMDLINE_FROM_BOOTLOADER
1966 bool "Use bootloader kernel arguments if available"
1967 help
1968 Uses the command-line options passed by the boot loader. If
1969 the boot loader doesn't provide any, the default kernel command
1970 string provided in CMDLINE will be used.
1972 config CMDLINE_EXTEND
1973 bool "Extend bootloader kernel arguments"
1974 help
1975 The command-line arguments provided by the boot loader will be
1976 appended to the default kernel command string.
1978 config CMDLINE_FORCE
1979 bool "Always use the default kernel command string"
1980 help
1981 Always use the default kernel command string, even if the boot
1982 loader passes other arguments to the kernel.
1983 This is useful if you cannot or don't want to change the
1984 command-line options your boot loader passes to the kernel.
1985 endchoice
1987 config XIP_KERNEL
1988 bool "Kernel Execute-In-Place from ROM"
1989 depends on !ZBOOT_ROM
1990 help
1991 Execute-In-Place allows the kernel to run from non-volatile storage
1992 directly addressable by the CPU, such as NOR flash. This saves RAM
1993 space since the text section of the kernel is not loaded from flash
1994 to RAM. Read-write sections, such as the data section and stack,
1995 are still copied to RAM. The XIP kernel is not compressed since
1996 it has to run directly from flash, so it will take more space to
1997 store it. The flash address used to link the kernel object files,
1998 and for storing it, is configuration dependent. Therefore, if you
1999 say Y here, you must know the proper physical address where to
2000 store the kernel image depending on your own flash memory usage.
2002 Also note that the make target becomes "make xipImage" rather than
2003 "make zImage" or "make Image". The final kernel binary to put in
2004 ROM memory will be arch/arm/boot/xipImage.
2006 If unsure, say N.
2008 config XIP_PHYS_ADDR
2009 hex "XIP Kernel Physical Location"
2010 depends on XIP_KERNEL
2011 default "0x00080000"
2012 help
2013 This is the physical address in your flash memory the kernel will
2014 be linked for and stored to. This address is dependent on your
2015 own flash usage.
2017 config KEXEC
2018 bool "Kexec system call (EXPERIMENTAL)"
2019 depends on EXPERIMENTAL
2020 help
2021 kexec is a system call that implements the ability to shutdown your
2022 current kernel, and to start another kernel. It is like a reboot
2023 but it is independent of the system firmware. And like a reboot
2024 you can start any kernel with it, not just Linux.
2026 It is an ongoing process to be certain the hardware in a machine
2027 is properly shutdown, so do not be surprised if this code does not
2028 initially work for you. It may help to enable device hotplugging
2029 support.
2031 config ATAGS_PROC
2032 bool "Export atags in procfs"
2033 depends on KEXEC
2034 default y
2035 help
2036 Should the atags used to boot the kernel be exported in an "atags"
2037 file in procfs. Useful with kexec.
2039 config CRASH_DUMP
2040 bool "Build kdump crash kernel (EXPERIMENTAL)"
2041 depends on EXPERIMENTAL
2042 help
2043 Generate crash dump after being started by kexec. This should
2044 be normally only set in special crash dump kernels which are
2045 loaded in the main kernel with kexec-tools into a specially
2046 reserved region and then later executed after a crash by
2047 kdump/kexec. The crash dump kernel must be compiled to a
2048 memory address not used by the main kernel
2050 For more details see Documentation/kdump/kdump.txt
2052 config AUTO_ZRELADDR
2053 bool "Auto calculation of the decompressed kernel image address"
2054 depends on !ZBOOT_ROM && !ARCH_U300
2055 help
2056 ZRELADDR is the physical address where the decompressed kernel
2057 image will be placed. If AUTO_ZRELADDR is selected, the address
2058 will be determined at run-time by masking the current IP with
2059 0xf8000000. This assumes the zImage being placed in the first 128MB
2060 from start of memory.
2062 endmenu
2064 menu "CPU Power Management"
2066 if ARCH_HAS_CPUFREQ
2068 source "drivers/cpufreq/Kconfig"
2070 config CPU_FREQ_IMX
2071 tristate "CPUfreq driver for i.MX CPUs"
2072 depends on ARCH_MXC && CPU_FREQ
2073 help
2074 This enables the CPUfreq driver for i.MX CPUs.
2076 config CPU_FREQ_SA1100
2077 bool
2079 config CPU_FREQ_SA1110
2080 bool
2082 config CPU_FREQ_INTEGRATOR
2083 tristate "CPUfreq driver for ARM Integrator CPUs"
2084 depends on ARCH_INTEGRATOR && CPU_FREQ
2085 default y
2086 help
2087 This enables the CPUfreq driver for ARM Integrator CPUs.
2089 For details, take a look at <file:Documentation/cpu-freq>.
2091 If in doubt, say Y.
2093 config CPU_FREQ_PXA
2094 bool
2095 depends on CPU_FREQ && ARCH_PXA && PXA25x
2096 default y
2097 select CPU_FREQ_TABLE
2098 select CPU_FREQ_DEFAULT_GOV_USERSPACE
2100 config CPU_FREQ_S3C
2101 bool
2102 help
2103 Internal configuration node for common cpufreq on Samsung SoC
2105 config CPU_FREQ_S3C24XX
2106 bool "CPUfreq driver for Samsung S3C24XX series CPUs (EXPERIMENTAL)"
2107 depends on ARCH_S3C2410 && CPU_FREQ && EXPERIMENTAL
2108 select CPU_FREQ_S3C
2109 help
2110 This enables the CPUfreq driver for the Samsung S3C24XX family
2111 of CPUs.
2113 For details, take a look at <file:Documentation/cpu-freq>.
2115 If in doubt, say N.
2117 config CPU_FREQ_S3C24XX_PLL
2118 bool "Support CPUfreq changing of PLL frequency (EXPERIMENTAL)"
2119 depends on CPU_FREQ_S3C24XX && EXPERIMENTAL
2120 help
2121 Compile in support for changing the PLL frequency from the
2122 S3C24XX series CPUfreq driver. The PLL takes time to settle
2123 after a frequency change, so by default it is not enabled.
2125 This also means that the PLL tables for the selected CPU(s) will
2126 be built which may increase the size of the kernel image.
2128 config CPU_FREQ_S3C24XX_DEBUG
2129 bool "Debug CPUfreq Samsung driver core"
2130 depends on CPU_FREQ_S3C24XX
2131 help
2132 Enable s3c_freq_dbg for the Samsung S3C CPUfreq core
2134 config CPU_FREQ_S3C24XX_IODEBUG
2135 bool "Debug CPUfreq Samsung driver IO timing"
2136 depends on CPU_FREQ_S3C24XX
2137 help
2138 Enable s3c_freq_iodbg for the Samsung S3C CPUfreq core
2140 config CPU_FREQ_S3C24XX_DEBUGFS
2141 bool "Export debugfs for CPUFreq"
2142 depends on CPU_FREQ_S3C24XX && DEBUG_FS
2143 help
2144 Export status information via debugfs.
2146 endif
2148 source "drivers/cpuidle/Kconfig"
2150 endmenu
2152 menu "Floating point emulation"
2154 comment "At least one emulation must be selected"
2156 config FPE_NWFPE
2157 bool "NWFPE math emulation"
2158 depends on (!AEABI || OABI_COMPAT) && !THUMB2_KERNEL
2159 ---help---
2160 Say Y to include the NWFPE floating point emulator in the kernel.
2161 This is necessary to run most binaries. Linux does not currently
2162 support floating point hardware so you need to say Y here even if
2163 your machine has an FPA or floating point co-processor podule.
2165 You may say N here if you are going to load the Acorn FPEmulator
2166 early in the bootup.
2168 config FPE_NWFPE_XP
2169 bool "Support extended precision"
2170 depends on FPE_NWFPE
2171 help
2172 Say Y to include 80-bit support in the kernel floating-point
2173 emulator. Otherwise, only 32 and 64-bit support is compiled in.
2174 Note that gcc does not generate 80-bit operations by default,
2175 so in most cases this option only enlarges the size of the
2176 floating point emulator without any good reason.
2178 You almost surely want to say N here.
2180 config FPE_FASTFPE
2181 bool "FastFPE math emulation (EXPERIMENTAL)"
2182 depends on (!AEABI || OABI_COMPAT) && !CPU_32v3 && EXPERIMENTAL
2183 ---help---
2184 Say Y here to include the FAST floating point emulator in the kernel.
2185 This is an experimental much faster emulator which now also has full
2186 precision for the mantissa. It does not support any exceptions.
2187 It is very simple, and approximately 3-6 times faster than NWFPE.
2189 It should be sufficient for most programs. It may be not suitable
2190 for scientific calculations, but you have to check this for yourself.
2191 If you do not feel you need a faster FP emulation you should better
2192 choose NWFPE.
2194 config VFP
2195 bool "VFP-format floating point maths"
2196 depends on CPU_V6 || CPU_V6K || CPU_ARM926T || CPU_V7 || CPU_FEROCEON
2197 help
2198 Say Y to include VFP support code in the kernel. This is needed
2199 if your hardware includes a VFP unit.
2201 Please see <file:Documentation/arm/VFP/release-notes.txt> for
2202 release notes and additional status information.
2204 Say N if your target does not have VFP hardware.
2206 config VFPv3
2207 bool
2208 depends on VFP
2209 default y if CPU_V7
2211 config NEON
2212 bool "Advanced SIMD (NEON) Extension support"
2213 depends on VFPv3 && CPU_V7
2214 help
2215 Say Y to include support code for NEON, the ARMv7 Advanced SIMD
2216 Extension.
2218 endmenu
2220 menu "Userspace binary formats"
2222 source "fs/Kconfig.binfmt"
2224 config ARTHUR
2225 tristate "RISC OS personality"
2226 depends on !AEABI
2227 help
2228 Say Y here to include the kernel code necessary if you want to run
2229 Acorn RISC OS/Arthur binaries under Linux. This code is still very
2230 experimental; if this sounds frightening, say N and sleep in peace.
2231 You can also say M here to compile this support as a module (which
2232 will be called arthur).
2234 endmenu
2236 menu "Power management options"
2238 source "kernel/power/Kconfig"
2240 config ARCH_SUSPEND_POSSIBLE
2241 depends on !ARCH_S5PC100
2242 depends on CPU_ARM920T || CPU_ARM926T || CPU_SA1100 || \
2243 CPU_V6 || CPU_V6K || CPU_V7 || CPU_XSC3 || CPU_XSCALE
2244 def_bool y
2246 config ARM_CPU_SUSPEND
2247 def_bool PM_SLEEP
2249 endmenu
2251 source "net/Kconfig"
2253 source "drivers/Kconfig"
2255 source "fs/Kconfig"
2257 source "arch/arm/Kconfig.debug"
2259 source "security/Kconfig"
2261 source "crypto/Kconfig"
2263 source "lib/Kconfig"