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net: introduce ptp one step time stamp mode for sync packets
[linux-2.6.git] / arch / arm / mach-omap2 / omap_hwmod_3xxx_data.c
blob25bf43b5a4ec02922049abd9fd16806297fc1b37
1 /*
2 * omap_hwmod_3xxx_data.c - hardware modules present on the OMAP3xxx chips
3 *
4 * Copyright (C) 2009-2011 Nokia Corporation
5 * Paul Walmsley
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 *
11 * The data in this file should be completely autogeneratable from
12 * the TI hardware database or other technical documentation.
13 *
14 * XXX these should be marked initdata for multi-OMAP kernels
15 */
16 #include <plat/omap_hwmod.h>
17 #include <mach/irqs.h>
18 #include <plat/cpu.h>
19 #include <plat/dma.h>
20 #include <plat/serial.h>
21 #include <plat/l3_3xxx.h>
22 #include <plat/l4_3xxx.h>
23 #include <plat/i2c.h>
24 #include <plat/gpio.h>
25 #include <plat/mmc.h>
26 #include <plat/mcbsp.h>
27 #include <plat/mcspi.h>
28 #include <plat/dmtimer.h>
29
30 #include "omap_hwmod_common_data.h"
31
32 #include "prm-regbits-34xx.h"
33 #include "cm-regbits-34xx.h"
34 #include "wd_timer.h"
35 #include <mach/am35xx.h>
36
37 /*
38 * OMAP3xxx hardware module integration data
39 *
40 * ALl of the data in this section should be autogeneratable from the
41 * TI hardware database or other technical documentation. Data that
42 * is driver-specific or driver-kernel integration-specific belongs
43 * elsewhere.
44 */
45
46 static struct omap_hwmod omap3xxx_mpu_hwmod;
47 static struct omap_hwmod omap3xxx_iva_hwmod;
48 static struct omap_hwmod omap3xxx_l3_main_hwmod;
49 static struct omap_hwmod omap3xxx_l4_core_hwmod;
50 static struct omap_hwmod omap3xxx_l4_per_hwmod;
51 static struct omap_hwmod omap3xxx_wd_timer2_hwmod;
52 static struct omap_hwmod omap3430es1_dss_core_hwmod;
53 static struct omap_hwmod omap3xxx_dss_core_hwmod;
54 static struct omap_hwmod omap3xxx_dss_dispc_hwmod;
55 static struct omap_hwmod omap3xxx_dss_dsi1_hwmod;
56 static struct omap_hwmod omap3xxx_dss_rfbi_hwmod;
57 static struct omap_hwmod omap3xxx_dss_venc_hwmod;
58 static struct omap_hwmod omap3xxx_i2c1_hwmod;
59 static struct omap_hwmod omap3xxx_i2c2_hwmod;
60 static struct omap_hwmod omap3xxx_i2c3_hwmod;
61 static struct omap_hwmod omap3xxx_gpio1_hwmod;
62 static struct omap_hwmod omap3xxx_gpio2_hwmod;
63 static struct omap_hwmod omap3xxx_gpio3_hwmod;
64 static struct omap_hwmod omap3xxx_gpio4_hwmod;
65 static struct omap_hwmod omap3xxx_gpio5_hwmod;
66 static struct omap_hwmod omap3xxx_gpio6_hwmod;
67 static struct omap_hwmod omap34xx_sr1_hwmod;
68 static struct omap_hwmod omap34xx_sr2_hwmod;
69 static struct omap_hwmod omap34xx_mcspi1;
70 static struct omap_hwmod omap34xx_mcspi2;
71 static struct omap_hwmod omap34xx_mcspi3;
72 static struct omap_hwmod omap34xx_mcspi4;
73 static struct omap_hwmod omap3xxx_mmc1_hwmod;
74 static struct omap_hwmod omap3xxx_mmc2_hwmod;
75 static struct omap_hwmod omap3xxx_mmc3_hwmod;
76 static struct omap_hwmod am35xx_usbhsotg_hwmod;
77
78 static struct omap_hwmod omap3xxx_dma_system_hwmod;
79
80 static struct omap_hwmod omap3xxx_mcbsp1_hwmod;
81 static struct omap_hwmod omap3xxx_mcbsp2_hwmod;
82 static struct omap_hwmod omap3xxx_mcbsp3_hwmod;
83 static struct omap_hwmod omap3xxx_mcbsp4_hwmod;
84 static struct omap_hwmod omap3xxx_mcbsp5_hwmod;
85 static struct omap_hwmod omap3xxx_mcbsp2_sidetone_hwmod;
86 static struct omap_hwmod omap3xxx_mcbsp3_sidetone_hwmod;
87
88 /* L3 -> L4_CORE interface */
89 static struct omap_hwmod_ocp_if omap3xxx_l3_main__l4_core = {
90 .master = &omap3xxx_l3_main_hwmod,
91 .slave = &omap3xxx_l4_core_hwmod,
92 .user = OCP_USER_MPU | OCP_USER_SDMA,
93 };
94
95 /* L3 -> L4_PER interface */
96 static struct omap_hwmod_ocp_if omap3xxx_l3_main__l4_per = {
97 .master = &omap3xxx_l3_main_hwmod,
98 .slave = &omap3xxx_l4_per_hwmod,
99 .user = OCP_USER_MPU | OCP_USER_SDMA,
100 };
101
102 /* L3 taret configuration and error log registers */
103 static struct omap_hwmod_irq_info omap3xxx_l3_main_irqs[] = {
104 { .irq = INT_34XX_L3_DBG_IRQ },
105 { .irq = INT_34XX_L3_APP_IRQ },
106 { .irq = -1 }
107 };
108
109 static struct omap_hwmod_addr_space omap3xxx_l3_main_addrs[] = {
110 {
111 .pa_start = 0x68000000,
112 .pa_end = 0x6800ffff,
113 .flags = ADDR_TYPE_RT,
114 },
115 { }
116 };
117
118 /* MPU -> L3 interface */
119 static struct omap_hwmod_ocp_if omap3xxx_mpu__l3_main = {
120 .master = &omap3xxx_mpu_hwmod,
121 .slave = &omap3xxx_l3_main_hwmod,
122 .addr = omap3xxx_l3_main_addrs,
123 .user = OCP_USER_MPU,
124 };
125
126 /* Slave interfaces on the L3 interconnect */
127 static struct omap_hwmod_ocp_if *omap3xxx_l3_main_slaves[] = {
128 &omap3xxx_mpu__l3_main,
129 };
130
131 /* DSS -> l3 */
132 static struct omap_hwmod_ocp_if omap3xxx_dss__l3 = {
133 .master = &omap3xxx_dss_core_hwmod,
134 .slave = &omap3xxx_l3_main_hwmod,
135 .fw = {
136 .omap2 = {
137 .l3_perm_bit = OMAP3_L3_CORE_FW_INIT_ID_DSS,
138 .flags = OMAP_FIREWALL_L3,
139 }
140 },
141 .user = OCP_USER_MPU | OCP_USER_SDMA,
142 };
143
144 /* Master interfaces on the L3 interconnect */
145 static struct omap_hwmod_ocp_if *omap3xxx_l3_main_masters[] = {
146 &omap3xxx_l3_main__l4_core,
147 &omap3xxx_l3_main__l4_per,
148 };
149
150 /* L3 */
151 static struct omap_hwmod omap3xxx_l3_main_hwmod = {
152 .name = "l3_main",
153 .class = &l3_hwmod_class,
154 .mpu_irqs = omap3xxx_l3_main_irqs,
155 .masters = omap3xxx_l3_main_masters,
156 .masters_cnt = ARRAY_SIZE(omap3xxx_l3_main_masters),
157 .slaves = omap3xxx_l3_main_slaves,
158 .slaves_cnt = ARRAY_SIZE(omap3xxx_l3_main_slaves),
159 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
160 .flags = HWMOD_NO_IDLEST,
161 };
162
163 static struct omap_hwmod omap3xxx_l4_wkup_hwmod;
164 static struct omap_hwmod omap3xxx_uart1_hwmod;
165 static struct omap_hwmod omap3xxx_uart2_hwmod;
166 static struct omap_hwmod omap3xxx_uart3_hwmod;
167 static struct omap_hwmod omap3xxx_uart4_hwmod;
168 static struct omap_hwmod omap3xxx_usbhsotg_hwmod;
169
170 /* l3_core -> usbhsotg interface */
171 static struct omap_hwmod_ocp_if omap3xxx_usbhsotg__l3 = {
172 .master = &omap3xxx_usbhsotg_hwmod,
173 .slave = &omap3xxx_l3_main_hwmod,
174 .clk = "core_l3_ick",
175 .user = OCP_USER_MPU,
176 };
177
178 /* l3_core -> am35xx_usbhsotg interface */
179 static struct omap_hwmod_ocp_if am35xx_usbhsotg__l3 = {
180 .master = &am35xx_usbhsotg_hwmod,
181 .slave = &omap3xxx_l3_main_hwmod,
182 .clk = "core_l3_ick",
183 .user = OCP_USER_MPU,
184 };
185 /* L4_CORE -> L4_WKUP interface */
186 static struct omap_hwmod_ocp_if omap3xxx_l4_core__l4_wkup = {
187 .master = &omap3xxx_l4_core_hwmod,
188 .slave = &omap3xxx_l4_wkup_hwmod,
189 .user = OCP_USER_MPU | OCP_USER_SDMA,
190 };
191
192 /* L4 CORE -> MMC1 interface */
193 static struct omap_hwmod_ocp_if omap3xxx_l4_core__mmc1 = {
194 .master = &omap3xxx_l4_core_hwmod,
195 .slave = &omap3xxx_mmc1_hwmod,
196 .clk = "mmchs1_ick",
197 .addr = omap2430_mmc1_addr_space,
198 .user = OCP_USER_MPU | OCP_USER_SDMA,
199 .flags = OMAP_FIREWALL_L4
200 };
201
202 /* L4 CORE -> MMC2 interface */
203 static struct omap_hwmod_ocp_if omap3xxx_l4_core__mmc2 = {
204 .master = &omap3xxx_l4_core_hwmod,
205 .slave = &omap3xxx_mmc2_hwmod,
206 .clk = "mmchs2_ick",
207 .addr = omap2430_mmc2_addr_space,
208 .user = OCP_USER_MPU | OCP_USER_SDMA,
209 .flags = OMAP_FIREWALL_L4
210 };
211
212 /* L4 CORE -> MMC3 interface */
213 static struct omap_hwmod_addr_space omap3xxx_mmc3_addr_space[] = {
214 {
215 .pa_start = 0x480ad000,
216 .pa_end = 0x480ad1ff,
217 .flags = ADDR_TYPE_RT,
218 },
219 { }
220 };
221
222 static struct omap_hwmod_ocp_if omap3xxx_l4_core__mmc3 = {
223 .master = &omap3xxx_l4_core_hwmod,
224 .slave = &omap3xxx_mmc3_hwmod,
225 .clk = "mmchs3_ick",
226 .addr = omap3xxx_mmc3_addr_space,
227 .user = OCP_USER_MPU | OCP_USER_SDMA,
228 .flags = OMAP_FIREWALL_L4
229 };
230
231 /* L4 CORE -> UART1 interface */
232 static struct omap_hwmod_addr_space omap3xxx_uart1_addr_space[] = {
233 {
234 .pa_start = OMAP3_UART1_BASE,
235 .pa_end = OMAP3_UART1_BASE + SZ_8K - 1,
236 .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
237 },
238 { }
239 };
240
241 static struct omap_hwmod_ocp_if omap3_l4_core__uart1 = {
242 .master = &omap3xxx_l4_core_hwmod,
243 .slave = &omap3xxx_uart1_hwmod,
244 .clk = "uart1_ick",
245 .addr = omap3xxx_uart1_addr_space,
246 .user = OCP_USER_MPU | OCP_USER_SDMA,
247 };
248
249 /* L4 CORE -> UART2 interface */
250 static struct omap_hwmod_addr_space omap3xxx_uart2_addr_space[] = {
251 {
252 .pa_start = OMAP3_UART2_BASE,
253 .pa_end = OMAP3_UART2_BASE + SZ_1K - 1,
254 .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
255 },
256 { }
257 };
258
259 static struct omap_hwmod_ocp_if omap3_l4_core__uart2 = {
260 .master = &omap3xxx_l4_core_hwmod,
261 .slave = &omap3xxx_uart2_hwmod,
262 .clk = "uart2_ick",
263 .addr = omap3xxx_uart2_addr_space,
264 .user = OCP_USER_MPU | OCP_USER_SDMA,
265 };
266
267 /* L4 PER -> UART3 interface */
268 static struct omap_hwmod_addr_space omap3xxx_uart3_addr_space[] = {
269 {
270 .pa_start = OMAP3_UART3_BASE,
271 .pa_end = OMAP3_UART3_BASE + SZ_1K - 1,
272 .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
273 },
274 { }
275 };
276
277 static struct omap_hwmod_ocp_if omap3_l4_per__uart3 = {
278 .master = &omap3xxx_l4_per_hwmod,
279 .slave = &omap3xxx_uart3_hwmod,
280 .clk = "uart3_ick",
281 .addr = omap3xxx_uart3_addr_space,
282 .user = OCP_USER_MPU | OCP_USER_SDMA,
283 };
284
285 /* L4 PER -> UART4 interface */
286 static struct omap_hwmod_addr_space omap3xxx_uart4_addr_space[] = {
287 {
288 .pa_start = OMAP3_UART4_BASE,
289 .pa_end = OMAP3_UART4_BASE + SZ_1K - 1,
290 .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
291 },
292 { }
293 };
294
295 static struct omap_hwmod_ocp_if omap3_l4_per__uart4 = {
296 .master = &omap3xxx_l4_per_hwmod,
297 .slave = &omap3xxx_uart4_hwmod,
298 .clk = "uart4_ick",
299 .addr = omap3xxx_uart4_addr_space,
300 .user = OCP_USER_MPU | OCP_USER_SDMA,
301 };
302
303 /* L4 CORE -> I2C1 interface */
304 static struct omap_hwmod_ocp_if omap3_l4_core__i2c1 = {
305 .master = &omap3xxx_l4_core_hwmod,
306 .slave = &omap3xxx_i2c1_hwmod,
307 .clk = "i2c1_ick",
308 .addr = omap2_i2c1_addr_space,
309 .fw = {
310 .omap2 = {
311 .l4_fw_region = OMAP3_L4_CORE_FW_I2C1_REGION,
312 .l4_prot_group = 7,
313 .flags = OMAP_FIREWALL_L4,
314 }
315 },
316 .user = OCP_USER_MPU | OCP_USER_SDMA,
317 };
318
319 /* L4 CORE -> I2C2 interface */
320 static struct omap_hwmod_ocp_if omap3_l4_core__i2c2 = {
321 .master = &omap3xxx_l4_core_hwmod,
322 .slave = &omap3xxx_i2c2_hwmod,
323 .clk = "i2c2_ick",
324 .addr = omap2_i2c2_addr_space,
325 .fw = {
326 .omap2 = {
327 .l4_fw_region = OMAP3_L4_CORE_FW_I2C2_REGION,
328 .l4_prot_group = 7,
329 .flags = OMAP_FIREWALL_L4,
330 }
331 },
332 .user = OCP_USER_MPU | OCP_USER_SDMA,
333 };
334
335 /* L4 CORE -> I2C3 interface */
336 static struct omap_hwmod_addr_space omap3xxx_i2c3_addr_space[] = {
337 {
338 .pa_start = 0x48060000,
339 .pa_end = 0x48060000 + SZ_128 - 1,
340 .flags = ADDR_TYPE_RT,
341 },
342 { }
343 };
344
345 static struct omap_hwmod_ocp_if omap3_l4_core__i2c3 = {
346 .master = &omap3xxx_l4_core_hwmod,
347 .slave = &omap3xxx_i2c3_hwmod,
348 .clk = "i2c3_ick",
349 .addr = omap3xxx_i2c3_addr_space,
350 .fw = {
351 .omap2 = {
352 .l4_fw_region = OMAP3_L4_CORE_FW_I2C3_REGION,
353 .l4_prot_group = 7,
354 .flags = OMAP_FIREWALL_L4,
355 }
356 },
357 .user = OCP_USER_MPU | OCP_USER_SDMA,
358 };
359
360 /* L4 CORE -> SR1 interface */
361 static struct omap_hwmod_addr_space omap3_sr1_addr_space[] = {
362 {
363 .pa_start = OMAP34XX_SR1_BASE,
364 .pa_end = OMAP34XX_SR1_BASE + SZ_1K - 1,
365 .flags = ADDR_TYPE_RT,
366 },
367 { }
368 };
369
370 static struct omap_hwmod_ocp_if omap3_l4_core__sr1 = {
371 .master = &omap3xxx_l4_core_hwmod,
372 .slave = &omap34xx_sr1_hwmod,
373 .clk = "sr_l4_ick",
374 .addr = omap3_sr1_addr_space,
375 .user = OCP_USER_MPU,
376 };
377
378 /* L4 CORE -> SR1 interface */
379 static struct omap_hwmod_addr_space omap3_sr2_addr_space[] = {
380 {
381 .pa_start = OMAP34XX_SR2_BASE,
382 .pa_end = OMAP34XX_SR2_BASE + SZ_1K - 1,
383 .flags = ADDR_TYPE_RT,
384 },
385 { }
386 };
387
388 static struct omap_hwmod_ocp_if omap3_l4_core__sr2 = {
389 .master = &omap3xxx_l4_core_hwmod,
390 .slave = &omap34xx_sr2_hwmod,
391 .clk = "sr_l4_ick",
392 .addr = omap3_sr2_addr_space,
393 .user = OCP_USER_MPU,
394 };
395
396 /*
397 * usbhsotg interface data
398 */
399
400 static struct omap_hwmod_addr_space omap3xxx_usbhsotg_addrs[] = {
401 {
402 .pa_start = OMAP34XX_HSUSB_OTG_BASE,
403 .pa_end = OMAP34XX_HSUSB_OTG_BASE + SZ_4K - 1,
404 .flags = ADDR_TYPE_RT
405 },
406 { }
407 };
408
409 /* l4_core -> usbhsotg */
410 static struct omap_hwmod_ocp_if omap3xxx_l4_core__usbhsotg = {
411 .master = &omap3xxx_l4_core_hwmod,
412 .slave = &omap3xxx_usbhsotg_hwmod,
413 .clk = "l4_ick",
414 .addr = omap3xxx_usbhsotg_addrs,
415 .user = OCP_USER_MPU,
416 };
417
418 static struct omap_hwmod_ocp_if *omap3xxx_usbhsotg_masters[] = {
419 &omap3xxx_usbhsotg__l3,
420 };
421
422 static struct omap_hwmod_ocp_if *omap3xxx_usbhsotg_slaves[] = {
423 &omap3xxx_l4_core__usbhsotg,
424 };
425
426 static struct omap_hwmod_addr_space am35xx_usbhsotg_addrs[] = {
427 {
428 .pa_start = AM35XX_IPSS_USBOTGSS_BASE,
429 .pa_end = AM35XX_IPSS_USBOTGSS_BASE + SZ_4K - 1,
430 .flags = ADDR_TYPE_RT
431 },
432 { }
433 };
434
435 /* l4_core -> usbhsotg */
436 static struct omap_hwmod_ocp_if am35xx_l4_core__usbhsotg = {
437 .master = &omap3xxx_l4_core_hwmod,
438 .slave = &am35xx_usbhsotg_hwmod,
439 .clk = "l4_ick",
440 .addr = am35xx_usbhsotg_addrs,
441 .user = OCP_USER_MPU,
442 };
443
444 static struct omap_hwmod_ocp_if *am35xx_usbhsotg_masters[] = {
445 &am35xx_usbhsotg__l3,
446 };
447
448 static struct omap_hwmod_ocp_if *am35xx_usbhsotg_slaves[] = {
449 &am35xx_l4_core__usbhsotg,
450 };
451 /* Slave interfaces on the L4_CORE interconnect */
452 static struct omap_hwmod_ocp_if *omap3xxx_l4_core_slaves[] = {
453 &omap3xxx_l3_main__l4_core,
454 };
455
456 /* L4 CORE */
457 static struct omap_hwmod omap3xxx_l4_core_hwmod = {
458 .name = "l4_core",
459 .class = &l4_hwmod_class,
460 .slaves = omap3xxx_l4_core_slaves,
461 .slaves_cnt = ARRAY_SIZE(omap3xxx_l4_core_slaves),
462 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
463 .flags = HWMOD_NO_IDLEST,
464 };
465
466 /* Slave interfaces on the L4_PER interconnect */
467 static struct omap_hwmod_ocp_if *omap3xxx_l4_per_slaves[] = {
468 &omap3xxx_l3_main__l4_per,
469 };
470
471 /* L4 PER */
472 static struct omap_hwmod omap3xxx_l4_per_hwmod = {
473 .name = "l4_per",
474 .class = &l4_hwmod_class,
475 .slaves = omap3xxx_l4_per_slaves,
476 .slaves_cnt = ARRAY_SIZE(omap3xxx_l4_per_slaves),
477 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
478 .flags = HWMOD_NO_IDLEST,
479 };
480
481 /* Slave interfaces on the L4_WKUP interconnect */
482 static struct omap_hwmod_ocp_if *omap3xxx_l4_wkup_slaves[] = {
483 &omap3xxx_l4_core__l4_wkup,
484 };
485
486 /* L4 WKUP */
487 static struct omap_hwmod omap3xxx_l4_wkup_hwmod = {
488 .name = "l4_wkup",
489 .class = &l4_hwmod_class,
490 .slaves = omap3xxx_l4_wkup_slaves,
491 .slaves_cnt = ARRAY_SIZE(omap3xxx_l4_wkup_slaves),
492 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
493 .flags = HWMOD_NO_IDLEST,
494 };
495
496 /* Master interfaces on the MPU device */
497 static struct omap_hwmod_ocp_if *omap3xxx_mpu_masters[] = {
498 &omap3xxx_mpu__l3_main,
499 };
500
501 /* MPU */
502 static struct omap_hwmod omap3xxx_mpu_hwmod = {
503 .name = "mpu",
504 .class = &mpu_hwmod_class,
505 .main_clk = "arm_fck",
506 .masters = omap3xxx_mpu_masters,
507 .masters_cnt = ARRAY_SIZE(omap3xxx_mpu_masters),
508 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
509 };
510
511 /*
512 * IVA2_2 interface data
513 */
514
515 /* IVA2 <- L3 interface */
516 static struct omap_hwmod_ocp_if omap3xxx_l3__iva = {
517 .master = &omap3xxx_l3_main_hwmod,
518 .slave = &omap3xxx_iva_hwmod,
519 .clk = "iva2_ck",
520 .user = OCP_USER_MPU | OCP_USER_SDMA,
521 };
522
523 static struct omap_hwmod_ocp_if *omap3xxx_iva_masters[] = {
524 &omap3xxx_l3__iva,
525 };
526
527 /*
528 * IVA2 (IVA2)
529 */
530
531 static struct omap_hwmod omap3xxx_iva_hwmod = {
532 .name = "iva",
533 .class = &iva_hwmod_class,
534 .masters = omap3xxx_iva_masters,
535 .masters_cnt = ARRAY_SIZE(omap3xxx_iva_masters),
536 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
537 };
538
539 /* timer class */
540 static struct omap_hwmod_class_sysconfig omap3xxx_timer_1ms_sysc = {
541 .rev_offs = 0x0000,
542 .sysc_offs = 0x0010,
543 .syss_offs = 0x0014,
544 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_CLOCKACTIVITY |
545 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
546 SYSC_HAS_EMUFREE | SYSC_HAS_AUTOIDLE),
547 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
548 .sysc_fields = &omap_hwmod_sysc_type1,
549 };
550
551 static struct omap_hwmod_class omap3xxx_timer_1ms_hwmod_class = {
552 .name = "timer",
553 .sysc = &omap3xxx_timer_1ms_sysc,
554 .rev = OMAP_TIMER_IP_VERSION_1,
555 };
556
557 static struct omap_hwmod_class_sysconfig omap3xxx_timer_sysc = {
558 .rev_offs = 0x0000,
559 .sysc_offs = 0x0010,
560 .syss_offs = 0x0014,
561 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_ENAWAKEUP |
562 SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
563 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
564 .sysc_fields = &omap_hwmod_sysc_type1,
565 };
566
567 static struct omap_hwmod_class omap3xxx_timer_hwmod_class = {
568 .name = "timer",
569 .sysc = &omap3xxx_timer_sysc,
570 .rev = OMAP_TIMER_IP_VERSION_1,
571 };
572
573 /* timer1 */
574 static struct omap_hwmod omap3xxx_timer1_hwmod;
575
576 static struct omap_hwmod_addr_space omap3xxx_timer1_addrs[] = {
577 {
578 .pa_start = 0x48318000,
579 .pa_end = 0x48318000 + SZ_1K - 1,
580 .flags = ADDR_TYPE_RT
581 },
582 { }
583 };
584
585 /* l4_wkup -> timer1 */
586 static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__timer1 = {
587 .master = &omap3xxx_l4_wkup_hwmod,
588 .slave = &omap3xxx_timer1_hwmod,
589 .clk = "gpt1_ick",
590 .addr = omap3xxx_timer1_addrs,
591 .user = OCP_USER_MPU | OCP_USER_SDMA,
592 };
593
594 /* timer1 slave port */
595 static struct omap_hwmod_ocp_if *omap3xxx_timer1_slaves[] = {
596 &omap3xxx_l4_wkup__timer1,
597 };
598
599 /* timer1 hwmod */
600 static struct omap_hwmod omap3xxx_timer1_hwmod = {
601 .name = "timer1",
602 .mpu_irqs = omap2_timer1_mpu_irqs,
603 .main_clk = "gpt1_fck",
604 .prcm = {
605 .omap2 = {
606 .prcm_reg_id = 1,
607 .module_bit = OMAP3430_EN_GPT1_SHIFT,
608 .module_offs = WKUP_MOD,
609 .idlest_reg_id = 1,
610 .idlest_idle_bit = OMAP3430_ST_GPT1_SHIFT,
611 },
612 },
613 .slaves = omap3xxx_timer1_slaves,
614 .slaves_cnt = ARRAY_SIZE(omap3xxx_timer1_slaves),
615 .class = &omap3xxx_timer_1ms_hwmod_class,
616 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
617 };
618
619 /* timer2 */
620 static struct omap_hwmod omap3xxx_timer2_hwmod;
621
622 static struct omap_hwmod_addr_space omap3xxx_timer2_addrs[] = {
623 {
624 .pa_start = 0x49032000,
625 .pa_end = 0x49032000 + SZ_1K - 1,
626 .flags = ADDR_TYPE_RT
627 },
628 { }
629 };
630
631 /* l4_per -> timer2 */
632 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer2 = {
633 .master = &omap3xxx_l4_per_hwmod,
634 .slave = &omap3xxx_timer2_hwmod,
635 .clk = "gpt2_ick",
636 .addr = omap3xxx_timer2_addrs,
637 .user = OCP_USER_MPU | OCP_USER_SDMA,
638 };
639
640 /* timer2 slave port */
641 static struct omap_hwmod_ocp_if *omap3xxx_timer2_slaves[] = {
642 &omap3xxx_l4_per__timer2,
643 };
644
645 /* timer2 hwmod */
646 static struct omap_hwmod omap3xxx_timer2_hwmod = {
647 .name = "timer2",
648 .mpu_irqs = omap2_timer2_mpu_irqs,
649 .main_clk = "gpt2_fck",
650 .prcm = {
651 .omap2 = {
652 .prcm_reg_id = 1,
653 .module_bit = OMAP3430_EN_GPT2_SHIFT,
654 .module_offs = OMAP3430_PER_MOD,
655 .idlest_reg_id = 1,
656 .idlest_idle_bit = OMAP3430_ST_GPT2_SHIFT,
657 },
658 },
659 .slaves = omap3xxx_timer2_slaves,
660 .slaves_cnt = ARRAY_SIZE(omap3xxx_timer2_slaves),
661 .class = &omap3xxx_timer_1ms_hwmod_class,
662 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
663 };
664
665 /* timer3 */
666 static struct omap_hwmod omap3xxx_timer3_hwmod;
667
668 static struct omap_hwmod_addr_space omap3xxx_timer3_addrs[] = {
669 {
670 .pa_start = 0x49034000,
671 .pa_end = 0x49034000 + SZ_1K - 1,
672 .flags = ADDR_TYPE_RT
673 },
674 { }
675 };
676
677 /* l4_per -> timer3 */
678 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer3 = {
679 .master = &omap3xxx_l4_per_hwmod,
680 .slave = &omap3xxx_timer3_hwmod,
681 .clk = "gpt3_ick",
682 .addr = omap3xxx_timer3_addrs,
683 .user = OCP_USER_MPU | OCP_USER_SDMA,
684 };
685
686 /* timer3 slave port */
687 static struct omap_hwmod_ocp_if *omap3xxx_timer3_slaves[] = {
688 &omap3xxx_l4_per__timer3,
689 };
690
691 /* timer3 hwmod */
692 static struct omap_hwmod omap3xxx_timer3_hwmod = {
693 .name = "timer3",
694 .mpu_irqs = omap2_timer3_mpu_irqs,
695 .main_clk = "gpt3_fck",
696 .prcm = {
697 .omap2 = {
698 .prcm_reg_id = 1,
699 .module_bit = OMAP3430_EN_GPT3_SHIFT,
700 .module_offs = OMAP3430_PER_MOD,
701 .idlest_reg_id = 1,
702 .idlest_idle_bit = OMAP3430_ST_GPT3_SHIFT,
703 },
704 },
705 .slaves = omap3xxx_timer3_slaves,
706 .slaves_cnt = ARRAY_SIZE(omap3xxx_timer3_slaves),
707 .class = &omap3xxx_timer_hwmod_class,
708 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
709 };
710
711 /* timer4 */
712 static struct omap_hwmod omap3xxx_timer4_hwmod;
713
714 static struct omap_hwmod_addr_space omap3xxx_timer4_addrs[] = {
715 {
716 .pa_start = 0x49036000,
717 .pa_end = 0x49036000 + SZ_1K - 1,
718 .flags = ADDR_TYPE_RT
719 },
720 { }
721 };
722
723 /* l4_per -> timer4 */
724 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer4 = {
725 .master = &omap3xxx_l4_per_hwmod,
726 .slave = &omap3xxx_timer4_hwmod,
727 .clk = "gpt4_ick",
728 .addr = omap3xxx_timer4_addrs,
729 .user = OCP_USER_MPU | OCP_USER_SDMA,
730 };
731
732 /* timer4 slave port */
733 static struct omap_hwmod_ocp_if *omap3xxx_timer4_slaves[] = {
734 &omap3xxx_l4_per__timer4,
735 };
736
737 /* timer4 hwmod */
738 static struct omap_hwmod omap3xxx_timer4_hwmod = {
739 .name = "timer4",
740 .mpu_irqs = omap2_timer4_mpu_irqs,
741 .main_clk = "gpt4_fck",
742 .prcm = {
743 .omap2 = {
744 .prcm_reg_id = 1,
745 .module_bit = OMAP3430_EN_GPT4_SHIFT,
746 .module_offs = OMAP3430_PER_MOD,
747 .idlest_reg_id = 1,
748 .idlest_idle_bit = OMAP3430_ST_GPT4_SHIFT,
749 },
750 },
751 .slaves = omap3xxx_timer4_slaves,
752 .slaves_cnt = ARRAY_SIZE(omap3xxx_timer4_slaves),
753 .class = &omap3xxx_timer_hwmod_class,
754 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
755 };
756
757 /* timer5 */
758 static struct omap_hwmod omap3xxx_timer5_hwmod;
759
760 static struct omap_hwmod_addr_space omap3xxx_timer5_addrs[] = {
761 {
762 .pa_start = 0x49038000,
763 .pa_end = 0x49038000 + SZ_1K - 1,
764 .flags = ADDR_TYPE_RT
765 },
766 { }
767 };
768
769 /* l4_per -> timer5 */
770 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer5 = {
771 .master = &omap3xxx_l4_per_hwmod,
772 .slave = &omap3xxx_timer5_hwmod,
773 .clk = "gpt5_ick",
774 .addr = omap3xxx_timer5_addrs,
775 .user = OCP_USER_MPU | OCP_USER_SDMA,
776 };
777
778 /* timer5 slave port */
779 static struct omap_hwmod_ocp_if *omap3xxx_timer5_slaves[] = {
780 &omap3xxx_l4_per__timer5,
781 };
782
783 /* timer5 hwmod */
784 static struct omap_hwmod omap3xxx_timer5_hwmod = {
785 .name = "timer5",
786 .mpu_irqs = omap2_timer5_mpu_irqs,
787 .main_clk = "gpt5_fck",
788 .prcm = {
789 .omap2 = {
790 .prcm_reg_id = 1,
791 .module_bit = OMAP3430_EN_GPT5_SHIFT,
792 .module_offs = OMAP3430_PER_MOD,
793 .idlest_reg_id = 1,
794 .idlest_idle_bit = OMAP3430_ST_GPT5_SHIFT,
795 },
796 },
797 .slaves = omap3xxx_timer5_slaves,
798 .slaves_cnt = ARRAY_SIZE(omap3xxx_timer5_slaves),
799 .class = &omap3xxx_timer_hwmod_class,
800 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
801 };
802
803 /* timer6 */
804 static struct omap_hwmod omap3xxx_timer6_hwmod;
805
806 static struct omap_hwmod_addr_space omap3xxx_timer6_addrs[] = {
807 {
808 .pa_start = 0x4903A000,
809 .pa_end = 0x4903A000 + SZ_1K - 1,
810 .flags = ADDR_TYPE_RT
811 },
812 { }
813 };
814
815 /* l4_per -> timer6 */
816 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer6 = {
817 .master = &omap3xxx_l4_per_hwmod,
818 .slave = &omap3xxx_timer6_hwmod,
819 .clk = "gpt6_ick",
820 .addr = omap3xxx_timer6_addrs,
821 .user = OCP_USER_MPU | OCP_USER_SDMA,
822 };
823
824 /* timer6 slave port */
825 static struct omap_hwmod_ocp_if *omap3xxx_timer6_slaves[] = {
826 &omap3xxx_l4_per__timer6,
827 };
828
829 /* timer6 hwmod */
830 static struct omap_hwmod omap3xxx_timer6_hwmod = {
831 .name = "timer6",
832 .mpu_irqs = omap2_timer6_mpu_irqs,
833 .main_clk = "gpt6_fck",
834 .prcm = {
835 .omap2 = {
836 .prcm_reg_id = 1,
837 .module_bit = OMAP3430_EN_GPT6_SHIFT,
838 .module_offs = OMAP3430_PER_MOD,
839 .idlest_reg_id = 1,
840 .idlest_idle_bit = OMAP3430_ST_GPT6_SHIFT,
841 },
842 },
843 .slaves = omap3xxx_timer6_slaves,
844 .slaves_cnt = ARRAY_SIZE(omap3xxx_timer6_slaves),
845 .class = &omap3xxx_timer_hwmod_class,
846 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
847 };
848
849 /* timer7 */
850 static struct omap_hwmod omap3xxx_timer7_hwmod;
851
852 static struct omap_hwmod_addr_space omap3xxx_timer7_addrs[] = {
853 {
854 .pa_start = 0x4903C000,
855 .pa_end = 0x4903C000 + SZ_1K - 1,
856 .flags = ADDR_TYPE_RT
857 },
858 { }
859 };
860
861 /* l4_per -> timer7 */
862 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer7 = {
863 .master = &omap3xxx_l4_per_hwmod,
864 .slave = &omap3xxx_timer7_hwmod,
865 .clk = "gpt7_ick",
866 .addr = omap3xxx_timer7_addrs,
867 .user = OCP_USER_MPU | OCP_USER_SDMA,
868 };
869
870 /* timer7 slave port */
871 static struct omap_hwmod_ocp_if *omap3xxx_timer7_slaves[] = {
872 &omap3xxx_l4_per__timer7,
873 };
874
875 /* timer7 hwmod */
876 static struct omap_hwmod omap3xxx_timer7_hwmod = {
877 .name = "timer7",
878 .mpu_irqs = omap2_timer7_mpu_irqs,
879 .main_clk = "gpt7_fck",
880 .prcm = {
881 .omap2 = {
882 .prcm_reg_id = 1,
883 .module_bit = OMAP3430_EN_GPT7_SHIFT,
884 .module_offs = OMAP3430_PER_MOD,
885 .idlest_reg_id = 1,
886 .idlest_idle_bit = OMAP3430_ST_GPT7_SHIFT,
887 },
888 },
889 .slaves = omap3xxx_timer7_slaves,
890 .slaves_cnt = ARRAY_SIZE(omap3xxx_timer7_slaves),
891 .class = &omap3xxx_timer_hwmod_class,
892 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
893 };
894
895 /* timer8 */
896 static struct omap_hwmod omap3xxx_timer8_hwmod;
897
898 static struct omap_hwmod_addr_space omap3xxx_timer8_addrs[] = {
899 {
900 .pa_start = 0x4903E000,
901 .pa_end = 0x4903E000 + SZ_1K - 1,
902 .flags = ADDR_TYPE_RT
903 },
904 { }
905 };
906
907 /* l4_per -> timer8 */
908 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer8 = {
909 .master = &omap3xxx_l4_per_hwmod,
910 .slave = &omap3xxx_timer8_hwmod,
911 .clk = "gpt8_ick",
912 .addr = omap3xxx_timer8_addrs,
913 .user = OCP_USER_MPU | OCP_USER_SDMA,
914 };
915
916 /* timer8 slave port */
917 static struct omap_hwmod_ocp_if *omap3xxx_timer8_slaves[] = {
918 &omap3xxx_l4_per__timer8,
919 };
920
921 /* timer8 hwmod */
922 static struct omap_hwmod omap3xxx_timer8_hwmod = {
923 .name = "timer8",
924 .mpu_irqs = omap2_timer8_mpu_irqs,
925 .main_clk = "gpt8_fck",
926 .prcm = {
927 .omap2 = {
928 .prcm_reg_id = 1,
929 .module_bit = OMAP3430_EN_GPT8_SHIFT,
930 .module_offs = OMAP3430_PER_MOD,
931 .idlest_reg_id = 1,
932 .idlest_idle_bit = OMAP3430_ST_GPT8_SHIFT,
933 },
934 },
935 .slaves = omap3xxx_timer8_slaves,
936 .slaves_cnt = ARRAY_SIZE(omap3xxx_timer8_slaves),
937 .class = &omap3xxx_timer_hwmod_class,
938 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
939 };
940
941 /* timer9 */
942 static struct omap_hwmod omap3xxx_timer9_hwmod;
943
944 static struct omap_hwmod_addr_space omap3xxx_timer9_addrs[] = {
945 {
946 .pa_start = 0x49040000,
947 .pa_end = 0x49040000 + SZ_1K - 1,
948 .flags = ADDR_TYPE_RT
949 },
950 { }
951 };
952
953 /* l4_per -> timer9 */
954 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer9 = {
955 .master = &omap3xxx_l4_per_hwmod,
956 .slave = &omap3xxx_timer9_hwmod,
957 .clk = "gpt9_ick",
958 .addr = omap3xxx_timer9_addrs,
959 .user = OCP_USER_MPU | OCP_USER_SDMA,
960 };
961
962 /* timer9 slave port */
963 static struct omap_hwmod_ocp_if *omap3xxx_timer9_slaves[] = {
964 &omap3xxx_l4_per__timer9,
965 };
966
967 /* timer9 hwmod */
968 static struct omap_hwmod omap3xxx_timer9_hwmod = {
969 .name = "timer9",
970 .mpu_irqs = omap2_timer9_mpu_irqs,
971 .main_clk = "gpt9_fck",
972 .prcm = {
973 .omap2 = {
974 .prcm_reg_id = 1,
975 .module_bit = OMAP3430_EN_GPT9_SHIFT,
976 .module_offs = OMAP3430_PER_MOD,
977 .idlest_reg_id = 1,
978 .idlest_idle_bit = OMAP3430_ST_GPT9_SHIFT,
979 },
980 },
981 .slaves = omap3xxx_timer9_slaves,
982 .slaves_cnt = ARRAY_SIZE(omap3xxx_timer9_slaves),
983 .class = &omap3xxx_timer_hwmod_class,
984 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
985 };
986
987 /* timer10 */
988 static struct omap_hwmod omap3xxx_timer10_hwmod;
989
990 /* l4_core -> timer10 */
991 static struct omap_hwmod_ocp_if omap3xxx_l4_core__timer10 = {
992 .master = &omap3xxx_l4_core_hwmod,
993 .slave = &omap3xxx_timer10_hwmod,
994 .clk = "gpt10_ick",
995 .addr = omap2_timer10_addrs,
996 .user = OCP_USER_MPU | OCP_USER_SDMA,
997 };
998
999 /* timer10 slave port */
1000 static struct omap_hwmod_ocp_if *omap3xxx_timer10_slaves[] = {
1001 &omap3xxx_l4_core__timer10,
1002 };
1003
1004 /* timer10 hwmod */
1005 static struct omap_hwmod omap3xxx_timer10_hwmod = {
1006 .name = "timer10",
1007 .mpu_irqs = omap2_timer10_mpu_irqs,
1008 .main_clk = "gpt10_fck",
1009 .prcm = {
1010 .omap2 = {
1011 .prcm_reg_id = 1,
1012 .module_bit = OMAP3430_EN_GPT10_SHIFT,
1013 .module_offs = CORE_MOD,
1014 .idlest_reg_id = 1,
1015 .idlest_idle_bit = OMAP3430_ST_GPT10_SHIFT,
1016 },
1017 },
1018 .slaves = omap3xxx_timer10_slaves,
1019 .slaves_cnt = ARRAY_SIZE(omap3xxx_timer10_slaves),
1020 .class = &omap3xxx_timer_1ms_hwmod_class,
1021 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
1022 };
1023
1024 /* timer11 */
1025 static struct omap_hwmod omap3xxx_timer11_hwmod;
1026
1027 /* l4_core -> timer11 */
1028 static struct omap_hwmod_ocp_if omap3xxx_l4_core__timer11 = {
1029 .master = &omap3xxx_l4_core_hwmod,
1030 .slave = &omap3xxx_timer11_hwmod,
1031 .clk = "gpt11_ick",
1032 .addr = omap2_timer11_addrs,
1033 .user = OCP_USER_MPU | OCP_USER_SDMA,
1034 };
1035
1036 /* timer11 slave port */
1037 static struct omap_hwmod_ocp_if *omap3xxx_timer11_slaves[] = {
1038 &omap3xxx_l4_core__timer11,
1039 };
1040
1041 /* timer11 hwmod */
1042 static struct omap_hwmod omap3xxx_timer11_hwmod = {
1043 .name = "timer11",
1044 .mpu_irqs = omap2_timer11_mpu_irqs,
1045 .main_clk = "gpt11_fck",
1046 .prcm = {
1047 .omap2 = {
1048 .prcm_reg_id = 1,
1049 .module_bit = OMAP3430_EN_GPT11_SHIFT,
1050 .module_offs = CORE_MOD,
1051 .idlest_reg_id = 1,
1052 .idlest_idle_bit = OMAP3430_ST_GPT11_SHIFT,
1053 },
1054 },
1055 .slaves = omap3xxx_timer11_slaves,
1056 .slaves_cnt = ARRAY_SIZE(omap3xxx_timer11_slaves),
1057 .class = &omap3xxx_timer_hwmod_class,
1058 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
1059 };
1060
1061 /* timer12*/
1062 static struct omap_hwmod omap3xxx_timer12_hwmod;
1063 static struct omap_hwmod_irq_info omap3xxx_timer12_mpu_irqs[] = {
1064 { .irq = 95, },
1065 { .irq = -1 }
1066 };
1067
1068 static struct omap_hwmod_addr_space omap3xxx_timer12_addrs[] = {
1069 {
1070 .pa_start = 0x48304000,
1071 .pa_end = 0x48304000 + SZ_1K - 1,
1072 .flags = ADDR_TYPE_RT
1073 },
1074 { }
1075 };
1076
1077 /* l4_core -> timer12 */
1078 static struct omap_hwmod_ocp_if omap3xxx_l4_core__timer12 = {
1079 .master = &omap3xxx_l4_core_hwmod,
1080 .slave = &omap3xxx_timer12_hwmod,
1081 .clk = "gpt12_ick",
1082 .addr = omap3xxx_timer12_addrs,
1083 .user = OCP_USER_MPU | OCP_USER_SDMA,
1084 };
1085
1086 /* timer12 slave port */
1087 static struct omap_hwmod_ocp_if *omap3xxx_timer12_slaves[] = {
1088 &omap3xxx_l4_core__timer12,
1089 };
1090
1091 /* timer12 hwmod */
1092 static struct omap_hwmod omap3xxx_timer12_hwmod = {
1093 .name = "timer12",
1094 .mpu_irqs = omap3xxx_timer12_mpu_irqs,
1095 .main_clk = "gpt12_fck",
1096 .prcm = {
1097 .omap2 = {
1098 .prcm_reg_id = 1,
1099 .module_bit = OMAP3430_EN_GPT12_SHIFT,
1100 .module_offs = WKUP_MOD,
1101 .idlest_reg_id = 1,
1102 .idlest_idle_bit = OMAP3430_ST_GPT12_SHIFT,
1103 },
1104 },
1105 .slaves = omap3xxx_timer12_slaves,
1106 .slaves_cnt = ARRAY_SIZE(omap3xxx_timer12_slaves),
1107 .class = &omap3xxx_timer_hwmod_class,
1108 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
1109 };
1110
1111 /* l4_wkup -> wd_timer2 */
1112 static struct omap_hwmod_addr_space omap3xxx_wd_timer2_addrs[] = {
1113 {
1114 .pa_start = 0x48314000,
1115 .pa_end = 0x4831407f,
1116 .flags = ADDR_TYPE_RT
1117 },
1118 { }
1119 };
1120
1121 static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__wd_timer2 = {
1122 .master = &omap3xxx_l4_wkup_hwmod,
1123 .slave = &omap3xxx_wd_timer2_hwmod,
1124 .clk = "wdt2_ick",
1125 .addr = omap3xxx_wd_timer2_addrs,
1126 .user = OCP_USER_MPU | OCP_USER_SDMA,
1127 };
1128
1129 /*
1130 * 'wd_timer' class
1131 * 32-bit watchdog upward counter that generates a pulse on the reset pin on
1132 * overflow condition
1133 */
1134
1135 static struct omap_hwmod_class_sysconfig omap3xxx_wd_timer_sysc = {
1136 .rev_offs = 0x0000,
1137 .sysc_offs = 0x0010,
1138 .syss_offs = 0x0014,
1139 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_EMUFREE |
1140 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
1141 SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
1142 SYSS_HAS_RESET_STATUS),
1143 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1144 .sysc_fields = &omap_hwmod_sysc_type1,
1145 };
1146
1147 /* I2C common */
1148 static struct omap_hwmod_class_sysconfig i2c_sysc = {
1149 .rev_offs = 0x00,
1150 .sysc_offs = 0x20,
1151 .syss_offs = 0x10,
1152 .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
1153 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
1154 SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
1155 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1156 .sysc_fields = &omap_hwmod_sysc_type1,
1157 };
1158
1159 static struct omap_hwmod_class omap3xxx_wd_timer_hwmod_class = {
1160 .name = "wd_timer",
1161 .sysc = &omap3xxx_wd_timer_sysc,
1162 .pre_shutdown = &omap2_wd_timer_disable
1163 };
1164
1165 /* wd_timer2 */
1166 static struct omap_hwmod_ocp_if *omap3xxx_wd_timer2_slaves[] = {
1167 &omap3xxx_l4_wkup__wd_timer2,
1168 };
1169
1170 static struct omap_hwmod omap3xxx_wd_timer2_hwmod = {
1171 .name = "wd_timer2",
1172 .class = &omap3xxx_wd_timer_hwmod_class,
1173 .main_clk = "wdt2_fck",
1174 .prcm = {
1175 .omap2 = {
1176 .prcm_reg_id = 1,
1177 .module_bit = OMAP3430_EN_WDT2_SHIFT,
1178 .module_offs = WKUP_MOD,
1179 .idlest_reg_id = 1,
1180 .idlest_idle_bit = OMAP3430_ST_WDT2_SHIFT,
1181 },
1182 },
1183 .slaves = omap3xxx_wd_timer2_slaves,
1184 .slaves_cnt = ARRAY_SIZE(omap3xxx_wd_timer2_slaves),
1185 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
1186 /*
1187 * XXX: Use software supervised mode, HW supervised smartidle seems to
1188 * block CORE power domain idle transitions. Maybe a HW bug in wdt2?
1189 */
1190 .flags = HWMOD_SWSUP_SIDLE,
1191 };
1192
1193 /* UART1 */
1194
1195 static struct omap_hwmod_ocp_if *omap3xxx_uart1_slaves[] = {
1196 &omap3_l4_core__uart1,
1197 };
1198
1199 static struct omap_hwmod omap3xxx_uart1_hwmod = {
1200 .name = "uart1",
1201 .mpu_irqs = omap2_uart1_mpu_irqs,
1202 .sdma_reqs = omap2_uart1_sdma_reqs,
1203 .main_clk = "uart1_fck",
1204 .prcm = {
1205 .omap2 = {
1206 .module_offs = CORE_MOD,
1207 .prcm_reg_id = 1,
1208 .module_bit = OMAP3430_EN_UART1_SHIFT,
1209 .idlest_reg_id = 1,
1210 .idlest_idle_bit = OMAP3430_EN_UART1_SHIFT,
1211 },
1212 },
1213 .slaves = omap3xxx_uart1_slaves,
1214 .slaves_cnt = ARRAY_SIZE(omap3xxx_uart1_slaves),
1215 .class = &omap2_uart_class,
1216 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
1217 };
1218
1219 /* UART2 */
1220
1221 static struct omap_hwmod_ocp_if *omap3xxx_uart2_slaves[] = {
1222 &omap3_l4_core__uart2,
1223 };
1224
1225 static struct omap_hwmod omap3xxx_uart2_hwmod = {
1226 .name = "uart2",
1227 .mpu_irqs = omap2_uart2_mpu_irqs,
1228 .sdma_reqs = omap2_uart2_sdma_reqs,
1229 .main_clk = "uart2_fck",
1230 .prcm = {
1231 .omap2 = {
1232 .module_offs = CORE_MOD,
1233 .prcm_reg_id = 1,
1234 .module_bit = OMAP3430_EN_UART2_SHIFT,
1235 .idlest_reg_id = 1,
1236 .idlest_idle_bit = OMAP3430_EN_UART2_SHIFT,
1237 },
1238 },
1239 .slaves = omap3xxx_uart2_slaves,
1240 .slaves_cnt = ARRAY_SIZE(omap3xxx_uart2_slaves),
1241 .class = &omap2_uart_class,
1242 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
1243 };
1244
1245 /* UART3 */
1246
1247 static struct omap_hwmod_ocp_if *omap3xxx_uart3_slaves[] = {
1248 &omap3_l4_per__uart3,
1249 };
1250
1251 static struct omap_hwmod omap3xxx_uart3_hwmod = {
1252 .name = "uart3",
1253 .mpu_irqs = omap2_uart3_mpu_irqs,
1254 .sdma_reqs = omap2_uart3_sdma_reqs,
1255 .main_clk = "uart3_fck",
1256 .prcm = {
1257 .omap2 = {
1258 .module_offs = OMAP3430_PER_MOD,
1259 .prcm_reg_id = 1,
1260 .module_bit = OMAP3430_EN_UART3_SHIFT,
1261 .idlest_reg_id = 1,
1262 .idlest_idle_bit = OMAP3430_EN_UART3_SHIFT,
1263 },
1264 },
1265 .slaves = omap3xxx_uart3_slaves,
1266 .slaves_cnt = ARRAY_SIZE(omap3xxx_uart3_slaves),
1267 .class = &omap2_uart_class,
1268 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
1269 };
1270
1271 /* UART4 */
1272
1273 static struct omap_hwmod_irq_info uart4_mpu_irqs[] = {
1274 { .irq = INT_36XX_UART4_IRQ, },
1275 { .irq = -1 }
1276 };
1277
1278 static struct omap_hwmod_dma_info uart4_sdma_reqs[] = {
1279 { .name = "rx", .dma_req = OMAP36XX_DMA_UART4_RX, },
1280 { .name = "tx", .dma_req = OMAP36XX_DMA_UART4_TX, },
1281 { .dma_req = -1 }
1282 };
1283
1284 static struct omap_hwmod_ocp_if *omap3xxx_uart4_slaves[] = {
1285 &omap3_l4_per__uart4,
1286 };
1287
1288 static struct omap_hwmod omap3xxx_uart4_hwmod = {
1289 .name = "uart4",
1290 .mpu_irqs = uart4_mpu_irqs,
1291 .sdma_reqs = uart4_sdma_reqs,
1292 .main_clk = "uart4_fck",
1293 .prcm = {
1294 .omap2 = {
1295 .module_offs = OMAP3430_PER_MOD,
1296 .prcm_reg_id = 1,
1297 .module_bit = OMAP3630_EN_UART4_SHIFT,
1298 .idlest_reg_id = 1,
1299 .idlest_idle_bit = OMAP3630_EN_UART4_SHIFT,
1300 },
1301 },
1302 .slaves = omap3xxx_uart4_slaves,
1303 .slaves_cnt = ARRAY_SIZE(omap3xxx_uart4_slaves),
1304 .class = &omap2_uart_class,
1305 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3630ES1),
1306 };
1307
1308 static struct omap_hwmod_class i2c_class = {
1309 .name = "i2c",
1310 .sysc = &i2c_sysc,
1311 .rev = OMAP_I2C_IP_VERSION_1,
1312 .reset = &omap_i2c_reset,
1313 };
1314
1315 static struct omap_hwmod_dma_info omap3xxx_dss_sdma_chs[] = {
1316 { .name = "dispc", .dma_req = 5 },
1317 { .name = "dsi1", .dma_req = 74 },
1318 { .dma_req = -1 }
1319 };
1320
1321 /* dss */
1322 /* dss master ports */
1323 static struct omap_hwmod_ocp_if *omap3xxx_dss_masters[] = {
1324 &omap3xxx_dss__l3,
1325 };
1326
1327 /* l4_core -> dss */
1328 static struct omap_hwmod_ocp_if omap3430es1_l4_core__dss = {
1329 .master = &omap3xxx_l4_core_hwmod,
1330 .slave = &omap3430es1_dss_core_hwmod,
1331 .clk = "dss_ick",
1332 .addr = omap2_dss_addrs,
1333 .fw = {
1334 .omap2 = {
1335 .l4_fw_region = OMAP3ES1_L4_CORE_FW_DSS_CORE_REGION,
1336 .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP,
1337 .flags = OMAP_FIREWALL_L4,
1338 }
1339 },
1340 .user = OCP_USER_MPU | OCP_USER_SDMA,
1341 };
1342
1343 static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss = {
1344 .master = &omap3xxx_l4_core_hwmod,
1345 .slave = &omap3xxx_dss_core_hwmod,
1346 .clk = "dss_ick",
1347 .addr = omap2_dss_addrs,
1348 .fw = {
1349 .omap2 = {
1350 .l4_fw_region = OMAP3_L4_CORE_FW_DSS_CORE_REGION,
1351 .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP,
1352 .flags = OMAP_FIREWALL_L4,
1353 }
1354 },
1355 .user = OCP_USER_MPU | OCP_USER_SDMA,
1356 };
1357
1358 /* dss slave ports */
1359 static struct omap_hwmod_ocp_if *omap3430es1_dss_slaves[] = {
1360 &omap3430es1_l4_core__dss,
1361 };
1362
1363 static struct omap_hwmod_ocp_if *omap3xxx_dss_slaves[] = {
1364 &omap3xxx_l4_core__dss,
1365 };
1366
1367 static struct omap_hwmod_opt_clk dss_opt_clks[] = {
1368 { .role = "tv_clk", .clk = "dss_tv_fck" },
1369 { .role = "video_clk", .clk = "dss_96m_fck" },
1370 { .role = "sys_clk", .clk = "dss2_alwon_fck" },
1371 };
1372
1373 static struct omap_hwmod omap3430es1_dss_core_hwmod = {
1374 .name = "dss_core",
1375 .class = &omap2_dss_hwmod_class,
1376 .main_clk = "dss1_alwon_fck", /* instead of dss_fck */
1377 .sdma_reqs = omap3xxx_dss_sdma_chs,
1378 .prcm = {
1379 .omap2 = {
1380 .prcm_reg_id = 1,
1381 .module_bit = OMAP3430_EN_DSS1_SHIFT,
1382 .module_offs = OMAP3430_DSS_MOD,
1383 .idlest_reg_id = 1,
1384 .idlest_stdby_bit = OMAP3430ES1_ST_DSS_SHIFT,
1385 },
1386 },
1387 .opt_clks = dss_opt_clks,
1388 .opt_clks_cnt = ARRAY_SIZE(dss_opt_clks),
1389 .slaves = omap3430es1_dss_slaves,
1390 .slaves_cnt = ARRAY_SIZE(omap3430es1_dss_slaves),
1391 .masters = omap3xxx_dss_masters,
1392 .masters_cnt = ARRAY_SIZE(omap3xxx_dss_masters),
1393 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES1),
1394 .flags = HWMOD_NO_IDLEST,
1395 };
1396
1397 static struct omap_hwmod omap3xxx_dss_core_hwmod = {
1398 .name = "dss_core",
1399 .class = &omap2_dss_hwmod_class,
1400 .main_clk = "dss1_alwon_fck", /* instead of dss_fck */
1401 .sdma_reqs = omap3xxx_dss_sdma_chs,
1402 .prcm = {
1403 .omap2 = {
1404 .prcm_reg_id = 1,
1405 .module_bit = OMAP3430_EN_DSS1_SHIFT,
1406 .module_offs = OMAP3430_DSS_MOD,
1407 .idlest_reg_id = 1,
1408 .idlest_idle_bit = OMAP3430ES2_ST_DSS_IDLE_SHIFT,
1409 .idlest_stdby_bit = OMAP3430ES2_ST_DSS_STDBY_SHIFT,
1410 },
1411 },
1412 .opt_clks = dss_opt_clks,
1413 .opt_clks_cnt = ARRAY_SIZE(dss_opt_clks),
1414 .slaves = omap3xxx_dss_slaves,
1415 .slaves_cnt = ARRAY_SIZE(omap3xxx_dss_slaves),
1416 .masters = omap3xxx_dss_masters,
1417 .masters_cnt = ARRAY_SIZE(omap3xxx_dss_masters),
1418 .omap_chip = OMAP_CHIP_INIT(CHIP_GE_OMAP3430ES2 |
1419 CHIP_IS_OMAP3630ES1 | CHIP_GE_OMAP3630ES1_1),
1420 };
1421
1422 /* l4_core -> dss_dispc */
1423 static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_dispc = {
1424 .master = &omap3xxx_l4_core_hwmod,
1425 .slave = &omap3xxx_dss_dispc_hwmod,
1426 .clk = "dss_ick",
1427 .addr = omap2_dss_dispc_addrs,
1428 .fw = {
1429 .omap2 = {
1430 .l4_fw_region = OMAP3_L4_CORE_FW_DSS_DISPC_REGION,
1431 .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP,
1432 .flags = OMAP_FIREWALL_L4,
1433 }
1434 },
1435 .user = OCP_USER_MPU | OCP_USER_SDMA,
1436 };
1437
1438 /* dss_dispc slave ports */
1439 static struct omap_hwmod_ocp_if *omap3xxx_dss_dispc_slaves[] = {
1440 &omap3xxx_l4_core__dss_dispc,
1441 };
1442
1443 static struct omap_hwmod omap3xxx_dss_dispc_hwmod = {
1444 .name = "dss_dispc",
1445 .class = &omap2_dispc_hwmod_class,
1446 .mpu_irqs = omap2_dispc_irqs,
1447 .main_clk = "dss1_alwon_fck",
1448 .prcm = {
1449 .omap2 = {
1450 .prcm_reg_id = 1,
1451 .module_bit = OMAP3430_EN_DSS1_SHIFT,
1452 .module_offs = OMAP3430_DSS_MOD,
1453 },
1454 },
1455 .slaves = omap3xxx_dss_dispc_slaves,
1456 .slaves_cnt = ARRAY_SIZE(omap3xxx_dss_dispc_slaves),
1457 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES1 |
1458 CHIP_GE_OMAP3430ES2 | CHIP_IS_OMAP3630ES1 |
1459 CHIP_GE_OMAP3630ES1_1),
1460 .flags = HWMOD_NO_IDLEST,
1461 };
1462
1463 /*
1464 * 'dsi' class
1465 * display serial interface controller
1466 */
1467
1468 static struct omap_hwmod_class omap3xxx_dsi_hwmod_class = {
1469 .name = "dsi",
1470 };
1471
1472 static struct omap_hwmod_irq_info omap3xxx_dsi1_irqs[] = {
1473 { .irq = 25 },
1474 { .irq = -1 }
1475 };
1476
1477 /* dss_dsi1 */
1478 static struct omap_hwmod_addr_space omap3xxx_dss_dsi1_addrs[] = {
1479 {
1480 .pa_start = 0x4804FC00,
1481 .pa_end = 0x4804FFFF,
1482 .flags = ADDR_TYPE_RT
1483 },
1484 { }
1485 };
1486
1487 /* l4_core -> dss_dsi1 */
1488 static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_dsi1 = {
1489 .master = &omap3xxx_l4_core_hwmod,
1490 .slave = &omap3xxx_dss_dsi1_hwmod,
1491 .addr = omap3xxx_dss_dsi1_addrs,
1492 .fw = {
1493 .omap2 = {
1494 .l4_fw_region = OMAP3_L4_CORE_FW_DSS_DSI_REGION,
1495 .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP,
1496 .flags = OMAP_FIREWALL_L4,
1497 }
1498 },
1499 .user = OCP_USER_MPU | OCP_USER_SDMA,
1500 };
1501
1502 /* dss_dsi1 slave ports */
1503 static struct omap_hwmod_ocp_if *omap3xxx_dss_dsi1_slaves[] = {
1504 &omap3xxx_l4_core__dss_dsi1,
1505 };
1506
1507 static struct omap_hwmod omap3xxx_dss_dsi1_hwmod = {
1508 .name = "dss_dsi1",
1509 .class = &omap3xxx_dsi_hwmod_class,
1510 .mpu_irqs = omap3xxx_dsi1_irqs,
1511 .main_clk = "dss1_alwon_fck",
1512 .prcm = {
1513 .omap2 = {
1514 .prcm_reg_id = 1,
1515 .module_bit = OMAP3430_EN_DSS1_SHIFT,
1516 .module_offs = OMAP3430_DSS_MOD,
1517 },
1518 },
1519 .slaves = omap3xxx_dss_dsi1_slaves,
1520 .slaves_cnt = ARRAY_SIZE(omap3xxx_dss_dsi1_slaves),
1521 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES1 |
1522 CHIP_GE_OMAP3430ES2 | CHIP_IS_OMAP3630ES1 |
1523 CHIP_GE_OMAP3630ES1_1),
1524 .flags = HWMOD_NO_IDLEST,
1525 };
1526
1527 /* l4_core -> dss_rfbi */
1528 static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_rfbi = {
1529 .master = &omap3xxx_l4_core_hwmod,
1530 .slave = &omap3xxx_dss_rfbi_hwmod,
1531 .clk = "dss_ick",
1532 .addr = omap2_dss_rfbi_addrs,
1533 .fw = {
1534 .omap2 = {
1535 .l4_fw_region = OMAP3_L4_CORE_FW_DSS_RFBI_REGION,
1536 .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP ,
1537 .flags = OMAP_FIREWALL_L4,
1538 }
1539 },
1540 .user = OCP_USER_MPU | OCP_USER_SDMA,
1541 };
1542
1543 /* dss_rfbi slave ports */
1544 static struct omap_hwmod_ocp_if *omap3xxx_dss_rfbi_slaves[] = {
1545 &omap3xxx_l4_core__dss_rfbi,
1546 };
1547
1548 static struct omap_hwmod omap3xxx_dss_rfbi_hwmod = {
1549 .name = "dss_rfbi",
1550 .class = &omap2_rfbi_hwmod_class,
1551 .main_clk = "dss1_alwon_fck",
1552 .prcm = {
1553 .omap2 = {
1554 .prcm_reg_id = 1,
1555 .module_bit = OMAP3430_EN_DSS1_SHIFT,
1556 .module_offs = OMAP3430_DSS_MOD,
1557 },
1558 },
1559 .slaves = omap3xxx_dss_rfbi_slaves,
1560 .slaves_cnt = ARRAY_SIZE(omap3xxx_dss_rfbi_slaves),
1561 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES1 |
1562 CHIP_GE_OMAP3430ES2 | CHIP_IS_OMAP3630ES1 |
1563 CHIP_GE_OMAP3630ES1_1),
1564 .flags = HWMOD_NO_IDLEST,
1565 };
1566
1567 /* l4_core -> dss_venc */
1568 static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_venc = {
1569 .master = &omap3xxx_l4_core_hwmod,
1570 .slave = &omap3xxx_dss_venc_hwmod,
1571 .clk = "dss_tv_fck",
1572 .addr = omap2_dss_venc_addrs,
1573 .fw = {
1574 .omap2 = {
1575 .l4_fw_region = OMAP3_L4_CORE_FW_DSS_VENC_REGION,
1576 .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP,
1577 .flags = OMAP_FIREWALL_L4,
1578 }
1579 },
1580 .flags = OCPIF_SWSUP_IDLE,
1581 .user = OCP_USER_MPU | OCP_USER_SDMA,
1582 };
1583
1584 /* dss_venc slave ports */
1585 static struct omap_hwmod_ocp_if *omap3xxx_dss_venc_slaves[] = {
1586 &omap3xxx_l4_core__dss_venc,
1587 };
1588
1589 static struct omap_hwmod omap3xxx_dss_venc_hwmod = {
1590 .name = "dss_venc",
1591 .class = &omap2_venc_hwmod_class,
1592 .main_clk = "dss1_alwon_fck",
1593 .prcm = {
1594 .omap2 = {
1595 .prcm_reg_id = 1,
1596 .module_bit = OMAP3430_EN_DSS1_SHIFT,
1597 .module_offs = OMAP3430_DSS_MOD,
1598 },
1599 },
1600 .slaves = omap3xxx_dss_venc_slaves,
1601 .slaves_cnt = ARRAY_SIZE(omap3xxx_dss_venc_slaves),
1602 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES1 |
1603 CHIP_GE_OMAP3430ES2 | CHIP_IS_OMAP3630ES1 |
1604 CHIP_GE_OMAP3630ES1_1),
1605 .flags = HWMOD_NO_IDLEST,
1606 };
1607
1608 /* I2C1 */
1609
1610 static struct omap_i2c_dev_attr i2c1_dev_attr = {
1611 .fifo_depth = 8, /* bytes */
1612 .flags = OMAP_I2C_FLAG_APPLY_ERRATA_I207 |
1613 OMAP_I2C_FLAG_RESET_REGS_POSTIDLE |
1614 OMAP_I2C_FLAG_BUS_SHIFT_2,
1615 };
1616
1617 static struct omap_hwmod_ocp_if *omap3xxx_i2c1_slaves[] = {
1618 &omap3_l4_core__i2c1,
1619 };
1620
1621 static struct omap_hwmod omap3xxx_i2c1_hwmod = {
1622 .name = "i2c1",
1623 .flags = HWMOD_16BIT_REG,
1624 .mpu_irqs = omap2_i2c1_mpu_irqs,
1625 .sdma_reqs = omap2_i2c1_sdma_reqs,
1626 .main_clk = "i2c1_fck",
1627 .prcm = {
1628 .omap2 = {
1629 .module_offs = CORE_MOD,
1630 .prcm_reg_id = 1,
1631 .module_bit = OMAP3430_EN_I2C1_SHIFT,
1632 .idlest_reg_id = 1,
1633 .idlest_idle_bit = OMAP3430_ST_I2C1_SHIFT,
1634 },
1635 },
1636 .slaves = omap3xxx_i2c1_slaves,
1637 .slaves_cnt = ARRAY_SIZE(omap3xxx_i2c1_slaves),
1638 .class = &i2c_class,
1639 .dev_attr = &i2c1_dev_attr,
1640 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
1641 };
1642
1643 /* I2C2 */
1644
1645 static struct omap_i2c_dev_attr i2c2_dev_attr = {
1646 .fifo_depth = 8, /* bytes */
1647 .flags = OMAP_I2C_FLAG_APPLY_ERRATA_I207 |
1648 OMAP_I2C_FLAG_RESET_REGS_POSTIDLE |
1649 OMAP_I2C_FLAG_BUS_SHIFT_2,
1650 };
1651
1652 static struct omap_hwmod_ocp_if *omap3xxx_i2c2_slaves[] = {
1653 &omap3_l4_core__i2c2,
1654 };
1655
1656 static struct omap_hwmod omap3xxx_i2c2_hwmod = {
1657 .name = "i2c2",
1658 .flags = HWMOD_16BIT_REG,
1659 .mpu_irqs = omap2_i2c2_mpu_irqs,
1660 .sdma_reqs = omap2_i2c2_sdma_reqs,
1661 .main_clk = "i2c2_fck",
1662 .prcm = {
1663 .omap2 = {
1664 .module_offs = CORE_MOD,
1665 .prcm_reg_id = 1,
1666 .module_bit = OMAP3430_EN_I2C2_SHIFT,
1667 .idlest_reg_id = 1,
1668 .idlest_idle_bit = OMAP3430_ST_I2C2_SHIFT,
1669 },
1670 },
1671 .slaves = omap3xxx_i2c2_slaves,
1672 .slaves_cnt = ARRAY_SIZE(omap3xxx_i2c2_slaves),
1673 .class = &i2c_class,
1674 .dev_attr = &i2c2_dev_attr,
1675 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
1676 };
1677
1678 /* I2C3 */
1679
1680 static struct omap_i2c_dev_attr i2c3_dev_attr = {
1681 .fifo_depth = 64, /* bytes */
1682 .flags = OMAP_I2C_FLAG_APPLY_ERRATA_I207 |
1683 OMAP_I2C_FLAG_RESET_REGS_POSTIDLE |
1684 OMAP_I2C_FLAG_BUS_SHIFT_2,
1685 };
1686
1687 static struct omap_hwmod_irq_info i2c3_mpu_irqs[] = {
1688 { .irq = INT_34XX_I2C3_IRQ, },
1689 { .irq = -1 }
1690 };
1691
1692 static struct omap_hwmod_dma_info i2c3_sdma_reqs[] = {
1693 { .name = "tx", .dma_req = OMAP34XX_DMA_I2C3_TX },
1694 { .name = "rx", .dma_req = OMAP34XX_DMA_I2C3_RX },
1695 { .dma_req = -1 }
1696 };
1697
1698 static struct omap_hwmod_ocp_if *omap3xxx_i2c3_slaves[] = {
1699 &omap3_l4_core__i2c3,
1700 };
1701
1702 static struct omap_hwmod omap3xxx_i2c3_hwmod = {
1703 .name = "i2c3",
1704 .flags = HWMOD_16BIT_REG,
1705 .mpu_irqs = i2c3_mpu_irqs,
1706 .sdma_reqs = i2c3_sdma_reqs,
1707 .main_clk = "i2c3_fck",
1708 .prcm = {
1709 .omap2 = {
1710 .module_offs = CORE_MOD,
1711 .prcm_reg_id = 1,
1712 .module_bit = OMAP3430_EN_I2C3_SHIFT,
1713 .idlest_reg_id = 1,
1714 .idlest_idle_bit = OMAP3430_ST_I2C3_SHIFT,
1715 },
1716 },
1717 .slaves = omap3xxx_i2c3_slaves,
1718 .slaves_cnt = ARRAY_SIZE(omap3xxx_i2c3_slaves),
1719 .class = &i2c_class,
1720 .dev_attr = &i2c3_dev_attr,
1721 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
1722 };
1723
1724 /* l4_wkup -> gpio1 */
1725 static struct omap_hwmod_addr_space omap3xxx_gpio1_addrs[] = {
1726 {
1727 .pa_start = 0x48310000,
1728 .pa_end = 0x483101ff,
1729 .flags = ADDR_TYPE_RT
1730 },
1731 { }
1732 };
1733
1734 static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__gpio1 = {
1735 .master = &omap3xxx_l4_wkup_hwmod,
1736 .slave = &omap3xxx_gpio1_hwmod,
1737 .addr = omap3xxx_gpio1_addrs,
1738 .user = OCP_USER_MPU | OCP_USER_SDMA,
1739 };
1740
1741 /* l4_per -> gpio2 */
1742 static struct omap_hwmod_addr_space omap3xxx_gpio2_addrs[] = {
1743 {
1744 .pa_start = 0x49050000,
1745 .pa_end = 0x490501ff,
1746 .flags = ADDR_TYPE_RT
1747 },
1748 { }
1749 };
1750
1751 static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio2 = {
1752 .master = &omap3xxx_l4_per_hwmod,
1753 .slave = &omap3xxx_gpio2_hwmod,
1754 .addr = omap3xxx_gpio2_addrs,
1755 .user = OCP_USER_MPU | OCP_USER_SDMA,
1756 };
1757
1758 /* l4_per -> gpio3 */
1759 static struct omap_hwmod_addr_space omap3xxx_gpio3_addrs[] = {
1760 {
1761 .pa_start = 0x49052000,
1762 .pa_end = 0x490521ff,
1763 .flags = ADDR_TYPE_RT
1764 },
1765 { }
1766 };
1767
1768 static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio3 = {
1769 .master = &omap3xxx_l4_per_hwmod,
1770 .slave = &omap3xxx_gpio3_hwmod,
1771 .addr = omap3xxx_gpio3_addrs,
1772 .user = OCP_USER_MPU | OCP_USER_SDMA,
1773 };
1774
1775 /* l4_per -> gpio4 */
1776 static struct omap_hwmod_addr_space omap3xxx_gpio4_addrs[] = {
1777 {
1778 .pa_start = 0x49054000,
1779 .pa_end = 0x490541ff,
1780 .flags = ADDR_TYPE_RT
1781 },
1782 { }
1783 };
1784
1785 static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio4 = {
1786 .master = &omap3xxx_l4_per_hwmod,
1787 .slave = &omap3xxx_gpio4_hwmod,
1788 .addr = omap3xxx_gpio4_addrs,
1789 .user = OCP_USER_MPU | OCP_USER_SDMA,
1790 };
1791
1792 /* l4_per -> gpio5 */
1793 static struct omap_hwmod_addr_space omap3xxx_gpio5_addrs[] = {
1794 {
1795 .pa_start = 0x49056000,
1796 .pa_end = 0x490561ff,
1797 .flags = ADDR_TYPE_RT
1798 },
1799 { }
1800 };
1801
1802 static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio5 = {
1803 .master = &omap3xxx_l4_per_hwmod,
1804 .slave = &omap3xxx_gpio5_hwmod,
1805 .addr = omap3xxx_gpio5_addrs,
1806 .user = OCP_USER_MPU | OCP_USER_SDMA,
1807 };
1808
1809 /* l4_per -> gpio6 */
1810 static struct omap_hwmod_addr_space omap3xxx_gpio6_addrs[] = {
1811 {
1812 .pa_start = 0x49058000,
1813 .pa_end = 0x490581ff,
1814 .flags = ADDR_TYPE_RT
1815 },
1816 { }
1817 };
1818
1819 static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio6 = {
1820 .master = &omap3xxx_l4_per_hwmod,
1821 .slave = &omap3xxx_gpio6_hwmod,
1822 .addr = omap3xxx_gpio6_addrs,
1823 .user = OCP_USER_MPU | OCP_USER_SDMA,
1824 };
1825
1826 /*
1827 * 'gpio' class
1828 * general purpose io module
1829 */
1830
1831 static struct omap_hwmod_class_sysconfig omap3xxx_gpio_sysc = {
1832 .rev_offs = 0x0000,
1833 .sysc_offs = 0x0010,
1834 .syss_offs = 0x0014,
1835 .sysc_flags = (SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
1836 SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
1837 SYSS_HAS_RESET_STATUS),
1838 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1839 .sysc_fields = &omap_hwmod_sysc_type1,
1840 };
1841
1842 static struct omap_hwmod_class omap3xxx_gpio_hwmod_class = {
1843 .name = "gpio",
1844 .sysc = &omap3xxx_gpio_sysc,
1845 .rev = 1,
1846 };
1847
1848 /* gpio_dev_attr*/
1849 static struct omap_gpio_dev_attr gpio_dev_attr = {
1850 .bank_width = 32,
1851 .dbck_flag = true,
1852 };
1853
1854 /* gpio1 */
1855 static struct omap_hwmod_opt_clk gpio1_opt_clks[] = {
1856 { .role = "dbclk", .clk = "gpio1_dbck", },
1857 };
1858
1859 static struct omap_hwmod_ocp_if *omap3xxx_gpio1_slaves[] = {
1860 &omap3xxx_l4_wkup__gpio1,
1861 };
1862
1863 static struct omap_hwmod omap3xxx_gpio1_hwmod = {
1864 .name = "gpio1",
1865 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1866 .mpu_irqs = omap2_gpio1_irqs,
1867 .main_clk = "gpio1_ick",
1868 .opt_clks = gpio1_opt_clks,
1869 .opt_clks_cnt = ARRAY_SIZE(gpio1_opt_clks),
1870 .prcm = {
1871 .omap2 = {
1872 .prcm_reg_id = 1,
1873 .module_bit = OMAP3430_EN_GPIO1_SHIFT,
1874 .module_offs = WKUP_MOD,
1875 .idlest_reg_id = 1,
1876 .idlest_idle_bit = OMAP3430_ST_GPIO1_SHIFT,
1877 },
1878 },
1879 .slaves = omap3xxx_gpio1_slaves,
1880 .slaves_cnt = ARRAY_SIZE(omap3xxx_gpio1_slaves),
1881 .class = &omap3xxx_gpio_hwmod_class,
1882 .dev_attr = &gpio_dev_attr,
1883 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
1884 };
1885
1886 /* gpio2 */
1887 static struct omap_hwmod_opt_clk gpio2_opt_clks[] = {
1888 { .role = "dbclk", .clk = "gpio2_dbck", },
1889 };
1890
1891 static struct omap_hwmod_ocp_if *omap3xxx_gpio2_slaves[] = {
1892 &omap3xxx_l4_per__gpio2,
1893 };
1894
1895 static struct omap_hwmod omap3xxx_gpio2_hwmod = {
1896 .name = "gpio2",
1897 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1898 .mpu_irqs = omap2_gpio2_irqs,
1899 .main_clk = "gpio2_ick",
1900 .opt_clks = gpio2_opt_clks,
1901 .opt_clks_cnt = ARRAY_SIZE(gpio2_opt_clks),
1902 .prcm = {
1903 .omap2 = {
1904 .prcm_reg_id = 1,
1905 .module_bit = OMAP3430_EN_GPIO2_SHIFT,
1906 .module_offs = OMAP3430_PER_MOD,
1907 .idlest_reg_id = 1,
1908 .idlest_idle_bit = OMAP3430_ST_GPIO2_SHIFT,
1909 },
1910 },
1911 .slaves = omap3xxx_gpio2_slaves,
1912 .slaves_cnt = ARRAY_SIZE(omap3xxx_gpio2_slaves),
1913 .class = &omap3xxx_gpio_hwmod_class,
1914 .dev_attr = &gpio_dev_attr,
1915 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
1916 };
1917
1918 /* gpio3 */
1919 static struct omap_hwmod_opt_clk gpio3_opt_clks[] = {
1920 { .role = "dbclk", .clk = "gpio3_dbck", },
1921 };
1922
1923 static struct omap_hwmod_ocp_if *omap3xxx_gpio3_slaves[] = {
1924 &omap3xxx_l4_per__gpio3,
1925 };
1926
1927 static struct omap_hwmod omap3xxx_gpio3_hwmod = {
1928 .name = "gpio3",
1929 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1930 .mpu_irqs = omap2_gpio3_irqs,
1931 .main_clk = "gpio3_ick",
1932 .opt_clks = gpio3_opt_clks,
1933 .opt_clks_cnt = ARRAY_SIZE(gpio3_opt_clks),
1934 .prcm = {
1935 .omap2 = {
1936 .prcm_reg_id = 1,
1937 .module_bit = OMAP3430_EN_GPIO3_SHIFT,
1938 .module_offs = OMAP3430_PER_MOD,
1939 .idlest_reg_id = 1,
1940 .idlest_idle_bit = OMAP3430_ST_GPIO3_SHIFT,
1941 },
1942 },
1943 .slaves = omap3xxx_gpio3_slaves,
1944 .slaves_cnt = ARRAY_SIZE(omap3xxx_gpio3_slaves),
1945 .class = &omap3xxx_gpio_hwmod_class,
1946 .dev_attr = &gpio_dev_attr,
1947 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
1948 };
1949
1950 /* gpio4 */
1951 static struct omap_hwmod_opt_clk gpio4_opt_clks[] = {
1952 { .role = "dbclk", .clk = "gpio4_dbck", },
1953 };
1954
1955 static struct omap_hwmod_ocp_if *omap3xxx_gpio4_slaves[] = {
1956 &omap3xxx_l4_per__gpio4,
1957 };
1958
1959 static struct omap_hwmod omap3xxx_gpio4_hwmod = {
1960 .name = "gpio4",
1961 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1962 .mpu_irqs = omap2_gpio4_irqs,
1963 .main_clk = "gpio4_ick",
1964 .opt_clks = gpio4_opt_clks,
1965 .opt_clks_cnt = ARRAY_SIZE(gpio4_opt_clks),
1966 .prcm = {
1967 .omap2 = {
1968 .prcm_reg_id = 1,
1969 .module_bit = OMAP3430_EN_GPIO4_SHIFT,
1970 .module_offs = OMAP3430_PER_MOD,
1971 .idlest_reg_id = 1,
1972 .idlest_idle_bit = OMAP3430_ST_GPIO4_SHIFT,
1973 },
1974 },
1975 .slaves = omap3xxx_gpio4_slaves,
1976 .slaves_cnt = ARRAY_SIZE(omap3xxx_gpio4_slaves),
1977 .class = &omap3xxx_gpio_hwmod_class,
1978 .dev_attr = &gpio_dev_attr,
1979 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
1980 };
1981
1982 /* gpio5 */
1983 static struct omap_hwmod_irq_info omap3xxx_gpio5_irqs[] = {
1984 { .irq = 33 }, /* INT_34XX_GPIO_BANK5 */
1985 { .irq = -1 }
1986 };
1987
1988 static struct omap_hwmod_opt_clk gpio5_opt_clks[] = {
1989 { .role = "dbclk", .clk = "gpio5_dbck", },
1990 };
1991
1992 static struct omap_hwmod_ocp_if *omap3xxx_gpio5_slaves[] = {
1993 &omap3xxx_l4_per__gpio5,
1994 };
1995
1996 static struct omap_hwmod omap3xxx_gpio5_hwmod = {
1997 .name = "gpio5",
1998 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1999 .mpu_irqs = omap3xxx_gpio5_irqs,
2000 .main_clk = "gpio5_ick",
2001 .opt_clks = gpio5_opt_clks,
2002 .opt_clks_cnt = ARRAY_SIZE(gpio5_opt_clks),
2003 .prcm = {
2004 .omap2 = {
2005 .prcm_reg_id = 1,
2006 .module_bit = OMAP3430_EN_GPIO5_SHIFT,
2007 .module_offs = OMAP3430_PER_MOD,
2008 .idlest_reg_id = 1,
2009 .idlest_idle_bit = OMAP3430_ST_GPIO5_SHIFT,
2010 },
2011 },
2012 .slaves = omap3xxx_gpio5_slaves,
2013 .slaves_cnt = ARRAY_SIZE(omap3xxx_gpio5_slaves),
2014 .class = &omap3xxx_gpio_hwmod_class,
2015 .dev_attr = &gpio_dev_attr,
2016 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
2017 };
2018
2019 /* gpio6 */
2020 static struct omap_hwmod_irq_info omap3xxx_gpio6_irqs[] = {
2021 { .irq = 34 }, /* INT_34XX_GPIO_BANK6 */
2022 { .irq = -1 }
2023 };
2024
2025 static struct omap_hwmod_opt_clk gpio6_opt_clks[] = {
2026 { .role = "dbclk", .clk = "gpio6_dbck", },
2027 };
2028
2029 static struct omap_hwmod_ocp_if *omap3xxx_gpio6_slaves[] = {
2030 &omap3xxx_l4_per__gpio6,
2031 };
2032
2033 static struct omap_hwmod omap3xxx_gpio6_hwmod = {
2034 .name = "gpio6",
2035 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
2036 .mpu_irqs = omap3xxx_gpio6_irqs,
2037 .main_clk = "gpio6_ick",
2038 .opt_clks = gpio6_opt_clks,
2039 .opt_clks_cnt = ARRAY_SIZE(gpio6_opt_clks),
2040 .prcm = {
2041 .omap2 = {
2042 .prcm_reg_id = 1,
2043 .module_bit = OMAP3430_EN_GPIO6_SHIFT,
2044 .module_offs = OMAP3430_PER_MOD,
2045 .idlest_reg_id = 1,
2046 .idlest_idle_bit = OMAP3430_ST_GPIO6_SHIFT,
2047 },
2048 },
2049 .slaves = omap3xxx_gpio6_slaves,
2050 .slaves_cnt = ARRAY_SIZE(omap3xxx_gpio6_slaves),
2051 .class = &omap3xxx_gpio_hwmod_class,
2052 .dev_attr = &gpio_dev_attr,
2053 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
2054 };
2055
2056 /* dma_system -> L3 */
2057 static struct omap_hwmod_ocp_if omap3xxx_dma_system__l3 = {
2058 .master = &omap3xxx_dma_system_hwmod,
2059 .slave = &omap3xxx_l3_main_hwmod,
2060 .clk = "core_l3_ick",
2061 .user = OCP_USER_MPU | OCP_USER_SDMA,
2062 };
2063
2064 /* dma attributes */
2065 static struct omap_dma_dev_attr dma_dev_attr = {
2066 .dev_caps = RESERVE_CHANNEL | DMA_LINKED_LCH | GLOBAL_PRIORITY |
2067 IS_CSSA_32 | IS_CDSA_32 | IS_RW_PRIORITY,
2068 .lch_count = 32,
2069 };
2070
2071 static struct omap_hwmod_class_sysconfig omap3xxx_dma_sysc = {
2072 .rev_offs = 0x0000,
2073 .sysc_offs = 0x002c,
2074 .syss_offs = 0x0028,
2075 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
2076 SYSC_HAS_MIDLEMODE | SYSC_HAS_CLOCKACTIVITY |
2077 SYSC_HAS_EMUFREE | SYSC_HAS_AUTOIDLE |
2078 SYSS_HAS_RESET_STATUS),
2079 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2080 MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
2081 .sysc_fields = &omap_hwmod_sysc_type1,
2082 };
2083
2084 static struct omap_hwmod_class omap3xxx_dma_hwmod_class = {
2085 .name = "dma",
2086 .sysc = &omap3xxx_dma_sysc,
2087 };
2088
2089 /* dma_system */
2090 static struct omap_hwmod_addr_space omap3xxx_dma_system_addrs[] = {
2091 {
2092 .pa_start = 0x48056000,
2093 .pa_end = 0x48056fff,
2094 .flags = ADDR_TYPE_RT
2095 },
2096 { }
2097 };
2098
2099 /* dma_system master ports */
2100 static struct omap_hwmod_ocp_if *omap3xxx_dma_system_masters[] = {
2101 &omap3xxx_dma_system__l3,
2102 };
2103
2104 /* l4_cfg -> dma_system */
2105 static struct omap_hwmod_ocp_if omap3xxx_l4_core__dma_system = {
2106 .master = &omap3xxx_l4_core_hwmod,
2107 .slave = &omap3xxx_dma_system_hwmod,
2108 .clk = "core_l4_ick",
2109 .addr = omap3xxx_dma_system_addrs,
2110 .user = OCP_USER_MPU | OCP_USER_SDMA,
2111 };
2112
2113 /* dma_system slave ports */
2114 static struct omap_hwmod_ocp_if *omap3xxx_dma_system_slaves[] = {
2115 &omap3xxx_l4_core__dma_system,
2116 };
2117
2118 static struct omap_hwmod omap3xxx_dma_system_hwmod = {
2119 .name = "dma",
2120 .class = &omap3xxx_dma_hwmod_class,
2121 .mpu_irqs = omap2_dma_system_irqs,
2122 .main_clk = "core_l3_ick",
2123 .prcm = {
2124 .omap2 = {
2125 .module_offs = CORE_MOD,
2126 .prcm_reg_id = 1,
2127 .module_bit = OMAP3430_ST_SDMA_SHIFT,
2128 .idlest_reg_id = 1,
2129 .idlest_idle_bit = OMAP3430_ST_SDMA_SHIFT,
2130 },
2131 },
2132 .slaves = omap3xxx_dma_system_slaves,
2133 .slaves_cnt = ARRAY_SIZE(omap3xxx_dma_system_slaves),
2134 .masters = omap3xxx_dma_system_masters,
2135 .masters_cnt = ARRAY_SIZE(omap3xxx_dma_system_masters),
2136 .dev_attr = &dma_dev_attr,
2137 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
2138 .flags = HWMOD_NO_IDLEST,
2139 };
2140
2141 /*
2142 * 'mcbsp' class
2143 * multi channel buffered serial port controller
2144 */
2145
2146 static struct omap_hwmod_class_sysconfig omap3xxx_mcbsp_sysc = {
2147 .sysc_offs = 0x008c,
2148 .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_ENAWAKEUP |
2149 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
2150 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
2151 .sysc_fields = &omap_hwmod_sysc_type1,
2152 .clockact = 0x2,
2153 };
2154
2155 static struct omap_hwmod_class omap3xxx_mcbsp_hwmod_class = {
2156 .name = "mcbsp",
2157 .sysc = &omap3xxx_mcbsp_sysc,
2158 .rev = MCBSP_CONFIG_TYPE3,
2159 };
2160
2161 /* mcbsp1 */
2162 static struct omap_hwmod_irq_info omap3xxx_mcbsp1_irqs[] = {
2163 { .name = "irq", .irq = 16 },
2164 { .name = "tx", .irq = 59 },
2165 { .name = "rx", .irq = 60 },
2166 { .irq = -1 }
2167 };
2168
2169 static struct omap_hwmod_addr_space omap3xxx_mcbsp1_addrs[] = {
2170 {
2171 .name = "mpu",
2172 .pa_start = 0x48074000,
2173 .pa_end = 0x480740ff,
2174 .flags = ADDR_TYPE_RT
2175 },
2176 { }
2177 };
2178
2179 /* l4_core -> mcbsp1 */
2180 static struct omap_hwmod_ocp_if omap3xxx_l4_core__mcbsp1 = {
2181 .master = &omap3xxx_l4_core_hwmod,
2182 .slave = &omap3xxx_mcbsp1_hwmod,
2183 .clk = "mcbsp1_ick",
2184 .addr = omap3xxx_mcbsp1_addrs,
2185 .user = OCP_USER_MPU | OCP_USER_SDMA,
2186 };
2187
2188 /* mcbsp1 slave ports */
2189 static struct omap_hwmod_ocp_if *omap3xxx_mcbsp1_slaves[] = {
2190 &omap3xxx_l4_core__mcbsp1,
2191 };
2192
2193 static struct omap_hwmod omap3xxx_mcbsp1_hwmod = {
2194 .name = "mcbsp1",
2195 .class = &omap3xxx_mcbsp_hwmod_class,
2196 .mpu_irqs = omap3xxx_mcbsp1_irqs,
2197 .sdma_reqs = omap2_mcbsp1_sdma_reqs,
2198 .main_clk = "mcbsp1_fck",
2199 .prcm = {
2200 .omap2 = {
2201 .prcm_reg_id = 1,
2202 .module_bit = OMAP3430_EN_MCBSP1_SHIFT,
2203 .module_offs = CORE_MOD,
2204 .idlest_reg_id = 1,
2205 .idlest_idle_bit = OMAP3430_ST_MCBSP1_SHIFT,
2206 },
2207 },
2208 .slaves = omap3xxx_mcbsp1_slaves,
2209 .slaves_cnt = ARRAY_SIZE(omap3xxx_mcbsp1_slaves),
2210 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
2211 };
2212
2213 /* mcbsp2 */
2214 static struct omap_hwmod_irq_info omap3xxx_mcbsp2_irqs[] = {
2215 { .name = "irq", .irq = 17 },
2216 { .name = "tx", .irq = 62 },
2217 { .name = "rx", .irq = 63 },
2218 { .irq = -1 }
2219 };
2220
2221 static struct omap_hwmod_addr_space omap3xxx_mcbsp2_addrs[] = {
2222 {
2223 .name = "mpu",
2224 .pa_start = 0x49022000,
2225 .pa_end = 0x490220ff,
2226 .flags = ADDR_TYPE_RT
2227 },
2228 { }
2229 };
2230
2231 /* l4_per -> mcbsp2 */
2232 static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp2 = {
2233 .master = &omap3xxx_l4_per_hwmod,
2234 .slave = &omap3xxx_mcbsp2_hwmod,
2235 .clk = "mcbsp2_ick",
2236 .addr = omap3xxx_mcbsp2_addrs,
2237 .user = OCP_USER_MPU | OCP_USER_SDMA,
2238 };
2239
2240 /* mcbsp2 slave ports */
2241 static struct omap_hwmod_ocp_if *omap3xxx_mcbsp2_slaves[] = {
2242 &omap3xxx_l4_per__mcbsp2,
2243 };
2244
2245 static struct omap_mcbsp_dev_attr omap34xx_mcbsp2_dev_attr = {
2246 .sidetone = "mcbsp2_sidetone",
2247 };
2248
2249 static struct omap_hwmod omap3xxx_mcbsp2_hwmod = {
2250 .name = "mcbsp2",
2251 .class = &omap3xxx_mcbsp_hwmod_class,
2252 .mpu_irqs = omap3xxx_mcbsp2_irqs,
2253 .sdma_reqs = omap2_mcbsp2_sdma_reqs,
2254 .main_clk = "mcbsp2_fck",
2255 .prcm = {
2256 .omap2 = {
2257 .prcm_reg_id = 1,
2258 .module_bit = OMAP3430_EN_MCBSP2_SHIFT,
2259 .module_offs = OMAP3430_PER_MOD,
2260 .idlest_reg_id = 1,
2261 .idlest_idle_bit = OMAP3430_ST_MCBSP2_SHIFT,
2262 },
2263 },
2264 .slaves = omap3xxx_mcbsp2_slaves,
2265 .slaves_cnt = ARRAY_SIZE(omap3xxx_mcbsp2_slaves),
2266 .dev_attr = &omap34xx_mcbsp2_dev_attr,
2267 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
2268 };
2269
2270 /* mcbsp3 */
2271 static struct omap_hwmod_irq_info omap3xxx_mcbsp3_irqs[] = {
2272 { .name = "irq", .irq = 22 },
2273 { .name = "tx", .irq = 89 },
2274 { .name = "rx", .irq = 90 },
2275 { .irq = -1 }
2276 };
2277
2278 static struct omap_hwmod_addr_space omap3xxx_mcbsp3_addrs[] = {
2279 {
2280 .name = "mpu",
2281 .pa_start = 0x49024000,
2282 .pa_end = 0x490240ff,
2283 .flags = ADDR_TYPE_RT
2284 },
2285 { }
2286 };
2287
2288 /* l4_per -> mcbsp3 */
2289 static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp3 = {
2290 .master = &omap3xxx_l4_per_hwmod,
2291 .slave = &omap3xxx_mcbsp3_hwmod,
2292 .clk = "mcbsp3_ick",
2293 .addr = omap3xxx_mcbsp3_addrs,
2294 .user = OCP_USER_MPU | OCP_USER_SDMA,
2295 };
2296
2297 /* mcbsp3 slave ports */
2298 static struct omap_hwmod_ocp_if *omap3xxx_mcbsp3_slaves[] = {
2299 &omap3xxx_l4_per__mcbsp3,
2300 };
2301
2302 static struct omap_mcbsp_dev_attr omap34xx_mcbsp3_dev_attr = {
2303 .sidetone = "mcbsp3_sidetone",
2304 };
2305
2306 static struct omap_hwmod omap3xxx_mcbsp3_hwmod = {
2307 .name = "mcbsp3",
2308 .class = &omap3xxx_mcbsp_hwmod_class,
2309 .mpu_irqs = omap3xxx_mcbsp3_irqs,
2310 .sdma_reqs = omap2_mcbsp3_sdma_reqs,
2311 .main_clk = "mcbsp3_fck",
2312 .prcm = {
2313 .omap2 = {
2314 .prcm_reg_id = 1,
2315 .module_bit = OMAP3430_EN_MCBSP3_SHIFT,
2316 .module_offs = OMAP3430_PER_MOD,
2317 .idlest_reg_id = 1,
2318 .idlest_idle_bit = OMAP3430_ST_MCBSP3_SHIFT,
2319 },
2320 },
2321 .slaves = omap3xxx_mcbsp3_slaves,
2322 .slaves_cnt = ARRAY_SIZE(omap3xxx_mcbsp3_slaves),
2323 .dev_attr = &omap34xx_mcbsp3_dev_attr,
2324 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
2325 };
2326
2327 /* mcbsp4 */
2328 static struct omap_hwmod_irq_info omap3xxx_mcbsp4_irqs[] = {
2329 { .name = "irq", .irq = 23 },
2330 { .name = "tx", .irq = 54 },
2331 { .name = "rx", .irq = 55 },
2332 { .irq = -1 }
2333 };
2334
2335 static struct omap_hwmod_dma_info omap3xxx_mcbsp4_sdma_chs[] = {
2336 { .name = "rx", .dma_req = 20 },
2337 { .name = "tx", .dma_req = 19 },
2338 { .dma_req = -1 }
2339 };
2340
2341 static struct omap_hwmod_addr_space omap3xxx_mcbsp4_addrs[] = {
2342 {
2343 .name = "mpu",
2344 .pa_start = 0x49026000,
2345 .pa_end = 0x490260ff,
2346 .flags = ADDR_TYPE_RT
2347 },
2348 { }
2349 };
2350
2351 /* l4_per -> mcbsp4 */
2352 static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp4 = {
2353 .master = &omap3xxx_l4_per_hwmod,
2354 .slave = &omap3xxx_mcbsp4_hwmod,
2355 .clk = "mcbsp4_ick",
2356 .addr = omap3xxx_mcbsp4_addrs,
2357 .user = OCP_USER_MPU | OCP_USER_SDMA,
2358 };
2359
2360 /* mcbsp4 slave ports */
2361 static struct omap_hwmod_ocp_if *omap3xxx_mcbsp4_slaves[] = {
2362 &omap3xxx_l4_per__mcbsp4,
2363 };
2364
2365 static struct omap_hwmod omap3xxx_mcbsp4_hwmod = {
2366 .name = "mcbsp4",
2367 .class = &omap3xxx_mcbsp_hwmod_class,
2368 .mpu_irqs = omap3xxx_mcbsp4_irqs,
2369 .sdma_reqs = omap3xxx_mcbsp4_sdma_chs,
2370 .main_clk = "mcbsp4_fck",
2371 .prcm = {
2372 .omap2 = {
2373 .prcm_reg_id = 1,
2374 .module_bit = OMAP3430_EN_MCBSP4_SHIFT,
2375 .module_offs = OMAP3430_PER_MOD,
2376 .idlest_reg_id = 1,
2377 .idlest_idle_bit = OMAP3430_ST_MCBSP4_SHIFT,
2378 },
2379 },
2380 .slaves = omap3xxx_mcbsp4_slaves,
2381 .slaves_cnt = ARRAY_SIZE(omap3xxx_mcbsp4_slaves),
2382 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
2383 };
2384
2385 /* mcbsp5 */
2386 static struct omap_hwmod_irq_info omap3xxx_mcbsp5_irqs[] = {
2387 { .name = "irq", .irq = 27 },
2388 { .name = "tx", .irq = 81 },
2389 { .name = "rx", .irq = 82 },
2390 { .irq = -1 }
2391 };
2392
2393 static struct omap_hwmod_dma_info omap3xxx_mcbsp5_sdma_chs[] = {
2394 { .name = "rx", .dma_req = 22 },
2395 { .name = "tx", .dma_req = 21 },
2396 { .dma_req = -1 }
2397 };
2398
2399 static struct omap_hwmod_addr_space omap3xxx_mcbsp5_addrs[] = {
2400 {
2401 .name = "mpu",
2402 .pa_start = 0x48096000,
2403 .pa_end = 0x480960ff,
2404 .flags = ADDR_TYPE_RT
2405 },
2406 { }
2407 };
2408
2409 /* l4_core -> mcbsp5 */
2410 static struct omap_hwmod_ocp_if omap3xxx_l4_core__mcbsp5 = {
2411 .master = &omap3xxx_l4_core_hwmod,
2412 .slave = &omap3xxx_mcbsp5_hwmod,
2413 .clk = "mcbsp5_ick",
2414 .addr = omap3xxx_mcbsp5_addrs,
2415 .user = OCP_USER_MPU | OCP_USER_SDMA,
2416 };
2417
2418 /* mcbsp5 slave ports */
2419 static struct omap_hwmod_ocp_if *omap3xxx_mcbsp5_slaves[] = {
2420 &omap3xxx_l4_core__mcbsp5,
2421 };
2422
2423 static struct omap_hwmod omap3xxx_mcbsp5_hwmod = {
2424 .name = "mcbsp5",
2425 .class = &omap3xxx_mcbsp_hwmod_class,
2426 .mpu_irqs = omap3xxx_mcbsp5_irqs,
2427 .sdma_reqs = omap3xxx_mcbsp5_sdma_chs,
2428 .main_clk = "mcbsp5_fck",
2429 .prcm = {
2430 .omap2 = {
2431 .prcm_reg_id = 1,
2432 .module_bit = OMAP3430_EN_MCBSP5_SHIFT,
2433 .module_offs = CORE_MOD,
2434 .idlest_reg_id = 1,
2435 .idlest_idle_bit = OMAP3430_ST_MCBSP5_SHIFT,
2436 },
2437 },
2438 .slaves = omap3xxx_mcbsp5_slaves,
2439 .slaves_cnt = ARRAY_SIZE(omap3xxx_mcbsp5_slaves),
2440 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
2441 };
2442 /* 'mcbsp sidetone' class */
2443
2444 static struct omap_hwmod_class_sysconfig omap3xxx_mcbsp_sidetone_sysc = {
2445 .sysc_offs = 0x0010,
2446 .sysc_flags = SYSC_HAS_AUTOIDLE,
2447 .sysc_fields = &omap_hwmod_sysc_type1,
2448 };
2449
2450 static struct omap_hwmod_class omap3xxx_mcbsp_sidetone_hwmod_class = {
2451 .name = "mcbsp_sidetone",
2452 .sysc = &omap3xxx_mcbsp_sidetone_sysc,
2453 };
2454
2455 /* mcbsp2_sidetone */
2456 static struct omap_hwmod_irq_info omap3xxx_mcbsp2_sidetone_irqs[] = {
2457 { .name = "irq", .irq = 4 },
2458 { .irq = -1 }
2459 };
2460
2461 static struct omap_hwmod_addr_space omap3xxx_mcbsp2_sidetone_addrs[] = {
2462 {
2463 .name = "sidetone",
2464 .pa_start = 0x49028000,
2465 .pa_end = 0x490280ff,
2466 .flags = ADDR_TYPE_RT
2467 },
2468 { }
2469 };
2470
2471 /* l4_per -> mcbsp2_sidetone */
2472 static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp2_sidetone = {
2473 .master = &omap3xxx_l4_per_hwmod,
2474 .slave = &omap3xxx_mcbsp2_sidetone_hwmod,
2475 .clk = "mcbsp2_ick",
2476 .addr = omap3xxx_mcbsp2_sidetone_addrs,
2477 .user = OCP_USER_MPU,
2478 };
2479
2480 /* mcbsp2_sidetone slave ports */
2481 static struct omap_hwmod_ocp_if *omap3xxx_mcbsp2_sidetone_slaves[] = {
2482 &omap3xxx_l4_per__mcbsp2_sidetone,
2483 };
2484
2485 static struct omap_hwmod omap3xxx_mcbsp2_sidetone_hwmod = {
2486 .name = "mcbsp2_sidetone",
2487 .class = &omap3xxx_mcbsp_sidetone_hwmod_class,
2488 .mpu_irqs = omap3xxx_mcbsp2_sidetone_irqs,
2489 .main_clk = "mcbsp2_fck",
2490 .prcm = {
2491 .omap2 = {
2492 .prcm_reg_id = 1,
2493 .module_bit = OMAP3430_EN_MCBSP2_SHIFT,
2494 .module_offs = OMAP3430_PER_MOD,
2495 .idlest_reg_id = 1,
2496 .idlest_idle_bit = OMAP3430_ST_MCBSP2_SHIFT,
2497 },
2498 },
2499 .slaves = omap3xxx_mcbsp2_sidetone_slaves,
2500 .slaves_cnt = ARRAY_SIZE(omap3xxx_mcbsp2_sidetone_slaves),
2501 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
2502 };
2503
2504 /* mcbsp3_sidetone */
2505 static struct omap_hwmod_irq_info omap3xxx_mcbsp3_sidetone_irqs[] = {
2506 { .name = "irq", .irq = 5 },
2507 { .irq = -1 }
2508 };
2509
2510 static struct omap_hwmod_addr_space omap3xxx_mcbsp3_sidetone_addrs[] = {
2511 {
2512 .name = "sidetone",
2513 .pa_start = 0x4902A000,
2514 .pa_end = 0x4902A0ff,
2515 .flags = ADDR_TYPE_RT
2516 },
2517 { }
2518 };
2519
2520 /* l4_per -> mcbsp3_sidetone */
2521 static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp3_sidetone = {
2522 .master = &omap3xxx_l4_per_hwmod,
2523 .slave = &omap3xxx_mcbsp3_sidetone_hwmod,
2524 .clk = "mcbsp3_ick",
2525 .addr = omap3xxx_mcbsp3_sidetone_addrs,
2526 .user = OCP_USER_MPU,
2527 };
2528
2529 /* mcbsp3_sidetone slave ports */
2530 static struct omap_hwmod_ocp_if *omap3xxx_mcbsp3_sidetone_slaves[] = {
2531 &omap3xxx_l4_per__mcbsp3_sidetone,
2532 };
2533
2534 static struct omap_hwmod omap3xxx_mcbsp3_sidetone_hwmod = {
2535 .name = "mcbsp3_sidetone",
2536 .class = &omap3xxx_mcbsp_sidetone_hwmod_class,
2537 .mpu_irqs = omap3xxx_mcbsp3_sidetone_irqs,
2538 .main_clk = "mcbsp3_fck",
2539 .prcm = {
2540 .omap2 = {
2541 .prcm_reg_id = 1,
2542 .module_bit = OMAP3430_EN_MCBSP3_SHIFT,
2543 .module_offs = OMAP3430_PER_MOD,
2544 .idlest_reg_id = 1,
2545 .idlest_idle_bit = OMAP3430_ST_MCBSP3_SHIFT,
2546 },
2547 },
2548 .slaves = omap3xxx_mcbsp3_sidetone_slaves,
2549 .slaves_cnt = ARRAY_SIZE(omap3xxx_mcbsp3_sidetone_slaves),
2550 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
2551 };
2552
2553
2554 /* SR common */
2555 static struct omap_hwmod_sysc_fields omap34xx_sr_sysc_fields = {
2556 .clkact_shift = 20,
2557 };
2558
2559 static struct omap_hwmod_class_sysconfig omap34xx_sr_sysc = {
2560 .sysc_offs = 0x24,
2561 .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_NO_CACHE),
2562 .clockact = CLOCKACT_TEST_ICLK,
2563 .sysc_fields = &omap34xx_sr_sysc_fields,
2564 };
2565
2566 static struct omap_hwmod_class omap34xx_smartreflex_hwmod_class = {
2567 .name = "smartreflex",
2568 .sysc = &omap34xx_sr_sysc,
2569 .rev = 1,
2570 };
2571
2572 static struct omap_hwmod_sysc_fields omap36xx_sr_sysc_fields = {
2573 .sidle_shift = 24,
2574 .enwkup_shift = 26
2575 };
2576
2577 static struct omap_hwmod_class_sysconfig omap36xx_sr_sysc = {
2578 .sysc_offs = 0x38,
2579 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
2580 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_ENAWAKEUP |
2581 SYSC_NO_CACHE),
2582 .sysc_fields = &omap36xx_sr_sysc_fields,
2583 };
2584
2585 static struct omap_hwmod_class omap36xx_smartreflex_hwmod_class = {
2586 .name = "smartreflex",
2587 .sysc = &omap36xx_sr_sysc,
2588 .rev = 2,
2589 };
2590
2591 /* SR1 */
2592 static struct omap_hwmod_ocp_if *omap3_sr1_slaves[] = {
2593 &omap3_l4_core__sr1,
2594 };
2595
2596 static struct omap_hwmod omap34xx_sr1_hwmod = {
2597 .name = "sr1_hwmod",
2598 .class = &omap34xx_smartreflex_hwmod_class,
2599 .main_clk = "sr1_fck",
2600 .vdd_name = "mpu",
2601 .prcm = {
2602 .omap2 = {
2603 .prcm_reg_id = 1,
2604 .module_bit = OMAP3430_EN_SR1_SHIFT,
2605 .module_offs = WKUP_MOD,
2606 .idlest_reg_id = 1,
2607 .idlest_idle_bit = OMAP3430_EN_SR1_SHIFT,
2608 },
2609 },
2610 .slaves = omap3_sr1_slaves,
2611 .slaves_cnt = ARRAY_SIZE(omap3_sr1_slaves),
2612 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES2 |
2613 CHIP_IS_OMAP3430ES3_0 |
2614 CHIP_IS_OMAP3430ES3_1),
2615 .flags = HWMOD_SET_DEFAULT_CLOCKACT,
2616 };
2617
2618 static struct omap_hwmod omap36xx_sr1_hwmod = {
2619 .name = "sr1_hwmod",
2620 .class = &omap36xx_smartreflex_hwmod_class,
2621 .main_clk = "sr1_fck",
2622 .vdd_name = "mpu",
2623 .prcm = {
2624 .omap2 = {
2625 .prcm_reg_id = 1,
2626 .module_bit = OMAP3430_EN_SR1_SHIFT,
2627 .module_offs = WKUP_MOD,
2628 .idlest_reg_id = 1,
2629 .idlest_idle_bit = OMAP3430_EN_SR1_SHIFT,
2630 },
2631 },
2632 .slaves = omap3_sr1_slaves,
2633 .slaves_cnt = ARRAY_SIZE(omap3_sr1_slaves),
2634 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3630ES1),
2635 };
2636
2637 /* SR2 */
2638 static struct omap_hwmod_ocp_if *omap3_sr2_slaves[] = {
2639 &omap3_l4_core__sr2,
2640 };
2641
2642 static struct omap_hwmod omap34xx_sr2_hwmod = {
2643 .name = "sr2_hwmod",
2644 .class = &omap34xx_smartreflex_hwmod_class,
2645 .main_clk = "sr2_fck",
2646 .vdd_name = "core",
2647 .prcm = {
2648 .omap2 = {
2649 .prcm_reg_id = 1,
2650 .module_bit = OMAP3430_EN_SR2_SHIFT,
2651 .module_offs = WKUP_MOD,
2652 .idlest_reg_id = 1,
2653 .idlest_idle_bit = OMAP3430_EN_SR2_SHIFT,
2654 },
2655 },
2656 .slaves = omap3_sr2_slaves,
2657 .slaves_cnt = ARRAY_SIZE(omap3_sr2_slaves),
2658 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES2 |
2659 CHIP_IS_OMAP3430ES3_0 |
2660 CHIP_IS_OMAP3430ES3_1),
2661 .flags = HWMOD_SET_DEFAULT_CLOCKACT,
2662 };
2663
2664 static struct omap_hwmod omap36xx_sr2_hwmod = {
2665 .name = "sr2_hwmod",
2666 .class = &omap36xx_smartreflex_hwmod_class,
2667 .main_clk = "sr2_fck",
2668 .vdd_name = "core",
2669 .prcm = {
2670 .omap2 = {
2671 .prcm_reg_id = 1,
2672 .module_bit = OMAP3430_EN_SR2_SHIFT,
2673 .module_offs = WKUP_MOD,
2674 .idlest_reg_id = 1,
2675 .idlest_idle_bit = OMAP3430_EN_SR2_SHIFT,
2676 },
2677 },
2678 .slaves = omap3_sr2_slaves,
2679 .slaves_cnt = ARRAY_SIZE(omap3_sr2_slaves),
2680 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3630ES1),
2681 };
2682
2683 /*
2684 * 'mailbox' class
2685 * mailbox module allowing communication between the on-chip processors
2686 * using a queued mailbox-interrupt mechanism.
2687 */
2688
2689 static struct omap_hwmod_class_sysconfig omap3xxx_mailbox_sysc = {
2690 .rev_offs = 0x000,
2691 .sysc_offs = 0x010,
2692 .syss_offs = 0x014,
2693 .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
2694 SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
2695 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
2696 .sysc_fields = &omap_hwmod_sysc_type1,
2697 };
2698
2699 static struct omap_hwmod_class omap3xxx_mailbox_hwmod_class = {
2700 .name = "mailbox",
2701 .sysc = &omap3xxx_mailbox_sysc,
2702 };
2703
2704 static struct omap_hwmod omap3xxx_mailbox_hwmod;
2705 static struct omap_hwmod_irq_info omap3xxx_mailbox_irqs[] = {
2706 { .irq = 26 },
2707 { .irq = -1 }
2708 };
2709
2710 static struct omap_hwmod_addr_space omap3xxx_mailbox_addrs[] = {
2711 {
2712 .pa_start = 0x48094000,
2713 .pa_end = 0x480941ff,
2714 .flags = ADDR_TYPE_RT,
2715 },
2716 { }
2717 };
2718
2719 /* l4_core -> mailbox */
2720 static struct omap_hwmod_ocp_if omap3xxx_l4_core__mailbox = {
2721 .master = &omap3xxx_l4_core_hwmod,
2722 .slave = &omap3xxx_mailbox_hwmod,
2723 .addr = omap3xxx_mailbox_addrs,
2724 .user = OCP_USER_MPU | OCP_USER_SDMA,
2725 };
2726
2727 /* mailbox slave ports */
2728 static struct omap_hwmod_ocp_if *omap3xxx_mailbox_slaves[] = {
2729 &omap3xxx_l4_core__mailbox,
2730 };
2731
2732 static struct omap_hwmod omap3xxx_mailbox_hwmod = {
2733 .name = "mailbox",
2734 .class = &omap3xxx_mailbox_hwmod_class,
2735 .mpu_irqs = omap3xxx_mailbox_irqs,
2736 .main_clk = "mailboxes_ick",
2737 .prcm = {
2738 .omap2 = {
2739 .prcm_reg_id = 1,
2740 .module_bit = OMAP3430_EN_MAILBOXES_SHIFT,
2741 .module_offs = CORE_MOD,
2742 .idlest_reg_id = 1,
2743 .idlest_idle_bit = OMAP3430_ST_MAILBOXES_SHIFT,
2744 },
2745 },
2746 .slaves = omap3xxx_mailbox_slaves,
2747 .slaves_cnt = ARRAY_SIZE(omap3xxx_mailbox_slaves),
2748 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
2749 };
2750
2751 /* l4 core -> mcspi1 interface */
2752 static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi1 = {
2753 .master = &omap3xxx_l4_core_hwmod,
2754 .slave = &omap34xx_mcspi1,
2755 .clk = "mcspi1_ick",
2756 .addr = omap2_mcspi1_addr_space,
2757 .user = OCP_USER_MPU | OCP_USER_SDMA,
2758 };
2759
2760 /* l4 core -> mcspi2 interface */
2761 static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi2 = {
2762 .master = &omap3xxx_l4_core_hwmod,
2763 .slave = &omap34xx_mcspi2,
2764 .clk = "mcspi2_ick",
2765 .addr = omap2_mcspi2_addr_space,
2766 .user = OCP_USER_MPU | OCP_USER_SDMA,
2767 };
2768
2769 /* l4 core -> mcspi3 interface */
2770 static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi3 = {
2771 .master = &omap3xxx_l4_core_hwmod,
2772 .slave = &omap34xx_mcspi3,
2773 .clk = "mcspi3_ick",
2774 .addr = omap2430_mcspi3_addr_space,
2775 .user = OCP_USER_MPU | OCP_USER_SDMA,
2776 };
2777
2778 /* l4 core -> mcspi4 interface */
2779 static struct omap_hwmod_addr_space omap34xx_mcspi4_addr_space[] = {
2780 {
2781 .pa_start = 0x480ba000,
2782 .pa_end = 0x480ba0ff,
2783 .flags = ADDR_TYPE_RT,
2784 },
2785 { }
2786 };
2787
2788 static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi4 = {
2789 .master = &omap3xxx_l4_core_hwmod,
2790 .slave = &omap34xx_mcspi4,
2791 .clk = "mcspi4_ick",
2792 .addr = omap34xx_mcspi4_addr_space,
2793 .user = OCP_USER_MPU | OCP_USER_SDMA,
2794 };
2795
2796 /*
2797 * 'mcspi' class
2798 * multichannel serial port interface (mcspi) / master/slave synchronous serial
2799 * bus
2800 */
2801
2802 static struct omap_hwmod_class_sysconfig omap34xx_mcspi_sysc = {
2803 .rev_offs = 0x0000,
2804 .sysc_offs = 0x0010,
2805 .syss_offs = 0x0014,
2806 .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
2807 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
2808 SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
2809 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
2810 .sysc_fields = &omap_hwmod_sysc_type1,
2811 };
2812
2813 static struct omap_hwmod_class omap34xx_mcspi_class = {
2814 .name = "mcspi",
2815 .sysc = &omap34xx_mcspi_sysc,
2816 .rev = OMAP3_MCSPI_REV,
2817 };
2818
2819 /* mcspi1 */
2820 static struct omap_hwmod_ocp_if *omap34xx_mcspi1_slaves[] = {
2821 &omap34xx_l4_core__mcspi1,
2822 };
2823
2824 static struct omap2_mcspi_dev_attr omap_mcspi1_dev_attr = {
2825 .num_chipselect = 4,
2826 };
2827
2828 static struct omap_hwmod omap34xx_mcspi1 = {
2829 .name = "mcspi1",
2830 .mpu_irqs = omap2_mcspi1_mpu_irqs,
2831 .sdma_reqs = omap2_mcspi1_sdma_reqs,
2832 .main_clk = "mcspi1_fck",
2833 .prcm = {
2834 .omap2 = {
2835 .module_offs = CORE_MOD,
2836 .prcm_reg_id = 1,
2837 .module_bit = OMAP3430_EN_MCSPI1_SHIFT,
2838 .idlest_reg_id = 1,
2839 .idlest_idle_bit = OMAP3430_ST_MCSPI1_SHIFT,
2840 },
2841 },
2842 .slaves = omap34xx_mcspi1_slaves,
2843 .slaves_cnt = ARRAY_SIZE(omap34xx_mcspi1_slaves),
2844 .class = &omap34xx_mcspi_class,
2845 .dev_attr = &omap_mcspi1_dev_attr,
2846 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
2847 };
2848
2849 /* mcspi2 */
2850 static struct omap_hwmod_ocp_if *omap34xx_mcspi2_slaves[] = {
2851 &omap34xx_l4_core__mcspi2,
2852 };
2853
2854 static struct omap2_mcspi_dev_attr omap_mcspi2_dev_attr = {
2855 .num_chipselect = 2,
2856 };
2857
2858 static struct omap_hwmod omap34xx_mcspi2 = {
2859 .name = "mcspi2",
2860 .mpu_irqs = omap2_mcspi2_mpu_irqs,
2861 .sdma_reqs = omap2_mcspi2_sdma_reqs,
2862 .main_clk = "mcspi2_fck",
2863 .prcm = {
2864 .omap2 = {
2865 .module_offs = CORE_MOD,
2866 .prcm_reg_id = 1,
2867 .module_bit = OMAP3430_EN_MCSPI2_SHIFT,
2868 .idlest_reg_id = 1,
2869 .idlest_idle_bit = OMAP3430_ST_MCSPI2_SHIFT,
2870 },
2871 },
2872 .slaves = omap34xx_mcspi2_slaves,
2873 .slaves_cnt = ARRAY_SIZE(omap34xx_mcspi2_slaves),
2874 .class = &omap34xx_mcspi_class,
2875 .dev_attr = &omap_mcspi2_dev_attr,
2876 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
2877 };
2878
2879 /* mcspi3 */
2880 static struct omap_hwmod_irq_info omap34xx_mcspi3_mpu_irqs[] = {
2881 { .name = "irq", .irq = 91 }, /* 91 */
2882 { .irq = -1 }
2883 };
2884
2885 static struct omap_hwmod_dma_info omap34xx_mcspi3_sdma_reqs[] = {
2886 { .name = "tx0", .dma_req = 15 },
2887 { .name = "rx0", .dma_req = 16 },
2888 { .name = "tx1", .dma_req = 23 },
2889 { .name = "rx1", .dma_req = 24 },
2890 { .dma_req = -1 }
2891 };
2892
2893 static struct omap_hwmod_ocp_if *omap34xx_mcspi3_slaves[] = {
2894 &omap34xx_l4_core__mcspi3,
2895 };
2896
2897 static struct omap2_mcspi_dev_attr omap_mcspi3_dev_attr = {
2898 .num_chipselect = 2,
2899 };
2900
2901 static struct omap_hwmod omap34xx_mcspi3 = {
2902 .name = "mcspi3",
2903 .mpu_irqs = omap34xx_mcspi3_mpu_irqs,
2904 .sdma_reqs = omap34xx_mcspi3_sdma_reqs,
2905 .main_clk = "mcspi3_fck",
2906 .prcm = {
2907 .omap2 = {
2908 .module_offs = CORE_MOD,
2909 .prcm_reg_id = 1,
2910 .module_bit = OMAP3430_EN_MCSPI3_SHIFT,
2911 .idlest_reg_id = 1,
2912 .idlest_idle_bit = OMAP3430_ST_MCSPI3_SHIFT,
2913 },
2914 },
2915 .slaves = omap34xx_mcspi3_slaves,
2916 .slaves_cnt = ARRAY_SIZE(omap34xx_mcspi3_slaves),
2917 .class = &omap34xx_mcspi_class,
2918 .dev_attr = &omap_mcspi3_dev_attr,
2919 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
2920 };
2921
2922 /* SPI4 */
2923 static struct omap_hwmod_irq_info omap34xx_mcspi4_mpu_irqs[] = {
2924 { .name = "irq", .irq = INT_34XX_SPI4_IRQ }, /* 48 */
2925 { .irq = -1 }
2926 };
2927
2928 static struct omap_hwmod_dma_info omap34xx_mcspi4_sdma_reqs[] = {
2929 { .name = "tx0", .dma_req = 70 }, /* DMA_SPI4_TX0 */
2930 { .name = "rx0", .dma_req = 71 }, /* DMA_SPI4_RX0 */
2931 { .dma_req = -1 }
2932 };
2933
2934 static struct omap_hwmod_ocp_if *omap34xx_mcspi4_slaves[] = {
2935 &omap34xx_l4_core__mcspi4,
2936 };
2937
2938 static struct omap2_mcspi_dev_attr omap_mcspi4_dev_attr = {
2939 .num_chipselect = 1,
2940 };
2941
2942 static struct omap_hwmod omap34xx_mcspi4 = {
2943 .name = "mcspi4",
2944 .mpu_irqs = omap34xx_mcspi4_mpu_irqs,
2945 .sdma_reqs = omap34xx_mcspi4_sdma_reqs,
2946 .main_clk = "mcspi4_fck",
2947 .prcm = {
2948 .omap2 = {
2949 .module_offs = CORE_MOD,
2950 .prcm_reg_id = 1,
2951 .module_bit = OMAP3430_EN_MCSPI4_SHIFT,
2952 .idlest_reg_id = 1,
2953 .idlest_idle_bit = OMAP3430_ST_MCSPI4_SHIFT,
2954 },
2955 },
2956 .slaves = omap34xx_mcspi4_slaves,
2957 .slaves_cnt = ARRAY_SIZE(omap34xx_mcspi4_slaves),
2958 .class = &omap34xx_mcspi_class,
2959 .dev_attr = &omap_mcspi4_dev_attr,
2960 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
2961 };
2962
2963 /*
2964 * usbhsotg
2965 */
2966 static struct omap_hwmod_class_sysconfig omap3xxx_usbhsotg_sysc = {
2967 .rev_offs = 0x0400,
2968 .sysc_offs = 0x0404,
2969 .syss_offs = 0x0408,
2970 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE|
2971 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
2972 SYSC_HAS_AUTOIDLE),
2973 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2974 MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
2975 .sysc_fields = &omap_hwmod_sysc_type1,
2976 };
2977
2978 static struct omap_hwmod_class usbotg_class = {
2979 .name = "usbotg",
2980 .sysc = &omap3xxx_usbhsotg_sysc,
2981 };
2982 /* usb_otg_hs */
2983 static struct omap_hwmod_irq_info omap3xxx_usbhsotg_mpu_irqs[] = {
2984
2985 { .name = "mc", .irq = 92 },
2986 { .name = "dma", .irq = 93 },
2987 { .irq = -1 }
2988 };
2989
2990 static struct omap_hwmod omap3xxx_usbhsotg_hwmod = {
2991 .name = "usb_otg_hs",
2992 .mpu_irqs = omap3xxx_usbhsotg_mpu_irqs,
2993 .main_clk = "hsotgusb_ick",
2994 .prcm = {
2995 .omap2 = {
2996 .prcm_reg_id = 1,
2997 .module_bit = OMAP3430_EN_HSOTGUSB_SHIFT,
2998 .module_offs = CORE_MOD,
2999 .idlest_reg_id = 1,
3000 .idlest_idle_bit = OMAP3430ES2_ST_HSOTGUSB_IDLE_SHIFT,
3001 .idlest_stdby_bit = OMAP3430ES2_ST_HSOTGUSB_STDBY_SHIFT
3002 },
3003 },
3004 .masters = omap3xxx_usbhsotg_masters,
3005 .masters_cnt = ARRAY_SIZE(omap3xxx_usbhsotg_masters),
3006 .slaves = omap3xxx_usbhsotg_slaves,
3007 .slaves_cnt = ARRAY_SIZE(omap3xxx_usbhsotg_slaves),
3008 .class = &usbotg_class,
3009
3010 /*
3011 * Erratum ID: i479 idle_req / idle_ack mechanism potentially
3012 * broken when autoidle is enabled
3013 * workaround is to disable the autoidle bit at module level.
3014 */
3015 .flags = HWMOD_NO_OCP_AUTOIDLE | HWMOD_SWSUP_SIDLE
3016 | HWMOD_SWSUP_MSTANDBY,
3017 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
3018 };
3019
3020 /* usb_otg_hs */
3021 static struct omap_hwmod_irq_info am35xx_usbhsotg_mpu_irqs[] = {
3022
3023 { .name = "mc", .irq = 71 },
3024 { .irq = -1 }
3025 };
3026
3027 static struct omap_hwmod_class am35xx_usbotg_class = {
3028 .name = "am35xx_usbotg",
3029 .sysc = NULL,
3030 };
3031
3032 static struct omap_hwmod am35xx_usbhsotg_hwmod = {
3033 .name = "am35x_otg_hs",
3034 .mpu_irqs = am35xx_usbhsotg_mpu_irqs,
3035 .main_clk = NULL,
3036 .prcm = {
3037 .omap2 = {
3038 },
3039 },
3040 .masters = am35xx_usbhsotg_masters,
3041 .masters_cnt = ARRAY_SIZE(am35xx_usbhsotg_masters),
3042 .slaves = am35xx_usbhsotg_slaves,
3043 .slaves_cnt = ARRAY_SIZE(am35xx_usbhsotg_slaves),
3044 .class = &am35xx_usbotg_class,
3045 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES3_1)
3046 };
3047
3048 /* MMC/SD/SDIO common */
3049
3050 static struct omap_hwmod_class_sysconfig omap34xx_mmc_sysc = {
3051 .rev_offs = 0x1fc,
3052 .sysc_offs = 0x10,
3053 .syss_offs = 0x14,
3054 .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
3055 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
3056 SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
3057 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
3058 .sysc_fields = &omap_hwmod_sysc_type1,
3059 };
3060
3061 static struct omap_hwmod_class omap34xx_mmc_class = {
3062 .name = "mmc",
3063 .sysc = &omap34xx_mmc_sysc,
3064 };
3065
3066 /* MMC/SD/SDIO1 */
3067
3068 static struct omap_hwmod_irq_info omap34xx_mmc1_mpu_irqs[] = {
3069 { .irq = 83, },
3070 { .irq = -1 }
3071 };
3072
3073 static struct omap_hwmod_dma_info omap34xx_mmc1_sdma_reqs[] = {
3074 { .name = "tx", .dma_req = 61, },
3075 { .name = "rx", .dma_req = 62, },
3076 { .dma_req = -1 }
3077 };
3078
3079 static struct omap_hwmod_opt_clk omap34xx_mmc1_opt_clks[] = {
3080 { .role = "dbck", .clk = "omap_32k_fck", },
3081 };
3082
3083 static struct omap_hwmod_ocp_if *omap3xxx_mmc1_slaves[] = {
3084 &omap3xxx_l4_core__mmc1,
3085 };
3086
3087 static struct omap_mmc_dev_attr mmc1_dev_attr = {
3088 .flags = OMAP_HSMMC_SUPPORTS_DUAL_VOLT,
3089 };
3090
3091 static struct omap_hwmod omap3xxx_mmc1_hwmod = {
3092 .name = "mmc1",
3093 .mpu_irqs = omap34xx_mmc1_mpu_irqs,
3094 .sdma_reqs = omap34xx_mmc1_sdma_reqs,
3095 .opt_clks = omap34xx_mmc1_opt_clks,
3096 .opt_clks_cnt = ARRAY_SIZE(omap34xx_mmc1_opt_clks),
3097 .main_clk = "mmchs1_fck",
3098 .prcm = {
3099 .omap2 = {
3100 .module_offs = CORE_MOD,
3101 .prcm_reg_id = 1,
3102 .module_bit = OMAP3430_EN_MMC1_SHIFT,
3103 .idlest_reg_id = 1,
3104 .idlest_idle_bit = OMAP3430_ST_MMC1_SHIFT,
3105 },
3106 },
3107 .dev_attr = &mmc1_dev_attr,
3108 .slaves = omap3xxx_mmc1_slaves,
3109 .slaves_cnt = ARRAY_SIZE(omap3xxx_mmc1_slaves),
3110 .class = &omap34xx_mmc_class,
3111 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
3112 };
3113
3114 /* MMC/SD/SDIO2 */
3115
3116 static struct omap_hwmod_irq_info omap34xx_mmc2_mpu_irqs[] = {
3117 { .irq = INT_24XX_MMC2_IRQ, },
3118 { .irq = -1 }
3119 };
3120
3121 static struct omap_hwmod_dma_info omap34xx_mmc2_sdma_reqs[] = {
3122 { .name = "tx", .dma_req = 47, },
3123 { .name = "rx", .dma_req = 48, },
3124 { .dma_req = -1 }
3125 };
3126
3127 static struct omap_hwmod_opt_clk omap34xx_mmc2_opt_clks[] = {
3128 { .role = "dbck", .clk = "omap_32k_fck", },
3129 };
3130
3131 static struct omap_hwmod_ocp_if *omap3xxx_mmc2_slaves[] = {
3132 &omap3xxx_l4_core__mmc2,
3133 };
3134
3135 static struct omap_hwmod omap3xxx_mmc2_hwmod = {
3136 .name = "mmc2",
3137 .mpu_irqs = omap34xx_mmc2_mpu_irqs,
3138 .sdma_reqs = omap34xx_mmc2_sdma_reqs,
3139 .opt_clks = omap34xx_mmc2_opt_clks,
3140 .opt_clks_cnt = ARRAY_SIZE(omap34xx_mmc2_opt_clks),
3141 .main_clk = "mmchs2_fck",
3142 .prcm = {
3143 .omap2 = {
3144 .module_offs = CORE_MOD,
3145 .prcm_reg_id = 1,
3146 .module_bit = OMAP3430_EN_MMC2_SHIFT,
3147 .idlest_reg_id = 1,
3148 .idlest_idle_bit = OMAP3430_ST_MMC2_SHIFT,
3149 },
3150 },
3151 .slaves = omap3xxx_mmc2_slaves,
3152 .slaves_cnt = ARRAY_SIZE(omap3xxx_mmc2_slaves),
3153 .class = &omap34xx_mmc_class,
3154 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
3155 };
3156
3157 /* MMC/SD/SDIO3 */
3158
3159 static struct omap_hwmod_irq_info omap34xx_mmc3_mpu_irqs[] = {
3160 { .irq = 94, },
3161 { .irq = -1 }
3162 };
3163
3164 static struct omap_hwmod_dma_info omap34xx_mmc3_sdma_reqs[] = {
3165 { .name = "tx", .dma_req = 77, },
3166 { .name = "rx", .dma_req = 78, },
3167 { .dma_req = -1 }
3168 };
3169
3170 static struct omap_hwmod_opt_clk omap34xx_mmc3_opt_clks[] = {
3171 { .role = "dbck", .clk = "omap_32k_fck", },
3172 };
3173
3174 static struct omap_hwmod_ocp_if *omap3xxx_mmc3_slaves[] = {
3175 &omap3xxx_l4_core__mmc3,
3176 };
3177
3178 static struct omap_hwmod omap3xxx_mmc3_hwmod = {
3179 .name = "mmc3",
3180 .mpu_irqs = omap34xx_mmc3_mpu_irqs,
3181 .sdma_reqs = omap34xx_mmc3_sdma_reqs,
3182 .opt_clks = omap34xx_mmc3_opt_clks,
3183 .opt_clks_cnt = ARRAY_SIZE(omap34xx_mmc3_opt_clks),
3184 .main_clk = "mmchs3_fck",
3185 .prcm = {
3186 .omap2 = {
3187 .prcm_reg_id = 1,
3188 .module_bit = OMAP3430_EN_MMC3_SHIFT,
3189 .idlest_reg_id = 1,
3190 .idlest_idle_bit = OMAP3430_ST_MMC3_SHIFT,
3191 },
3192 },
3193 .slaves = omap3xxx_mmc3_slaves,
3194 .slaves_cnt = ARRAY_SIZE(omap3xxx_mmc3_slaves),
3195 .class = &omap34xx_mmc_class,
3196 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
3197 };
3198
3199 static __initdata struct omap_hwmod *omap3xxx_hwmods[] = {
3200 &omap3xxx_l3_main_hwmod,
3201 &omap3xxx_l4_core_hwmod,
3202 &omap3xxx_l4_per_hwmod,
3203 &omap3xxx_l4_wkup_hwmod,
3204 &omap3xxx_mmc1_hwmod,
3205 &omap3xxx_mmc2_hwmod,
3206 &omap3xxx_mmc3_hwmod,
3207 &omap3xxx_mpu_hwmod,
3208 &omap3xxx_iva_hwmod,
3209
3210 &omap3xxx_timer1_hwmod,
3211 &omap3xxx_timer2_hwmod,
3212 &omap3xxx_timer3_hwmod,
3213 &omap3xxx_timer4_hwmod,
3214 &omap3xxx_timer5_hwmod,
3215 &omap3xxx_timer6_hwmod,
3216 &omap3xxx_timer7_hwmod,
3217 &omap3xxx_timer8_hwmod,
3218 &omap3xxx_timer9_hwmod,
3219 &omap3xxx_timer10_hwmod,
3220 &omap3xxx_timer11_hwmod,
3221 &omap3xxx_timer12_hwmod,
3222
3223 &omap3xxx_wd_timer2_hwmod,
3224 &omap3xxx_uart1_hwmod,
3225 &omap3xxx_uart2_hwmod,
3226 &omap3xxx_uart3_hwmod,
3227 &omap3xxx_uart4_hwmod,
3228 /* dss class */
3229 &omap3430es1_dss_core_hwmod,
3230 &omap3xxx_dss_core_hwmod,
3231 &omap3xxx_dss_dispc_hwmod,
3232 &omap3xxx_dss_dsi1_hwmod,
3233 &omap3xxx_dss_rfbi_hwmod,
3234 &omap3xxx_dss_venc_hwmod,
3235
3236 /* i2c class */
3237 &omap3xxx_i2c1_hwmod,
3238 &omap3xxx_i2c2_hwmod,
3239 &omap3xxx_i2c3_hwmod,
3240 &omap34xx_sr1_hwmod,
3241 &omap34xx_sr2_hwmod,
3242 &omap36xx_sr1_hwmod,
3243 &omap36xx_sr2_hwmod,
3244
3245
3246 /* gpio class */
3247 &omap3xxx_gpio1_hwmod,
3248 &omap3xxx_gpio2_hwmod,
3249 &omap3xxx_gpio3_hwmod,
3250 &omap3xxx_gpio4_hwmod,
3251 &omap3xxx_gpio5_hwmod,
3252 &omap3xxx_gpio6_hwmod,
3253
3254 /* dma_system class*/
3255 &omap3xxx_dma_system_hwmod,
3256
3257 /* mcbsp class */
3258 &omap3xxx_mcbsp1_hwmod,
3259 &omap3xxx_mcbsp2_hwmod,
3260 &omap3xxx_mcbsp3_hwmod,
3261 &omap3xxx_mcbsp4_hwmod,
3262 &omap3xxx_mcbsp5_hwmod,
3263 &omap3xxx_mcbsp2_sidetone_hwmod,
3264 &omap3xxx_mcbsp3_sidetone_hwmod,
3265
3266 /* mailbox class */
3267 &omap3xxx_mailbox_hwmod,
3268
3269 /* mcspi class */
3270 &omap34xx_mcspi1,
3271 &omap34xx_mcspi2,
3272 &omap34xx_mcspi3,
3273 &omap34xx_mcspi4,
3274
3275 /* usbotg class */
3276 &omap3xxx_usbhsotg_hwmod,
3277
3278 /* usbotg for am35x */
3279 &am35xx_usbhsotg_hwmod,
3280
3281 NULL,
3282 };
3283
3284 int __init omap3xxx_hwmod_init(void)
3285 {
3286 return omap_hwmod_register(omap3xxx_hwmods);
3287 }
Linus' kernel tree