2 * Driver for the NVIDIA Tegra pinmux
4 * Copyright (c) 2011, NVIDIA CORPORATION. All rights reserved.
7 * Copyright (C) 2010 Google, Inc.
8 * Copyright (C) 2010 NVIDIA Corporation
9 * Copyright (C) 2009-2011 ST-Ericsson AB
11 * This program is free software; you can redistribute it and/or modify it
12 * under the terms and conditions of the GNU General Public License,
13 * version 2, as published by the Free Software Foundation.
15 * This program is distributed in the hope it will be useful, but WITHOUT
16 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
17 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
21 #include <linux/err.h>
22 #include <linux/init.h>
24 #include <linux/module.h>
25 #include <linux/of_device.h>
26 #include <linux/pinctrl/pinctrl.h>
27 #include <linux/pinctrl/pinmux.h>
28 #include <linux/pinctrl/pinconf.h>
30 #include <mach/pinconf-tegra.h>
32 #include "pinctrl-tegra.h"
34 #define DRIVER_NAME "tegra-pinmux-disabled"
38 struct pinctrl_dev
*pctl
;
40 const struct tegra_pinctrl_soc_data
*soc
;
46 static inline u32
pmx_readl(struct tegra_pmx
*pmx
, u32 bank
, u32 reg
)
48 return readl(pmx
->regs
[bank
] + reg
);
51 static inline void pmx_writel(struct tegra_pmx
*pmx
, u32 val
, u32 bank
, u32 reg
)
53 writel(val
, pmx
->regs
[bank
] + reg
);
56 static int tegra_pinctrl_list_groups(struct pinctrl_dev
*pctldev
,
59 struct tegra_pmx
*pmx
= pinctrl_dev_get_drvdata(pctldev
);
61 if (group
>= pmx
->soc
->ngroups
)
67 static const char *tegra_pinctrl_get_group_name(struct pinctrl_dev
*pctldev
,
70 struct tegra_pmx
*pmx
= pinctrl_dev_get_drvdata(pctldev
);
72 if (group
>= pmx
->soc
->ngroups
)
75 return pmx
->soc
->groups
[group
].name
;
78 static int tegra_pinctrl_get_group_pins(struct pinctrl_dev
*pctldev
,
80 const unsigned **pins
,
83 struct tegra_pmx
*pmx
= pinctrl_dev_get_drvdata(pctldev
);
85 if (group
>= pmx
->soc
->ngroups
)
88 *pins
= pmx
->soc
->groups
[group
].pins
;
89 *num_pins
= pmx
->soc
->groups
[group
].npins
;
94 static void tegra_pinctrl_pin_dbg_show(struct pinctrl_dev
*pctldev
,
98 seq_printf(s
, " " DRIVER_NAME
);
101 static struct pinctrl_ops tegra_pinctrl_ops
= {
102 .list_groups
= tegra_pinctrl_list_groups
,
103 .get_group_name
= tegra_pinctrl_get_group_name
,
104 .get_group_pins
= tegra_pinctrl_get_group_pins
,
105 .pin_dbg_show
= tegra_pinctrl_pin_dbg_show
,
108 static int tegra_pinctrl_list_funcs(struct pinctrl_dev
*pctldev
,
111 struct tegra_pmx
*pmx
= pinctrl_dev_get_drvdata(pctldev
);
113 if (function
>= pmx
->soc
->nfunctions
)
119 static const char *tegra_pinctrl_get_func_name(struct pinctrl_dev
*pctldev
,
122 struct tegra_pmx
*pmx
= pinctrl_dev_get_drvdata(pctldev
);
124 if (function
>= pmx
->soc
->nfunctions
)
127 return pmx
->soc
->functions
[function
].name
;
130 static int tegra_pinctrl_get_func_groups(struct pinctrl_dev
*pctldev
,
132 const char * const **groups
,
133 unsigned * const num_groups
)
135 struct tegra_pmx
*pmx
= pinctrl_dev_get_drvdata(pctldev
);
137 if (function
>= pmx
->soc
->nfunctions
)
140 *groups
= pmx
->soc
->functions
[function
].groups
;
141 *num_groups
= pmx
->soc
->functions
[function
].ngroups
;
146 static int tegra_pinctrl_enable(struct pinctrl_dev
*pctldev
, unsigned function
,
149 struct tegra_pmx
*pmx
= pinctrl_dev_get_drvdata(pctldev
);
150 const struct tegra_pingroup
*g
;
154 if (group
>= pmx
->soc
->ngroups
)
156 g
= &pmx
->soc
->groups
[group
];
161 for (i
= 0; i
< ARRAY_SIZE(g
->funcs
); i
++) {
162 if (g
->funcs
[i
] == function
)
165 if (i
== ARRAY_SIZE(g
->funcs
))
168 val
= pmx_readl(pmx
, g
->mux_bank
, g
->mux_reg
);
169 val
&= ~(0x3 << g
->mux_bit
);
170 val
|= i
<< g
->mux_bit
;
171 pmx_writel(pmx
, val
, g
->mux_bank
, g
->mux_reg
);
176 static void tegra_pinctrl_disable(struct pinctrl_dev
*pctldev
,
177 unsigned function
, unsigned group
)
179 struct tegra_pmx
*pmx
= pinctrl_dev_get_drvdata(pctldev
);
180 const struct tegra_pingroup
*g
;
183 if (group
>= pmx
->soc
->ngroups
)
185 g
= &pmx
->soc
->groups
[group
];
190 val
= pmx_readl(pmx
, g
->mux_bank
, g
->mux_reg
);
191 val
&= ~(0x3 << g
->mux_bit
);
192 val
|= g
->func_safe
<< g
->mux_bit
;
193 pmx_writel(pmx
, val
, g
->mux_bank
, g
->mux_reg
);
196 static struct pinmux_ops tegra_pinmux_ops
= {
197 .list_functions
= tegra_pinctrl_list_funcs
,
198 .get_function_name
= tegra_pinctrl_get_func_name
,
199 .get_function_groups
= tegra_pinctrl_get_func_groups
,
200 .enable
= tegra_pinctrl_enable
,
201 .disable
= tegra_pinctrl_disable
,
204 static int tegra_pinconf_reg(struct tegra_pmx
*pmx
,
205 const struct tegra_pingroup
*g
,
206 enum tegra_pinconf_param param
,
207 s8
*bank
, s16
*reg
, s8
*bit
, s8
*width
)
210 case TEGRA_PINCONF_PARAM_PULL
:
211 *bank
= g
->pupd_bank
;
216 case TEGRA_PINCONF_PARAM_TRISTATE
:
222 case TEGRA_PINCONF_PARAM_ENABLE_INPUT
:
223 *bank
= g
->einput_bank
;
224 *reg
= g
->einput_reg
;
225 *bit
= g
->einput_bit
;
228 case TEGRA_PINCONF_PARAM_OPEN_DRAIN
:
229 *bank
= g
->odrain_bank
;
230 *reg
= g
->odrain_reg
;
231 *bit
= g
->odrain_bit
;
234 case TEGRA_PINCONF_PARAM_LOCK
:
235 *bank
= g
->lock_bank
;
240 case TEGRA_PINCONF_PARAM_IORESET
:
241 *bank
= g
->ioreset_bank
;
242 *reg
= g
->ioreset_reg
;
243 *bit
= g
->ioreset_bit
;
246 case TEGRA_PINCONF_PARAM_HIGH_SPEED_MODE
:
252 case TEGRA_PINCONF_PARAM_SCHMITT
:
255 *bit
= g
->schmitt_bit
;
258 case TEGRA_PINCONF_PARAM_LOW_POWER_MODE
:
264 case TEGRA_PINCONF_PARAM_DRIVE_DOWN_STRENGTH
:
268 *width
= g
->drvdn_width
;
270 case TEGRA_PINCONF_PARAM_DRIVE_UP_STRENGTH
:
274 *width
= g
->drvup_width
;
276 case TEGRA_PINCONF_PARAM_SLEW_RATE_FALLING
:
280 *width
= g
->slwf_width
;
282 case TEGRA_PINCONF_PARAM_SLEW_RATE_RISING
:
286 *width
= g
->slwr_width
;
289 dev_err(pmx
->dev
, "Invalid config param %04x\n", param
);
295 "Config param %04x not supported on group %s\n",
303 static int tegra_pinconf_get(struct pinctrl_dev
*pctldev
,
304 unsigned pin
, unsigned long *config
)
309 static int tegra_pinconf_set(struct pinctrl_dev
*pctldev
,
310 unsigned pin
, unsigned long config
)
315 static int tegra_pinconf_group_get(struct pinctrl_dev
*pctldev
,
316 unsigned group
, unsigned long *config
)
318 struct tegra_pmx
*pmx
= pinctrl_dev_get_drvdata(pctldev
);
319 enum tegra_pinconf_param param
= TEGRA_PINCONF_UNPACK_PARAM(*config
);
321 const struct tegra_pingroup
*g
;
327 if (group
>= pmx
->soc
->ngroups
)
329 g
= &pmx
->soc
->groups
[group
];
331 ret
= tegra_pinconf_reg(pmx
, g
, param
, &bank
, ®
, &bit
, &width
);
335 val
= pmx_readl(pmx
, bank
, reg
);
336 mask
= (1 << width
) - 1;
337 arg
= (val
>> bit
) & mask
;
339 *config
= TEGRA_PINCONF_PACK(param
, arg
);
344 static int tegra_pinconf_group_set(struct pinctrl_dev
*pctldev
,
345 unsigned group
, unsigned long config
)
347 struct tegra_pmx
*pmx
= pinctrl_dev_get_drvdata(pctldev
);
348 enum tegra_pinconf_param param
= TEGRA_PINCONF_UNPACK_PARAM(config
);
349 u16 arg
= TEGRA_PINCONF_UNPACK_ARG(config
);
350 const struct tegra_pingroup
*g
;
356 if (group
>= pmx
->soc
->ngroups
)
358 g
= &pmx
->soc
->groups
[group
];
360 ret
= tegra_pinconf_reg(pmx
, g
, param
, &bank
, ®
, &bit
, &width
);
364 val
= pmx_readl(pmx
, bank
, reg
);
366 /* LOCK can't be cleared */
367 if (param
== TEGRA_PINCONF_PARAM_LOCK
) {
368 if ((val
& BIT(bit
)) && !arg
)
372 /* Special-case Boolean values; allow any non-zero as true */
376 /* Range-check user-supplied value */
377 mask
= (1 << width
) - 1;
381 /* Update register */
382 val
&= ~(mask
<< bit
);
384 pmx_writel(pmx
, val
, bank
, reg
);
389 static void tegra_pinconf_dbg_show(struct pinctrl_dev
*pctldev
,
390 struct seq_file
*s
, unsigned offset
)
394 static void tegra_pinconf_group_dbg_show(struct pinctrl_dev
*pctldev
,
395 struct seq_file
*s
, unsigned selector
)
399 struct pinconf_ops tegra_pinconf_ops
= {
400 .pin_config_get
= tegra_pinconf_get
,
401 .pin_config_set
= tegra_pinconf_set
,
402 .pin_config_group_get
= tegra_pinconf_group_get
,
403 .pin_config_group_set
= tegra_pinconf_group_set
,
404 .pin_config_dbg_show
= tegra_pinconf_dbg_show
,
405 .pin_config_group_dbg_show
= tegra_pinconf_group_dbg_show
,
408 static struct pinctrl_gpio_range tegra_pinctrl_gpio_range
= {
409 .name
= "Tegra GPIOs",
414 static struct pinctrl_desc tegra_pinctrl_desc
= {
416 .pctlops
= &tegra_pinctrl_ops
,
417 .pmxops
= &tegra_pinmux_ops
,
418 .confops
= &tegra_pinconf_ops
,
419 .owner
= THIS_MODULE
,
422 static struct of_device_id tegra_pinctrl_of_match
[] __devinitdata
= {
423 #ifdef CONFIG_PINCTRL_TEGRA20
425 .compatible
= "nvidia,tegra20-pinmux-disabled",
426 .data
= tegra20_pinctrl_init
,
429 #ifdef CONFIG_PINCTRL_TEGRA30
431 .compatible
= "nvidia,tegra30-pinmux-disabled",
432 .data
= tegra30_pinctrl_init
,
438 static int __devinit
tegra_pinctrl_probe(struct platform_device
*pdev
)
440 const struct of_device_id
*match
;
441 tegra_pinctrl_soc_initf initf
= NULL
;
442 struct tegra_pmx
*pmx
;
443 struct resource
*res
;
446 match
= of_match_device(tegra_pinctrl_of_match
, &pdev
->dev
);
448 initf
= (tegra_pinctrl_soc_initf
)match
->data
;
449 #ifdef CONFIG_PINCTRL_TEGRA20
451 initf
= tegra20_pinctrl_init
;
455 "Could not determine SoC-specific init func\n");
459 pmx
= devm_kzalloc(&pdev
->dev
, sizeof(*pmx
), GFP_KERNEL
);
461 dev_err(&pdev
->dev
, "Can't alloc tegra_pmx\n");
464 pmx
->dev
= &pdev
->dev
;
468 tegra_pinctrl_gpio_range
.npins
= pmx
->soc
->ngpios
;
469 tegra_pinctrl_desc
.pins
= pmx
->soc
->pins
;
470 tegra_pinctrl_desc
.npins
= pmx
->soc
->npins
;
473 res
= platform_get_resource(pdev
, IORESOURCE_MEM
, i
);
479 pmx
->regs
= devm_kzalloc(&pdev
->dev
, pmx
->nbanks
* sizeof(*pmx
->regs
),
482 dev_err(&pdev
->dev
, "Can't alloc regs pointer\n");
486 for (i
= 0; i
< pmx
->nbanks
; i
++) {
487 res
= platform_get_resource(pdev
, IORESOURCE_MEM
, i
);
489 dev_err(&pdev
->dev
, "Missing MEM resource\n");
493 if (!devm_request_mem_region(&pdev
->dev
, res
->start
,
495 dev_name(&pdev
->dev
))) {
497 "Couldn't request MEM resource %d\n", i
);
501 pmx
->regs
[i
] = devm_ioremap(&pdev
->dev
, res
->start
,
504 dev_err(&pdev
->dev
, "Couldn't ioremap regs %d\n", i
);
509 pmx
->pctl
= pinctrl_register(&tegra_pinctrl_desc
, &pdev
->dev
, pmx
);
510 if (IS_ERR(pmx
->pctl
)) {
511 dev_err(&pdev
->dev
, "Couldn't register pinctrl driver\n");
512 return PTR_ERR(pmx
->pctl
);
515 pinctrl_add_gpio_range(pmx
->pctl
, &tegra_pinctrl_gpio_range
);
517 platform_set_drvdata(pdev
, pmx
);
519 dev_dbg(&pdev
->dev
, "Probed Tegra pinctrl driver\n");
524 static int __devexit
tegra_pinctrl_remove(struct platform_device
*pdev
)
526 struct tegra_pmx
*pmx
= platform_get_drvdata(pdev
);
528 pinctrl_remove_gpio_range(pmx
->pctl
, &tegra_pinctrl_gpio_range
);
529 pinctrl_unregister(pmx
->pctl
);
534 static struct platform_driver tegra_pinctrl_driver
= {
537 .owner
= THIS_MODULE
,
538 .of_match_table
= tegra_pinctrl_of_match
,
540 .probe
= tegra_pinctrl_probe
,
541 .remove
= __devexit_p(tegra_pinctrl_remove
),
544 static int __init
tegra_pinctrl_init(void)
546 return platform_driver_register(&tegra_pinctrl_driver
);
548 arch_initcall(tegra_pinctrl_init
);
550 static void __exit
tegra_pinctrl_exit(void)
552 platform_driver_unregister(&tegra_pinctrl_driver
);
554 module_exit(tegra_pinctrl_exit
);
556 MODULE_AUTHOR("Stephen Warren <swarren@nvidia.com>");
557 MODULE_DESCRIPTION("NVIDIA Tegra pinctrl driver");
558 MODULE_LICENSE("GPL v2");
559 MODULE_DEVICE_TABLE(of
, tegra_pinctrl_of_match
);