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[PATCH] libata: rename ata_down_sata_spd_limit() and friends
[linux-2.6.git] / drivers / scsi / sata_sil24.c
blob8c167250f4c9e82ad9cefcc4099c4c14dd4339a7
1 /*
2 * sata_sil24.c - Driver for Silicon Image 3124/3132 SATA-2 controllers
3 *
4 * Copyright 2005 Tejun Heo
5 *
6 * Based on preview driver from Silicon Image.
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the
10 * Free Software Foundation; either version 2, or (at your option) any
11 * later version.
12 *
13 * This program is distributed in the hope that it will be useful, but
14 * WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
16 * General Public License for more details.
17 *
18 */
19
20 #include <linux/kernel.h>
21 #include <linux/module.h>
22 #include <linux/pci.h>
23 #include <linux/blkdev.h>
24 #include <linux/delay.h>
25 #include <linux/interrupt.h>
26 #include <linux/dma-mapping.h>
27 #include <linux/device.h>
28 #include <scsi/scsi_host.h>
29 #include <scsi/scsi_cmnd.h>
30 #include <linux/libata.h>
31 #include <asm/io.h>
32
33 #define DRV_NAME "sata_sil24"
34 #define DRV_VERSION "0.24"
35
36 /*
37 * Port request block (PRB) 32 bytes
38 */
39 struct sil24_prb {
40 u16 ctrl;
41 u16 prot;
42 u32 rx_cnt;
43 u8 fis[6 * 4];
44 };
45
46 /*
47 * Scatter gather entry (SGE) 16 bytes
48 */
49 struct sil24_sge {
50 u64 addr;
51 u32 cnt;
52 u32 flags;
53 };
54
55 /*
56 * Port multiplier
57 */
58 struct sil24_port_multiplier {
59 u32 diag;
60 u32 sactive;
61 };
62
63 enum {
64 /*
65 * Global controller registers (128 bytes @ BAR0)
66 */
67 /* 32 bit regs */
68 HOST_SLOT_STAT = 0x00, /* 32 bit slot stat * 4 */
69 HOST_CTRL = 0x40,
70 HOST_IRQ_STAT = 0x44,
71 HOST_PHY_CFG = 0x48,
72 HOST_BIST_CTRL = 0x50,
73 HOST_BIST_PTRN = 0x54,
74 HOST_BIST_STAT = 0x58,
75 HOST_MEM_BIST_STAT = 0x5c,
76 HOST_FLASH_CMD = 0x70,
77 /* 8 bit regs */
78 HOST_FLASH_DATA = 0x74,
79 HOST_TRANSITION_DETECT = 0x75,
80 HOST_GPIO_CTRL = 0x76,
81 HOST_I2C_ADDR = 0x78, /* 32 bit */
82 HOST_I2C_DATA = 0x7c,
83 HOST_I2C_XFER_CNT = 0x7e,
84 HOST_I2C_CTRL = 0x7f,
85
86 /* HOST_SLOT_STAT bits */
87 HOST_SSTAT_ATTN = (1 << 31),
88
89 /* HOST_CTRL bits */
90 HOST_CTRL_M66EN = (1 << 16), /* M66EN PCI bus signal */
91 HOST_CTRL_TRDY = (1 << 17), /* latched PCI TRDY */
92 HOST_CTRL_STOP = (1 << 18), /* latched PCI STOP */
93 HOST_CTRL_DEVSEL = (1 << 19), /* latched PCI DEVSEL */
94 HOST_CTRL_REQ64 = (1 << 20), /* latched PCI REQ64 */
95
96 /*
97 * Port registers
98 * (8192 bytes @ +0x0000, +0x2000, +0x4000 and +0x6000 @ BAR2)
99 */
100 PORT_REGS_SIZE = 0x2000,
101 PORT_PRB = 0x0000, /* (32 bytes PRB + 16 bytes SGEs * 6) * 31 (3968 bytes) */
102
103 PORT_PM = 0x0f80, /* 8 bytes PM * 16 (128 bytes) */
104 /* 32 bit regs */
105 PORT_CTRL_STAT = 0x1000, /* write: ctrl-set, read: stat */
106 PORT_CTRL_CLR = 0x1004, /* write: ctrl-clear */
107 PORT_IRQ_STAT = 0x1008, /* high: status, low: interrupt */
108 PORT_IRQ_ENABLE_SET = 0x1010, /* write: enable-set */
109 PORT_IRQ_ENABLE_CLR = 0x1014, /* write: enable-clear */
110 PORT_ACTIVATE_UPPER_ADDR= 0x101c,
111 PORT_EXEC_FIFO = 0x1020, /* command execution fifo */
112 PORT_CMD_ERR = 0x1024, /* command error number */
113 PORT_FIS_CFG = 0x1028,
114 PORT_FIFO_THRES = 0x102c,
115 /* 16 bit regs */
116 PORT_DECODE_ERR_CNT = 0x1040,
117 PORT_DECODE_ERR_THRESH = 0x1042,
118 PORT_CRC_ERR_CNT = 0x1044,
119 PORT_CRC_ERR_THRESH = 0x1046,
120 PORT_HSHK_ERR_CNT = 0x1048,
121 PORT_HSHK_ERR_THRESH = 0x104a,
122 /* 32 bit regs */
123 PORT_PHY_CFG = 0x1050,
124 PORT_SLOT_STAT = 0x1800,
125 PORT_CMD_ACTIVATE = 0x1c00, /* 64 bit cmd activate * 31 (248 bytes) */
126 PORT_EXEC_DIAG = 0x1e00, /* 32bit exec diag * 16 (64 bytes, 0-10 used on 3124) */
127 PORT_PSD_DIAG = 0x1e40, /* 32bit psd diag * 16 (64 bytes, 0-8 used on 3124) */
128 PORT_SCONTROL = 0x1f00,
129 PORT_SSTATUS = 0x1f04,
130 PORT_SERROR = 0x1f08,
131 PORT_SACTIVE = 0x1f0c,
132
133 /* PORT_CTRL_STAT bits */
134 PORT_CS_PORT_RST = (1 << 0), /* port reset */
135 PORT_CS_DEV_RST = (1 << 1), /* device reset */
136 PORT_CS_INIT = (1 << 2), /* port initialize */
137 PORT_CS_IRQ_WOC = (1 << 3), /* interrupt write one to clear */
138 PORT_CS_CDB16 = (1 << 5), /* 0=12b cdb, 1=16b cdb */
139 PORT_CS_RESUME = (1 << 6), /* port resume */
140 PORT_CS_32BIT_ACTV = (1 << 10), /* 32-bit activation */
141 PORT_CS_PM_EN = (1 << 13), /* port multiplier enable */
142 PORT_CS_RDY = (1 << 31), /* port ready to accept commands */
143
144 /* PORT_IRQ_STAT/ENABLE_SET/CLR */
145 /* bits[11:0] are masked */
146 PORT_IRQ_COMPLETE = (1 << 0), /* command(s) completed */
147 PORT_IRQ_ERROR = (1 << 1), /* command execution error */
148 PORT_IRQ_PORTRDY_CHG = (1 << 2), /* port ready change */
149 PORT_IRQ_PWR_CHG = (1 << 3), /* power management change */
150 PORT_IRQ_PHYRDY_CHG = (1 << 4), /* PHY ready change */
151 PORT_IRQ_COMWAKE = (1 << 5), /* COMWAKE received */
152 PORT_IRQ_UNK_FIS = (1 << 6), /* unknown FIS received */
153 PORT_IRQ_DEV_XCHG = (1 << 7), /* device exchanged */
154 PORT_IRQ_8B10B = (1 << 8), /* 8b/10b decode error threshold */
155 PORT_IRQ_CRC = (1 << 9), /* CRC error threshold */
156 PORT_IRQ_HANDSHAKE = (1 << 10), /* handshake error threshold */
157 PORT_IRQ_SDB_NOTIFY = (1 << 11), /* SDB notify received */
158
159 /* bits[27:16] are unmasked (raw) */
160 PORT_IRQ_RAW_SHIFT = 16,
161 PORT_IRQ_MASKED_MASK = 0x7ff,
162 PORT_IRQ_RAW_MASK = (0x7ff << PORT_IRQ_RAW_SHIFT),
163
164 /* ENABLE_SET/CLR specific, intr steering - 2 bit field */
165 PORT_IRQ_STEER_SHIFT = 30,
166 PORT_IRQ_STEER_MASK = (3 << PORT_IRQ_STEER_SHIFT),
167
168 /* PORT_CMD_ERR constants */
169 PORT_CERR_DEV = 1, /* Error bit in D2H Register FIS */
170 PORT_CERR_SDB = 2, /* Error bit in SDB FIS */
171 PORT_CERR_DATA = 3, /* Error in data FIS not detected by dev */
172 PORT_CERR_SEND = 4, /* Initial cmd FIS transmission failure */
173 PORT_CERR_INCONSISTENT = 5, /* Protocol mismatch */
174 PORT_CERR_DIRECTION = 6, /* Data direction mismatch */
175 PORT_CERR_UNDERRUN = 7, /* Ran out of SGEs while writing */
176 PORT_CERR_OVERRUN = 8, /* Ran out of SGEs while reading */
177 PORT_CERR_PKT_PROT = 11, /* DIR invalid in 1st PIO setup of ATAPI */
178 PORT_CERR_SGT_BOUNDARY = 16, /* PLD ecode 00 - SGT not on qword boundary */
179 PORT_CERR_SGT_TGTABRT = 17, /* PLD ecode 01 - target abort */
180 PORT_CERR_SGT_MSTABRT = 18, /* PLD ecode 10 - master abort */
181 PORT_CERR_SGT_PCIPERR = 19, /* PLD ecode 11 - PCI parity err while fetching SGT */
182 PORT_CERR_CMD_BOUNDARY = 24, /* ctrl[15:13] 001 - PRB not on qword boundary */
183 PORT_CERR_CMD_TGTABRT = 25, /* ctrl[15:13] 010 - target abort */
184 PORT_CERR_CMD_MSTABRT = 26, /* ctrl[15:13] 100 - master abort */
185 PORT_CERR_CMD_PCIPERR = 27, /* ctrl[15:13] 110 - PCI parity err while fetching PRB */
186 PORT_CERR_XFR_UNDEF = 32, /* PSD ecode 00 - undefined */
187 PORT_CERR_XFR_TGTABRT = 33, /* PSD ecode 01 - target abort */
188 PORT_CERR_XFR_MSTABRT = 34, /* PSD ecode 10 - master abort */
189 PORT_CERR_XFR_PCIPERR = 35, /* PSD ecode 11 - PCI prity err during transfer */
190 PORT_CERR_SENDSERVICE = 36, /* FIS received while sending service */
191
192 /* bits of PRB control field */
193 PRB_CTRL_PROTOCOL = (1 << 0), /* override def. ATA protocol */
194 PRB_CTRL_PACKET_READ = (1 << 4), /* PACKET cmd read */
195 PRB_CTRL_PACKET_WRITE = (1 << 5), /* PACKET cmd write */
196 PRB_CTRL_NIEN = (1 << 6), /* Mask completion irq */
197 PRB_CTRL_SRST = (1 << 7), /* Soft reset request (ign BSY?) */
198
199 /* PRB protocol field */
200 PRB_PROT_PACKET = (1 << 0),
201 PRB_PROT_TCQ = (1 << 1),
202 PRB_PROT_NCQ = (1 << 2),
203 PRB_PROT_READ = (1 << 3),
204 PRB_PROT_WRITE = (1 << 4),
205 PRB_PROT_TRANSPARENT = (1 << 5),
206
207 /*
208 * Other constants
209 */
210 SGE_TRM = (1 << 31), /* Last SGE in chain */
211 SGE_LNK = (1 << 30), /* linked list
212 Points to SGT, not SGE */
213 SGE_DRD = (1 << 29), /* discard data read (/dev/null)
214 data address ignored */
215
216 /* board id */
217 BID_SIL3124 = 0,
218 BID_SIL3132 = 1,
219 BID_SIL3131 = 2,
220
221 /* host flags */
222 SIL24_COMMON_FLAGS = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
223 ATA_FLAG_MMIO | ATA_FLAG_PIO_DMA,
224 SIL24_FLAG_PCIX_IRQ_WOC = (1 << 24), /* IRQ loss errata on PCI-X */
225
226 IRQ_STAT_4PORTS = 0xf,
227 };
228
229 struct sil24_ata_block {
230 struct sil24_prb prb;
231 struct sil24_sge sge[LIBATA_MAX_PRD];
232 };
233
234 struct sil24_atapi_block {
235 struct sil24_prb prb;
236 u8 cdb[16];
237 struct sil24_sge sge[LIBATA_MAX_PRD - 1];
238 };
239
240 union sil24_cmd_block {
241 struct sil24_ata_block ata;
242 struct sil24_atapi_block atapi;
243 };
244
245 /*
246 * ap->private_data
247 *
248 * The preview driver always returned 0 for status. We emulate it
249 * here from the previous interrupt.
250 */
251 struct sil24_port_priv {
252 union sil24_cmd_block *cmd_block; /* 32 cmd blocks */
253 dma_addr_t cmd_block_dma; /* DMA base addr for them */
254 struct ata_taskfile tf; /* Cached taskfile registers */
255 };
256
257 /* ap->host_set->private_data */
258 struct sil24_host_priv {
259 void __iomem *host_base; /* global controller control (128 bytes @BAR0) */
260 void __iomem *port_base; /* port registers (4 * 8192 bytes @BAR2) */
261 };
262
263 static void sil24_dev_config(struct ata_port *ap, struct ata_device *dev);
264 static u8 sil24_check_status(struct ata_port *ap);
265 static u32 sil24_scr_read(struct ata_port *ap, unsigned sc_reg);
266 static void sil24_scr_write(struct ata_port *ap, unsigned sc_reg, u32 val);
267 static void sil24_tf_read(struct ata_port *ap, struct ata_taskfile *tf);
268 static int sil24_probe_reset(struct ata_port *ap, unsigned int *classes);
269 static void sil24_qc_prep(struct ata_queued_cmd *qc);
270 static unsigned int sil24_qc_issue(struct ata_queued_cmd *qc);
271 static void sil24_irq_clear(struct ata_port *ap);
272 static void sil24_eng_timeout(struct ata_port *ap);
273 static irqreturn_t sil24_interrupt(int irq, void *dev_instance, struct pt_regs *regs);
274 static int sil24_port_start(struct ata_port *ap);
275 static void sil24_port_stop(struct ata_port *ap);
276 static void sil24_host_stop(struct ata_host_set *host_set);
277 static int sil24_init_one(struct pci_dev *pdev, const struct pci_device_id *ent);
278
279 static const struct pci_device_id sil24_pci_tbl[] = {
280 { 0x1095, 0x3124, PCI_ANY_ID, PCI_ANY_ID, 0, 0, BID_SIL3124 },
281 { 0x8086, 0x3124, PCI_ANY_ID, PCI_ANY_ID, 0, 0, BID_SIL3124 },
282 { 0x1095, 0x3132, PCI_ANY_ID, PCI_ANY_ID, 0, 0, BID_SIL3132 },
283 { 0x1095, 0x3131, PCI_ANY_ID, PCI_ANY_ID, 0, 0, BID_SIL3131 },
284 { 0x1095, 0x3531, PCI_ANY_ID, PCI_ANY_ID, 0, 0, BID_SIL3131 },
285 { } /* terminate list */
286 };
287
288 static struct pci_driver sil24_pci_driver = {
289 .name = DRV_NAME,
290 .id_table = sil24_pci_tbl,
291 .probe = sil24_init_one,
292 .remove = ata_pci_remove_one, /* safe? */
293 };
294
295 static struct scsi_host_template sil24_sht = {
296 .module = THIS_MODULE,
297 .name = DRV_NAME,
298 .ioctl = ata_scsi_ioctl,
299 .queuecommand = ata_scsi_queuecmd,
300 .can_queue = ATA_DEF_QUEUE,
301 .this_id = ATA_SHT_THIS_ID,
302 .sg_tablesize = LIBATA_MAX_PRD,
303 .cmd_per_lun = ATA_SHT_CMD_PER_LUN,
304 .emulated = ATA_SHT_EMULATED,
305 .use_clustering = ATA_SHT_USE_CLUSTERING,
306 .proc_name = DRV_NAME,
307 .dma_boundary = ATA_DMA_BOUNDARY,
308 .slave_configure = ata_scsi_slave_config,
309 .bios_param = ata_std_bios_param,
310 };
311
312 static const struct ata_port_operations sil24_ops = {
313 .port_disable = ata_port_disable,
314
315 .dev_config = sil24_dev_config,
316
317 .check_status = sil24_check_status,
318 .check_altstatus = sil24_check_status,
319 .dev_select = ata_noop_dev_select,
320
321 .tf_read = sil24_tf_read,
322
323 .probe_reset = sil24_probe_reset,
324
325 .qc_prep = sil24_qc_prep,
326 .qc_issue = sil24_qc_issue,
327
328 .eng_timeout = sil24_eng_timeout,
329
330 .irq_handler = sil24_interrupt,
331 .irq_clear = sil24_irq_clear,
332
333 .scr_read = sil24_scr_read,
334 .scr_write = sil24_scr_write,
335
336 .port_start = sil24_port_start,
337 .port_stop = sil24_port_stop,
338 .host_stop = sil24_host_stop,
339 };
340
341 /*
342 * Use bits 30-31 of host_flags to encode available port numbers.
343 * Current maxium is 4.
344 */
345 #define SIL24_NPORTS2FLAG(nports) ((((unsigned)(nports) - 1) & 0x3) << 30)
346 #define SIL24_FLAG2NPORTS(flag) ((((flag) >> 30) & 0x3) + 1)
347
348 static struct ata_port_info sil24_port_info[] = {
349 /* sil_3124 */
350 {
351 .sht = &sil24_sht,
352 .host_flags = SIL24_COMMON_FLAGS | SIL24_NPORTS2FLAG(4) |
353 SIL24_FLAG_PCIX_IRQ_WOC,
354 .pio_mask = 0x1f, /* pio0-4 */
355 .mwdma_mask = 0x07, /* mwdma0-2 */
356 .udma_mask = 0x3f, /* udma0-5 */
357 .port_ops = &sil24_ops,
358 },
359 /* sil_3132 */
360 {
361 .sht = &sil24_sht,
362 .host_flags = SIL24_COMMON_FLAGS | SIL24_NPORTS2FLAG(2),
363 .pio_mask = 0x1f, /* pio0-4 */
364 .mwdma_mask = 0x07, /* mwdma0-2 */
365 .udma_mask = 0x3f, /* udma0-5 */
366 .port_ops = &sil24_ops,
367 },
368 /* sil_3131/sil_3531 */
369 {
370 .sht = &sil24_sht,
371 .host_flags = SIL24_COMMON_FLAGS | SIL24_NPORTS2FLAG(1),
372 .pio_mask = 0x1f, /* pio0-4 */
373 .mwdma_mask = 0x07, /* mwdma0-2 */
374 .udma_mask = 0x3f, /* udma0-5 */
375 .port_ops = &sil24_ops,
376 },
377 };
378
379 static void sil24_dev_config(struct ata_port *ap, struct ata_device *dev)
380 {
381 void __iomem *port = (void __iomem *)ap->ioaddr.cmd_addr;
382
383 if (dev->cdb_len == 16)
384 writel(PORT_CS_CDB16, port + PORT_CTRL_STAT);
385 else
386 writel(PORT_CS_CDB16, port + PORT_CTRL_CLR);
387 }
388
389 static inline void sil24_update_tf(struct ata_port *ap)
390 {
391 struct sil24_port_priv *pp = ap->private_data;
392 void __iomem *port = (void __iomem *)ap->ioaddr.cmd_addr;
393 struct sil24_prb __iomem *prb = port;
394 u8 fis[6 * 4];
395
396 memcpy_fromio(fis, prb->fis, 6 * 4);
397 ata_tf_from_fis(fis, &pp->tf);
398 }
399
400 static u8 sil24_check_status(struct ata_port *ap)
401 {
402 struct sil24_port_priv *pp = ap->private_data;
403 return pp->tf.command;
404 }
405
406 static int sil24_scr_map[] = {
407 [SCR_CONTROL] = 0,
408 [SCR_STATUS] = 1,
409 [SCR_ERROR] = 2,
410 [SCR_ACTIVE] = 3,
411 };
412
413 static u32 sil24_scr_read(struct ata_port *ap, unsigned sc_reg)
414 {
415 void __iomem *scr_addr = (void __iomem *)ap->ioaddr.scr_addr;
416 if (sc_reg < ARRAY_SIZE(sil24_scr_map)) {
417 void __iomem *addr;
418 addr = scr_addr + sil24_scr_map[sc_reg] * 4;
419 return readl(scr_addr + sil24_scr_map[sc_reg] * 4);
420 }
421 return 0xffffffffU;
422 }
423
424 static void sil24_scr_write(struct ata_port *ap, unsigned sc_reg, u32 val)
425 {
426 void __iomem *scr_addr = (void __iomem *)ap->ioaddr.scr_addr;
427 if (sc_reg < ARRAY_SIZE(sil24_scr_map)) {
428 void __iomem *addr;
429 addr = scr_addr + sil24_scr_map[sc_reg] * 4;
430 writel(val, scr_addr + sil24_scr_map[sc_reg] * 4);
431 }
432 }
433
434 static void sil24_tf_read(struct ata_port *ap, struct ata_taskfile *tf)
435 {
436 struct sil24_port_priv *pp = ap->private_data;
437 *tf = pp->tf;
438 }
439
440 static int sil24_init_port(struct ata_port *ap)
441 {
442 void __iomem *port = (void __iomem *)ap->ioaddr.cmd_addr;
443 u32 tmp;
444
445 writel(PORT_CS_INIT, port + PORT_CTRL_STAT);
446 ata_wait_register(port + PORT_CTRL_STAT,
447 PORT_CS_INIT, PORT_CS_INIT, 10, 100);
448 tmp = ata_wait_register(port + PORT_CTRL_STAT,
449 PORT_CS_RDY, 0, 10, 100);
450
451 if ((tmp & (PORT_CS_INIT | PORT_CS_RDY)) != PORT_CS_RDY)
452 return -EIO;
453 return 0;
454 }
455
456 static int sil24_softreset(struct ata_port *ap, unsigned int *class)
457 {
458 void __iomem *port = (void __iomem *)ap->ioaddr.cmd_addr;
459 struct sil24_port_priv *pp = ap->private_data;
460 struct sil24_prb *prb = &pp->cmd_block[0].ata.prb;
461 dma_addr_t paddr = pp->cmd_block_dma;
462 u32 mask, irq_enable, irq_stat;
463 const char *reason;
464
465 DPRINTK("ENTER\n");
466
467 if (!sata_dev_present(ap)) {
468 DPRINTK("PHY reports no device\n");
469 *class = ATA_DEV_NONE;
470 goto out;
471 }
472
473 /* temporarily turn off IRQs during SRST */
474 irq_enable = readl(port + PORT_IRQ_ENABLE_SET);
475 writel(irq_enable, port + PORT_IRQ_ENABLE_CLR);
476
477 /* put the port into known state */
478 if (sil24_init_port(ap)) {
479 reason ="port not ready";
480 goto err;
481 }
482
483 /* do SRST */
484 prb->ctrl = cpu_to_le16(PRB_CTRL_SRST);
485 prb->fis[1] = 0; /* no PM yet */
486
487 writel((u32)paddr, port + PORT_CMD_ACTIVATE);
488 writel((u64)paddr >> 32, port + PORT_CMD_ACTIVATE + 4);
489
490 mask = (PORT_IRQ_COMPLETE | PORT_IRQ_ERROR) << PORT_IRQ_RAW_SHIFT;
491 irq_stat = ata_wait_register(port + PORT_IRQ_STAT, mask, 0x0,
492 100, ATA_TMOUT_BOOT / HZ * 1000);
493
494 writel(irq_stat, port + PORT_IRQ_STAT); /* clear IRQs */
495 irq_stat >>= PORT_IRQ_RAW_SHIFT;
496
497 /* restore IRQs */
498 writel(irq_enable, port + PORT_IRQ_ENABLE_SET);
499
500 if (!(irq_stat & PORT_IRQ_COMPLETE)) {
501 if (irq_stat & PORT_IRQ_ERROR)
502 reason = "SRST command error";
503 else
504 reason = "timeout";
505 goto err;
506 }
507
508 sil24_update_tf(ap);
509 *class = ata_dev_classify(&pp->tf);
510
511 if (*class == ATA_DEV_UNKNOWN)
512 *class = ATA_DEV_NONE;
513
514 out:
515 DPRINTK("EXIT, class=%u\n", *class);
516 return 0;
517
518 err:
519 printk(KERN_ERR "ata%u: softreset failed (%s)\n", ap->id, reason);
520 return -EIO;
521 }
522
523 static int sil24_hardreset(struct ata_port *ap, unsigned int *class)
524 {
525 void __iomem *port = (void __iomem *)ap->ioaddr.cmd_addr;
526 const char *reason;
527 int tout_msec;
528 u32 tmp;
529
530 /* sil24 does the right thing(tm) without any protection */
531 sata_set_spd(ap);
532
533 tout_msec = 100;
534 if (sata_dev_present(ap))
535 tout_msec = 5000;
536
537 writel(PORT_CS_DEV_RST, port + PORT_CTRL_STAT);
538 tmp = ata_wait_register(port + PORT_CTRL_STAT,
539 PORT_CS_DEV_RST, PORT_CS_DEV_RST, 10, tout_msec);
540
541 /* SStatus oscillates between zero and valid status for short
542 * duration after DEV_RST, give it time to settle.
543 */
544 msleep(100);
545
546 if (tmp & PORT_CS_DEV_RST) {
547 if (!sata_dev_present(ap))
548 return 0;
549 reason = "link not ready";
550 goto err;
551 }
552
553 if (ata_busy_sleep(ap, ATA_TMOUT_BOOT_QUICK, ATA_TMOUT_BOOT)) {
554 reason = "device not ready";
555 goto err;
556 }
557
558 /* sil24 doesn't report device class code after hardreset,
559 * leave *class alone.
560 */
561 return 0;
562
563 err:
564 printk(KERN_ERR "ata%u: hardreset failed (%s)\n", ap->id, reason);
565 return -EIO;
566 }
567
568 static int sil24_probe_reset(struct ata_port *ap, unsigned int *classes)
569 {
570 return ata_drive_probe_reset(ap, ata_std_probeinit,
571 sil24_softreset, sil24_hardreset,
572 ata_std_postreset, classes);
573 }
574
575 static inline void sil24_fill_sg(struct ata_queued_cmd *qc,
576 struct sil24_sge *sge)
577 {
578 struct scatterlist *sg;
579 unsigned int idx = 0;
580
581 ata_for_each_sg(sg, qc) {
582 sge->addr = cpu_to_le64(sg_dma_address(sg));
583 sge->cnt = cpu_to_le32(sg_dma_len(sg));
584 if (ata_sg_is_last(sg, qc))
585 sge->flags = cpu_to_le32(SGE_TRM);
586 else
587 sge->flags = 0;
588
589 sge++;
590 idx++;
591 }
592 }
593
594 static void sil24_qc_prep(struct ata_queued_cmd *qc)
595 {
596 struct ata_port *ap = qc->ap;
597 struct sil24_port_priv *pp = ap->private_data;
598 union sil24_cmd_block *cb = pp->cmd_block + qc->tag;
599 struct sil24_prb *prb;
600 struct sil24_sge *sge;
601 u16 ctrl = 0;
602
603 switch (qc->tf.protocol) {
604 case ATA_PROT_PIO:
605 case ATA_PROT_DMA:
606 case ATA_PROT_NODATA:
607 prb = &cb->ata.prb;
608 sge = cb->ata.sge;
609 break;
610
611 case ATA_PROT_ATAPI:
612 case ATA_PROT_ATAPI_DMA:
613 case ATA_PROT_ATAPI_NODATA:
614 prb = &cb->atapi.prb;
615 sge = cb->atapi.sge;
616 memset(cb->atapi.cdb, 0, 32);
617 memcpy(cb->atapi.cdb, qc->cdb, qc->dev->cdb_len);
618
619 if (qc->tf.protocol != ATA_PROT_ATAPI_NODATA) {
620 if (qc->tf.flags & ATA_TFLAG_WRITE)
621 ctrl = PRB_CTRL_PACKET_WRITE;
622 else
623 ctrl = PRB_CTRL_PACKET_READ;
624 }
625 break;
626
627 default:
628 prb = NULL; /* shut up, gcc */
629 sge = NULL;
630 BUG();
631 }
632
633 prb->ctrl = cpu_to_le16(ctrl);
634 ata_tf_to_fis(&qc->tf, prb->fis, 0);
635
636 if (qc->flags & ATA_QCFLAG_DMAMAP)
637 sil24_fill_sg(qc, sge);
638 }
639
640 static unsigned int sil24_qc_issue(struct ata_queued_cmd *qc)
641 {
642 struct ata_port *ap = qc->ap;
643 void __iomem *port = (void __iomem *)ap->ioaddr.cmd_addr;
644 struct sil24_port_priv *pp = ap->private_data;
645 dma_addr_t paddr = pp->cmd_block_dma + qc->tag * sizeof(*pp->cmd_block);
646
647 writel((u32)paddr, port + PORT_CMD_ACTIVATE);
648 writel((u64)paddr >> 32, port + PORT_CMD_ACTIVATE + 4);
649
650 return 0;
651 }
652
653 static void sil24_irq_clear(struct ata_port *ap)
654 {
655 /* unused */
656 }
657
658 static int __sil24_restart_controller(void __iomem *port)
659 {
660 u32 tmp;
661 int cnt;
662
663 writel(PORT_CS_INIT, port + PORT_CTRL_STAT);
664
665 /* Max ~10ms */
666 for (cnt = 0; cnt < 10000; cnt++) {
667 tmp = readl(port + PORT_CTRL_STAT);
668 if (tmp & PORT_CS_RDY)
669 return 0;
670 udelay(1);
671 }
672
673 return -1;
674 }
675
676 static void sil24_restart_controller(struct ata_port *ap)
677 {
678 if (__sil24_restart_controller((void __iomem *)ap->ioaddr.cmd_addr))
679 printk(KERN_ERR DRV_NAME
680 " ata%u: failed to restart controller\n", ap->id);
681 }
682
683 static int __sil24_reset_controller(void __iomem *port)
684 {
685 int cnt;
686 u32 tmp;
687
688 /* Reset controller state. Is this correct? */
689 writel(PORT_CS_DEV_RST, port + PORT_CTRL_STAT);
690 readl(port + PORT_CTRL_STAT); /* sync */
691
692 /* Max ~100ms */
693 for (cnt = 0; cnt < 1000; cnt++) {
694 udelay(100);
695 tmp = readl(port + PORT_CTRL_STAT);
696 if (!(tmp & PORT_CS_DEV_RST))
697 break;
698 }
699
700 if (tmp & PORT_CS_DEV_RST)
701 return -1;
702
703 if (tmp & PORT_CS_RDY)
704 return 0;
705
706 return __sil24_restart_controller(port);
707 }
708
709 static void sil24_reset_controller(struct ata_port *ap)
710 {
711 printk(KERN_NOTICE DRV_NAME
712 " ata%u: resetting controller...\n", ap->id);
713 if (__sil24_reset_controller((void __iomem *)ap->ioaddr.cmd_addr))
714 printk(KERN_ERR DRV_NAME
715 " ata%u: failed to reset controller\n", ap->id);
716 }
717
718 static void sil24_eng_timeout(struct ata_port *ap)
719 {
720 struct ata_queued_cmd *qc;
721
722 qc = ata_qc_from_tag(ap, ap->active_tag);
723
724 printk(KERN_ERR "ata%u: command timeout\n", ap->id);
725 qc->err_mask |= AC_ERR_TIMEOUT;
726 ata_eh_qc_complete(qc);
727
728 sil24_reset_controller(ap);
729 }
730
731 static void sil24_error_intr(struct ata_port *ap, u32 slot_stat)
732 {
733 struct ata_queued_cmd *qc = ata_qc_from_tag(ap, ap->active_tag);
734 struct sil24_port_priv *pp = ap->private_data;
735 void __iomem *port = (void __iomem *)ap->ioaddr.cmd_addr;
736 u32 irq_stat, cmd_err, sstatus, serror;
737 unsigned int err_mask;
738
739 irq_stat = readl(port + PORT_IRQ_STAT);
740 writel(irq_stat, port + PORT_IRQ_STAT); /* clear irq */
741
742 if (!(irq_stat & PORT_IRQ_ERROR)) {
743 /* ignore non-completion, non-error irqs for now */
744 printk(KERN_WARNING DRV_NAME
745 "ata%u: non-error exception irq (irq_stat %x)\n",
746 ap->id, irq_stat);
747 return;
748 }
749
750 cmd_err = readl(port + PORT_CMD_ERR);
751 sstatus = readl(port + PORT_SSTATUS);
752 serror = readl(port + PORT_SERROR);
753 if (serror)
754 writel(serror, port + PORT_SERROR);
755
756 /*
757 * Don't log ATAPI device errors. They're supposed to happen
758 * and any serious errors will be logged using sense data by
759 * the SCSI layer.
760 */
761 if (ap->device[0].class != ATA_DEV_ATAPI || cmd_err > PORT_CERR_SDB)
762 printk("ata%u: error interrupt on port%d\n"
763 " stat=0x%x irq=0x%x cmd_err=%d sstatus=0x%x serror=0x%x\n",
764 ap->id, ap->port_no, slot_stat, irq_stat, cmd_err, sstatus, serror);
765
766 if (cmd_err == PORT_CERR_DEV || cmd_err == PORT_CERR_SDB) {
767 /*
768 * Device is reporting error, tf registers are valid.
769 */
770 sil24_update_tf(ap);
771 err_mask = ac_err_mask(pp->tf.command);
772 sil24_restart_controller(ap);
773 } else {
774 /*
775 * Other errors. libata currently doesn't have any
776 * mechanism to report these errors. Just turn on
777 * ATA_ERR.
778 */
779 err_mask = AC_ERR_OTHER;
780 sil24_reset_controller(ap);
781 }
782
783 if (qc) {
784 qc->err_mask |= err_mask;
785 ata_qc_complete(qc);
786 }
787 }
788
789 static inline void sil24_host_intr(struct ata_port *ap)
790 {
791 struct ata_queued_cmd *qc = ata_qc_from_tag(ap, ap->active_tag);
792 void __iomem *port = (void __iomem *)ap->ioaddr.cmd_addr;
793 u32 slot_stat;
794
795 slot_stat = readl(port + PORT_SLOT_STAT);
796 if (!(slot_stat & HOST_SSTAT_ATTN)) {
797 struct sil24_port_priv *pp = ap->private_data;
798
799 if (ap->flags & SIL24_FLAG_PCIX_IRQ_WOC)
800 writel(PORT_IRQ_COMPLETE, port + PORT_IRQ_STAT);
801
802 /*
803 * !HOST_SSAT_ATTN guarantees successful completion,
804 * so reading back tf registers is unnecessary for
805 * most commands. TODO: read tf registers for
806 * commands which require these values on successful
807 * completion (EXECUTE DEVICE DIAGNOSTIC, CHECK POWER,
808 * DEVICE RESET and READ PORT MULTIPLIER (any more?).
809 */
810 sil24_update_tf(ap);
811
812 if (qc) {
813 qc->err_mask |= ac_err_mask(pp->tf.command);
814 ata_qc_complete(qc);
815 }
816 } else
817 sil24_error_intr(ap, slot_stat);
818 }
819
820 static irqreturn_t sil24_interrupt(int irq, void *dev_instance, struct pt_regs *regs)
821 {
822 struct ata_host_set *host_set = dev_instance;
823 struct sil24_host_priv *hpriv = host_set->private_data;
824 unsigned handled = 0;
825 u32 status;
826 int i;
827
828 status = readl(hpriv->host_base + HOST_IRQ_STAT);
829
830 if (status == 0xffffffff) {
831 printk(KERN_ERR DRV_NAME ": IRQ status == 0xffffffff, "
832 "PCI fault or device removal?\n");
833 goto out;
834 }
835
836 if (!(status & IRQ_STAT_4PORTS))
837 goto out;
838
839 spin_lock(&host_set->lock);
840
841 for (i = 0; i < host_set->n_ports; i++)
842 if (status & (1 << i)) {
843 struct ata_port *ap = host_set->ports[i];
844 if (ap && !(ap->flags & ATA_FLAG_DISABLED)) {
845 sil24_host_intr(host_set->ports[i]);
846 handled++;
847 } else
848 printk(KERN_ERR DRV_NAME
849 ": interrupt from disabled port %d\n", i);
850 }
851
852 spin_unlock(&host_set->lock);
853 out:
854 return IRQ_RETVAL(handled);
855 }
856
857 static inline void sil24_cblk_free(struct sil24_port_priv *pp, struct device *dev)
858 {
859 const size_t cb_size = sizeof(*pp->cmd_block);
860
861 dma_free_coherent(dev, cb_size, pp->cmd_block, pp->cmd_block_dma);
862 }
863
864 static int sil24_port_start(struct ata_port *ap)
865 {
866 struct device *dev = ap->host_set->dev;
867 struct sil24_port_priv *pp;
868 union sil24_cmd_block *cb;
869 size_t cb_size = sizeof(*cb);
870 dma_addr_t cb_dma;
871 int rc = -ENOMEM;
872
873 pp = kzalloc(sizeof(*pp), GFP_KERNEL);
874 if (!pp)
875 goto err_out;
876
877 pp->tf.command = ATA_DRDY;
878
879 cb = dma_alloc_coherent(dev, cb_size, &cb_dma, GFP_KERNEL);
880 if (!cb)
881 goto err_out_pp;
882 memset(cb, 0, cb_size);
883
884 rc = ata_pad_alloc(ap, dev);
885 if (rc)
886 goto err_out_pad;
887
888 pp->cmd_block = cb;
889 pp->cmd_block_dma = cb_dma;
890
891 ap->private_data = pp;
892
893 return 0;
894
895 err_out_pad:
896 sil24_cblk_free(pp, dev);
897 err_out_pp:
898 kfree(pp);
899 err_out:
900 return rc;
901 }
902
903 static void sil24_port_stop(struct ata_port *ap)
904 {
905 struct device *dev = ap->host_set->dev;
906 struct sil24_port_priv *pp = ap->private_data;
907
908 sil24_cblk_free(pp, dev);
909 ata_pad_free(ap, dev);
910 kfree(pp);
911 }
912
913 static void sil24_host_stop(struct ata_host_set *host_set)
914 {
915 struct sil24_host_priv *hpriv = host_set->private_data;
916 struct pci_dev *pdev = to_pci_dev(host_set->dev);
917
918 pci_iounmap(pdev, hpriv->host_base);
919 pci_iounmap(pdev, hpriv->port_base);
920 kfree(hpriv);
921 }
922
923 static int sil24_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
924 {
925 static int printed_version = 0;
926 unsigned int board_id = (unsigned int)ent->driver_data;
927 struct ata_port_info *pinfo = &sil24_port_info[board_id];
928 struct ata_probe_ent *probe_ent = NULL;
929 struct sil24_host_priv *hpriv = NULL;
930 void __iomem *host_base = NULL;
931 void __iomem *port_base = NULL;
932 int i, rc;
933 u32 tmp;
934
935 if (!printed_version++)
936 dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n");
937
938 rc = pci_enable_device(pdev);
939 if (rc)
940 return rc;
941
942 rc = pci_request_regions(pdev, DRV_NAME);
943 if (rc)
944 goto out_disable;
945
946 rc = -ENOMEM;
947 /* map mmio registers */
948 host_base = pci_iomap(pdev, 0, 0);
949 if (!host_base)
950 goto out_free;
951 port_base = pci_iomap(pdev, 2, 0);
952 if (!port_base)
953 goto out_free;
954
955 /* allocate & init probe_ent and hpriv */
956 probe_ent = kzalloc(sizeof(*probe_ent), GFP_KERNEL);
957 if (!probe_ent)
958 goto out_free;
959
960 hpriv = kzalloc(sizeof(*hpriv), GFP_KERNEL);
961 if (!hpriv)
962 goto out_free;
963
964 probe_ent->dev = pci_dev_to_dev(pdev);
965 INIT_LIST_HEAD(&probe_ent->node);
966
967 probe_ent->sht = pinfo->sht;
968 probe_ent->host_flags = pinfo->host_flags;
969 probe_ent->pio_mask = pinfo->pio_mask;
970 probe_ent->mwdma_mask = pinfo->mwdma_mask;
971 probe_ent->udma_mask = pinfo->udma_mask;
972 probe_ent->port_ops = pinfo->port_ops;
973 probe_ent->n_ports = SIL24_FLAG2NPORTS(pinfo->host_flags);
974
975 probe_ent->irq = pdev->irq;
976 probe_ent->irq_flags = SA_SHIRQ;
977 probe_ent->mmio_base = port_base;
978 probe_ent->private_data = hpriv;
979
980 hpriv->host_base = host_base;
981 hpriv->port_base = port_base;
982
983 /*
984 * Configure the device
985 */
986 if (!pci_set_dma_mask(pdev, DMA_64BIT_MASK)) {
987 rc = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK);
988 if (rc) {
989 rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
990 if (rc) {
991 dev_printk(KERN_ERR, &pdev->dev,
992 "64-bit DMA enable failed\n");
993 goto out_free;
994 }
995 }
996 } else {
997 rc = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
998 if (rc) {
999 dev_printk(KERN_ERR, &pdev->dev,
1000 "32-bit DMA enable failed\n");
1001 goto out_free;
1002 }
1003 rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
1004 if (rc) {
1005 dev_printk(KERN_ERR, &pdev->dev,
1006 "32-bit consistent DMA enable failed\n");
1007 goto out_free;
1008 }
1009 }
1010
1011 /* GPIO off */
1012 writel(0, host_base + HOST_FLASH_CMD);
1013
1014 /* Apply workaround for completion IRQ loss on PCI-X errata */
1015 if (probe_ent->host_flags & SIL24_FLAG_PCIX_IRQ_WOC) {
1016 tmp = readl(host_base + HOST_CTRL);
1017 if (tmp & (HOST_CTRL_TRDY | HOST_CTRL_STOP | HOST_CTRL_DEVSEL))
1018 dev_printk(KERN_INFO, &pdev->dev,
1019 "Applying completion IRQ loss on PCI-X "
1020 "errata fix\n");
1021 else
1022 probe_ent->host_flags &= ~SIL24_FLAG_PCIX_IRQ_WOC;
1023 }
1024
1025 /* clear global reset & mask interrupts during initialization */
1026 writel(0, host_base + HOST_CTRL);
1027
1028 for (i = 0; i < probe_ent->n_ports; i++) {
1029 void __iomem *port = port_base + i * PORT_REGS_SIZE;
1030 unsigned long portu = (unsigned long)port;
1031
1032 probe_ent->port[i].cmd_addr = portu + PORT_PRB;
1033 probe_ent->port[i].scr_addr = portu + PORT_SCONTROL;
1034
1035 ata_std_ports(&probe_ent->port[i]);
1036
1037 /* Initial PHY setting */
1038 writel(0x20c, port + PORT_PHY_CFG);
1039
1040 /* Clear port RST */
1041 tmp = readl(port + PORT_CTRL_STAT);
1042 if (tmp & PORT_CS_PORT_RST) {
1043 writel(PORT_CS_PORT_RST, port + PORT_CTRL_CLR);
1044 tmp = ata_wait_register(port + PORT_CTRL_STAT,
1045 PORT_CS_PORT_RST,
1046 PORT_CS_PORT_RST, 10, 100);
1047 if (tmp & PORT_CS_PORT_RST)
1048 dev_printk(KERN_ERR, &pdev->dev,
1049 "failed to clear port RST\n");
1050 }
1051
1052 /* Configure IRQ WoC */
1053 if (probe_ent->host_flags & SIL24_FLAG_PCIX_IRQ_WOC)
1054 writel(PORT_CS_IRQ_WOC, port + PORT_CTRL_STAT);
1055 else
1056 writel(PORT_CS_IRQ_WOC, port + PORT_CTRL_CLR);
1057
1058 /* Zero error counters. */
1059 writel(0x8000, port + PORT_DECODE_ERR_THRESH);
1060 writel(0x8000, port + PORT_CRC_ERR_THRESH);
1061 writel(0x8000, port + PORT_HSHK_ERR_THRESH);
1062 writel(0x0000, port + PORT_DECODE_ERR_CNT);
1063 writel(0x0000, port + PORT_CRC_ERR_CNT);
1064 writel(0x0000, port + PORT_HSHK_ERR_CNT);
1065
1066 /* Always use 64bit activation */
1067 writel(PORT_CS_32BIT_ACTV, port + PORT_CTRL_CLR);
1068
1069 /* Configure interrupts */
1070 writel(0xffff, port + PORT_IRQ_ENABLE_CLR);
1071 writel(PORT_IRQ_COMPLETE | PORT_IRQ_ERROR |
1072 PORT_IRQ_SDB_NOTIFY, port + PORT_IRQ_ENABLE_SET);
1073
1074 /* Clear interrupts */
1075 writel(0x0fff0fff, port + PORT_IRQ_STAT);
1076 writel(PORT_CS_IRQ_WOC, port + PORT_CTRL_CLR);
1077
1078 /* Clear port multiplier enable and resume bits */
1079 writel(PORT_CS_PM_EN | PORT_CS_RESUME, port + PORT_CTRL_CLR);
1080 }
1081
1082 /* Turn on interrupts */
1083 writel(IRQ_STAT_4PORTS, host_base + HOST_CTRL);
1084
1085 pci_set_master(pdev);
1086
1087 /* FIXME: check ata_device_add return value */
1088 ata_device_add(probe_ent);
1089
1090 kfree(probe_ent);
1091 return 0;
1092
1093 out_free:
1094 if (host_base)
1095 pci_iounmap(pdev, host_base);
1096 if (port_base)
1097 pci_iounmap(pdev, port_base);
1098 kfree(probe_ent);
1099 kfree(hpriv);
1100 pci_release_regions(pdev);
1101 out_disable:
1102 pci_disable_device(pdev);
1103 return rc;
1104 }
1105
1106 static int __init sil24_init(void)
1107 {
1108 return pci_module_init(&sil24_pci_driver);
1109 }
1110
1111 static void __exit sil24_exit(void)
1112 {
1113 pci_unregister_driver(&sil24_pci_driver);
1114 }
1115
1116 MODULE_AUTHOR("Tejun Heo");
1117 MODULE_DESCRIPTION("Silicon Image 3124/3132 SATA low-level driver");
1118 MODULE_LICENSE("GPL");
1119 MODULE_DEVICE_TABLE(pci, sil24_pci_tbl);
1120
1121 module_init(sil24_init);
1122 module_exit(sil24_exit);
Linus' kernel tree