2 * ata_piix.c - Intel PATA/SATA controllers
4 * Maintained by: Jeff Garzik <jgarzik@pobox.com>
5 * Please ALWAYS copy linux-ide@vger.kernel.org
9 * Copyright 2003-2005 Red Hat Inc
10 * Copyright 2003-2005 Jeff Garzik
13 * Copyright header from piix.c:
15 * Copyright (C) 1998-1999 Andrzej Krzysztofowicz, Author and Maintainer
16 * Copyright (C) 1998-2000 Andre Hedrick <andre@linux-ide.org>
17 * Copyright (C) 2003 Red Hat Inc
20 * This program is free software; you can redistribute it and/or modify
21 * it under the terms of the GNU General Public License as published by
22 * the Free Software Foundation; either version 2, or (at your option)
25 * This program is distributed in the hope that it will be useful,
26 * but WITHOUT ANY WARRANTY; without even the implied warranty of
27 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
28 * GNU General Public License for more details.
30 * You should have received a copy of the GNU General Public License
31 * along with this program; see the file COPYING. If not, write to
32 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
35 * libata documentation is available via 'make {ps|pdf}docs',
36 * as Documentation/DocBook/libata.*
38 * Hardware documentation available at http://developer.intel.com/
41 * Publically available from Intel web site. Errata documentation
42 * is also publically available. As an aide to anyone hacking on this
43 * driver the list of errata that are relevant is below, going back to
44 * PIIX4. Older device documentation is now a bit tricky to find.
46 * The chipsets all follow very much the same design. The orginal Triton
47 * series chipsets do _not_ support independant device timings, but this
48 * is fixed in Triton II. With the odd mobile exception the chips then
49 * change little except in gaining more modes until SATA arrives. This
50 * driver supports only the chips with independant timing (that is those
51 * with SITRE and the 0x44 timing register). See pata_oldpiix and pata_mpiix
52 * for the early chip drivers.
57 * PIIX4 errata #9 - Only on ultra obscure hw
58 * ICH3 errata #13 - Not observed to affect real hw
61 * Things we must deal with
62 * PIIX4 errata #10 - BM IDE hang with non UDMA
63 * (must stop/start dma to recover)
64 * 440MX errata #15 - As PIIX4 errata #10
65 * PIIX4 errata #15 - Must not read control registers
66 * during a PIO transfer
67 * 440MX errata #13 - As PIIX4 errata #15
68 * ICH2 errata #21 - DMA mode 0 doesn't work right
69 * ICH0/1 errata #55 - As ICH2 errata #21
70 * ICH2 spec c #9 - Extra operations needed to handle
71 * drive hotswap [NOT YET SUPPORTED]
72 * ICH2 spec c #20 - IDE PRD must not cross a 64K boundary
73 * and must be dword aligned
74 * ICH2 spec c #24 - UDMA mode 4,5 t85/86 should be 6ns not 3.3
75 * ICH7 errata #16 - MWDMA1 timings are incorrect
77 * Should have been BIOS fixed:
78 * 450NX: errata #19 - DMA hangs on old 450NX
79 * 450NX: errata #20 - DMA hangs on old 450NX
80 * 450NX: errata #25 - Corruption with DMA on old 450NX
81 * ICH3 errata #15 - IDE deadlock under high load
82 * (BIOS must set dev 31 fn 0 bit 23)
83 * ICH3 errata #18 - Don't use native mode
86 #include <linux/kernel.h>
87 #include <linux/module.h>
88 #include <linux/pci.h>
89 #include <linux/init.h>
90 #include <linux/blkdev.h>
91 #include <linux/delay.h>
92 #include <linux/device.h>
93 #include <scsi/scsi_host.h>
94 #include <linux/libata.h>
95 #include <linux/dmi.h>
97 #define DRV_NAME "ata_piix"
98 #define DRV_VERSION "2.13"
101 PIIX_IOCFG
= 0x54, /* IDE I/O configuration register */
102 ICH5_PMR
= 0x90, /* port mapping register */
103 ICH5_PCS
= 0x92, /* port control and status */
109 PIIX_FLAG_CHECKINTR
= (1 << 28), /* make sure PCI INTx enabled */
110 PIIX_FLAG_SIDPR
= (1 << 29), /* SATA idx/data pair regs */
112 PIIX_PATA_FLAGS
= ATA_FLAG_SLAVE_POSS
,
113 PIIX_SATA_FLAGS
= ATA_FLAG_SATA
| PIIX_FLAG_CHECKINTR
,
115 PIIX_80C_PRI
= (1 << 5) | (1 << 4),
116 PIIX_80C_SEC
= (1 << 7) | (1 << 6),
118 /* constants for mapping table */
124 NA
= -2, /* not avaliable */
125 RV
= -3, /* reserved */
127 PIIX_AHCI_DEVICE
= 6,
129 /* host->flags bits */
130 PIIX_HOST_BROKEN_SUSPEND
= (1 << 24),
133 enum piix_controller_ids
{
135 piix_pata_mwdma
, /* PIIX3 MWDMA only */
136 piix_pata_33
, /* PIIX4 at 33Mhz */
137 ich_pata_33
, /* ICH up to UDMA 33 only */
138 ich_pata_66
, /* ICH up to 66 Mhz */
139 ich_pata_100
, /* ICH up to UDMA 100 */
140 ich_pata_100_nomwdma1
, /* ICH up to UDMA 100 but with no MWDMA1*/
146 ich8m_apple_sata
, /* locks up on second port enable */
148 piix_pata_vmw
, /* PIIX4 for VMware, spurious DMA_ERR */
153 const u16 port_enable
;
157 struct piix_host_priv
{
163 static int piix_init_one(struct pci_dev
*pdev
,
164 const struct pci_device_id
*ent
);
165 static void piix_remove_one(struct pci_dev
*pdev
);
166 static int piix_pata_prereset(struct ata_link
*link
, unsigned long deadline
);
167 static void piix_set_piomode(struct ata_port
*ap
, struct ata_device
*adev
);
168 static void piix_set_dmamode(struct ata_port
*ap
, struct ata_device
*adev
);
169 static void ich_set_dmamode(struct ata_port
*ap
, struct ata_device
*adev
);
170 static int ich_pata_cable_detect(struct ata_port
*ap
);
171 static u8
piix_vmw_bmdma_status(struct ata_port
*ap
);
172 static int piix_sidpr_scr_read(struct ata_link
*link
,
173 unsigned int reg
, u32
*val
);
174 static int piix_sidpr_scr_write(struct ata_link
*link
,
175 unsigned int reg
, u32 val
);
177 static int piix_pci_device_suspend(struct pci_dev
*pdev
, pm_message_t mesg
);
178 static int piix_pci_device_resume(struct pci_dev
*pdev
);
181 static unsigned int in_module_init
= 1;
183 static const struct pci_device_id piix_pci_tbl
[] = {
184 /* Intel PIIX3 for the 430HX etc */
185 { 0x8086, 0x7010, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, piix_pata_mwdma
},
187 { 0x8086, 0x7111, 0x15ad, 0x1976, 0, 0, piix_pata_vmw
},
188 /* Intel PIIX4 for the 430TX/440BX/MX chipset: UDMA 33 */
189 /* Also PIIX4E (fn3 rev 2) and PIIX4M (fn3 rev 3) */
190 { 0x8086, 0x7111, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, piix_pata_33
},
192 { 0x8086, 0x7199, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, piix_pata_33
},
194 { 0x8086, 0x7601, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, piix_pata_33
},
196 { 0x8086, 0x84CA, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, piix_pata_33
},
197 /* Intel ICH (i810, i815, i840) UDMA 66*/
198 { 0x8086, 0x2411, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, ich_pata_66
},
199 /* Intel ICH0 : UDMA 33*/
200 { 0x8086, 0x2421, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, ich_pata_33
},
202 { 0x8086, 0x244A, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, ich_pata_100
},
203 /* Intel ICH2 (i810E2, i845, 850, 860) UDMA 100 */
204 { 0x8086, 0x244B, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, ich_pata_100
},
206 { 0x8086, 0x248A, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, ich_pata_100
},
207 /* Intel ICH3 (E7500/1) UDMA 100 */
208 { 0x8086, 0x248B, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, ich_pata_100
},
209 /* Intel ICH4 (i845GV, i845E, i852, i855) UDMA 100 */
210 { 0x8086, 0x24CA, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, ich_pata_100
},
211 { 0x8086, 0x24CB, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, ich_pata_100
},
213 { 0x8086, 0x24DB, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, ich_pata_100
},
215 { 0x8086, 0x245B, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, ich_pata_100
},
216 /* ESB (855GME/875P + 6300ESB) UDMA 100 */
217 { 0x8086, 0x25A2, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, ich_pata_100
},
218 /* ICH6 (and 6) (i915) UDMA 100 */
219 { 0x8086, 0x266F, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, ich_pata_100
},
220 /* ICH7/7-R (i945, i975) UDMA 100*/
221 { 0x8086, 0x27DF, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, ich_pata_100_nomwdma1
},
222 { 0x8086, 0x269E, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, ich_pata_100_nomwdma1
},
223 /* ICH8 Mobile PATA Controller */
224 { 0x8086, 0x2850, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, ich_pata_100
},
226 /* NOTE: The following PCI ids must be kept in sync with the
227 * list in drivers/pci/quirks.c.
231 { 0x8086, 0x24d1, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, ich5_sata
},
233 { 0x8086, 0x24df, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, ich5_sata
},
234 /* 6300ESB (ICH5 variant with broken PCS present bits) */
235 { 0x8086, 0x25a3, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, ich5_sata
},
236 /* 6300ESB pretending RAID */
237 { 0x8086, 0x25b0, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, ich5_sata
},
238 /* 82801FB/FW (ICH6/ICH6W) */
239 { 0x8086, 0x2651, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, ich6_sata
},
240 /* 82801FR/FRW (ICH6R/ICH6RW) */
241 { 0x8086, 0x2652, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, ich6_sata
},
242 /* 82801FBM ICH6M (ICH6R with only port 0 and 2 implemented).
243 * Attach iff the controller is in IDE mode. */
244 { 0x8086, 0x2653, PCI_ANY_ID
, PCI_ANY_ID
,
245 PCI_CLASS_STORAGE_IDE
<< 8, 0xffff00, ich6m_sata
},
246 /* 82801GB/GR/GH (ICH7, identical to ICH6) */
247 { 0x8086, 0x27c0, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, ich6_sata
},
248 /* 2801GBM/GHM (ICH7M, identical to ICH6M) */
249 { 0x8086, 0x27c4, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, ich6m_sata
},
250 /* Enterprise Southbridge 2 (631xESB/632xESB) */
251 { 0x8086, 0x2680, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, ich6_sata
},
252 /* SATA Controller 1 IDE (ICH8) */
253 { 0x8086, 0x2820, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, ich8_sata
},
254 /* SATA Controller 2 IDE (ICH8) */
255 { 0x8086, 0x2825, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, ich8_2port_sata
},
256 /* Mobile SATA Controller IDE (ICH8M), Apple */
257 { 0x8086, 0x2828, 0x106b, 0x00a0, 0, 0, ich8m_apple_sata
},
258 { 0x8086, 0x2828, 0x106b, 0x00a1, 0, 0, ich8m_apple_sata
},
259 { 0x8086, 0x2828, 0x106b, 0x00a3, 0, 0, ich8m_apple_sata
},
260 /* Mobile SATA Controller IDE (ICH8M) */
261 { 0x8086, 0x2828, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, ich8_sata
},
262 /* SATA Controller IDE (ICH9) */
263 { 0x8086, 0x2920, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, ich8_sata
},
264 /* SATA Controller IDE (ICH9) */
265 { 0x8086, 0x2921, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, ich8_2port_sata
},
266 /* SATA Controller IDE (ICH9) */
267 { 0x8086, 0x2926, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, ich8_2port_sata
},
268 /* SATA Controller IDE (ICH9M) */
269 { 0x8086, 0x2928, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, ich8_2port_sata
},
270 /* SATA Controller IDE (ICH9M) */
271 { 0x8086, 0x292d, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, ich8_2port_sata
},
272 /* SATA Controller IDE (ICH9M) */
273 { 0x8086, 0x292e, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, ich8_sata
},
274 /* SATA Controller IDE (Tolapai) */
275 { 0x8086, 0x5028, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, tolapai_sata
},
276 /* SATA Controller IDE (ICH10) */
277 { 0x8086, 0x3a00, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, ich8_sata
},
278 /* SATA Controller IDE (ICH10) */
279 { 0x8086, 0x3a06, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, ich8_2port_sata
},
280 /* SATA Controller IDE (ICH10) */
281 { 0x8086, 0x3a20, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, ich8_sata
},
282 /* SATA Controller IDE (ICH10) */
283 { 0x8086, 0x3a26, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, ich8_2port_sata
},
284 /* SATA Controller IDE (PCH) */
285 { 0x8086, 0x3b20, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, ich8_sata
},
286 /* SATA Controller IDE (PCH) */
287 { 0x8086, 0x3b21, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, ich8_2port_sata
},
288 /* SATA Controller IDE (PCH) */
289 { 0x8086, 0x3b26, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, ich8_2port_sata
},
290 /* SATA Controller IDE (PCH) */
291 { 0x8086, 0x3b28, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, ich8_sata
},
292 /* SATA Controller IDE (PCH) */
293 { 0x8086, 0x3b2d, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, ich8_2port_sata
},
294 /* SATA Controller IDE (PCH) */
295 { 0x8086, 0x3b2e, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, ich8_sata
},
296 { } /* terminate list */
299 static struct pci_driver piix_pci_driver
= {
301 .id_table
= piix_pci_tbl
,
302 .probe
= piix_init_one
,
303 .remove
= piix_remove_one
,
305 .suspend
= piix_pci_device_suspend
,
306 .resume
= piix_pci_device_resume
,
310 static struct scsi_host_template piix_sht
= {
311 ATA_BMDMA_SHT(DRV_NAME
),
314 static struct ata_port_operations piix_pata_ops
= {
315 .inherits
= &ata_bmdma32_port_ops
,
316 .cable_detect
= ata_cable_40wire
,
317 .set_piomode
= piix_set_piomode
,
318 .set_dmamode
= piix_set_dmamode
,
319 .prereset
= piix_pata_prereset
,
322 static struct ata_port_operations piix_vmw_ops
= {
323 .inherits
= &piix_pata_ops
,
324 .bmdma_status
= piix_vmw_bmdma_status
,
327 static struct ata_port_operations ich_pata_ops
= {
328 .inherits
= &piix_pata_ops
,
329 .cable_detect
= ich_pata_cable_detect
,
330 .set_dmamode
= ich_set_dmamode
,
333 static struct ata_port_operations piix_sata_ops
= {
334 .inherits
= &ata_bmdma_port_ops
,
337 static struct ata_port_operations piix_sidpr_sata_ops
= {
338 .inherits
= &piix_sata_ops
,
339 .hardreset
= sata_std_hardreset
,
340 .scr_read
= piix_sidpr_scr_read
,
341 .scr_write
= piix_sidpr_scr_write
,
344 static const struct piix_map_db ich5_map_db
= {
348 /* PM PS SM SS MAP */
349 { P0
, NA
, P1
, NA
}, /* 000b */
350 { P1
, NA
, P0
, NA
}, /* 001b */
353 { P0
, P1
, IDE
, IDE
}, /* 100b */
354 { P1
, P0
, IDE
, IDE
}, /* 101b */
355 { IDE
, IDE
, P0
, P1
}, /* 110b */
356 { IDE
, IDE
, P1
, P0
}, /* 111b */
360 static const struct piix_map_db ich6_map_db
= {
364 /* PM PS SM SS MAP */
365 { P0
, P2
, P1
, P3
}, /* 00b */
366 { IDE
, IDE
, P1
, P3
}, /* 01b */
367 { P0
, P2
, IDE
, IDE
}, /* 10b */
372 static const struct piix_map_db ich6m_map_db
= {
376 /* Map 01b isn't specified in the doc but some notebooks use
377 * it anyway. MAP 01b have been spotted on both ICH6M and
381 /* PM PS SM SS MAP */
382 { P0
, P2
, NA
, NA
}, /* 00b */
383 { IDE
, IDE
, P1
, P3
}, /* 01b */
384 { P0
, P2
, IDE
, IDE
}, /* 10b */
389 static const struct piix_map_db ich8_map_db
= {
393 /* PM PS SM SS MAP */
394 { P0
, P2
, P1
, P3
}, /* 00b (hardwired when in AHCI) */
396 { P0
, P2
, IDE
, IDE
}, /* 10b (IDE mode) */
401 static const struct piix_map_db ich8_2port_map_db
= {
405 /* PM PS SM SS MAP */
406 { P0
, NA
, P1
, NA
}, /* 00b */
407 { RV
, RV
, RV
, RV
}, /* 01b */
408 { RV
, RV
, RV
, RV
}, /* 10b */
413 static const struct piix_map_db ich8m_apple_map_db
= {
417 /* PM PS SM SS MAP */
418 { P0
, NA
, NA
, NA
}, /* 00b */
420 { P0
, P2
, IDE
, IDE
}, /* 10b */
425 static const struct piix_map_db tolapai_map_db
= {
429 /* PM PS SM SS MAP */
430 { P0
, NA
, P1
, NA
}, /* 00b */
431 { RV
, RV
, RV
, RV
}, /* 01b */
432 { RV
, RV
, RV
, RV
}, /* 10b */
437 static const struct piix_map_db
*piix_map_db_table
[] = {
438 [ich5_sata
] = &ich5_map_db
,
439 [ich6_sata
] = &ich6_map_db
,
440 [ich6m_sata
] = &ich6m_map_db
,
441 [ich8_sata
] = &ich8_map_db
,
442 [ich8_2port_sata
] = &ich8_2port_map_db
,
443 [ich8m_apple_sata
] = &ich8m_apple_map_db
,
444 [tolapai_sata
] = &tolapai_map_db
,
447 static struct ata_port_info piix_port_info
[] = {
448 [piix_pata_mwdma
] = /* PIIX3 MWDMA only */
450 .flags
= PIIX_PATA_FLAGS
,
451 .pio_mask
= ATA_PIO4
,
452 .mwdma_mask
= ATA_MWDMA12_ONLY
, /* mwdma1-2 ?? CHECK 0 should be ok but slow */
453 .port_ops
= &piix_pata_ops
,
456 [piix_pata_33
] = /* PIIX4 at 33MHz */
458 .flags
= PIIX_PATA_FLAGS
,
459 .pio_mask
= ATA_PIO4
,
460 .mwdma_mask
= ATA_MWDMA12_ONLY
, /* mwdma1-2 ?? CHECK 0 should be ok but slow */
461 .udma_mask
= ATA_UDMA2
,
462 .port_ops
= &piix_pata_ops
,
465 [ich_pata_33
] = /* ICH0 - ICH at 33Mhz*/
467 .flags
= PIIX_PATA_FLAGS
,
468 .pio_mask
= ATA_PIO4
,
469 .mwdma_mask
= ATA_MWDMA12_ONLY
, /* Check: maybe MWDMA0 is ok */
470 .udma_mask
= ATA_UDMA2
,
471 .port_ops
= &ich_pata_ops
,
474 [ich_pata_66
] = /* ICH controllers up to 66MHz */
476 .flags
= PIIX_PATA_FLAGS
,
477 .pio_mask
= ATA_PIO4
,
478 .mwdma_mask
= ATA_MWDMA12_ONLY
, /* MWDMA0 is broken on chip */
479 .udma_mask
= ATA_UDMA4
,
480 .port_ops
= &ich_pata_ops
,
485 .flags
= PIIX_PATA_FLAGS
| PIIX_FLAG_CHECKINTR
,
486 .pio_mask
= ATA_PIO4
,
487 .mwdma_mask
= ATA_MWDMA12_ONLY
,
488 .udma_mask
= ATA_UDMA5
,
489 .port_ops
= &ich_pata_ops
,
492 [ich_pata_100_nomwdma1
] =
494 .flags
= PIIX_PATA_FLAGS
| PIIX_FLAG_CHECKINTR
,
495 .pio_mask
= ATA_PIO4
,
496 .mwdma_mask
= ATA_MWDMA2_ONLY
,
497 .udma_mask
= ATA_UDMA5
,
498 .port_ops
= &ich_pata_ops
,
503 .flags
= PIIX_SATA_FLAGS
,
504 .pio_mask
= ATA_PIO4
,
505 .mwdma_mask
= ATA_MWDMA2
,
506 .udma_mask
= ATA_UDMA6
,
507 .port_ops
= &piix_sata_ops
,
512 .flags
= PIIX_SATA_FLAGS
,
513 .pio_mask
= ATA_PIO4
,
514 .mwdma_mask
= ATA_MWDMA2
,
515 .udma_mask
= ATA_UDMA6
,
516 .port_ops
= &piix_sata_ops
,
521 .flags
= PIIX_SATA_FLAGS
,
522 .pio_mask
= ATA_PIO4
,
523 .mwdma_mask
= ATA_MWDMA2
,
524 .udma_mask
= ATA_UDMA6
,
525 .port_ops
= &piix_sata_ops
,
530 .flags
= PIIX_SATA_FLAGS
| PIIX_FLAG_SIDPR
,
531 .pio_mask
= ATA_PIO4
,
532 .mwdma_mask
= ATA_MWDMA2
,
533 .udma_mask
= ATA_UDMA6
,
534 .port_ops
= &piix_sata_ops
,
539 .flags
= PIIX_SATA_FLAGS
| PIIX_FLAG_SIDPR
,
540 .pio_mask
= ATA_PIO4
,
541 .mwdma_mask
= ATA_MWDMA2
,
542 .udma_mask
= ATA_UDMA6
,
543 .port_ops
= &piix_sata_ops
,
548 .flags
= PIIX_SATA_FLAGS
,
549 .pio_mask
= ATA_PIO4
,
550 .mwdma_mask
= ATA_MWDMA2
,
551 .udma_mask
= ATA_UDMA6
,
552 .port_ops
= &piix_sata_ops
,
557 .flags
= PIIX_SATA_FLAGS
,
558 .pio_mask
= ATA_PIO4
,
559 .mwdma_mask
= ATA_MWDMA2
,
560 .udma_mask
= ATA_UDMA6
,
561 .port_ops
= &piix_sata_ops
,
566 .flags
= PIIX_PATA_FLAGS
,
567 .pio_mask
= ATA_PIO4
,
568 .mwdma_mask
= ATA_MWDMA12_ONLY
, /* mwdma1-2 ?? CHECK 0 should be ok but slow */
569 .udma_mask
= ATA_UDMA2
,
570 .port_ops
= &piix_vmw_ops
,
575 static struct pci_bits piix_enable_bits
[] = {
576 { 0x41U
, 1U, 0x80UL
, 0x80UL
}, /* port 0 */
577 { 0x43U
, 1U, 0x80UL
, 0x80UL
}, /* port 1 */
580 MODULE_AUTHOR("Andre Hedrick, Alan Cox, Andrzej Krzysztofowicz, Jeff Garzik");
581 MODULE_DESCRIPTION("SCSI low-level driver for Intel PIIX/ICH ATA controllers");
582 MODULE_LICENSE("GPL");
583 MODULE_DEVICE_TABLE(pci
, piix_pci_tbl
);
584 MODULE_VERSION(DRV_VERSION
);
593 * List of laptops that use short cables rather than 80 wire
596 static const struct ich_laptop ich_laptop
[] = {
597 /* devid, subvendor, subdev */
598 { 0x27DF, 0x0005, 0x0280 }, /* ICH7 on Acer 5602WLMi */
599 { 0x27DF, 0x1025, 0x0102 }, /* ICH7 on Acer 5602aWLMi */
600 { 0x27DF, 0x1025, 0x0110 }, /* ICH7 on Acer 3682WLMi */
601 { 0x27DF, 0x1043, 0x1267 }, /* ICH7 on Asus W5F */
602 { 0x27DF, 0x103C, 0x30A1 }, /* ICH7 on HP Compaq nc2400 */
603 { 0x27DF, 0x1071, 0xD221 }, /* ICH7 on Hercules EC-900 */
604 { 0x24CA, 0x1025, 0x0061 }, /* ICH4 on ACER Aspire 2023WLMi */
605 { 0x24CA, 0x1025, 0x003d }, /* ICH4 on ACER TM290 */
606 { 0x266F, 0x1025, 0x0066 }, /* ICH6 on ACER Aspire 1694WLMi */
607 { 0x2653, 0x1043, 0x82D8 }, /* ICH6M on Asus Eee 701 */
608 { 0x27df, 0x104d, 0x900e }, /* ICH7 on Sony TZ-90 */
614 * ich_pata_cable_detect - Probe host controller cable detect info
615 * @ap: Port for which cable detect info is desired
617 * Read 80c cable indicator from ATA PCI device's PCI config
618 * register. This register is normally set by firmware (BIOS).
621 * None (inherited from caller).
624 static int ich_pata_cable_detect(struct ata_port
*ap
)
626 struct pci_dev
*pdev
= to_pci_dev(ap
->host
->dev
);
627 struct piix_host_priv
*hpriv
= ap
->host
->private_data
;
628 const struct ich_laptop
*lap
= &ich_laptop
[0];
631 /* Check for specials - Acer Aspire 5602WLMi */
632 while (lap
->device
) {
633 if (lap
->device
== pdev
->device
&&
634 lap
->subvendor
== pdev
->subsystem_vendor
&&
635 lap
->subdevice
== pdev
->subsystem_device
)
636 return ATA_CBL_PATA40_SHORT
;
641 /* check BIOS cable detect results */
642 mask
= ap
->port_no
== 0 ? PIIX_80C_PRI
: PIIX_80C_SEC
;
643 if ((hpriv
->saved_iocfg
& mask
) == 0)
644 return ATA_CBL_PATA40
;
645 return ATA_CBL_PATA80
;
649 * piix_pata_prereset - prereset for PATA host controller
651 * @deadline: deadline jiffies for the operation
654 * None (inherited from caller).
656 static int piix_pata_prereset(struct ata_link
*link
, unsigned long deadline
)
658 struct ata_port
*ap
= link
->ap
;
659 struct pci_dev
*pdev
= to_pci_dev(ap
->host
->dev
);
661 if (!pci_test_config_bits(pdev
, &piix_enable_bits
[ap
->port_no
]))
663 return ata_sff_prereset(link
, deadline
);
667 * piix_set_piomode - Initialize host controller PATA PIO timings
668 * @ap: Port whose timings we are configuring
671 * Set PIO mode for device, in host controller PCI config space.
674 * None (inherited from caller).
677 static void piix_set_piomode(struct ata_port
*ap
, struct ata_device
*adev
)
679 unsigned int pio
= adev
->pio_mode
- XFER_PIO_0
;
680 struct pci_dev
*dev
= to_pci_dev(ap
->host
->dev
);
681 unsigned int is_slave
= (adev
->devno
!= 0);
682 unsigned int master_port
= ap
->port_no
? 0x42 : 0x40;
683 unsigned int slave_port
= 0x44;
690 * See Intel Document 298600-004 for the timing programing rules
691 * for ICH controllers.
694 static const /* ISP RTC */
695 u8 timings
[][2] = { { 0, 0 },
702 control
|= 1; /* TIME1 enable */
703 if (ata_pio_need_iordy(adev
))
704 control
|= 2; /* IE enable */
706 /* Intel specifies that the PPE functionality is for disk only */
707 if (adev
->class == ATA_DEV_ATA
)
708 control
|= 4; /* PPE enable */
710 /* PIO configuration clears DTE unconditionally. It will be
711 * programmed in set_dmamode which is guaranteed to be called
712 * after set_piomode if any DMA mode is available.
714 pci_read_config_word(dev
, master_port
, &master_data
);
716 /* clear TIME1|IE1|PPE1|DTE1 */
717 master_data
&= 0xff0f;
718 /* Enable SITRE (separate slave timing register) */
719 master_data
|= 0x4000;
720 /* enable PPE1, IE1 and TIME1 as needed */
721 master_data
|= (control
<< 4);
722 pci_read_config_byte(dev
, slave_port
, &slave_data
);
723 slave_data
&= (ap
->port_no
? 0x0f : 0xf0);
724 /* Load the timing nibble for this slave */
725 slave_data
|= ((timings
[pio
][0] << 2) | timings
[pio
][1])
726 << (ap
->port_no
? 4 : 0);
728 /* clear ISP|RCT|TIME0|IE0|PPE0|DTE0 */
729 master_data
&= 0xccf0;
730 /* Enable PPE, IE and TIME as appropriate */
731 master_data
|= control
;
732 /* load ISP and RCT */
734 (timings
[pio
][0] << 12) |
735 (timings
[pio
][1] << 8);
737 pci_write_config_word(dev
, master_port
, master_data
);
739 pci_write_config_byte(dev
, slave_port
, slave_data
);
741 /* Ensure the UDMA bit is off - it will be turned back on if
745 pci_read_config_byte(dev
, 0x48, &udma_enable
);
746 udma_enable
&= ~(1 << (2 * ap
->port_no
+ adev
->devno
));
747 pci_write_config_byte(dev
, 0x48, udma_enable
);
752 * do_pata_set_dmamode - Initialize host controller PATA PIO timings
753 * @ap: Port whose timings we are configuring
754 * @adev: Drive in question
755 * @isich: set if the chip is an ICH device
757 * Set UDMA mode for device, in host controller PCI config space.
760 * None (inherited from caller).
763 static void do_pata_set_dmamode(struct ata_port
*ap
, struct ata_device
*adev
, int isich
)
765 struct pci_dev
*dev
= to_pci_dev(ap
->host
->dev
);
766 u8 master_port
= ap
->port_no
? 0x42 : 0x40;
768 u8 speed
= adev
->dma_mode
;
769 int devid
= adev
->devno
+ 2 * ap
->port_no
;
772 static const /* ISP RTC */
773 u8 timings
[][2] = { { 0, 0 },
779 pci_read_config_word(dev
, master_port
, &master_data
);
781 pci_read_config_byte(dev
, 0x48, &udma_enable
);
783 if (speed
>= XFER_UDMA_0
) {
784 unsigned int udma
= adev
->dma_mode
- XFER_UDMA_0
;
787 int u_clock
, u_speed
;
790 * UDMA is handled by a combination of clock switching and
791 * selection of dividers
793 * Handy rule: Odd modes are UDMATIMx 01, even are 02
794 * except UDMA0 which is 00
796 u_speed
= min(2 - (udma
& 1), udma
);
798 u_clock
= 0x1000; /* 100Mhz */
800 u_clock
= 1; /* 66Mhz */
802 u_clock
= 0; /* 33Mhz */
804 udma_enable
|= (1 << devid
);
806 /* Load the CT/RP selection */
807 pci_read_config_word(dev
, 0x4A, &udma_timing
);
808 udma_timing
&= ~(3 << (4 * devid
));
809 udma_timing
|= u_speed
<< (4 * devid
);
810 pci_write_config_word(dev
, 0x4A, udma_timing
);
813 /* Select a 33/66/100Mhz clock */
814 pci_read_config_word(dev
, 0x54, &ideconf
);
815 ideconf
&= ~(0x1001 << devid
);
816 ideconf
|= u_clock
<< devid
;
817 /* For ICH or later we should set bit 10 for better
818 performance (WR_PingPong_En) */
819 pci_write_config_word(dev
, 0x54, ideconf
);
823 * MWDMA is driven by the PIO timings. We must also enable
824 * IORDY unconditionally along with TIME1. PPE has already
825 * been set when the PIO timing was set.
827 unsigned int mwdma
= adev
->dma_mode
- XFER_MW_DMA_0
;
828 unsigned int control
;
830 const unsigned int needed_pio
[3] = {
831 XFER_PIO_0
, XFER_PIO_3
, XFER_PIO_4
833 int pio
= needed_pio
[mwdma
] - XFER_PIO_0
;
835 control
= 3; /* IORDY|TIME1 */
837 /* If the drive MWDMA is faster than it can do PIO then
838 we must force PIO into PIO0 */
840 if (adev
->pio_mode
< needed_pio
[mwdma
])
841 /* Enable DMA timing only */
842 control
|= 8; /* PIO cycles in PIO0 */
844 if (adev
->devno
) { /* Slave */
845 master_data
&= 0xFF4F; /* Mask out IORDY|TIME1|DMAONLY */
846 master_data
|= control
<< 4;
847 pci_read_config_byte(dev
, 0x44, &slave_data
);
848 slave_data
&= (ap
->port_no
? 0x0f : 0xf0);
849 /* Load the matching timing */
850 slave_data
|= ((timings
[pio
][0] << 2) | timings
[pio
][1]) << (ap
->port_no
? 4 : 0);
851 pci_write_config_byte(dev
, 0x44, slave_data
);
852 } else { /* Master */
853 master_data
&= 0xCCF4; /* Mask out IORDY|TIME1|DMAONLY
854 and master timing bits */
855 master_data
|= control
;
857 (timings
[pio
][0] << 12) |
858 (timings
[pio
][1] << 8);
862 udma_enable
&= ~(1 << devid
);
863 pci_write_config_word(dev
, master_port
, master_data
);
866 /* Don't scribble on 0x48 if the controller does not support UDMA */
868 pci_write_config_byte(dev
, 0x48, udma_enable
);
872 * piix_set_dmamode - Initialize host controller PATA DMA timings
873 * @ap: Port whose timings we are configuring
876 * Set MW/UDMA mode for device, in host controller PCI config space.
879 * None (inherited from caller).
882 static void piix_set_dmamode(struct ata_port
*ap
, struct ata_device
*adev
)
884 do_pata_set_dmamode(ap
, adev
, 0);
888 * ich_set_dmamode - Initialize host controller PATA DMA timings
889 * @ap: Port whose timings we are configuring
892 * Set MW/UDMA mode for device, in host controller PCI config space.
895 * None (inherited from caller).
898 static void ich_set_dmamode(struct ata_port
*ap
, struct ata_device
*adev
)
900 do_pata_set_dmamode(ap
, adev
, 1);
904 * Serial ATA Index/Data Pair Superset Registers access
906 * Beginning from ICH8, there's a sane way to access SCRs using index
907 * and data register pair located at BAR5 which means that we have
908 * separate SCRs for master and slave. This is handled using libata
909 * slave_link facility.
911 static const int piix_sidx_map
[] = {
917 static void piix_sidpr_sel(struct ata_link
*link
, unsigned int reg
)
919 struct ata_port
*ap
= link
->ap
;
920 struct piix_host_priv
*hpriv
= ap
->host
->private_data
;
922 iowrite32(((ap
->port_no
* 2 + link
->pmp
) << 8) | piix_sidx_map
[reg
],
923 hpriv
->sidpr
+ PIIX_SIDPR_IDX
);
926 static int piix_sidpr_scr_read(struct ata_link
*link
,
927 unsigned int reg
, u32
*val
)
929 struct piix_host_priv
*hpriv
= link
->ap
->host
->private_data
;
931 if (reg
>= ARRAY_SIZE(piix_sidx_map
))
934 piix_sidpr_sel(link
, reg
);
935 *val
= ioread32(hpriv
->sidpr
+ PIIX_SIDPR_DATA
);
939 static int piix_sidpr_scr_write(struct ata_link
*link
,
940 unsigned int reg
, u32 val
)
942 struct piix_host_priv
*hpriv
= link
->ap
->host
->private_data
;
944 if (reg
>= ARRAY_SIZE(piix_sidx_map
))
947 piix_sidpr_sel(link
, reg
);
948 iowrite32(val
, hpriv
->sidpr
+ PIIX_SIDPR_DATA
);
953 static int piix_broken_suspend(void)
955 static const struct dmi_system_id sysids
[] = {
959 DMI_MATCH(DMI_SYS_VENDOR
, "TOSHIBA"),
960 DMI_MATCH(DMI_PRODUCT_NAME
, "TECRA M3"),
966 DMI_MATCH(DMI_SYS_VENDOR
, "TOSHIBA"),
967 DMI_MATCH(DMI_PRODUCT_NAME
, "Tecra M3"),
973 DMI_MATCH(DMI_SYS_VENDOR
, "TOSHIBA"),
974 DMI_MATCH(DMI_PRODUCT_NAME
, "Tecra M4"),
980 DMI_MATCH(DMI_SYS_VENDOR
, "TOSHIBA"),
981 DMI_MATCH(DMI_PRODUCT_NAME
, "TECRA M4"),
987 DMI_MATCH(DMI_SYS_VENDOR
, "TOSHIBA"),
988 DMI_MATCH(DMI_PRODUCT_NAME
, "TECRA M5"),
994 DMI_MATCH(DMI_SYS_VENDOR
, "TOSHIBA"),
995 DMI_MATCH(DMI_PRODUCT_NAME
, "TECRA M6"),
1001 DMI_MATCH(DMI_SYS_VENDOR
, "TOSHIBA"),
1002 DMI_MATCH(DMI_PRODUCT_NAME
, "TECRA M7"),
1006 .ident
= "TECRA A8",
1008 DMI_MATCH(DMI_SYS_VENDOR
, "TOSHIBA"),
1009 DMI_MATCH(DMI_PRODUCT_NAME
, "TECRA A8"),
1013 .ident
= "Satellite R20",
1015 DMI_MATCH(DMI_SYS_VENDOR
, "TOSHIBA"),
1016 DMI_MATCH(DMI_PRODUCT_NAME
, "Satellite R20"),
1020 .ident
= "Satellite R25",
1022 DMI_MATCH(DMI_SYS_VENDOR
, "TOSHIBA"),
1023 DMI_MATCH(DMI_PRODUCT_NAME
, "Satellite R25"),
1027 .ident
= "Satellite U200",
1029 DMI_MATCH(DMI_SYS_VENDOR
, "TOSHIBA"),
1030 DMI_MATCH(DMI_PRODUCT_NAME
, "Satellite U200"),
1034 .ident
= "Satellite U200",
1036 DMI_MATCH(DMI_SYS_VENDOR
, "TOSHIBA"),
1037 DMI_MATCH(DMI_PRODUCT_NAME
, "SATELLITE U200"),
1041 .ident
= "Satellite Pro U200",
1043 DMI_MATCH(DMI_SYS_VENDOR
, "TOSHIBA"),
1044 DMI_MATCH(DMI_PRODUCT_NAME
, "SATELLITE PRO U200"),
1048 .ident
= "Satellite U205",
1050 DMI_MATCH(DMI_SYS_VENDOR
, "TOSHIBA"),
1051 DMI_MATCH(DMI_PRODUCT_NAME
, "Satellite U205"),
1055 .ident
= "SATELLITE U205",
1057 DMI_MATCH(DMI_SYS_VENDOR
, "TOSHIBA"),
1058 DMI_MATCH(DMI_PRODUCT_NAME
, "SATELLITE U205"),
1062 .ident
= "Portege M500",
1064 DMI_MATCH(DMI_SYS_VENDOR
, "TOSHIBA"),
1065 DMI_MATCH(DMI_PRODUCT_NAME
, "PORTEGE M500"),
1069 .ident
= "VGN-BX297XP",
1071 DMI_MATCH(DMI_SYS_VENDOR
, "Sony Corporation"),
1072 DMI_MATCH(DMI_PRODUCT_NAME
, "VGN-BX297XP"),
1076 { } /* terminate list */
1078 static const char *oemstrs
[] = {
1083 if (dmi_check_system(sysids
))
1086 for (i
= 0; i
< ARRAY_SIZE(oemstrs
); i
++)
1087 if (dmi_find_device(DMI_DEV_TYPE_OEM_STRING
, oemstrs
[i
], NULL
))
1090 /* TECRA M4 sometimes forgets its identify and reports bogus
1091 * DMI information. As the bogus information is a bit
1092 * generic, match as many entries as possible. This manual
1093 * matching is necessary because dmi_system_id.matches is
1094 * limited to four entries.
1096 if (dmi_match(DMI_SYS_VENDOR
, "TOSHIBA") &&
1097 dmi_match(DMI_PRODUCT_NAME
, "000000") &&
1098 dmi_match(DMI_PRODUCT_VERSION
, "000000") &&
1099 dmi_match(DMI_PRODUCT_SERIAL
, "000000") &&
1100 dmi_match(DMI_BOARD_VENDOR
, "TOSHIBA") &&
1101 dmi_match(DMI_BOARD_NAME
, "Portable PC") &&
1102 dmi_match(DMI_BOARD_VERSION
, "Version A0"))
1108 static int piix_pci_device_suspend(struct pci_dev
*pdev
, pm_message_t mesg
)
1110 struct ata_host
*host
= dev_get_drvdata(&pdev
->dev
);
1111 unsigned long flags
;
1114 rc
= ata_host_suspend(host
, mesg
);
1118 /* Some braindamaged ACPI suspend implementations expect the
1119 * controller to be awake on entry; otherwise, it burns cpu
1120 * cycles and power trying to do something to the sleeping
1123 if (piix_broken_suspend() && (mesg
.event
& PM_EVENT_SLEEP
)) {
1124 pci_save_state(pdev
);
1126 /* mark its power state as "unknown", since we don't
1127 * know if e.g. the BIOS will change its device state
1130 if (pdev
->current_state
== PCI_D0
)
1131 pdev
->current_state
= PCI_UNKNOWN
;
1133 /* tell resume that it's waking up from broken suspend */
1134 spin_lock_irqsave(&host
->lock
, flags
);
1135 host
->flags
|= PIIX_HOST_BROKEN_SUSPEND
;
1136 spin_unlock_irqrestore(&host
->lock
, flags
);
1138 ata_pci_device_do_suspend(pdev
, mesg
);
1143 static int piix_pci_device_resume(struct pci_dev
*pdev
)
1145 struct ata_host
*host
= dev_get_drvdata(&pdev
->dev
);
1146 unsigned long flags
;
1149 if (host
->flags
& PIIX_HOST_BROKEN_SUSPEND
) {
1150 spin_lock_irqsave(&host
->lock
, flags
);
1151 host
->flags
&= ~PIIX_HOST_BROKEN_SUSPEND
;
1152 spin_unlock_irqrestore(&host
->lock
, flags
);
1154 pci_set_power_state(pdev
, PCI_D0
);
1155 pci_restore_state(pdev
);
1157 /* PCI device wasn't disabled during suspend. Use
1158 * pci_reenable_device() to avoid affecting the enable
1161 rc
= pci_reenable_device(pdev
);
1163 dev_printk(KERN_ERR
, &pdev
->dev
, "failed to enable "
1164 "device after resume (%d)\n", rc
);
1166 rc
= ata_pci_device_do_resume(pdev
);
1169 ata_host_resume(host
);
1175 static u8
piix_vmw_bmdma_status(struct ata_port
*ap
)
1177 return ata_bmdma_status(ap
) & ~ATA_DMA_ERR
;
1180 #define AHCI_PCI_BAR 5
1181 #define AHCI_GLOBAL_CTL 0x04
1182 #define AHCI_ENABLE (1 << 31)
1183 static int piix_disable_ahci(struct pci_dev
*pdev
)
1189 /* BUG: pci_enable_device has not yet been called. This
1190 * works because this device is usually set up by BIOS.
1193 if (!pci_resource_start(pdev
, AHCI_PCI_BAR
) ||
1194 !pci_resource_len(pdev
, AHCI_PCI_BAR
))
1197 mmio
= pci_iomap(pdev
, AHCI_PCI_BAR
, 64);
1201 tmp
= ioread32(mmio
+ AHCI_GLOBAL_CTL
);
1202 if (tmp
& AHCI_ENABLE
) {
1203 tmp
&= ~AHCI_ENABLE
;
1204 iowrite32(tmp
, mmio
+ AHCI_GLOBAL_CTL
);
1206 tmp
= ioread32(mmio
+ AHCI_GLOBAL_CTL
);
1207 if (tmp
& AHCI_ENABLE
)
1211 pci_iounmap(pdev
, mmio
);
1216 * piix_check_450nx_errata - Check for problem 450NX setup
1217 * @ata_dev: the PCI device to check
1219 * Check for the present of 450NX errata #19 and errata #25. If
1220 * they are found return an error code so we can turn off DMA
1223 static int __devinit
piix_check_450nx_errata(struct pci_dev
*ata_dev
)
1225 struct pci_dev
*pdev
= NULL
;
1227 int no_piix_dma
= 0;
1229 while ((pdev
= pci_get_device(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82454NX
, pdev
)) != NULL
) {
1230 /* Look for 450NX PXB. Check for problem configurations
1231 A PCI quirk checks bit 6 already */
1232 pci_read_config_word(pdev
, 0x41, &cfg
);
1233 /* Only on the original revision: IDE DMA can hang */
1234 if (pdev
->revision
== 0x00)
1236 /* On all revisions below 5 PXB bus lock must be disabled for IDE */
1237 else if (cfg
& (1<<14) && pdev
->revision
< 5)
1241 dev_printk(KERN_WARNING
, &ata_dev
->dev
, "450NX errata present, disabling IDE DMA.\n");
1242 if (no_piix_dma
== 2)
1243 dev_printk(KERN_WARNING
, &ata_dev
->dev
, "A BIOS update may resolve this.\n");
1247 static void __devinit
piix_init_pcs(struct ata_host
*host
,
1248 const struct piix_map_db
*map_db
)
1250 struct pci_dev
*pdev
= to_pci_dev(host
->dev
);
1253 pci_read_config_word(pdev
, ICH5_PCS
, &pcs
);
1255 new_pcs
= pcs
| map_db
->port_enable
;
1257 if (new_pcs
!= pcs
) {
1258 DPRINTK("updating PCS from 0x%x to 0x%x\n", pcs
, new_pcs
);
1259 pci_write_config_word(pdev
, ICH5_PCS
, new_pcs
);
1264 static const int *__devinit
piix_init_sata_map(struct pci_dev
*pdev
,
1265 struct ata_port_info
*pinfo
,
1266 const struct piix_map_db
*map_db
)
1269 int i
, invalid_map
= 0;
1272 pci_read_config_byte(pdev
, ICH5_PMR
, &map_value
);
1274 map
= map_db
->map
[map_value
& map_db
->mask
];
1276 dev_printk(KERN_INFO
, &pdev
->dev
, "MAP [");
1277 for (i
= 0; i
< 4; i
++) {
1289 WARN_ON((i
& 1) || map
[i
+ 1] != IDE
);
1290 pinfo
[i
/ 2] = piix_port_info
[ich_pata_100
];
1296 printk(" P%d", map
[i
]);
1298 pinfo
[i
/ 2].flags
|= ATA_FLAG_SLAVE_POSS
;
1305 dev_printk(KERN_ERR
, &pdev
->dev
,
1306 "invalid MAP value %u\n", map_value
);
1311 static bool piix_no_sidpr(struct ata_host
*host
)
1313 struct pci_dev
*pdev
= to_pci_dev(host
->dev
);
1316 * Samsung DB-P70 only has three ATA ports exposed and
1317 * curiously the unconnected first port reports link online
1318 * while not responding to SRST protocol causing excessive
1321 * Unfortunately, the system doesn't carry enough DMI
1322 * information to identify the machine but does have subsystem
1323 * vendor and device set. As it's unclear whether the
1324 * subsystem vendor/device is used only for this specific
1325 * board, the port can't be disabled solely with the
1326 * information; however, turning off SIDPR access works around
1327 * the problem. Turn it off.
1329 * This problem is reported in bnc#441240.
1331 * https://bugzilla.novell.com/show_bug.cgi?id=441420
1333 if (pdev
->vendor
== PCI_VENDOR_ID_INTEL
&& pdev
->device
== 0x2920 &&
1334 pdev
->subsystem_vendor
== PCI_VENDOR_ID_SAMSUNG
&&
1335 pdev
->subsystem_device
== 0xb049) {
1336 dev_printk(KERN_WARNING
, host
->dev
,
1337 "Samsung DB-P70 detected, disabling SIDPR\n");
1344 static int __devinit
piix_init_sidpr(struct ata_host
*host
)
1346 struct pci_dev
*pdev
= to_pci_dev(host
->dev
);
1347 struct piix_host_priv
*hpriv
= host
->private_data
;
1348 struct ata_link
*link0
= &host
->ports
[0]->link
;
1352 /* check for availability */
1353 for (i
= 0; i
< 4; i
++)
1354 if (hpriv
->map
[i
] == IDE
)
1357 /* is it blacklisted? */
1358 if (piix_no_sidpr(host
))
1361 if (!(host
->ports
[0]->flags
& PIIX_FLAG_SIDPR
))
1364 if (pci_resource_start(pdev
, PIIX_SIDPR_BAR
) == 0 ||
1365 pci_resource_len(pdev
, PIIX_SIDPR_BAR
) != PIIX_SIDPR_LEN
)
1368 if (pcim_iomap_regions(pdev
, 1 << PIIX_SIDPR_BAR
, DRV_NAME
))
1371 hpriv
->sidpr
= pcim_iomap_table(pdev
)[PIIX_SIDPR_BAR
];
1373 /* SCR access via SIDPR doesn't work on some configurations.
1374 * Give it a test drive by inhibiting power save modes which
1377 piix_sidpr_scr_read(link0
, SCR_CONTROL
, &scontrol
);
1379 /* if IPM is already 3, SCR access is probably working. Don't
1380 * un-inhibit power save modes as BIOS might have inhibited
1381 * them for a reason.
1383 if ((scontrol
& 0xf00) != 0x300) {
1385 piix_sidpr_scr_write(link0
, SCR_CONTROL
, scontrol
);
1386 piix_sidpr_scr_read(link0
, SCR_CONTROL
, &scontrol
);
1388 if ((scontrol
& 0xf00) != 0x300) {
1389 dev_printk(KERN_INFO
, host
->dev
, "SCR access via "
1390 "SIDPR is available but doesn't work\n");
1395 /* okay, SCRs available, set ops and ask libata for slave_link */
1396 for (i
= 0; i
< 2; i
++) {
1397 struct ata_port
*ap
= host
->ports
[i
];
1399 ap
->ops
= &piix_sidpr_sata_ops
;
1401 if (ap
->flags
& ATA_FLAG_SLAVE_POSS
) {
1402 rc
= ata_slave_link_init(ap
);
1411 static void piix_iocfg_bit18_quirk(struct ata_host
*host
)
1413 static const struct dmi_system_id sysids
[] = {
1415 /* Clevo M570U sets IOCFG bit 18 if the cdrom
1416 * isn't used to boot the system which
1417 * disables the channel.
1421 DMI_MATCH(DMI_SYS_VENDOR
, "Clevo Co."),
1422 DMI_MATCH(DMI_PRODUCT_NAME
, "M570U"),
1426 { } /* terminate list */
1428 struct pci_dev
*pdev
= to_pci_dev(host
->dev
);
1429 struct piix_host_priv
*hpriv
= host
->private_data
;
1431 if (!dmi_check_system(sysids
))
1434 /* The datasheet says that bit 18 is NOOP but certain systems
1435 * seem to use it to disable a channel. Clear the bit on the
1438 if (hpriv
->saved_iocfg
& (1 << 18)) {
1439 dev_printk(KERN_INFO
, &pdev
->dev
,
1440 "applying IOCFG bit18 quirk\n");
1441 pci_write_config_dword(pdev
, PIIX_IOCFG
,
1442 hpriv
->saved_iocfg
& ~(1 << 18));
1446 static bool piix_broken_system_poweroff(struct pci_dev
*pdev
)
1448 static const struct dmi_system_id broken_systems
[] = {
1450 .ident
= "HP Compaq 2510p",
1452 DMI_MATCH(DMI_SYS_VENDOR
, "Hewlett-Packard"),
1453 DMI_MATCH(DMI_PRODUCT_NAME
, "HP Compaq 2510p"),
1455 /* PCI slot number of the controller */
1456 .driver_data
= (void *)0x1FUL
,
1459 { } /* terminate list */
1461 const struct dmi_system_id
*dmi
= dmi_first_match(broken_systems
);
1464 unsigned long slot
= (unsigned long)dmi
->driver_data
;
1465 /* apply the quirk only to on-board controllers */
1466 return slot
== PCI_SLOT(pdev
->devfn
);
1473 * piix_init_one - Register PIIX ATA PCI device with kernel services
1474 * @pdev: PCI device to register
1475 * @ent: Entry in piix_pci_tbl matching with @pdev
1477 * Called from kernel PCI layer. We probe for combined mode (sigh),
1478 * and then hand over control to libata, for it to do the rest.
1481 * Inherited from PCI layer (may sleep).
1484 * Zero on success, or -ERRNO value.
1487 static int __devinit
piix_init_one(struct pci_dev
*pdev
,
1488 const struct pci_device_id
*ent
)
1490 static int printed_version
;
1491 struct device
*dev
= &pdev
->dev
;
1492 struct ata_port_info port_info
[2];
1493 const struct ata_port_info
*ppi
[] = { &port_info
[0], &port_info
[1] };
1494 unsigned long port_flags
;
1495 struct ata_host
*host
;
1496 struct piix_host_priv
*hpriv
;
1499 if (!printed_version
++)
1500 dev_printk(KERN_DEBUG
, &pdev
->dev
,
1501 "version " DRV_VERSION
"\n");
1503 /* no hotplugging support (FIXME) */
1504 if (!in_module_init
)
1507 if (piix_broken_system_poweroff(pdev
)) {
1508 piix_port_info
[ent
->driver_data
].flags
|=
1509 ATA_FLAG_NO_POWEROFF_SPINDOWN
|
1510 ATA_FLAG_NO_HIBERNATE_SPINDOWN
;
1511 dev_info(&pdev
->dev
, "quirky BIOS, skipping spindown "
1512 "on poweroff and hibernation\n");
1515 port_info
[0] = piix_port_info
[ent
->driver_data
];
1516 port_info
[1] = piix_port_info
[ent
->driver_data
];
1518 port_flags
= port_info
[0].flags
;
1520 /* enable device and prepare host */
1521 rc
= pcim_enable_device(pdev
);
1525 hpriv
= devm_kzalloc(dev
, sizeof(*hpriv
), GFP_KERNEL
);
1529 /* Save IOCFG, this will be used for cable detection, quirk
1530 * detection and restoration on detach. This is necessary
1531 * because some ACPI implementations mess up cable related
1532 * bits on _STM. Reported on kernel bz#11879.
1534 pci_read_config_dword(pdev
, PIIX_IOCFG
, &hpriv
->saved_iocfg
);
1536 /* ICH6R may be driven by either ata_piix or ahci driver
1537 * regardless of BIOS configuration. Make sure AHCI mode is
1540 if (pdev
->vendor
== PCI_VENDOR_ID_INTEL
&& pdev
->device
== 0x2652) {
1541 rc
= piix_disable_ahci(pdev
);
1546 /* SATA map init can change port_info, do it before prepping host */
1547 if (port_flags
& ATA_FLAG_SATA
)
1548 hpriv
->map
= piix_init_sata_map(pdev
, port_info
,
1549 piix_map_db_table
[ent
->driver_data
]);
1551 rc
= ata_pci_sff_prepare_host(pdev
, ppi
, &host
);
1554 host
->private_data
= hpriv
;
1556 /* initialize controller */
1557 if (port_flags
& ATA_FLAG_SATA
) {
1558 piix_init_pcs(host
, piix_map_db_table
[ent
->driver_data
]);
1559 rc
= piix_init_sidpr(host
);
1564 /* apply IOCFG bit18 quirk */
1565 piix_iocfg_bit18_quirk(host
);
1567 /* On ICH5, some BIOSen disable the interrupt using the
1568 * PCI_COMMAND_INTX_DISABLE bit added in PCI 2.3.
1569 * On ICH6, this bit has the same effect, but only when
1570 * MSI is disabled (and it is disabled, as we don't use
1571 * message-signalled interrupts currently).
1573 if (port_flags
& PIIX_FLAG_CHECKINTR
)
1576 if (piix_check_450nx_errata(pdev
)) {
1577 /* This writes into the master table but it does not
1578 really matter for this errata as we will apply it to
1579 all the PIIX devices on the board */
1580 host
->ports
[0]->mwdma_mask
= 0;
1581 host
->ports
[0]->udma_mask
= 0;
1582 host
->ports
[1]->mwdma_mask
= 0;
1583 host
->ports
[1]->udma_mask
= 0;
1586 pci_set_master(pdev
);
1587 return ata_pci_sff_activate_host(host
, ata_sff_interrupt
, &piix_sht
);
1590 static void piix_remove_one(struct pci_dev
*pdev
)
1592 struct ata_host
*host
= dev_get_drvdata(&pdev
->dev
);
1593 struct piix_host_priv
*hpriv
= host
->private_data
;
1595 pci_write_config_dword(pdev
, PIIX_IOCFG
, hpriv
->saved_iocfg
);
1597 ata_pci_remove_one(pdev
);
1600 static int __init
piix_init(void)
1604 DPRINTK("pci_register_driver\n");
1605 rc
= pci_register_driver(&piix_pci_driver
);
1615 static void __exit
piix_exit(void)
1617 pci_unregister_driver(&piix_pci_driver
);
1620 module_init(piix_init
);
1621 module_exit(piix_exit
);