drivers/spi/spi-sh-hspi.c

   1 /*
   2  * SuperH HSPI bus driver
   3  *
   4  * Copyright (C) 2011  Kuninori Morimoto
   5  *
   6  * Based on spi-sh.c:
   7  * Based on pxa2xx_spi.c:
   8  * Copyright (C) 2011 Renesas Solutions Corp.
   9  * Copyright (C) 2005 Stephen Street / StreetFire Sound Labs
  10  *
  11  * This program is free software; you can redistribute it and/or modify
  12  * it under the terms of the GNU General Public License as published by
  13  * the Free Software Foundation; version 2 of the License.
  14  *
  15  * This program is distributed in the hope that it will be useful,
  16  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  17  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  18  * GNU General Public License for more details.
  19  *
  20  * You should have received a copy of the GNU General Public License
  21  * along with this program; if not, write to the Free Software
  22  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
  23  *
  24  */
  25
  26 #include <linux/clk.h>
  27 #include <linux/module.h>
  28 #include <linux/kernel.h>
  29 #include <linux/timer.h>
  30 #include <linux/delay.h>
  31 #include <linux/list.h>
  32 #include <linux/interrupt.h>
  33 #include <linux/platform_device.h>
  34 #include <linux/pm_runtime.h>
  35 #include <linux/io.h>
  36 #include <linux/spi/spi.h>
  37 #include <linux/spi/sh_hspi.h>
  38
  39 #define SPCR    0x00
  40 #define SPSR    0x04
  41 #define SPSCR   0x08
  42 #define SPTBR   0x0C
  43 #define SPRBR   0x10
  44 #define SPCR2   0x14
  45
  46 /* SPSR */
  47 #define RXFL    (1 << 2)
  48
  49 #define hspi2info(h)    (h->dev->platform_data)
  50
  51 struct hspi_priv {
  52         void __iomem *addr;
  53         struct spi_master *master;
  54         struct device *dev;
  55         struct clk *clk;
  56 };
  57
  58 /*
  59  *              basic function
  60  */
  61 static void hspi_write(struct hspi_priv *hspi, int reg, u32 val)
  62 {
  63         iowrite32(val, hspi->addr + reg);
  64 }
  65
  66 static u32 hspi_read(struct hspi_priv *hspi, int reg)
  67 {
  68         return ioread32(hspi->addr + reg);
  69 }
  70
  71 static void hspi_bit_set(struct hspi_priv *hspi, int reg, u32 mask, u32 set)
  72 {
  73         u32 val = hspi_read(hspi, reg);
  74
  75         val &= ~mask;
  76         val |= set & mask;
  77
  78         hspi_write(hspi, reg, val);
  79 }
  80
  81 /*
  82  *              transfer function
  83  */
  84 static int hspi_status_check_timeout(struct hspi_priv *hspi, u32 mask, u32 val)
  85 {
  86         int t = 256;
  87
  88         while (t--) {
  89                 if ((mask & hspi_read(hspi, SPSR)) == val)
  90                         return 0;
  91
  92                 udelay(10);
  93         }
  94
  95         dev_err(hspi->dev, "timeout\n");
  96         return -ETIMEDOUT;
  97 }
  98
  99 /*
 100  *              spi master function
 101  */
 102 static int hspi_prepare_transfer(struct spi_master *master)
 103 {
 104         struct hspi_priv *hspi = spi_master_get_devdata(master);
 105
 106         pm_runtime_get_sync(hspi->dev);
 107         return 0;
 108 }
 109
 110 static int hspi_unprepare_transfer(struct spi_master *master)
 111 {
 112         struct hspi_priv *hspi = spi_master_get_devdata(master);
 113
 114         pm_runtime_put_sync(hspi->dev);
 115         return 0;
 116 }
 117
 118 #define hspi_hw_cs_enable(hspi)         hspi_hw_cs_ctrl(hspi, 0)
 119 #define hspi_hw_cs_disable(hspi)        hspi_hw_cs_ctrl(hspi, 1)
 120 static void hspi_hw_cs_ctrl(struct hspi_priv *hspi, int hi)
 121 {
 122         hspi_bit_set(hspi, SPSCR, (1 << 6), (hi) << 6);
 123 }
 124
 125 static void hspi_hw_setup(struct hspi_priv *hspi,
 126                           struct spi_message *msg,
 127                           struct spi_transfer *t)
 128 {
 129         struct spi_device *spi = msg->spi;
 130         struct device *dev = hspi->dev;
 131         u32 target_rate;
 132         u32 spcr, idiv_clk;
 133         u32 rate, best_rate, min, tmp;
 134
 135         target_rate = t ? t->speed_hz : 0;
 136         if (!target_rate)
 137                 target_rate = spi->max_speed_hz;
 138
 139         /*
 140          * find best IDIV/CLKCx settings
 141          */
 142         min = ~0;
 143         best_rate = 0;
 144         spcr = 0;
 145         for (idiv_clk = 0x00; idiv_clk <= 0x3F; idiv_clk++) {
 146                 rate = clk_get_rate(hspi->clk);
 147
 148                 /* IDIV calculation */
 149                 if (idiv_clk & (1 << 5))
 150                         rate /= 128;
 151                 else
 152                         rate /= 16;
 153
 154                 /* CLKCx calculation */
 155                 rate /= (((idiv_clk & 0x1F) + 1) * 2) ;
 156
 157                 /* save best settings */
 158                 tmp = abs(target_rate - rate);
 159                 if (tmp < min) {
 160                         min = tmp;
 161                         spcr = idiv_clk;
 162                         best_rate = rate;
 163                 }
 164         }
 165
 166         if (spi->mode & SPI_CPHA)
 167                 spcr |= 1 << 7;
 168         if (spi->mode & SPI_CPOL)
 169                 spcr |= 1 << 6;
 170
 171         dev_dbg(dev, "speed %d/%d\n", target_rate, best_rate);
 172
 173         hspi_write(hspi, SPCR, spcr);
 174         hspi_write(hspi, SPSR, 0x0);
 175         hspi_write(hspi, SPSCR, 0x21);  /* master mode / CS control */
 176 }
 177
 178 static int hspi_transfer_one_message(struct spi_master *master,
 179                                      struct spi_message *msg)
 180 {
 181         struct hspi_priv *hspi = spi_master_get_devdata(master);
 182         struct spi_transfer *t;
 183         u32 tx;
 184         u32 rx;
 185         int ret, i;
 186         unsigned int cs_change;
 187         const int nsecs = 50;
 188
 189         dev_dbg(hspi->dev, "%s\n", __func__);
 190
 191         cs_change = 1;
 192         ret = 0;
 193         list_for_each_entry(t, &msg->transfers, transfer_list) {
 194
 195                 if (cs_change) {
 196                         hspi_hw_setup(hspi, msg, t);
 197                         hspi_hw_cs_enable(hspi);
 198                         ndelay(nsecs);
 199                 }
 200                 cs_change = t->cs_change;
 201
 202                 for (i = 0; i < t->len; i++) {
 203
 204                         /* wait remains */
 205                         ret = hspi_status_check_timeout(hspi, 0x1, 0);
 206                         if (ret < 0)
 207                                 break;
 208
 209                         tx = 0;
 210                         if (t->tx_buf)
 211                                 tx = (u32)((u8 *)t->tx_buf)[i];
 212
 213                         hspi_write(hspi, SPTBR, tx);
 214
 215                         /* wait recive */
 216                         ret = hspi_status_check_timeout(hspi, 0x4, 0x4);
 217                         if (ret < 0)
 218                                 break;
 219
 220                         rx = hspi_read(hspi, SPRBR);
 221                         if (t->rx_buf)
 222                                 ((u8 *)t->rx_buf)[i] = (u8)rx;
 223
 224                 }
 225
 226                 msg->actual_length += t->len;
 227
 228                 if (t->delay_usecs)
 229                         udelay(t->delay_usecs);
 230
 231                 if (cs_change) {
 232                         ndelay(nsecs);
 233                         hspi_hw_cs_disable(hspi);
 234                         ndelay(nsecs);
 235                 }
 236         }
 237
 238         msg->status = ret;
 239         if (!cs_change) {
 240                 ndelay(nsecs);
 241                 hspi_hw_cs_disable(hspi);
 242         }
 243         spi_finalize_current_message(master);
 244
 245         return ret;
 246 }
 247
 248 static int hspi_setup(struct spi_device *spi)
 249 {
 250         struct hspi_priv *hspi = spi_master_get_devdata(spi->master);
 251         struct device *dev = hspi->dev;
 252
 253         if (8 != spi->bits_per_word) {
 254                 dev_err(dev, "bits_per_word should be 8\n");
 255                 return -EIO;
 256         }
 257
 258         dev_dbg(dev, "%s setup\n", spi->modalias);
 259
 260         return 0;
 261 }
 262
 263 static void hspi_cleanup(struct spi_device *spi)
 264 {
 265         struct hspi_priv *hspi = spi_master_get_devdata(spi->master);
 266         struct device *dev = hspi->dev;
 267
 268         dev_dbg(dev, "%s cleanup\n", spi->modalias);
 269 }
 270
 271 static int hspi_probe(struct platform_device *pdev)
 272 {
 273         struct resource *res;
 274         struct spi_master *master;
 275         struct hspi_priv *hspi;
 276         struct clk *clk;
 277         int ret;
 278
 279         /* get base addr */
 280         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 281         if (!res) {
 282                 dev_err(&pdev->dev, "invalid resource\n");
 283                 return -EINVAL;
 284         }
 285
 286         master = spi_alloc_master(&pdev->dev, sizeof(*hspi));
 287         if (!master) {
 288                 dev_err(&pdev->dev, "spi_alloc_master error.\n");
 289                 return -ENOMEM;
 290         }
 291
 292         clk = clk_get(NULL, "shyway_clk");
 293         if (IS_ERR(clk)) {
 294                 dev_err(&pdev->dev, "shyway_clk is required\n");
 295                 ret = -EINVAL;
 296                 goto error0;
 297         }
 298
 299         hspi = spi_master_get_devdata(master);
 300         platform_set_drvdata(pdev, hspi);
 301
 302         /* init hspi */
 303         hspi->master    = master;
 304         hspi->dev       = &pdev->dev;
 305         hspi->clk       = clk;
 306         hspi->addr      = devm_ioremap(hspi->dev,
 307                                        res->start, resource_size(res));
 308         if (!hspi->addr) {
 309                 dev_err(&pdev->dev, "ioremap error.\n");
 310                 ret = -ENOMEM;
 311                 goto error1;
 312         }
 313
 314         master->num_chipselect  = 1;
 315         master->bus_num         = pdev->id;
 316         master->setup           = hspi_setup;
 317         master->cleanup         = hspi_cleanup;
 318         master->mode_bits       = SPI_CPOL | SPI_CPHA;
 319         master->prepare_transfer_hardware       = hspi_prepare_transfer;
 320         master->transfer_one_message            = hspi_transfer_one_message;
 321         master->unprepare_transfer_hardware     = hspi_unprepare_transfer;
 322         ret = spi_register_master(master);
 323         if (ret < 0) {
 324                 dev_err(&pdev->dev, "spi_register_master error.\n");
 325                 goto error1;
 326         }
 327
 328         pm_runtime_enable(&pdev->dev);
 329
 330         dev_info(&pdev->dev, "probed\n");
 331
 332         return 0;
 333
 334  error1:
 335         clk_put(clk);
 336  error0:
 337         spi_master_put(master);
 338
 339         return ret;
 340 }
 341
 342 static int hspi_remove(struct platform_device *pdev)
 343 {
 344         struct hspi_priv *hspi = platform_get_drvdata(pdev);
 345
 346         pm_runtime_disable(&pdev->dev);
 347
 348         clk_put(hspi->clk);
 349         spi_unregister_master(hspi->master);
 350
 351         return 0;
 352 }
 353
 354 static struct platform_driver hspi_driver = {
 355         .probe = hspi_probe,
 356         .remove = hspi_remove,
 357         .driver = {
 358                 .name = "sh-hspi",
 359                 .owner = THIS_MODULE,
 360         },
 361 };
 362 module_platform_driver(hspi_driver);
 363
 364 MODULE_DESCRIPTION("SuperH HSPI bus driver");
 365 MODULE_LICENSE("GPL");
 366 MODULE_AUTHOR("Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>");
 367 MODULE_ALIAS("platform:sh_spi");