Linux 3.11-rc2
[linux-2.6.git] / drivers / net / dsa / mv88e6060.c
blob7a54ec04b4181210961f2819c7fca1e260cb7661
1 /*
2 * net/dsa/mv88e6060.c - Driver for Marvell 88e6060 switch chips
3 * Copyright (c) 2008-2009 Marvell Semiconductor
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or
8 * (at your option) any later version.
9 */
11 #include <linux/delay.h>
12 #include <linux/jiffies.h>
13 #include <linux/list.h>
14 #include <linux/module.h>
15 #include <linux/netdevice.h>
16 #include <linux/phy.h>
17 #include <net/dsa.h>
19 #define REG_PORT(p) (8 + (p))
20 #define REG_GLOBAL 0x0f
22 static int reg_read(struct dsa_switch *ds, int addr, int reg)
24 return mdiobus_read(ds->master_mii_bus, ds->pd->sw_addr + addr, reg);
27 #define REG_READ(addr, reg) \
28 ({ \
29 int __ret; \
31 __ret = reg_read(ds, addr, reg); \
32 if (__ret < 0) \
33 return __ret; \
34 __ret; \
38 static int reg_write(struct dsa_switch *ds, int addr, int reg, u16 val)
40 return mdiobus_write(ds->master_mii_bus, ds->pd->sw_addr + addr,
41 reg, val);
44 #define REG_WRITE(addr, reg, val) \
45 ({ \
46 int __ret; \
48 __ret = reg_write(ds, addr, reg, val); \
49 if (__ret < 0) \
50 return __ret; \
53 static char *mv88e6060_probe(struct mii_bus *bus, int sw_addr)
55 int ret;
57 ret = mdiobus_read(bus, sw_addr + REG_PORT(0), 0x03);
58 if (ret >= 0) {
59 ret &= 0xfff0;
60 if (ret == 0x0600)
61 return "Marvell 88E6060";
64 return NULL;
67 static int mv88e6060_switch_reset(struct dsa_switch *ds)
69 int i;
70 int ret;
71 unsigned long timeout;
73 /* Set all ports to the disabled state. */
74 for (i = 0; i < 6; i++) {
75 ret = REG_READ(REG_PORT(i), 0x04);
76 REG_WRITE(REG_PORT(i), 0x04, ret & 0xfffc);
79 /* Wait for transmit queues to drain. */
80 usleep_range(2000, 4000);
82 /* Reset the switch. */
83 REG_WRITE(REG_GLOBAL, 0x0a, 0xa130);
85 /* Wait up to one second for reset to complete. */
86 timeout = jiffies + 1 * HZ;
87 while (time_before(jiffies, timeout)) {
88 ret = REG_READ(REG_GLOBAL, 0x00);
89 if ((ret & 0x8000) == 0x0000)
90 break;
92 usleep_range(1000, 2000);
94 if (time_after(jiffies, timeout))
95 return -ETIMEDOUT;
97 return 0;
100 static int mv88e6060_setup_global(struct dsa_switch *ds)
102 /* Disable discarding of frames with excessive collisions,
103 * set the maximum frame size to 1536 bytes, and mask all
104 * interrupt sources.
106 REG_WRITE(REG_GLOBAL, 0x04, 0x0800);
108 /* Enable automatic address learning, set the address
109 * database size to 1024 entries, and set the default aging
110 * time to 5 minutes.
112 REG_WRITE(REG_GLOBAL, 0x0a, 0x2130);
114 return 0;
117 static int mv88e6060_setup_port(struct dsa_switch *ds, int p)
119 int addr = REG_PORT(p);
121 /* Do not force flow control, disable Ingress and Egress
122 * Header tagging, disable VLAN tunneling, and set the port
123 * state to Forwarding. Additionally, if this is the CPU
124 * port, enable Ingress and Egress Trailer tagging mode.
126 REG_WRITE(addr, 0x04, dsa_is_cpu_port(ds, p) ? 0x4103 : 0x0003);
128 /* Port based VLAN map: give each port its own address
129 * database, allow the CPU port to talk to each of the 'real'
130 * ports, and allow each of the 'real' ports to only talk to
131 * the CPU port.
133 REG_WRITE(addr, 0x06,
134 ((p & 0xf) << 12) |
135 (dsa_is_cpu_port(ds, p) ?
136 ds->phys_port_mask :
137 (1 << ds->dst->cpu_port)));
139 /* Port Association Vector: when learning source addresses
140 * of packets, add the address to the address database using
141 * a port bitmap that has only the bit for this port set and
142 * the other bits clear.
144 REG_WRITE(addr, 0x0b, 1 << p);
146 return 0;
149 static int mv88e6060_setup(struct dsa_switch *ds)
151 int i;
152 int ret;
154 ret = mv88e6060_switch_reset(ds);
155 if (ret < 0)
156 return ret;
158 /* @@@ initialise atu */
160 ret = mv88e6060_setup_global(ds);
161 if (ret < 0)
162 return ret;
164 for (i = 0; i < 6; i++) {
165 ret = mv88e6060_setup_port(ds, i);
166 if (ret < 0)
167 return ret;
170 return 0;
173 static int mv88e6060_set_addr(struct dsa_switch *ds, u8 *addr)
175 REG_WRITE(REG_GLOBAL, 0x01, (addr[0] << 8) | addr[1]);
176 REG_WRITE(REG_GLOBAL, 0x02, (addr[2] << 8) | addr[3]);
177 REG_WRITE(REG_GLOBAL, 0x03, (addr[4] << 8) | addr[5]);
179 return 0;
182 static int mv88e6060_port_to_phy_addr(int port)
184 if (port >= 0 && port <= 5)
185 return port;
186 return -1;
189 static int mv88e6060_phy_read(struct dsa_switch *ds, int port, int regnum)
191 int addr;
193 addr = mv88e6060_port_to_phy_addr(port);
194 if (addr == -1)
195 return 0xffff;
197 return reg_read(ds, addr, regnum);
200 static int
201 mv88e6060_phy_write(struct dsa_switch *ds, int port, int regnum, u16 val)
203 int addr;
205 addr = mv88e6060_port_to_phy_addr(port);
206 if (addr == -1)
207 return 0xffff;
209 return reg_write(ds, addr, regnum, val);
212 static void mv88e6060_poll_link(struct dsa_switch *ds)
214 int i;
216 for (i = 0; i < DSA_MAX_PORTS; i++) {
217 struct net_device *dev;
218 int uninitialized_var(port_status);
219 int link;
220 int speed;
221 int duplex;
222 int fc;
224 dev = ds->ports[i];
225 if (dev == NULL)
226 continue;
228 link = 0;
229 if (dev->flags & IFF_UP) {
230 port_status = reg_read(ds, REG_PORT(i), 0x00);
231 if (port_status < 0)
232 continue;
234 link = !!(port_status & 0x1000);
237 if (!link) {
238 if (netif_carrier_ok(dev)) {
239 netdev_info(dev, "link down\n");
240 netif_carrier_off(dev);
242 continue;
245 speed = (port_status & 0x0100) ? 100 : 10;
246 duplex = (port_status & 0x0200) ? 1 : 0;
247 fc = ((port_status & 0xc000) == 0xc000) ? 1 : 0;
249 if (!netif_carrier_ok(dev)) {
250 netdev_info(dev,
251 "link up, %d Mb/s, %s duplex, flow control %sabled\n",
252 speed,
253 duplex ? "full" : "half",
254 fc ? "en" : "dis");
255 netif_carrier_on(dev);
260 static struct dsa_switch_driver mv88e6060_switch_driver = {
261 .tag_protocol = htons(ETH_P_TRAILER),
262 .probe = mv88e6060_probe,
263 .setup = mv88e6060_setup,
264 .set_addr = mv88e6060_set_addr,
265 .phy_read = mv88e6060_phy_read,
266 .phy_write = mv88e6060_phy_write,
267 .poll_link = mv88e6060_poll_link,
270 static int __init mv88e6060_init(void)
272 register_switch_driver(&mv88e6060_switch_driver);
273 return 0;
275 module_init(mv88e6060_init);
277 static void __exit mv88e6060_cleanup(void)
279 unregister_switch_driver(&mv88e6060_switch_driver);
281 module_exit(mv88e6060_cleanup);
283 MODULE_AUTHOR("Lennert Buytenhek <buytenh@wantstofly.org>");
284 MODULE_DESCRIPTION("Driver for Marvell 88E6060 ethernet switch chip");
285 MODULE_LICENSE("GPL");
286 MODULE_ALIAS("platform:mv88e6060");