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[PATCH] fs/ext3/: small cleanups
[linux-2.6.git] / drivers / video / aty / radeonfb.h
blob217e00ab4a2d284ba899679e39727fb9b4d5dee6
1 #ifndef __RADEONFB_H__
2 #define __RADEONFB_H__
3
4 #include <linux/config.h>
5 #include <linux/module.h>
6 #include <linux/kernel.h>
7 #include <linux/sched.h>
8 #include <linux/delay.h>
9 #include <linux/pci.h>
10 #include <linux/fb.h>
11
12
13 #ifdef CONFIG_FB_RADEON_I2C
14 #include <linux/i2c.h>
15 #include <linux/i2c-algo-bit.h>
16 #endif
17
18 #include <asm/io.h>
19
20 #ifdef CONFIG_PPC_OF
21 #include <asm/prom.h>
22 #endif
23
24 #include <video/radeon.h>
25
26 /***************************************************************
27 * Most of the definitions here are adapted right from XFree86 *
28 ***************************************************************/
29
30
31 /*
32 * Chip families. Must fit in the low 16 bits of a long word
33 */
34 enum radeon_family {
35 CHIP_FAMILY_UNKNOW,
36 CHIP_FAMILY_LEGACY,
37 CHIP_FAMILY_RADEON,
38 CHIP_FAMILY_RV100,
39 CHIP_FAMILY_RS100, /* U1 (IGP320M) or A3 (IGP320)*/
40 CHIP_FAMILY_RV200,
41 CHIP_FAMILY_RS200, /* U2 (IGP330M/340M/350M) or A4 (IGP330/340/345/350),
42 RS250 (IGP 7000) */
43 CHIP_FAMILY_R200,
44 CHIP_FAMILY_RV250,
45 CHIP_FAMILY_RS300, /* Radeon 9000 IGP */
46 CHIP_FAMILY_RV280,
47 CHIP_FAMILY_R300,
48 CHIP_FAMILY_R350,
49 CHIP_FAMILY_RV350,
50 CHIP_FAMILY_RV380, /* RV370/RV380/M22/M24 */
51 CHIP_FAMILY_R420, /* R420/R423/M18 */
52 CHIP_FAMILY_LAST,
53 };
54
55 #define IS_RV100_VARIANT(rinfo) (((rinfo)->family == CHIP_FAMILY_RV100) || \
56 ((rinfo)->family == CHIP_FAMILY_RV200) || \
57 ((rinfo)->family == CHIP_FAMILY_RS100) || \
58 ((rinfo)->family == CHIP_FAMILY_RS200) || \
59 ((rinfo)->family == CHIP_FAMILY_RV250) || \
60 ((rinfo)->family == CHIP_FAMILY_RV280) || \
61 ((rinfo)->family == CHIP_FAMILY_RS300))
62
63
64 #define IS_R300_VARIANT(rinfo) (((rinfo)->family == CHIP_FAMILY_R300) || \
65 ((rinfo)->family == CHIP_FAMILY_RV350) || \
66 ((rinfo)->family == CHIP_FAMILY_R350) || \
67 ((rinfo)->family == CHIP_FAMILY_RV380) || \
68 ((rinfo)->family == CHIP_FAMILY_R420))
69
70 /*
71 * Chip flags
72 */
73 enum radeon_chip_flags {
74 CHIP_FAMILY_MASK = 0x0000ffffUL,
75 CHIP_FLAGS_MASK = 0xffff0000UL,
76 CHIP_IS_MOBILITY = 0x00010000UL,
77 CHIP_IS_IGP = 0x00020000UL,
78 CHIP_HAS_CRTC2 = 0x00040000UL,
79 };
80
81 /*
82 * Errata workarounds
83 */
84 enum radeon_errata {
85 CHIP_ERRATA_R300_CG = 0x00000001,
86 CHIP_ERRATA_PLL_DUMMYREADS = 0x00000002,
87 CHIP_ERRATA_PLL_DELAY = 0x00000004,
88 };
89
90
91 /*
92 * Monitor types
93 */
94 enum radeon_montype {
95 MT_NONE = 0,
96 MT_CRT, /* CRT */
97 MT_LCD, /* LCD */
98 MT_DFP, /* DVI */
99 MT_CTV, /* composite TV */
100 MT_STV /* S-Video out */
101 };
102
103 /*
104 * DDC i2c ports
105 */
106 enum ddc_type {
107 ddc_none,
108 ddc_monid,
109 ddc_dvi,
110 ddc_vga,
111 ddc_crt2,
112 };
113
114 /*
115 * Connector types
116 */
117 enum conn_type {
118 conn_none,
119 conn_proprietary,
120 conn_crt,
121 conn_DVI_I,
122 conn_DVI_D,
123 };
124
125
126 /*
127 * PLL infos
128 */
129 struct pll_info {
130 int ppll_max;
131 int ppll_min;
132 int sclk, mclk;
133 int ref_div;
134 int ref_clk;
135 };
136
137
138 /*
139 * This structure contains the various registers manipulated by this
140 * driver for setting or restoring a mode. It's mostly copied from
141 * XFree's RADEONSaveRec structure. A few chip settings might still be
142 * tweaked without beeing reflected or saved in these registers though
143 */
144 struct radeon_regs {
145 /* Common registers */
146 u32 ovr_clr;
147 u32 ovr_wid_left_right;
148 u32 ovr_wid_top_bottom;
149 u32 ov0_scale_cntl;
150 u32 mpp_tb_config;
151 u32 mpp_gp_config;
152 u32 subpic_cntl;
153 u32 viph_control;
154 u32 i2c_cntl_1;
155 u32 gen_int_cntl;
156 u32 cap0_trig_cntl;
157 u32 cap1_trig_cntl;
158 u32 bus_cntl;
159 u32 surface_cntl;
160 u32 bios_5_scratch;
161
162 /* Other registers to save for VT switches or driver load/unload */
163 u32 dp_datatype;
164 u32 rbbm_soft_reset;
165 u32 clock_cntl_index;
166 u32 amcgpio_en_reg;
167 u32 amcgpio_mask;
168
169 /* Surface/tiling registers */
170 u32 surf_lower_bound[8];
171 u32 surf_upper_bound[8];
172 u32 surf_info[8];
173
174 /* CRTC registers */
175 u32 crtc_gen_cntl;
176 u32 crtc_ext_cntl;
177 u32 dac_cntl;
178 u32 crtc_h_total_disp;
179 u32 crtc_h_sync_strt_wid;
180 u32 crtc_v_total_disp;
181 u32 crtc_v_sync_strt_wid;
182 u32 crtc_offset;
183 u32 crtc_offset_cntl;
184 u32 crtc_pitch;
185 u32 disp_merge_cntl;
186 u32 grph_buffer_cntl;
187 u32 crtc_more_cntl;
188
189 /* CRTC2 registers */
190 u32 crtc2_gen_cntl;
191 u32 dac2_cntl;
192 u32 disp_output_cntl;
193 u32 disp_hw_debug;
194 u32 disp2_merge_cntl;
195 u32 grph2_buffer_cntl;
196 u32 crtc2_h_total_disp;
197 u32 crtc2_h_sync_strt_wid;
198 u32 crtc2_v_total_disp;
199 u32 crtc2_v_sync_strt_wid;
200 u32 crtc2_offset;
201 u32 crtc2_offset_cntl;
202 u32 crtc2_pitch;
203
204 /* Flat panel regs */
205 u32 fp_crtc_h_total_disp;
206 u32 fp_crtc_v_total_disp;
207 u32 fp_gen_cntl;
208 u32 fp2_gen_cntl;
209 u32 fp_h_sync_strt_wid;
210 u32 fp2_h_sync_strt_wid;
211 u32 fp_horz_stretch;
212 u32 fp_panel_cntl;
213 u32 fp_v_sync_strt_wid;
214 u32 fp2_v_sync_strt_wid;
215 u32 fp_vert_stretch;
216 u32 lvds_gen_cntl;
217 u32 lvds_pll_cntl;
218 u32 tmds_crc;
219 u32 tmds_transmitter_cntl;
220
221 /* Computed values for PLL */
222 u32 dot_clock_freq;
223 int feedback_div;
224 int post_div;
225
226 /* PLL registers */
227 u32 ppll_div_3;
228 u32 ppll_ref_div;
229 u32 vclk_ecp_cntl;
230 u32 clk_cntl_index;
231
232 /* Computed values for PLL2 */
233 u32 dot_clock_freq_2;
234 int feedback_div_2;
235 int post_div_2;
236
237 /* PLL2 registers */
238 u32 p2pll_ref_div;
239 u32 p2pll_div_0;
240 u32 htotal_cntl2;
241
242 /* Palette */
243 int palette_valid;
244 };
245
246 struct panel_info {
247 int xres, yres;
248 int valid;
249 int clock;
250 int hOver_plus, hSync_width, hblank;
251 int vOver_plus, vSync_width, vblank;
252 int hAct_high, vAct_high, interlaced;
253 int pwr_delay;
254 int use_bios_dividers;
255 int ref_divider;
256 int post_divider;
257 int fbk_divider;
258 };
259
260 struct radeonfb_info;
261
262 #ifdef CONFIG_FB_RADEON_I2C
263 struct radeon_i2c_chan {
264 struct radeonfb_info *rinfo;
265 u32 ddc_reg;
266 struct i2c_adapter adapter;
267 struct i2c_algo_bit_data algo;
268 };
269 #endif
270
271 enum radeon_pm_mode {
272 radeon_pm_none = 0, /* Nothing supported */
273 radeon_pm_d2 = 0x00000001, /* Can do D2 state */
274 radeon_pm_off = 0x00000002, /* Can resume from D3 cold */
275 };
276
277 struct radeonfb_info {
278 struct fb_info *info;
279
280 struct radeon_regs state;
281 struct radeon_regs init_state;
282
283 char name[DEVICE_NAME_SIZE];
284
285 unsigned long mmio_base_phys;
286 unsigned long fb_base_phys;
287
288 void __iomem *mmio_base;
289 void __iomem *fb_base;
290
291 unsigned long fb_local_base;
292
293 struct pci_dev *pdev;
294 #ifdef CONFIG_PPC_OF
295 struct device_node *of_node;
296 #endif
297
298 void __iomem *bios_seg;
299 int fp_bios_start;
300
301 u32 pseudo_palette[17];
302 struct { u8 red, green, blue, pad; }
303 palette[256];
304
305 int chipset;
306 u8 family;
307 u8 rev;
308 unsigned int errata;
309 unsigned long video_ram;
310 unsigned long mapped_vram;
311 int vram_width;
312 int vram_ddr;
313
314 int pitch, bpp, depth;
315
316 int has_CRTC2;
317 int is_mobility;
318 int is_IGP;
319 int reversed_DAC;
320 int reversed_TMDS;
321 struct panel_info panel_info;
322 int mon1_type;
323 u8 *mon1_EDID;
324 struct fb_videomode *mon1_modedb;
325 int mon1_dbsize;
326 int mon2_type;
327 u8 *mon2_EDID;
328
329 u32 dp_gui_master_cntl;
330
331 struct pll_info pll;
332
333 int mtrr_hdl;
334
335 int pm_reg;
336 u32 save_regs[100];
337 int asleep;
338 int lock_blank;
339 int dynclk;
340 int no_schedule;
341 enum radeon_pm_mode pm_mode;
342 void (*reinit_func)(struct radeonfb_info *rinfo);
343
344 /* Lock on register access */
345 spinlock_t reg_lock;
346
347 /* Timer used for delayed LVDS operations */
348 struct timer_list lvds_timer;
349 u32 pending_lvds_gen_cntl;
350
351 #ifdef CONFIG_FB_RADEON_I2C
352 struct radeon_i2c_chan i2c[4];
353 #endif
354
355 u32 cfg_save[64];
356 };
357
358
359 #define PRIMARY_MONITOR(rinfo) (rinfo->mon1_type)
360
361
362 /*
363 * Debugging stuffs
364 */
365 #ifdef CONFIG_FB_RADEON_DEBUG
366 #define DEBUG 1
367 #else
368 #define DEBUG 0
369 #endif
370
371 #if DEBUG
372 #define RTRACE printk
373 #else
374 #define RTRACE if(0) printk
375 #endif
376
377
378 /*
379 * IO macros
380 */
381
382 /* Note about this function: we have some rare cases where we must not schedule,
383 * this typically happen with our special "wake up early" hook which allows us to
384 * wake up the graphic chip (and thus get the console back) before everything else
385 * on some machines that support that mecanism. At this point, interrupts are off
386 * and scheduling is not permitted
387 */
388 static inline void _radeon_msleep(struct radeonfb_info *rinfo, unsigned long ms)
389 {
390 if (rinfo->no_schedule || oops_in_progress)
391 mdelay(ms);
392 else
393 msleep(ms);
394 }
395
396
397 #define INREG8(addr) readb((rinfo->mmio_base)+addr)
398 #define OUTREG8(addr,val) writeb(val, (rinfo->mmio_base)+addr)
399 #define INREG16(addr) readw((rinfo->mmio_base)+addr)
400 #define OUTREG16(addr,val) writew(val, (rinfo->mmio_base)+addr)
401 #define INREG(addr) readl((rinfo->mmio_base)+addr)
402 #define OUTREG(addr,val) writel(val, (rinfo->mmio_base)+addr)
403
404 static inline void _OUTREGP(struct radeonfb_info *rinfo, u32 addr,
405 u32 val, u32 mask)
406 {
407 unsigned long flags;
408 unsigned int tmp;
409
410 spin_lock_irqsave(&rinfo->reg_lock, flags);
411 tmp = INREG(addr);
412 tmp &= (mask);
413 tmp |= (val);
414 OUTREG(addr, tmp);
415 spin_unlock_irqrestore(&rinfo->reg_lock, flags);
416 }
417
418 #define OUTREGP(addr,val,mask) _OUTREGP(rinfo, addr, val,mask)
419
420 /*
421 * Note about PLL register accesses:
422 *
423 * I have removed the spinlock on them on purpose. The driver now
424 * expects that it will only manipulate the PLL registers in normal
425 * task environment, where radeon_msleep() will be called, protected
426 * by a semaphore (currently the console semaphore) so that no conflict
427 * will happen on the PLL register index.
428 *
429 * With the latest changes to the VT layer, this is guaranteed for all
430 * calls except the actual drawing/blits which aren't supposed to use
431 * the PLL registers anyway
432 *
433 * This is very important for the workarounds to work properly. The only
434 * possible exception to this rule is the call to unblank(), which may
435 * be done at irq time if an oops is in progress.
436 */
437 static inline void radeon_pll_errata_after_index(struct radeonfb_info *rinfo)
438 {
439 if (!(rinfo->errata & CHIP_ERRATA_PLL_DUMMYREADS))
440 return;
441
442 (void)INREG(CLOCK_CNTL_DATA);
443 (void)INREG(CRTC_GEN_CNTL);
444 }
445
446 static inline void radeon_pll_errata_after_data(struct radeonfb_info *rinfo)
447 {
448 if (rinfo->errata & CHIP_ERRATA_PLL_DELAY) {
449 /* we can't deal with posted writes here ... */
450 _radeon_msleep(rinfo, 5);
451 }
452 if (rinfo->errata & CHIP_ERRATA_R300_CG) {
453 u32 save, tmp;
454 save = INREG(CLOCK_CNTL_INDEX);
455 tmp = save & ~(0x3f | PLL_WR_EN);
456 OUTREG(CLOCK_CNTL_INDEX, tmp);
457 tmp = INREG(CLOCK_CNTL_DATA);
458 OUTREG(CLOCK_CNTL_INDEX, save);
459 }
460 }
461
462 static inline u32 __INPLL(struct radeonfb_info *rinfo, u32 addr)
463 {
464 u32 data;
465
466 OUTREG8(CLOCK_CNTL_INDEX, addr & 0x0000003f);
467 radeon_pll_errata_after_index(rinfo);
468 data = INREG(CLOCK_CNTL_DATA);
469 radeon_pll_errata_after_data(rinfo);
470 return data;
471 }
472
473 static inline void __OUTPLL(struct radeonfb_info *rinfo, unsigned int index,
474 u32 val)
475 {
476
477 OUTREG8(CLOCK_CNTL_INDEX, (index & 0x0000003f) | 0x00000080);
478 radeon_pll_errata_after_index(rinfo);
479 OUTREG(CLOCK_CNTL_DATA, val);
480 radeon_pll_errata_after_data(rinfo);
481 }
482
483
484 static inline void __OUTPLLP(struct radeonfb_info *rinfo, unsigned int index,
485 u32 val, u32 mask)
486 {
487 unsigned int tmp;
488
489 tmp = __INPLL(rinfo, index);
490 tmp &= (mask);
491 tmp |= (val);
492 __OUTPLL(rinfo, index, tmp);
493 }
494
495
496 #define INPLL(addr) __INPLL(rinfo, addr)
497 #define OUTPLL(index, val) __OUTPLL(rinfo, index, val)
498 #define OUTPLLP(index, val, mask) __OUTPLLP(rinfo, index, val, mask)
499
500
501 #define BIOS_IN8(v) (readb(rinfo->bios_seg + (v)))
502 #define BIOS_IN16(v) (readb(rinfo->bios_seg + (v)) | \
503 (readb(rinfo->bios_seg + (v) + 1) << 8))
504 #define BIOS_IN32(v) (readb(rinfo->bios_seg + (v)) | \
505 (readb(rinfo->bios_seg + (v) + 1) << 8) | \
506 (readb(rinfo->bios_seg + (v) + 2) << 16) | \
507 (readb(rinfo->bios_seg + (v) + 3) << 24))
508
509 /*
510 * Inline utilities
511 */
512 static inline int round_div(int num, int den)
513 {
514 return (num + (den / 2)) / den;
515 }
516
517 static inline int var_to_depth(const struct fb_var_screeninfo *var)
518 {
519 if (var->bits_per_pixel != 16)
520 return var->bits_per_pixel;
521 return (var->green.length == 5) ? 15 : 16;
522 }
523
524 static inline u32 radeon_get_dstbpp(u16 depth)
525 {
526 switch (depth) {
527 case 8:
528 return DST_8BPP;
529 case 15:
530 return DST_15BPP;
531 case 16:
532 return DST_16BPP;
533 case 32:
534 return DST_32BPP;
535 default:
536 return 0;
537 }
538 }
539
540 /*
541 * 2D Engine helper routines
542 */
543 static inline void radeon_engine_flush (struct radeonfb_info *rinfo)
544 {
545 int i;
546
547 /* initiate flush */
548 OUTREGP(RB2D_DSTCACHE_CTLSTAT, RB2D_DC_FLUSH_ALL,
549 ~RB2D_DC_FLUSH_ALL);
550
551 for (i=0; i < 2000000; i++) {
552 if (!(INREG(RB2D_DSTCACHE_CTLSTAT) & RB2D_DC_BUSY))
553 return;
554 udelay(1);
555 }
556 printk(KERN_ERR "radeonfb: Flush Timeout !\n");
557 }
558
559
560 static inline void _radeon_fifo_wait(struct radeonfb_info *rinfo, int entries)
561 {
562 int i;
563
564 for (i=0; i<2000000; i++) {
565 if ((INREG(RBBM_STATUS) & 0x7f) >= entries)
566 return;
567 udelay(1);
568 }
569 printk(KERN_ERR "radeonfb: FIFO Timeout !\n");
570 }
571
572
573 static inline void _radeon_engine_idle(struct radeonfb_info *rinfo)
574 {
575 int i;
576
577 /* ensure FIFO is empty before waiting for idle */
578 _radeon_fifo_wait (rinfo, 64);
579
580 for (i=0; i<2000000; i++) {
581 if (((INREG(RBBM_STATUS) & GUI_ACTIVE)) == 0) {
582 radeon_engine_flush (rinfo);
583 return;
584 }
585 udelay(1);
586 }
587 printk(KERN_ERR "radeonfb: Idle Timeout !\n");
588 }
589
590
591 #define radeon_engine_idle() _radeon_engine_idle(rinfo)
592 #define radeon_fifo_wait(entries) _radeon_fifo_wait(rinfo,entries)
593 #define radeon_msleep(ms) _radeon_msleep(rinfo,ms)
594
595
596 /* I2C Functions */
597 extern void radeon_create_i2c_busses(struct radeonfb_info *rinfo);
598 extern void radeon_delete_i2c_busses(struct radeonfb_info *rinfo);
599 extern int radeon_probe_i2c_connector(struct radeonfb_info *rinfo, int conn, u8 **out_edid);
600
601 /* PM Functions */
602 extern int radeonfb_pci_suspend(struct pci_dev *pdev, pm_message_t state);
603 extern int radeonfb_pci_resume(struct pci_dev *pdev);
604 extern void radeonfb_pm_init(struct radeonfb_info *rinfo, int dynclk);
605 extern void radeonfb_pm_exit(struct radeonfb_info *rinfo);
606
607 /* Monitor probe functions */
608 extern void radeon_probe_screens(struct radeonfb_info *rinfo,
609 const char *monitor_layout, int ignore_edid);
610 extern void radeon_check_modes(struct radeonfb_info *rinfo, const char *mode_option);
611 extern int radeon_match_mode(struct radeonfb_info *rinfo,
612 struct fb_var_screeninfo *dest,
613 const struct fb_var_screeninfo *src);
614
615 /* Accel functions */
616 extern void radeonfb_fillrect(struct fb_info *info, const struct fb_fillrect *region);
617 extern void radeonfb_copyarea(struct fb_info *info, const struct fb_copyarea *area);
618 extern void radeonfb_imageblit(struct fb_info *p, const struct fb_image *image);
619 extern int radeonfb_sync(struct fb_info *info);
620 extern void radeonfb_engine_init (struct radeonfb_info *rinfo);
621 extern void radeonfb_engine_reset(struct radeonfb_info *rinfo);
622
623 /* Other functions */
624 extern int radeon_screen_blank(struct radeonfb_info *rinfo, int blank, int mode_switch);
625 extern void radeon_write_mode (struct radeonfb_info *rinfo, struct radeon_regs *mode,
626 int reg_only);
627
628 #endif /* __RADEONFB_H__ */
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