2 * Fast Ethernet Controller (FEC) driver for Motorola MPC8xx.
3 * Copyright (c) 1997 Dan Malek (dmalek@jlc.net)
5 * Right now, I am very wasteful with the buffers. I allocate memory
6 * pages and then divide them into 2K frame buffers. This way I know I
7 * have buffers large enough to hold one frame within one buffer descriptor.
8 * Once I get this working, I will use 64 or 128 byte CPM buffers, which
9 * will be much more memory efficient and will easily handle lots of
12 * Much better multiple PHY support by Magnus Damm.
13 * Copyright (c) 2000 Ericsson Radio Systems AB.
15 * Support for FEC controller of ColdFire processors.
16 * Copyright (c) 2001-2005 Greg Ungerer (gerg@snapgear.com)
18 * Bug fixes and cleanup by Philippe De Muyter (phdm@macqel.be)
19 * Copyright (c) 2004-2006 Macq Electronique SA.
22 #include <linux/module.h>
23 #include <linux/kernel.h>
24 #include <linux/string.h>
25 #include <linux/ptrace.h>
26 #include <linux/errno.h>
27 #include <linux/ioport.h>
28 #include <linux/slab.h>
29 #include <linux/interrupt.h>
30 #include <linux/pci.h>
31 #include <linux/init.h>
32 #include <linux/delay.h>
33 #include <linux/netdevice.h>
34 #include <linux/etherdevice.h>
35 #include <linux/skbuff.h>
36 #include <linux/spinlock.h>
37 #include <linux/workqueue.h>
38 #include <linux/bitops.h>
40 #include <linux/irq.h>
41 #include <linux/clk.h>
42 #include <linux/platform_device.h>
43 #include <linux/phy.h>
44 #include <linux/fec.h>
46 #include <asm/cacheflush.h>
48 #ifndef CONFIG_ARCH_MXC
49 #include <asm/coldfire.h>
50 #include <asm/mcfsim.h>
55 #ifdef CONFIG_ARCH_MXC
56 #include <mach/hardware.h>
57 #define FEC_ALIGNMENT 0xf
59 #define FEC_ALIGNMENT 0x3
63 * Define the fixed address of the FEC hardware.
65 #if defined(CONFIG_M5272)
67 static unsigned char fec_mac_default
[] = {
68 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
72 * Some hardware gets it MAC address out of local flash memory.
73 * if this is non-zero then assume it is the address to get MAC from.
75 #if defined(CONFIG_NETtel)
76 #define FEC_FLASHMAC 0xf0006006
77 #elif defined(CONFIG_GILBARCONAP) || defined(CONFIG_SCALES)
78 #define FEC_FLASHMAC 0xf0006000
79 #elif defined(CONFIG_CANCam)
80 #define FEC_FLASHMAC 0xf0020000
81 #elif defined (CONFIG_M5272C3)
82 #define FEC_FLASHMAC (0xffe04000 + 4)
83 #elif defined(CONFIG_MOD5272)
84 #define FEC_FLASHMAC 0xffc0406b
86 #define FEC_FLASHMAC 0
88 #endif /* CONFIG_M5272 */
90 /* The number of Tx and Rx buffers. These are allocated from the page
91 * pool. The code may assume these are power of two, so it it best
92 * to keep them that size.
93 * We don't need to allocate pages for the transmitter. We just use
94 * the skbuffer directly.
96 #define FEC_ENET_RX_PAGES 8
97 #define FEC_ENET_RX_FRSIZE 2048
98 #define FEC_ENET_RX_FRPPG (PAGE_SIZE / FEC_ENET_RX_FRSIZE)
99 #define RX_RING_SIZE (FEC_ENET_RX_FRPPG * FEC_ENET_RX_PAGES)
100 #define FEC_ENET_TX_FRSIZE 2048
101 #define FEC_ENET_TX_FRPPG (PAGE_SIZE / FEC_ENET_TX_FRSIZE)
102 #define TX_RING_SIZE 16 /* Must be power of two */
103 #define TX_RING_MOD_MASK 15 /* for this to work */
105 #if (((RX_RING_SIZE + TX_RING_SIZE) * 8) > PAGE_SIZE)
106 #error "FEC: descriptor ring size constants too large"
109 /* Interrupt events/masks. */
110 #define FEC_ENET_HBERR ((uint)0x80000000) /* Heartbeat error */
111 #define FEC_ENET_BABR ((uint)0x40000000) /* Babbling receiver */
112 #define FEC_ENET_BABT ((uint)0x20000000) /* Babbling transmitter */
113 #define FEC_ENET_GRA ((uint)0x10000000) /* Graceful stop complete */
114 #define FEC_ENET_TXF ((uint)0x08000000) /* Full frame transmitted */
115 #define FEC_ENET_TXB ((uint)0x04000000) /* A buffer was transmitted */
116 #define FEC_ENET_RXF ((uint)0x02000000) /* Full frame received */
117 #define FEC_ENET_RXB ((uint)0x01000000) /* A buffer was received */
118 #define FEC_ENET_MII ((uint)0x00800000) /* MII interrupt */
119 #define FEC_ENET_EBERR ((uint)0x00400000) /* SDMA bus error */
121 /* The FEC stores dest/src/type, data, and checksum for receive packets.
123 #define PKT_MAXBUF_SIZE 1518
124 #define PKT_MINBUF_SIZE 64
125 #define PKT_MAXBLR_SIZE 1520
129 * The 5270/5271/5280/5282/532x RX control register also contains maximum frame
130 * size bits. Other FEC hardware does not, so we need to take that into
131 * account when setting it.
133 #if defined(CONFIG_M523x) || defined(CONFIG_M527x) || defined(CONFIG_M528x) || \
134 defined(CONFIG_M520x) || defined(CONFIG_M532x) || defined(CONFIG_ARCH_MXC)
135 #define OPT_FRAME_SIZE (PKT_MAXBUF_SIZE << 16)
137 #define OPT_FRAME_SIZE 0
140 /* The FEC buffer descriptors track the ring buffers. The rx_bd_base and
141 * tx_bd_base always point to the base of the buffer descriptors. The
142 * cur_rx and cur_tx point to the currently available buffer.
143 * The dirty_tx tracks the current buffer that is being sent by the
144 * controller. The cur_tx and dirty_tx are equal under both completely
145 * empty and completely full conditions. The empty/ready indicator in
146 * the buffer descriptor determines the actual condition.
148 struct fec_enet_private
{
149 /* Hardware registers of the FEC device */
152 struct net_device
*netdev
;
156 /* The saved address of a sent-in-place packet/buffer, for skfree(). */
157 unsigned char *tx_bounce
[TX_RING_SIZE
];
158 struct sk_buff
* tx_skbuff
[TX_RING_SIZE
];
159 struct sk_buff
* rx_skbuff
[RX_RING_SIZE
];
163 /* CPM dual port RAM relative addresses */
165 /* Address of Rx and Tx buffers */
166 struct bufdesc
*rx_bd_base
;
167 struct bufdesc
*tx_bd_base
;
168 /* The next free ring entry */
169 struct bufdesc
*cur_rx
, *cur_tx
;
170 /* The ring entries to be free()ed */
171 struct bufdesc
*dirty_tx
;
174 /* hold while accessing the HW like ringbuffer for tx/rx but not MAC */
177 struct platform_device
*pdev
;
181 /* Phylib and MDIO interface */
182 struct mii_bus
*mii_bus
;
183 struct phy_device
*phy_dev
;
186 phy_interface_t phy_interface
;
190 struct completion mdio_done
;
193 static irqreturn_t
fec_enet_interrupt(int irq
, void * dev_id
);
194 static void fec_enet_tx(struct net_device
*dev
);
195 static void fec_enet_rx(struct net_device
*dev
);
196 static int fec_enet_close(struct net_device
*dev
);
197 static void fec_restart(struct net_device
*dev
, int duplex
);
198 static void fec_stop(struct net_device
*dev
);
200 /* FEC MII MMFR bits definition */
201 #define FEC_MMFR_ST (1 << 30)
202 #define FEC_MMFR_OP_READ (2 << 28)
203 #define FEC_MMFR_OP_WRITE (1 << 28)
204 #define FEC_MMFR_PA(v) ((v & 0x1f) << 23)
205 #define FEC_MMFR_RA(v) ((v & 0x1f) << 18)
206 #define FEC_MMFR_TA (2 << 16)
207 #define FEC_MMFR_DATA(v) (v & 0xffff)
209 #define FEC_MII_TIMEOUT 1000 /* us */
211 /* Transmitter timeout */
212 #define TX_TIMEOUT (2 * HZ)
215 fec_enet_start_xmit(struct sk_buff
*skb
, struct net_device
*dev
)
217 struct fec_enet_private
*fep
= netdev_priv(dev
);
220 unsigned short status
;
224 /* Link is down or autonegotiation is in progress. */
225 return NETDEV_TX_BUSY
;
228 spin_lock_irqsave(&fep
->hw_lock
, flags
);
229 /* Fill in a Tx ring entry */
232 status
= bdp
->cbd_sc
;
234 if (status
& BD_ENET_TX_READY
) {
235 /* Ooops. All transmit buffers are full. Bail out.
236 * This should not happen, since dev->tbusy should be set.
238 printk("%s: tx queue full!.\n", dev
->name
);
239 spin_unlock_irqrestore(&fep
->hw_lock
, flags
);
240 return NETDEV_TX_BUSY
;
243 /* Clear all of the status flags */
244 status
&= ~BD_ENET_TX_STATS
;
246 /* Set buffer length and buffer pointer */
248 bdp
->cbd_datlen
= skb
->len
;
251 * On some FEC implementations data must be aligned on
252 * 4-byte boundaries. Use bounce buffers to copy data
253 * and get it aligned. Ugh.
255 if (((unsigned long) bufaddr
) & FEC_ALIGNMENT
) {
257 index
= bdp
- fep
->tx_bd_base
;
258 memcpy(fep
->tx_bounce
[index
], (void *)skb
->data
, skb
->len
);
259 bufaddr
= fep
->tx_bounce
[index
];
262 /* Save skb pointer */
263 fep
->tx_skbuff
[fep
->skb_cur
] = skb
;
265 dev
->stats
.tx_bytes
+= skb
->len
;
266 fep
->skb_cur
= (fep
->skb_cur
+1) & TX_RING_MOD_MASK
;
268 /* Push the data cache so the CPM does not get stale memory
271 bdp
->cbd_bufaddr
= dma_map_single(&dev
->dev
, bufaddr
,
272 FEC_ENET_TX_FRSIZE
, DMA_TO_DEVICE
);
274 /* Send it on its way. Tell FEC it's ready, interrupt when done,
275 * it's the last BD of the frame, and to put the CRC on the end.
277 status
|= (BD_ENET_TX_READY
| BD_ENET_TX_INTR
278 | BD_ENET_TX_LAST
| BD_ENET_TX_TC
);
279 bdp
->cbd_sc
= status
;
281 /* Trigger transmission start */
282 writel(0, fep
->hwp
+ FEC_X_DES_ACTIVE
);
284 /* If this was the last BD in the ring, start at the beginning again. */
285 if (status
& BD_ENET_TX_WRAP
)
286 bdp
= fep
->tx_bd_base
;
290 if (bdp
== fep
->dirty_tx
) {
292 netif_stop_queue(dev
);
297 spin_unlock_irqrestore(&fep
->hw_lock
, flags
);
303 fec_timeout(struct net_device
*dev
)
305 struct fec_enet_private
*fep
= netdev_priv(dev
);
307 dev
->stats
.tx_errors
++;
309 fec_restart(dev
, fep
->full_duplex
);
310 netif_wake_queue(dev
);
314 fec_enet_interrupt(int irq
, void * dev_id
)
316 struct net_device
*dev
= dev_id
;
317 struct fec_enet_private
*fep
= netdev_priv(dev
);
319 irqreturn_t ret
= IRQ_NONE
;
322 int_events
= readl(fep
->hwp
+ FEC_IEVENT
);
323 writel(int_events
, fep
->hwp
+ FEC_IEVENT
);
325 if (int_events
& FEC_ENET_RXF
) {
330 /* Transmit OK, or non-fatal error. Update the buffer
331 * descriptors. FEC handles all errors, we just discover
332 * them as part of the transmit process.
334 if (int_events
& FEC_ENET_TXF
) {
339 if (int_events
& FEC_ENET_MII
) {
341 complete(&fep
->mdio_done
);
343 } while (int_events
);
350 fec_enet_tx(struct net_device
*dev
)
352 struct fec_enet_private
*fep
;
354 unsigned short status
;
357 fep
= netdev_priv(dev
);
358 spin_lock(&fep
->hw_lock
);
361 while (((status
= bdp
->cbd_sc
) & BD_ENET_TX_READY
) == 0) {
362 if (bdp
== fep
->cur_tx
&& fep
->tx_full
== 0)
365 dma_unmap_single(&dev
->dev
, bdp
->cbd_bufaddr
, FEC_ENET_TX_FRSIZE
, DMA_TO_DEVICE
);
366 bdp
->cbd_bufaddr
= 0;
368 skb
= fep
->tx_skbuff
[fep
->skb_dirty
];
369 /* Check for errors. */
370 if (status
& (BD_ENET_TX_HB
| BD_ENET_TX_LC
|
371 BD_ENET_TX_RL
| BD_ENET_TX_UN
|
373 dev
->stats
.tx_errors
++;
374 if (status
& BD_ENET_TX_HB
) /* No heartbeat */
375 dev
->stats
.tx_heartbeat_errors
++;
376 if (status
& BD_ENET_TX_LC
) /* Late collision */
377 dev
->stats
.tx_window_errors
++;
378 if (status
& BD_ENET_TX_RL
) /* Retrans limit */
379 dev
->stats
.tx_aborted_errors
++;
380 if (status
& BD_ENET_TX_UN
) /* Underrun */
381 dev
->stats
.tx_fifo_errors
++;
382 if (status
& BD_ENET_TX_CSL
) /* Carrier lost */
383 dev
->stats
.tx_carrier_errors
++;
385 dev
->stats
.tx_packets
++;
388 if (status
& BD_ENET_TX_READY
)
389 printk("HEY! Enet xmit interrupt and TX_READY.\n");
391 /* Deferred means some collisions occurred during transmit,
392 * but we eventually sent the packet OK.
394 if (status
& BD_ENET_TX_DEF
)
395 dev
->stats
.collisions
++;
397 /* Free the sk buffer associated with this last transmit */
398 dev_kfree_skb_any(skb
);
399 fep
->tx_skbuff
[fep
->skb_dirty
] = NULL
;
400 fep
->skb_dirty
= (fep
->skb_dirty
+ 1) & TX_RING_MOD_MASK
;
402 /* Update pointer to next buffer descriptor to be transmitted */
403 if (status
& BD_ENET_TX_WRAP
)
404 bdp
= fep
->tx_bd_base
;
408 /* Since we have freed up a buffer, the ring is no longer full
412 if (netif_queue_stopped(dev
))
413 netif_wake_queue(dev
);
417 spin_unlock(&fep
->hw_lock
);
421 /* During a receive, the cur_rx points to the current incoming buffer.
422 * When we update through the ring, if the next incoming buffer has
423 * not been given to the system, we just set the empty indicator,
424 * effectively tossing the packet.
427 fec_enet_rx(struct net_device
*dev
)
429 struct fec_enet_private
*fep
= netdev_priv(dev
);
431 unsigned short status
;
440 spin_lock(&fep
->hw_lock
);
442 /* First, grab all of the stats for the incoming packet.
443 * These get messed up if we get called due to a busy condition.
447 while (!((status
= bdp
->cbd_sc
) & BD_ENET_RX_EMPTY
)) {
449 /* Since we have allocated space to hold a complete frame,
450 * the last indicator should be set.
452 if ((status
& BD_ENET_RX_LAST
) == 0)
453 printk("FEC ENET: rcv is not +last\n");
456 goto rx_processing_done
;
458 /* Check for errors. */
459 if (status
& (BD_ENET_RX_LG
| BD_ENET_RX_SH
| BD_ENET_RX_NO
|
460 BD_ENET_RX_CR
| BD_ENET_RX_OV
)) {
461 dev
->stats
.rx_errors
++;
462 if (status
& (BD_ENET_RX_LG
| BD_ENET_RX_SH
)) {
463 /* Frame too long or too short. */
464 dev
->stats
.rx_length_errors
++;
466 if (status
& BD_ENET_RX_NO
) /* Frame alignment */
467 dev
->stats
.rx_frame_errors
++;
468 if (status
& BD_ENET_RX_CR
) /* CRC Error */
469 dev
->stats
.rx_crc_errors
++;
470 if (status
& BD_ENET_RX_OV
) /* FIFO overrun */
471 dev
->stats
.rx_fifo_errors
++;
474 /* Report late collisions as a frame error.
475 * On this error, the BD is closed, but we don't know what we
476 * have in the buffer. So, just drop this frame on the floor.
478 if (status
& BD_ENET_RX_CL
) {
479 dev
->stats
.rx_errors
++;
480 dev
->stats
.rx_frame_errors
++;
481 goto rx_processing_done
;
484 /* Process the incoming frame. */
485 dev
->stats
.rx_packets
++;
486 pkt_len
= bdp
->cbd_datlen
;
487 dev
->stats
.rx_bytes
+= pkt_len
;
488 data
= (__u8
*)__va(bdp
->cbd_bufaddr
);
490 dma_unmap_single(NULL
, bdp
->cbd_bufaddr
, bdp
->cbd_datlen
,
493 /* This does 16 byte alignment, exactly what we need.
494 * The packet length includes FCS, but we don't want to
495 * include that when passing upstream as it messes up
496 * bridging applications.
498 skb
= dev_alloc_skb(pkt_len
- 4 + NET_IP_ALIGN
);
500 if (unlikely(!skb
)) {
501 printk("%s: Memory squeeze, dropping packet.\n",
503 dev
->stats
.rx_dropped
++;
505 skb_reserve(skb
, NET_IP_ALIGN
);
506 skb_put(skb
, pkt_len
- 4); /* Make room */
507 skb_copy_to_linear_data(skb
, data
, pkt_len
- 4);
508 skb
->protocol
= eth_type_trans(skb
, dev
);
512 bdp
->cbd_bufaddr
= dma_map_single(NULL
, data
, bdp
->cbd_datlen
,
515 /* Clear the status flags for this buffer */
516 status
&= ~BD_ENET_RX_STATS
;
518 /* Mark the buffer empty */
519 status
|= BD_ENET_RX_EMPTY
;
520 bdp
->cbd_sc
= status
;
522 /* Update BD pointer to next entry */
523 if (status
& BD_ENET_RX_WRAP
)
524 bdp
= fep
->rx_bd_base
;
527 /* Doing this here will keep the FEC running while we process
528 * incoming frames. On a heavily loaded network, we should be
529 * able to keep up at the expense of system resources.
531 writel(0, fep
->hwp
+ FEC_R_DES_ACTIVE
);
535 spin_unlock(&fep
->hw_lock
);
538 /* ------------------------------------------------------------------------- */
540 static void __inline__
fec_get_mac(struct net_device
*dev
)
542 struct fec_enet_private
*fep
= netdev_priv(dev
);
543 unsigned char *iap
, tmpaddr
[ETH_ALEN
];
547 * Get MAC address from FLASH.
548 * If it is all 1's or 0's, use the default.
550 iap
= (unsigned char *)FEC_FLASHMAC
;
551 if ((iap
[0] == 0) && (iap
[1] == 0) && (iap
[2] == 0) &&
552 (iap
[3] == 0) && (iap
[4] == 0) && (iap
[5] == 0))
553 iap
= fec_mac_default
;
554 if ((iap
[0] == 0xff) && (iap
[1] == 0xff) && (iap
[2] == 0xff) &&
555 (iap
[3] == 0xff) && (iap
[4] == 0xff) && (iap
[5] == 0xff))
556 iap
= fec_mac_default
;
558 *((unsigned long *) &tmpaddr
[0]) = readl(fep
->hwp
+ FEC_ADDR_LOW
);
559 *((unsigned short *) &tmpaddr
[4]) = (readl(fep
->hwp
+ FEC_ADDR_HIGH
) >> 16);
563 memcpy(dev
->dev_addr
, iap
, ETH_ALEN
);
565 /* Adjust MAC if using default MAC address */
566 if (iap
== fec_mac_default
)
567 dev
->dev_addr
[ETH_ALEN
-1] = fec_mac_default
[ETH_ALEN
-1] + fep
->index
;
571 /* ------------------------------------------------------------------------- */
576 static void fec_enet_adjust_link(struct net_device
*dev
)
578 struct fec_enet_private
*fep
= netdev_priv(dev
);
579 struct phy_device
*phy_dev
= fep
->phy_dev
;
582 int status_change
= 0;
584 spin_lock_irqsave(&fep
->hw_lock
, flags
);
586 /* Prevent a state halted on mii error */
587 if (fep
->mii_timeout
&& phy_dev
->state
== PHY_HALTED
) {
588 phy_dev
->state
= PHY_RESUMING
;
592 /* Duplex link change */
594 if (fep
->full_duplex
!= phy_dev
->duplex
) {
595 fec_restart(dev
, phy_dev
->duplex
);
600 /* Link on or off change */
601 if (phy_dev
->link
!= fep
->link
) {
602 fep
->link
= phy_dev
->link
;
604 fec_restart(dev
, phy_dev
->duplex
);
611 spin_unlock_irqrestore(&fep
->hw_lock
, flags
);
614 phy_print_status(phy_dev
);
617 static int fec_enet_mdio_read(struct mii_bus
*bus
, int mii_id
, int regnum
)
619 struct fec_enet_private
*fep
= bus
->priv
;
620 unsigned long time_left
;
622 fep
->mii_timeout
= 0;
623 init_completion(&fep
->mdio_done
);
625 /* start a read op */
626 writel(FEC_MMFR_ST
| FEC_MMFR_OP_READ
|
627 FEC_MMFR_PA(mii_id
) | FEC_MMFR_RA(regnum
) |
628 FEC_MMFR_TA
, fep
->hwp
+ FEC_MII_DATA
);
630 /* wait for end of transfer */
631 time_left
= wait_for_completion_timeout(&fep
->mdio_done
,
632 usecs_to_jiffies(FEC_MII_TIMEOUT
));
633 if (time_left
== 0) {
634 fep
->mii_timeout
= 1;
635 printk(KERN_ERR
"FEC: MDIO read timeout\n");
640 return FEC_MMFR_DATA(readl(fep
->hwp
+ FEC_MII_DATA
));
643 static int fec_enet_mdio_write(struct mii_bus
*bus
, int mii_id
, int regnum
,
646 struct fec_enet_private
*fep
= bus
->priv
;
647 unsigned long time_left
;
649 fep
->mii_timeout
= 0;
650 init_completion(&fep
->mdio_done
);
652 /* start a read op */
653 writel(FEC_MMFR_ST
| FEC_MMFR_OP_READ
|
654 FEC_MMFR_PA(mii_id
) | FEC_MMFR_RA(regnum
) |
655 FEC_MMFR_TA
| FEC_MMFR_DATA(value
),
656 fep
->hwp
+ FEC_MII_DATA
);
658 /* wait for end of transfer */
659 time_left
= wait_for_completion_timeout(&fep
->mdio_done
,
660 usecs_to_jiffies(FEC_MII_TIMEOUT
));
661 if (time_left
== 0) {
662 fep
->mii_timeout
= 1;
663 printk(KERN_ERR
"FEC: MDIO write timeout\n");
670 static int fec_enet_mdio_reset(struct mii_bus
*bus
)
675 static int fec_enet_mii_probe(struct net_device
*dev
)
677 struct fec_enet_private
*fep
= netdev_priv(dev
);
678 struct phy_device
*phy_dev
= NULL
;
683 /* find the first phy */
684 phy_dev
= phy_find_first(fep
->mii_bus
);
686 printk(KERN_ERR
"%s: no PHY found\n", dev
->name
);
690 /* attach the mac to the phy */
691 ret
= phy_connect_direct(dev
, phy_dev
,
692 &fec_enet_adjust_link
, 0,
693 PHY_INTERFACE_MODE_MII
);
695 printk(KERN_ERR
"%s: Could not attach to PHY\n", dev
->name
);
699 /* mask with MAC supported features */
700 phy_dev
->supported
&= PHY_BASIC_FEATURES
;
701 phy_dev
->advertising
= phy_dev
->supported
;
703 fep
->phy_dev
= phy_dev
;
705 fep
->full_duplex
= 0;
707 printk(KERN_INFO
"%s: Freescale FEC PHY driver [%s] "
708 "(mii_bus:phy_addr=%s, irq=%d)\n", dev
->name
,
709 fep
->phy_dev
->drv
->name
, dev_name(&fep
->phy_dev
->dev
),
715 static int fec_enet_mii_init(struct platform_device
*pdev
)
717 struct net_device
*dev
= platform_get_drvdata(pdev
);
718 struct fec_enet_private
*fep
= netdev_priv(dev
);
721 fep
->mii_timeout
= 0;
724 * Set MII speed to 2.5 MHz (= clk_get_rate() / 2 * phy_speed)
726 fep
->phy_speed
= DIV_ROUND_UP(clk_get_rate(fep
->clk
), 5000000) << 1;
727 writel(fep
->phy_speed
, fep
->hwp
+ FEC_MII_SPEED
);
729 fep
->mii_bus
= mdiobus_alloc();
730 if (fep
->mii_bus
== NULL
) {
735 fep
->mii_bus
->name
= "fec_enet_mii_bus";
736 fep
->mii_bus
->read
= fec_enet_mdio_read
;
737 fep
->mii_bus
->write
= fec_enet_mdio_write
;
738 fep
->mii_bus
->reset
= fec_enet_mdio_reset
;
739 snprintf(fep
->mii_bus
->id
, MII_BUS_ID_SIZE
, "%x", pdev
->id
);
740 fep
->mii_bus
->priv
= fep
;
741 fep
->mii_bus
->parent
= &pdev
->dev
;
743 fep
->mii_bus
->irq
= kmalloc(sizeof(int) * PHY_MAX_ADDR
, GFP_KERNEL
);
744 if (!fep
->mii_bus
->irq
) {
746 goto err_out_free_mdiobus
;
749 for (i
= 0; i
< PHY_MAX_ADDR
; i
++)
750 fep
->mii_bus
->irq
[i
] = PHY_POLL
;
752 platform_set_drvdata(dev
, fep
->mii_bus
);
754 if (mdiobus_register(fep
->mii_bus
))
755 goto err_out_free_mdio_irq
;
759 err_out_free_mdio_irq
:
760 kfree(fep
->mii_bus
->irq
);
761 err_out_free_mdiobus
:
762 mdiobus_free(fep
->mii_bus
);
767 static void fec_enet_mii_remove(struct fec_enet_private
*fep
)
770 phy_disconnect(fep
->phy_dev
);
771 mdiobus_unregister(fep
->mii_bus
);
772 kfree(fep
->mii_bus
->irq
);
773 mdiobus_free(fep
->mii_bus
);
776 static int fec_enet_get_settings(struct net_device
*dev
,
777 struct ethtool_cmd
*cmd
)
779 struct fec_enet_private
*fep
= netdev_priv(dev
);
780 struct phy_device
*phydev
= fep
->phy_dev
;
785 return phy_ethtool_gset(phydev
, cmd
);
788 static int fec_enet_set_settings(struct net_device
*dev
,
789 struct ethtool_cmd
*cmd
)
791 struct fec_enet_private
*fep
= netdev_priv(dev
);
792 struct phy_device
*phydev
= fep
->phy_dev
;
797 return phy_ethtool_sset(phydev
, cmd
);
800 static void fec_enet_get_drvinfo(struct net_device
*dev
,
801 struct ethtool_drvinfo
*info
)
803 struct fec_enet_private
*fep
= netdev_priv(dev
);
805 strcpy(info
->driver
, fep
->pdev
->dev
.driver
->name
);
806 strcpy(info
->version
, "Revision: 1.0");
807 strcpy(info
->bus_info
, dev_name(&dev
->dev
));
810 static struct ethtool_ops fec_enet_ethtool_ops
= {
811 .get_settings
= fec_enet_get_settings
,
812 .set_settings
= fec_enet_set_settings
,
813 .get_drvinfo
= fec_enet_get_drvinfo
,
814 .get_link
= ethtool_op_get_link
,
817 static int fec_enet_ioctl(struct net_device
*dev
, struct ifreq
*rq
, int cmd
)
819 struct fec_enet_private
*fep
= netdev_priv(dev
);
820 struct phy_device
*phydev
= fep
->phy_dev
;
822 if (!netif_running(dev
))
828 return phy_mii_ioctl(phydev
, if_mii(rq
), cmd
);
831 static void fec_enet_free_buffers(struct net_device
*dev
)
833 struct fec_enet_private
*fep
= netdev_priv(dev
);
838 bdp
= fep
->rx_bd_base
;
839 for (i
= 0; i
< RX_RING_SIZE
; i
++) {
840 skb
= fep
->rx_skbuff
[i
];
842 if (bdp
->cbd_bufaddr
)
843 dma_unmap_single(&dev
->dev
, bdp
->cbd_bufaddr
,
844 FEC_ENET_RX_FRSIZE
, DMA_FROM_DEVICE
);
850 bdp
= fep
->tx_bd_base
;
851 for (i
= 0; i
< TX_RING_SIZE
; i
++)
852 kfree(fep
->tx_bounce
[i
]);
855 static int fec_enet_alloc_buffers(struct net_device
*dev
)
857 struct fec_enet_private
*fep
= netdev_priv(dev
);
862 bdp
= fep
->rx_bd_base
;
863 for (i
= 0; i
< RX_RING_SIZE
; i
++) {
864 skb
= dev_alloc_skb(FEC_ENET_RX_FRSIZE
);
866 fec_enet_free_buffers(dev
);
869 fep
->rx_skbuff
[i
] = skb
;
871 bdp
->cbd_bufaddr
= dma_map_single(&dev
->dev
, skb
->data
,
872 FEC_ENET_RX_FRSIZE
, DMA_FROM_DEVICE
);
873 bdp
->cbd_sc
= BD_ENET_RX_EMPTY
;
877 /* Set the last buffer to wrap. */
879 bdp
->cbd_sc
|= BD_SC_WRAP
;
881 bdp
= fep
->tx_bd_base
;
882 for (i
= 0; i
< TX_RING_SIZE
; i
++) {
883 fep
->tx_bounce
[i
] = kmalloc(FEC_ENET_TX_FRSIZE
, GFP_KERNEL
);
886 bdp
->cbd_bufaddr
= 0;
890 /* Set the last buffer to wrap. */
892 bdp
->cbd_sc
|= BD_SC_WRAP
;
898 fec_enet_open(struct net_device
*dev
)
900 struct fec_enet_private
*fep
= netdev_priv(dev
);
903 /* I should reset the ring buffers here, but I don't yet know
904 * a simple way to do that.
907 ret
= fec_enet_alloc_buffers(dev
);
911 /* Probe and connect to PHY when open the interface */
912 ret
= fec_enet_mii_probe(dev
);
914 fec_enet_free_buffers(dev
);
917 phy_start(fep
->phy_dev
);
918 netif_start_queue(dev
);
924 fec_enet_close(struct net_device
*dev
)
926 struct fec_enet_private
*fep
= netdev_priv(dev
);
928 /* Don't know what to do yet. */
930 netif_stop_queue(dev
);
934 phy_disconnect(fep
->phy_dev
);
936 fec_enet_free_buffers(dev
);
941 /* Set or clear the multicast filter for this adaptor.
942 * Skeleton taken from sunlance driver.
943 * The CPM Ethernet implementation allows Multicast as well as individual
944 * MAC address filtering. Some of the drivers check to make sure it is
945 * a group multicast address, and discard those that are not. I guess I
946 * will do the same for now, but just remove the test if you want
947 * individual filtering as well (do the upper net layers want or support
948 * this kind of feature?).
951 #define HASH_BITS 6 /* #bits in hash */
952 #define CRC32_POLY 0xEDB88320
954 static void set_multicast_list(struct net_device
*dev
)
956 struct fec_enet_private
*fep
= netdev_priv(dev
);
957 struct netdev_hw_addr
*ha
;
958 unsigned int i
, bit
, data
, crc
, tmp
;
961 if (dev
->flags
& IFF_PROMISC
) {
962 tmp
= readl(fep
->hwp
+ FEC_R_CNTRL
);
964 writel(tmp
, fep
->hwp
+ FEC_R_CNTRL
);
968 tmp
= readl(fep
->hwp
+ FEC_R_CNTRL
);
970 writel(tmp
, fep
->hwp
+ FEC_R_CNTRL
);
972 if (dev
->flags
& IFF_ALLMULTI
) {
973 /* Catch all multicast addresses, so set the
976 writel(0xffffffff, fep
->hwp
+ FEC_GRP_HASH_TABLE_HIGH
);
977 writel(0xffffffff, fep
->hwp
+ FEC_GRP_HASH_TABLE_LOW
);
982 /* Clear filter and add the addresses in hash register
984 writel(0, fep
->hwp
+ FEC_GRP_HASH_TABLE_HIGH
);
985 writel(0, fep
->hwp
+ FEC_GRP_HASH_TABLE_LOW
);
987 netdev_for_each_mc_addr(ha
, dev
) {
988 /* Only support group multicast for now */
989 if (!(ha
->addr
[0] & 1))
992 /* calculate crc32 value of mac address */
995 for (i
= 0; i
< dev
->addr_len
; i
++) {
997 for (bit
= 0; bit
< 8; bit
++, data
>>= 1) {
999 (((crc
^ data
) & 1) ? CRC32_POLY
: 0);
1003 /* only upper 6 bits (HASH_BITS) are used
1004 * which point to specific bit in he hash registers
1006 hash
= (crc
>> (32 - HASH_BITS
)) & 0x3f;
1009 tmp
= readl(fep
->hwp
+ FEC_GRP_HASH_TABLE_HIGH
);
1010 tmp
|= 1 << (hash
- 32);
1011 writel(tmp
, fep
->hwp
+ FEC_GRP_HASH_TABLE_HIGH
);
1013 tmp
= readl(fep
->hwp
+ FEC_GRP_HASH_TABLE_LOW
);
1015 writel(tmp
, fep
->hwp
+ FEC_GRP_HASH_TABLE_LOW
);
1020 /* Set a MAC change in hardware. */
1022 fec_set_mac_address(struct net_device
*dev
, void *p
)
1024 struct fec_enet_private
*fep
= netdev_priv(dev
);
1025 struct sockaddr
*addr
= p
;
1027 if (!is_valid_ether_addr(addr
->sa_data
))
1028 return -EADDRNOTAVAIL
;
1030 memcpy(dev
->dev_addr
, addr
->sa_data
, dev
->addr_len
);
1032 writel(dev
->dev_addr
[3] | (dev
->dev_addr
[2] << 8) |
1033 (dev
->dev_addr
[1] << 16) | (dev
->dev_addr
[0] << 24),
1034 fep
->hwp
+ FEC_ADDR_LOW
);
1035 writel((dev
->dev_addr
[5] << 16) | (dev
->dev_addr
[4] << 24),
1036 fep
->hwp
+ FEC_ADDR_HIGH
);
1040 static const struct net_device_ops fec_netdev_ops
= {
1041 .ndo_open
= fec_enet_open
,
1042 .ndo_stop
= fec_enet_close
,
1043 .ndo_start_xmit
= fec_enet_start_xmit
,
1044 .ndo_set_multicast_list
= set_multicast_list
,
1045 .ndo_change_mtu
= eth_change_mtu
,
1046 .ndo_validate_addr
= eth_validate_addr
,
1047 .ndo_tx_timeout
= fec_timeout
,
1048 .ndo_set_mac_address
= fec_set_mac_address
,
1049 .ndo_do_ioctl
= fec_enet_ioctl
,
1053 * XXX: We need to clean up on failure exits here.
1055 * index is only used in legacy code
1057 static int fec_enet_init(struct net_device
*dev
, int index
)
1059 struct fec_enet_private
*fep
= netdev_priv(dev
);
1060 struct bufdesc
*cbd_base
;
1061 struct bufdesc
*bdp
;
1064 /* Allocate memory for buffer descriptors. */
1065 cbd_base
= dma_alloc_coherent(NULL
, PAGE_SIZE
, &fep
->bd_dma
,
1068 printk("FEC: allocate descriptor memory failed?\n");
1072 spin_lock_init(&fep
->hw_lock
);
1075 fep
->hwp
= (void __iomem
*)dev
->base_addr
;
1078 /* Set the Ethernet address */
1084 l
= readl(fep
->hwp
+ FEC_ADDR_LOW
);
1085 dev
->dev_addr
[0] = (unsigned char)((l
& 0xFF000000) >> 24);
1086 dev
->dev_addr
[1] = (unsigned char)((l
& 0x00FF0000) >> 16);
1087 dev
->dev_addr
[2] = (unsigned char)((l
& 0x0000FF00) >> 8);
1088 dev
->dev_addr
[3] = (unsigned char)((l
& 0x000000FF) >> 0);
1089 l
= readl(fep
->hwp
+ FEC_ADDR_HIGH
);
1090 dev
->dev_addr
[4] = (unsigned char)((l
& 0xFF000000) >> 24);
1091 dev
->dev_addr
[5] = (unsigned char)((l
& 0x00FF0000) >> 16);
1095 /* Set receive and transmit descriptor base. */
1096 fep
->rx_bd_base
= cbd_base
;
1097 fep
->tx_bd_base
= cbd_base
+ RX_RING_SIZE
;
1099 /* The FEC Ethernet specific entries in the device structure */
1100 dev
->watchdog_timeo
= TX_TIMEOUT
;
1101 dev
->netdev_ops
= &fec_netdev_ops
;
1102 dev
->ethtool_ops
= &fec_enet_ethtool_ops
;
1104 /* Initialize the receive buffer descriptors. */
1105 bdp
= fep
->rx_bd_base
;
1106 for (i
= 0; i
< RX_RING_SIZE
; i
++) {
1108 /* Initialize the BD for every fragment in the page. */
1113 /* Set the last buffer to wrap */
1115 bdp
->cbd_sc
|= BD_SC_WRAP
;
1117 /* ...and the same for transmit */
1118 bdp
= fep
->tx_bd_base
;
1119 for (i
= 0; i
< TX_RING_SIZE
; i
++) {
1121 /* Initialize the BD for every fragment in the page. */
1123 bdp
->cbd_bufaddr
= 0;
1127 /* Set the last buffer to wrap */
1129 bdp
->cbd_sc
|= BD_SC_WRAP
;
1131 fec_restart(dev
, 0);
1136 /* This function is called to start or restart the FEC during a link
1137 * change. This only happens when switching between half and full
1141 fec_restart(struct net_device
*dev
, int duplex
)
1143 struct fec_enet_private
*fep
= netdev_priv(dev
);
1146 /* Whack a reset. We should wait for this. */
1147 writel(1, fep
->hwp
+ FEC_ECNTRL
);
1150 /* Clear any outstanding interrupt. */
1151 writel(0xffc00000, fep
->hwp
+ FEC_IEVENT
);
1153 /* Reset all multicast. */
1154 writel(0, fep
->hwp
+ FEC_GRP_HASH_TABLE_HIGH
);
1155 writel(0, fep
->hwp
+ FEC_GRP_HASH_TABLE_LOW
);
1156 #ifndef CONFIG_M5272
1157 writel(0, fep
->hwp
+ FEC_HASH_TABLE_HIGH
);
1158 writel(0, fep
->hwp
+ FEC_HASH_TABLE_LOW
);
1161 /* Set maximum receive buffer size. */
1162 writel(PKT_MAXBLR_SIZE
, fep
->hwp
+ FEC_R_BUFF_SIZE
);
1164 /* Set receive and transmit descriptor base. */
1165 writel(fep
->bd_dma
, fep
->hwp
+ FEC_R_DES_START
);
1166 writel((unsigned long)fep
->bd_dma
+ sizeof(struct bufdesc
) * RX_RING_SIZE
,
1167 fep
->hwp
+ FEC_X_DES_START
);
1169 fep
->dirty_tx
= fep
->cur_tx
= fep
->tx_bd_base
;
1170 fep
->cur_rx
= fep
->rx_bd_base
;
1172 /* Reset SKB transmit buffers. */
1173 fep
->skb_cur
= fep
->skb_dirty
= 0;
1174 for (i
= 0; i
<= TX_RING_MOD_MASK
; i
++) {
1175 if (fep
->tx_skbuff
[i
]) {
1176 dev_kfree_skb_any(fep
->tx_skbuff
[i
]);
1177 fep
->tx_skbuff
[i
] = NULL
;
1181 /* Enable MII mode */
1183 /* MII enable / FD enable */
1184 writel(OPT_FRAME_SIZE
| 0x04, fep
->hwp
+ FEC_R_CNTRL
);
1185 writel(0x04, fep
->hwp
+ FEC_X_CNTRL
);
1187 /* MII enable / No Rcv on Xmit */
1188 writel(OPT_FRAME_SIZE
| 0x06, fep
->hwp
+ FEC_R_CNTRL
);
1189 writel(0x0, fep
->hwp
+ FEC_X_CNTRL
);
1191 fep
->full_duplex
= duplex
;
1194 writel(fep
->phy_speed
, fep
->hwp
+ FEC_MII_SPEED
);
1196 #ifdef FEC_MIIGSK_ENR
1197 if (fep
->phy_interface
== PHY_INTERFACE_MODE_RMII
) {
1198 /* disable the gasket and wait */
1199 writel(0, fep
->hwp
+ FEC_MIIGSK_ENR
);
1200 while (readl(fep
->hwp
+ FEC_MIIGSK_ENR
) & 4)
1203 /* configure the gasket: RMII, 50 MHz, no loopback, no echo */
1204 writel(1, fep
->hwp
+ FEC_MIIGSK_CFGR
);
1206 /* re-enable the gasket */
1207 writel(2, fep
->hwp
+ FEC_MIIGSK_ENR
);
1211 /* And last, enable the transmit and receive processing */
1212 writel(2, fep
->hwp
+ FEC_ECNTRL
);
1213 writel(0, fep
->hwp
+ FEC_R_DES_ACTIVE
);
1215 /* Enable interrupts we wish to service */
1216 writel(FEC_ENET_TXF
| FEC_ENET_RXF
| FEC_ENET_MII
,
1217 fep
->hwp
+ FEC_IMASK
);
1221 fec_stop(struct net_device
*dev
)
1223 struct fec_enet_private
*fep
= netdev_priv(dev
);
1225 /* We cannot expect a graceful transmit stop without link !!! */
1227 writel(1, fep
->hwp
+ FEC_X_CNTRL
); /* Graceful transmit stop */
1229 if (!(readl(fep
->hwp
+ FEC_IEVENT
) & FEC_ENET_GRA
))
1230 printk("fec_stop : Graceful transmit stop did not complete !\n");
1233 /* Whack a reset. We should wait for this. */
1234 writel(1, fep
->hwp
+ FEC_ECNTRL
);
1237 writel(fep
->phy_speed
, fep
->hwp
+ FEC_MII_SPEED
);
1240 static int __devinit
1241 fec_probe(struct platform_device
*pdev
)
1243 struct fec_enet_private
*fep
;
1244 struct fec_platform_data
*pdata
;
1245 struct net_device
*ndev
;
1246 int i
, irq
, ret
= 0;
1249 r
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
1253 r
= request_mem_region(r
->start
, resource_size(r
), pdev
->name
);
1257 /* Init network device */
1258 ndev
= alloc_etherdev(sizeof(struct fec_enet_private
));
1262 SET_NETDEV_DEV(ndev
, &pdev
->dev
);
1264 /* setup board info structure */
1265 fep
= netdev_priv(ndev
);
1266 memset(fep
, 0, sizeof(*fep
));
1268 ndev
->base_addr
= (unsigned long)ioremap(r
->start
, resource_size(r
));
1271 if (!ndev
->base_addr
) {
1273 goto failed_ioremap
;
1276 platform_set_drvdata(pdev
, ndev
);
1278 pdata
= pdev
->dev
.platform_data
;
1280 fep
->phy_interface
= pdata
->phy
;
1282 /* This device has up to three irqs on some platforms */
1283 for (i
= 0; i
< 3; i
++) {
1284 irq
= platform_get_irq(pdev
, i
);
1287 ret
= request_irq(irq
, fec_enet_interrupt
, IRQF_DISABLED
, pdev
->name
, ndev
);
1290 irq
= platform_get_irq(pdev
, i
);
1291 free_irq(irq
, ndev
);
1298 fep
->clk
= clk_get(&pdev
->dev
, "fec_clk");
1299 if (IS_ERR(fep
->clk
)) {
1300 ret
= PTR_ERR(fep
->clk
);
1303 clk_enable(fep
->clk
);
1305 ret
= fec_enet_init(ndev
, 0);
1309 ret
= fec_enet_mii_init(pdev
);
1311 goto failed_mii_init
;
1313 ret
= register_netdev(ndev
);
1315 goto failed_register
;
1320 fec_enet_mii_remove(fep
);
1323 clk_disable(fep
->clk
);
1326 for (i
= 0; i
< 3; i
++) {
1327 irq
= platform_get_irq(pdev
, i
);
1329 free_irq(irq
, ndev
);
1332 iounmap((void __iomem
*)ndev
->base_addr
);
1339 static int __devexit
1340 fec_drv_remove(struct platform_device
*pdev
)
1342 struct net_device
*ndev
= platform_get_drvdata(pdev
);
1343 struct fec_enet_private
*fep
= netdev_priv(ndev
);
1345 platform_set_drvdata(pdev
, NULL
);
1348 fec_enet_mii_remove(fep
);
1349 clk_disable(fep
->clk
);
1351 iounmap((void __iomem
*)ndev
->base_addr
);
1352 unregister_netdev(ndev
);
1359 fec_suspend(struct device
*dev
)
1361 struct net_device
*ndev
= dev_get_drvdata(dev
);
1362 struct fec_enet_private
*fep
;
1365 fep
= netdev_priv(ndev
);
1366 if (netif_running(ndev
))
1367 fec_enet_close(ndev
);
1368 clk_disable(fep
->clk
);
1374 fec_resume(struct device
*dev
)
1376 struct net_device
*ndev
= dev_get_drvdata(dev
);
1377 struct fec_enet_private
*fep
;
1380 fep
= netdev_priv(ndev
);
1381 clk_enable(fep
->clk
);
1382 if (netif_running(ndev
))
1383 fec_enet_open(ndev
);
1388 static const struct dev_pm_ops fec_pm_ops
= {
1389 .suspend
= fec_suspend
,
1390 .resume
= fec_resume
,
1391 .freeze
= fec_suspend
,
1393 .poweroff
= fec_suspend
,
1394 .restore
= fec_resume
,
1398 static struct platform_driver fec_driver
= {
1401 .owner
= THIS_MODULE
,
1407 .remove
= __devexit_p(fec_drv_remove
),
1411 fec_enet_module_init(void)
1413 printk(KERN_INFO
"FEC Ethernet Driver\n");
1415 return platform_driver_register(&fec_driver
);
1419 fec_enet_cleanup(void)
1421 platform_driver_unregister(&fec_driver
);
1424 module_exit(fec_enet_cleanup
);
1425 module_init(fec_enet_module_init
);
1427 MODULE_LICENSE("GPL");