drivers/net/benet/be_cmds.h

   1 /*
   2  * Copyright (C) 2005 - 2010 ServerEngines
   3  * All rights reserved.
   4  *
   5  * This program is free software; you can redistribute it and/or
   6  * modify it under the terms of the GNU General Public License version 2
   7  * as published by the Free Software Foundation.  The full GNU General
   8  * Public License is included in this distribution in the file called COPYING.
   9  *
  10  * Contact Information:
  11  * linux-drivers@serverengines.com
  12  *
  13  * ServerEngines
  14  * 209 N. Fair Oaks Ave
  15  * Sunnyvale, CA 94085
  16  */
  17
  18 /*
  19  * The driver sends configuration and managements command requests to the
  20  * firmware in the BE. These requests are communicated to the processor
  21  * using Work Request Blocks (WRBs) submitted to the MCC-WRB ring or via one
  22  * WRB inside a MAILBOX.
  23  * The commands are serviced by the ARM processor in the BladeEngine's MPU.
  24  */
  25
  26 struct be_sge {
  27         u32 pa_lo;
  28         u32 pa_hi;
  29         u32 len;
  30 };
  31
  32 #define MCC_WRB_EMBEDDED_MASK   1       /* bit 0 of dword 0*/
  33 #define MCC_WRB_SGE_CNT_SHIFT   3       /* bits 3 - 7 of dword 0 */
  34 #define MCC_WRB_SGE_CNT_MASK    0x1F    /* bits 3 - 7 of dword 0 */
  35 struct be_mcc_wrb {
  36         u32 embedded;           /* dword 0 */
  37         u32 payload_length;     /* dword 1 */
  38         u32 tag0;               /* dword 2 */
  39         u32 tag1;               /* dword 3 */
  40         u32 rsvd;               /* dword 4 */
  41         union {
  42                 u8 embedded_payload[236]; /* used by embedded cmds */
  43                 struct be_sge sgl[19];    /* used by non-embedded cmds */
  44         } payload;
  45 };
  46
  47 #define CQE_FLAGS_VALID_MASK            (1 << 31)
  48 #define CQE_FLAGS_ASYNC_MASK            (1 << 30)
  49 #define CQE_FLAGS_COMPLETED_MASK        (1 << 28)
  50 #define CQE_FLAGS_CONSUMED_MASK         (1 << 27)
  51
  52 /* Completion Status */
  53 enum {
  54         MCC_STATUS_SUCCESS = 0x0,
  55 /* The client does not have sufficient privileges to execute the command */
  56         MCC_STATUS_INSUFFICIENT_PRIVILEGES = 0x1,
  57 /* A parameter in the command was invalid. */
  58         MCC_STATUS_INVALID_PARAMETER = 0x2,
  59 /* There are insufficient chip resources to execute the command */
  60         MCC_STATUS_INSUFFICIENT_RESOURCES = 0x3,
  61 /* The command is completing because the queue was getting flushed */
  62         MCC_STATUS_QUEUE_FLUSHING = 0x4,
  63 /* The command is completing with a DMA error */
  64         MCC_STATUS_DMA_FAILED = 0x5,
  65         MCC_STATUS_NOT_SUPPORTED = 66
  66 };
  67
  68 #define CQE_STATUS_COMPL_MASK           0xFFFF
  69 #define CQE_STATUS_COMPL_SHIFT          0       /* bits 0 - 15 */
  70 #define CQE_STATUS_EXTD_MASK            0xFFFF
  71 #define CQE_STATUS_EXTD_SHIFT           16      /* bits 16 - 31 */
  72
  73 struct be_mcc_compl {
  74         u32 status;             /* dword 0 */
  75         u32 tag0;               /* dword 1 */
  76         u32 tag1;               /* dword 2 */
  77         u32 flags;              /* dword 3 */
  78 };
  79
  80 /* When the async bit of mcc_compl is set, the last 4 bytes of
  81  * mcc_compl is interpreted as follows:
  82  */
  83 #define ASYNC_TRAILER_EVENT_CODE_SHIFT  8       /* bits 8 - 15 */
  84 #define ASYNC_TRAILER_EVENT_CODE_MASK   0xFF
  85 #define ASYNC_TRAILER_EVENT_TYPE_SHIFT  16
  86 #define ASYNC_TRAILER_EVENT_TYPE_MASK   0xFF
  87 #define ASYNC_EVENT_CODE_LINK_STATE     0x1
  88 #define ASYNC_EVENT_CODE_GRP_5          0x5
  89 #define ASYNC_EVENT_QOS_SPEED           0x1
  90 #define ASYNC_EVENT_COS_PRIORITY        0x2
  91 struct be_async_event_trailer {
  92         u32 code;
  93 };
  94
  95 enum {
  96         ASYNC_EVENT_LINK_DOWN   = 0x0,
  97         ASYNC_EVENT_LINK_UP     = 0x1
  98 };
  99
 100 /* When the event code of an async trailer is link-state, the mcc_compl
 101  * must be interpreted as follows
 102  */
 103 struct be_async_event_link_state {
 104         u8 physical_port;
 105         u8 port_link_status;
 106         u8 port_duplex;
 107         u8 port_speed;
 108         u8 port_fault;
 109         u8 rsvd0[7];
 110         struct be_async_event_trailer trailer;
 111 } __packed;
 112
 113 /* When the event code of an async trailer is GRP-5 and event_type is QOS_SPEED
 114  * the mcc_compl must be interpreted as follows
 115  */
 116 struct be_async_event_grp5_qos_link_speed {
 117         u8 physical_port;
 118         u8 rsvd[5];
 119         u16 qos_link_speed;
 120         u32 event_tag;
 121         struct be_async_event_trailer trailer;
 122 } __packed;
 123
 124 /* When the event code of an async trailer is GRP5 and event type is
 125  * CoS-Priority, the mcc_compl must be interpreted as follows
 126  */
 127 struct be_async_event_grp5_cos_priority {
 128         u8 physical_port;
 129         u8 available_priority_bmap;
 130         u8 reco_default_priority;
 131         u8 valid;
 132         u8 rsvd0;
 133         u8 event_tag;
 134         struct be_async_event_trailer trailer;
 135 } __packed;
 136
 137 struct be_mcc_mailbox {
 138         struct be_mcc_wrb wrb;
 139         struct be_mcc_compl compl;
 140 };
 141
 142 #define CMD_SUBSYSTEM_COMMON    0x1
 143 #define CMD_SUBSYSTEM_ETH       0x3
 144 #define CMD_SUBSYSTEM_LOWLEVEL  0xb
 145
 146 #define OPCODE_COMMON_NTWK_MAC_QUERY                    1
 147 #define OPCODE_COMMON_NTWK_MAC_SET                      2
 148 #define OPCODE_COMMON_NTWK_MULTICAST_SET                3
 149 #define OPCODE_COMMON_NTWK_VLAN_CONFIG                  4
 150 #define OPCODE_COMMON_NTWK_LINK_STATUS_QUERY            5
 151 #define OPCODE_COMMON_READ_FLASHROM                     6
 152 #define OPCODE_COMMON_WRITE_FLASHROM                    7
 153 #define OPCODE_COMMON_CQ_CREATE                         12
 154 #define OPCODE_COMMON_EQ_CREATE                         13
 155 #define OPCODE_COMMON_MCC_CREATE                        21
 156 #define OPCODE_COMMON_SET_QOS                           28
 157 #define OPCODE_COMMON_MCC_CREATE_EXT                    90
 158 #define OPCODE_COMMON_SEEPROM_READ                      30
 159 #define OPCODE_COMMON_NTWK_RX_FILTER                    34
 160 #define OPCODE_COMMON_GET_FW_VERSION                    35
 161 #define OPCODE_COMMON_SET_FLOW_CONTROL                  36
 162 #define OPCODE_COMMON_GET_FLOW_CONTROL                  37
 163 #define OPCODE_COMMON_SET_FRAME_SIZE                    39
 164 #define OPCODE_COMMON_MODIFY_EQ_DELAY                   41
 165 #define OPCODE_COMMON_FIRMWARE_CONFIG                   42
 166 #define OPCODE_COMMON_NTWK_INTERFACE_CREATE             50
 167 #define OPCODE_COMMON_NTWK_INTERFACE_DESTROY            51
 168 #define OPCODE_COMMON_MCC_DESTROY                       53
 169 #define OPCODE_COMMON_CQ_DESTROY                        54
 170 #define OPCODE_COMMON_EQ_DESTROY                        55
 171 #define OPCODE_COMMON_QUERY_FIRMWARE_CONFIG             58
 172 #define OPCODE_COMMON_NTWK_PMAC_ADD                     59
 173 #define OPCODE_COMMON_NTWK_PMAC_DEL                     60
 174 #define OPCODE_COMMON_FUNCTION_RESET                    61
 175 #define OPCODE_COMMON_ENABLE_DISABLE_BEACON             69
 176 #define OPCODE_COMMON_GET_BEACON_STATE                  70
 177 #define OPCODE_COMMON_READ_TRANSRECV_DATA               73
 178 #define OPCODE_COMMON_GET_PHY_DETAILS                   102
 179
 180 #define OPCODE_ETH_RSS_CONFIG                           1
 181 #define OPCODE_ETH_ACPI_CONFIG                          2
 182 #define OPCODE_ETH_PROMISCUOUS                          3
 183 #define OPCODE_ETH_GET_STATISTICS                       4
 184 #define OPCODE_ETH_TX_CREATE                            7
 185 #define OPCODE_ETH_RX_CREATE                            8
 186 #define OPCODE_ETH_TX_DESTROY                           9
 187 #define OPCODE_ETH_RX_DESTROY                           10
 188 #define OPCODE_ETH_ACPI_WOL_MAGIC_CONFIG                12
 189
 190 #define OPCODE_LOWLEVEL_HOST_DDR_DMA                    17
 191 #define OPCODE_LOWLEVEL_LOOPBACK_TEST                   18
 192 #define OPCODE_LOWLEVEL_SET_LOOPBACK_MODE               19
 193
 194 struct be_cmd_req_hdr {
 195         u8 opcode;              /* dword 0 */
 196         u8 subsystem;           /* dword 0 */
 197         u8 port_number;         /* dword 0 */
 198         u8 domain;              /* dword 0 */
 199         u32 timeout;            /* dword 1 */
 200         u32 request_length;     /* dword 2 */
 201         u8 version;             /* dword 3 */
 202         u8 rsvd[3];             /* dword 3 */
 203 };
 204
 205 #define RESP_HDR_INFO_OPCODE_SHIFT      0       /* bits 0 - 7 */
 206 #define RESP_HDR_INFO_SUBSYS_SHIFT      8       /* bits 8 - 15 */
 207 struct be_cmd_resp_hdr {
 208         u32 info;               /* dword 0 */
 209         u32 status;             /* dword 1 */
 210         u32 response_length;    /* dword 2 */
 211         u32 actual_resp_len;    /* dword 3 */
 212 };
 213
 214 struct phys_addr {
 215         u32 lo;
 216         u32 hi;
 217 };
 218
 219 /**************************
 220  * BE Command definitions *
 221  **************************/
 222
 223 /* Pseudo amap definition in which each bit of the actual structure is defined
 224  * as a byte: used to calculate offset/shift/mask of each field */
 225 struct amap_eq_context {
 226         u8 cidx[13];            /* dword 0*/
 227         u8 rsvd0[3];            /* dword 0*/
 228         u8 epidx[13];           /* dword 0*/
 229         u8 valid;               /* dword 0*/
 230         u8 rsvd1;               /* dword 0*/
 231         u8 size;                /* dword 0*/
 232         u8 pidx[13];            /* dword 1*/
 233         u8 rsvd2[3];            /* dword 1*/
 234         u8 pd[10];              /* dword 1*/
 235         u8 count[3];            /* dword 1*/
 236         u8 solevent;            /* dword 1*/
 237         u8 stalled;             /* dword 1*/
 238         u8 armed;               /* dword 1*/
 239         u8 rsvd3[4];            /* dword 2*/
 240         u8 func[8];             /* dword 2*/
 241         u8 rsvd4;               /* dword 2*/
 242         u8 delaymult[10];       /* dword 2*/
 243         u8 rsvd5[2];            /* dword 2*/
 244         u8 phase[2];            /* dword 2*/
 245         u8 nodelay;             /* dword 2*/
 246         u8 rsvd6[4];            /* dword 2*/
 247         u8 rsvd7[32];           /* dword 3*/
 248 } __packed;
 249
 250 struct be_cmd_req_eq_create {
 251         struct be_cmd_req_hdr hdr;
 252         u16 num_pages;          /* sword */
 253         u16 rsvd0;              /* sword */
 254         u8 context[sizeof(struct amap_eq_context) / 8];
 255         struct phys_addr pages[8];
 256 } __packed;
 257
 258 struct be_cmd_resp_eq_create {
 259         struct be_cmd_resp_hdr resp_hdr;
 260         u16 eq_id;              /* sword */
 261         u16 rsvd0;              /* sword */
 262 } __packed;
 263
 264 /******************** Mac query ***************************/
 265 enum {
 266         MAC_ADDRESS_TYPE_STORAGE = 0x0,
 267         MAC_ADDRESS_TYPE_NETWORK = 0x1,
 268         MAC_ADDRESS_TYPE_PD = 0x2,
 269         MAC_ADDRESS_TYPE_MANAGEMENT = 0x3
 270 };
 271
 272 struct mac_addr {
 273         u16 size_of_struct;
 274         u8 addr[ETH_ALEN];
 275 } __packed;
 276
 277 struct be_cmd_req_mac_query {
 278         struct be_cmd_req_hdr hdr;
 279         u8 type;
 280         u8 permanent;
 281         u16 if_id;
 282 } __packed;
 283
 284 struct be_cmd_resp_mac_query {
 285         struct be_cmd_resp_hdr hdr;
 286         struct mac_addr mac;
 287 };
 288
 289 /******************** PMac Add ***************************/
 290 struct be_cmd_req_pmac_add {
 291         struct be_cmd_req_hdr hdr;
 292         u32 if_id;
 293         u8 mac_address[ETH_ALEN];
 294         u8 rsvd0[2];
 295 } __packed;
 296
 297 struct be_cmd_resp_pmac_add {
 298         struct be_cmd_resp_hdr hdr;
 299         u32 pmac_id;
 300 };
 301
 302 /******************** PMac Del ***************************/
 303 struct be_cmd_req_pmac_del {
 304         struct be_cmd_req_hdr hdr;
 305         u32 if_id;
 306         u32 pmac_id;
 307 };
 308
 309 /******************** Create CQ ***************************/
 310 /* Pseudo amap definition in which each bit of the actual structure is defined
 311  * as a byte: used to calculate offset/shift/mask of each field */
 312 struct amap_cq_context {
 313         u8 cidx[11];            /* dword 0*/
 314         u8 rsvd0;               /* dword 0*/
 315         u8 coalescwm[2];        /* dword 0*/
 316         u8 nodelay;             /* dword 0*/
 317         u8 epidx[11];           /* dword 0*/
 318         u8 rsvd1;               /* dword 0*/
 319         u8 count[2];            /* dword 0*/
 320         u8 valid;               /* dword 0*/
 321         u8 solevent;            /* dword 0*/
 322         u8 eventable;           /* dword 0*/
 323         u8 pidx[11];            /* dword 1*/
 324         u8 rsvd2;               /* dword 1*/
 325         u8 pd[10];              /* dword 1*/
 326         u8 eqid[8];             /* dword 1*/
 327         u8 stalled;             /* dword 1*/
 328         u8 armed;               /* dword 1*/
 329         u8 rsvd3[4];            /* dword 2*/
 330         u8 func[8];             /* dword 2*/
 331         u8 rsvd4[20];           /* dword 2*/
 332         u8 rsvd5[32];           /* dword 3*/
 333 } __packed;
 334
 335 struct be_cmd_req_cq_create {
 336         struct be_cmd_req_hdr hdr;
 337         u16 num_pages;
 338         u16 rsvd0;
 339         u8 context[sizeof(struct amap_cq_context) / 8];
 340         struct phys_addr pages[8];
 341 } __packed;
 342
 343 struct be_cmd_resp_cq_create {
 344         struct be_cmd_resp_hdr hdr;
 345         u16 cq_id;
 346         u16 rsvd0;
 347 } __packed;
 348
 349 /******************** Create MCCQ ***************************/
 350 /* Pseudo amap definition in which each bit of the actual structure is defined
 351  * as a byte: used to calculate offset/shift/mask of each field */
 352 struct amap_mcc_context {
 353         u8 con_index[14];
 354         u8 rsvd0[2];
 355         u8 ring_size[4];
 356         u8 fetch_wrb;
 357         u8 fetch_r2t;
 358         u8 cq_id[10];
 359         u8 prod_index[14];
 360         u8 fid[8];
 361         u8 pdid[9];
 362         u8 valid;
 363         u8 rsvd1[32];
 364         u8 rsvd2[32];
 365 } __packed;
 366
 367 struct be_cmd_req_mcc_create {
 368         struct be_cmd_req_hdr hdr;
 369         u16 num_pages;
 370         u16 rsvd0;
 371         u32 async_event_bitmap[1];
 372         u8 context[sizeof(struct amap_mcc_context) / 8];
 373         struct phys_addr pages[8];
 374 } __packed;
 375
 376 struct be_cmd_resp_mcc_create {
 377         struct be_cmd_resp_hdr hdr;
 378         u16 id;
 379         u16 rsvd0;
 380 } __packed;
 381
 382 /******************** Create TxQ ***************************/
 383 #define BE_ETH_TX_RING_TYPE_STANDARD            2
 384 #define BE_ULP1_NUM                             1
 385
 386 /* Pseudo amap definition in which each bit of the actual structure is defined
 387  * as a byte: used to calculate offset/shift/mask of each field */
 388 struct amap_tx_context {
 389         u8 rsvd0[16];           /* dword 0 */
 390         u8 tx_ring_size[4];     /* dword 0 */
 391         u8 rsvd1[26];           /* dword 0 */
 392         u8 pci_func_id[8];      /* dword 1 */
 393         u8 rsvd2[9];            /* dword 1 */
 394         u8 ctx_valid;           /* dword 1 */
 395         u8 cq_id_send[16];      /* dword 2 */
 396         u8 rsvd3[16];           /* dword 2 */
 397         u8 rsvd4[32];           /* dword 3 */
 398         u8 rsvd5[32];           /* dword 4 */
 399         u8 rsvd6[32];           /* dword 5 */
 400         u8 rsvd7[32];           /* dword 6 */
 401         u8 rsvd8[32];           /* dword 7 */
 402         u8 rsvd9[32];           /* dword 8 */
 403         u8 rsvd10[32];          /* dword 9 */
 404         u8 rsvd11[32];          /* dword 10 */
 405         u8 rsvd12[32];          /* dword 11 */
 406         u8 rsvd13[32];          /* dword 12 */
 407         u8 rsvd14[32];          /* dword 13 */
 408         u8 rsvd15[32];          /* dword 14 */
 409         u8 rsvd16[32];          /* dword 15 */
 410 } __packed;
 411
 412 struct be_cmd_req_eth_tx_create {
 413         struct be_cmd_req_hdr hdr;
 414         u8 num_pages;
 415         u8 ulp_num;
 416         u8 type;
 417         u8 bound_port;
 418         u8 context[sizeof(struct amap_tx_context) / 8];
 419         struct phys_addr pages[8];
 420 } __packed;
 421
 422 struct be_cmd_resp_eth_tx_create {
 423         struct be_cmd_resp_hdr hdr;
 424         u16 cid;
 425         u16 rsvd0;
 426 } __packed;
 427
 428 /******************** Create RxQ ***************************/
 429 struct be_cmd_req_eth_rx_create {
 430         struct be_cmd_req_hdr hdr;
 431         u16 cq_id;
 432         u8 frag_size;
 433         u8 num_pages;
 434         struct phys_addr pages[2];
 435         u32 interface_id;
 436         u16 max_frame_size;
 437         u16 rsvd0;
 438         u32 rss_queue;
 439 } __packed;
 440
 441 struct be_cmd_resp_eth_rx_create {
 442         struct be_cmd_resp_hdr hdr;
 443         u16 id;
 444         u8 rss_id;
 445         u8 rsvd0;
 446 } __packed;
 447
 448 /******************** Q Destroy  ***************************/
 449 /* Type of Queue to be destroyed */
 450 enum {
 451         QTYPE_EQ = 1,
 452         QTYPE_CQ,
 453         QTYPE_TXQ,
 454         QTYPE_RXQ,
 455         QTYPE_MCCQ
 456 };
 457
 458 struct be_cmd_req_q_destroy {
 459         struct be_cmd_req_hdr hdr;
 460         u16 id;
 461         u16 bypass_flush;       /* valid only for rx q destroy */
 462 } __packed;
 463
 464 /************ I/f Create (it's actually I/f Config Create)**********/
 465
 466 /* Capability flags for the i/f */
 467 enum be_if_flags {
 468         BE_IF_FLAGS_RSS = 0x4,
 469         BE_IF_FLAGS_PROMISCUOUS = 0x8,
 470         BE_IF_FLAGS_BROADCAST = 0x10,
 471         BE_IF_FLAGS_UNTAGGED = 0x20,
 472         BE_IF_FLAGS_ULP = 0x40,
 473         BE_IF_FLAGS_VLAN_PROMISCUOUS = 0x80,
 474         BE_IF_FLAGS_VLAN = 0x100,
 475         BE_IF_FLAGS_MCAST_PROMISCUOUS = 0x200,
 476         BE_IF_FLAGS_PASS_L2_ERRORS = 0x400,
 477         BE_IF_FLAGS_PASS_L3L4_ERRORS = 0x800
 478 };
 479
 480 /* An RX interface is an object with one or more MAC addresses and
 481  * filtering capabilities. */
 482 struct be_cmd_req_if_create {
 483         struct be_cmd_req_hdr hdr;
 484         u32 version;            /* ignore currently */
 485         u32 capability_flags;
 486         u32 enable_flags;
 487         u8 mac_addr[ETH_ALEN];
 488         u8 rsvd0;
 489         u8 pmac_invalid; /* if set, don't attach the mac addr to the i/f */
 490         u32 vlan_tag;    /* not used currently */
 491 } __packed;
 492
 493 struct be_cmd_resp_if_create {
 494         struct be_cmd_resp_hdr hdr;
 495         u32 interface_id;
 496         u32 pmac_id;
 497 };
 498
 499 /****** I/f Destroy(it's actually I/f Config Destroy )**********/
 500 struct be_cmd_req_if_destroy {
 501         struct be_cmd_req_hdr hdr;
 502         u32 interface_id;
 503 };
 504
 505 /*************** HW Stats Get **********************************/
 506 struct be_port_rxf_stats {
 507         u32 rx_bytes_lsd;       /* dword 0*/
 508         u32 rx_bytes_msd;       /* dword 1*/
 509         u32 rx_total_frames;    /* dword 2*/
 510         u32 rx_unicast_frames;  /* dword 3*/
 511         u32 rx_multicast_frames;        /* dword 4*/
 512         u32 rx_broadcast_frames;        /* dword 5*/
 513         u32 rx_crc_errors;      /* dword 6*/
 514         u32 rx_alignment_symbol_errors; /* dword 7*/
 515         u32 rx_pause_frames;    /* dword 8*/
 516         u32 rx_control_frames;  /* dword 9*/
 517         u32 rx_in_range_errors; /* dword 10*/
 518         u32 rx_out_range_errors;        /* dword 11*/
 519         u32 rx_frame_too_long;  /* dword 12*/
 520         u32 rx_address_match_errors;    /* dword 13*/
 521         u32 rx_vlan_mismatch;   /* dword 14*/
 522         u32 rx_dropped_too_small;       /* dword 15*/
 523         u32 rx_dropped_too_short;       /* dword 16*/
 524         u32 rx_dropped_header_too_small;        /* dword 17*/
 525         u32 rx_dropped_tcp_length;      /* dword 18*/
 526         u32 rx_dropped_runt;    /* dword 19*/
 527         u32 rx_64_byte_packets; /* dword 20*/
 528         u32 rx_65_127_byte_packets;     /* dword 21*/
 529         u32 rx_128_256_byte_packets;    /* dword 22*/
 530         u32 rx_256_511_byte_packets;    /* dword 23*/
 531         u32 rx_512_1023_byte_packets;   /* dword 24*/
 532         u32 rx_1024_1518_byte_packets;  /* dword 25*/
 533         u32 rx_1519_2047_byte_packets;  /* dword 26*/
 534         u32 rx_2048_4095_byte_packets;  /* dword 27*/
 535         u32 rx_4096_8191_byte_packets;  /* dword 28*/
 536         u32 rx_8192_9216_byte_packets;  /* dword 29*/
 537         u32 rx_ip_checksum_errs;        /* dword 30*/
 538         u32 rx_tcp_checksum_errs;       /* dword 31*/
 539         u32 rx_udp_checksum_errs;       /* dword 32*/
 540         u32 rx_non_rss_packets; /* dword 33*/
 541         u32 rx_ipv4_packets;    /* dword 34*/
 542         u32 rx_ipv6_packets;    /* dword 35*/
 543         u32 rx_ipv4_bytes_lsd;  /* dword 36*/
 544         u32 rx_ipv4_bytes_msd;  /* dword 37*/
 545         u32 rx_ipv6_bytes_lsd;  /* dword 38*/
 546         u32 rx_ipv6_bytes_msd;  /* dword 39*/
 547         u32 rx_chute1_packets;  /* dword 40*/
 548         u32 rx_chute2_packets;  /* dword 41*/
 549         u32 rx_chute3_packets;  /* dword 42*/
 550         u32 rx_management_packets;      /* dword 43*/
 551         u32 rx_switched_unicast_packets;        /* dword 44*/
 552         u32 rx_switched_multicast_packets;      /* dword 45*/
 553         u32 rx_switched_broadcast_packets;      /* dword 46*/
 554         u32 tx_bytes_lsd;       /* dword 47*/
 555         u32 tx_bytes_msd;       /* dword 48*/
 556         u32 tx_unicastframes;   /* dword 49*/
 557         u32 tx_multicastframes; /* dword 50*/
 558         u32 tx_broadcastframes; /* dword 51*/
 559         u32 tx_pauseframes;     /* dword 52*/
 560         u32 tx_controlframes;   /* dword 53*/
 561         u32 tx_64_byte_packets; /* dword 54*/
 562         u32 tx_65_127_byte_packets;     /* dword 55*/
 563         u32 tx_128_256_byte_packets;    /* dword 56*/
 564         u32 tx_256_511_byte_packets;    /* dword 57*/
 565         u32 tx_512_1023_byte_packets;   /* dword 58*/
 566         u32 tx_1024_1518_byte_packets;  /* dword 59*/
 567         u32 tx_1519_2047_byte_packets;  /* dword 60*/
 568         u32 tx_2048_4095_byte_packets;  /* dword 61*/
 569         u32 tx_4096_8191_byte_packets;  /* dword 62*/
 570         u32 tx_8192_9216_byte_packets;  /* dword 63*/
 571         u32 rx_fifo_overflow;   /* dword 64*/
 572         u32 rx_input_fifo_overflow;     /* dword 65*/
 573 };
 574
 575 struct be_rxf_stats {
 576         struct be_port_rxf_stats port[2];
 577         u32 rx_drops_no_pbuf;   /* dword 132*/
 578         u32 rx_drops_no_txpb;   /* dword 133*/
 579         u32 rx_drops_no_erx_descr;      /* dword 134*/
 580         u32 rx_drops_no_tpre_descr;     /* dword 135*/
 581         u32 management_rx_port_packets; /* dword 136*/
 582         u32 management_rx_port_bytes;   /* dword 137*/
 583         u32 management_rx_port_pause_frames;    /* dword 138*/
 584         u32 management_rx_port_errors;  /* dword 139*/
 585         u32 management_tx_port_packets; /* dword 140*/
 586         u32 management_tx_port_bytes;   /* dword 141*/
 587         u32 management_tx_port_pause;   /* dword 142*/
 588         u32 management_rx_port_rxfifo_overflow; /* dword 143*/
 589         u32 rx_drops_too_many_frags;    /* dword 144*/
 590         u32 rx_drops_invalid_ring;      /* dword 145*/
 591         u32 forwarded_packets;  /* dword 146*/
 592         u32 rx_drops_mtu;       /* dword 147*/
 593         u32 rsvd0[15];
 594 };
 595
 596 struct be_erx_stats {
 597         u32 rx_drops_no_fragments[44];     /* dwordS 0 to 43*/
 598         u32 debug_wdma_sent_hold;          /* dword 44*/
 599         u32 debug_wdma_pbfree_sent_hold;   /* dword 45*/
 600         u32 debug_wdma_zerobyte_pbfree_sent_hold; /* dword 46*/
 601         u32 debug_pmem_pbuf_dealloc;       /* dword 47*/
 602 };
 603
 604 struct be_hw_stats {
 605         struct be_rxf_stats rxf;
 606         u32 rsvd[48];
 607         struct be_erx_stats erx;
 608 };
 609
 610 struct be_cmd_req_get_stats {
 611         struct be_cmd_req_hdr hdr;
 612         u8 rsvd[sizeof(struct be_hw_stats)];
 613 };
 614
 615 struct be_cmd_resp_get_stats {
 616         struct be_cmd_resp_hdr hdr;
 617         struct be_hw_stats hw_stats;
 618 };
 619
 620 struct be_cmd_req_vlan_config {
 621         struct be_cmd_req_hdr hdr;
 622         u8 interface_id;
 623         u8 promiscuous;
 624         u8 untagged;
 625         u8 num_vlan;
 626         u16 normal_vlan[64];
 627 } __packed;
 628
 629 struct be_cmd_req_promiscuous_config {
 630         struct be_cmd_req_hdr hdr;
 631         u8 port0_promiscuous;
 632         u8 port1_promiscuous;
 633         u16 rsvd0;
 634 } __packed;
 635
 636 /******************** Multicast MAC Config *******************/
 637 #define BE_MAX_MC               64 /* set mcast promisc if > 64 */
 638 struct macaddr {
 639         u8 byte[ETH_ALEN];
 640 };
 641
 642 struct be_cmd_req_mcast_mac_config {
 643         struct be_cmd_req_hdr hdr;
 644         u16 num_mac;
 645         u8 promiscuous;
 646         u8 interface_id;
 647         struct macaddr mac[BE_MAX_MC];
 648 } __packed;
 649
 650 static inline struct be_hw_stats *
 651 hw_stats_from_cmd(struct be_cmd_resp_get_stats *cmd)
 652 {
 653         return &cmd->hw_stats;
 654 }
 655
 656 /******************** Link Status Query *******************/
 657 struct be_cmd_req_link_status {
 658         struct be_cmd_req_hdr hdr;
 659         u32 rsvd;
 660 };
 661
 662 enum {
 663         PHY_LINK_DUPLEX_NONE = 0x0,
 664         PHY_LINK_DUPLEX_HALF = 0x1,
 665         PHY_LINK_DUPLEX_FULL = 0x2
 666 };
 667
 668 enum {
 669         PHY_LINK_SPEED_ZERO = 0x0,      /* => No link */
 670         PHY_LINK_SPEED_10MBPS = 0x1,
 671         PHY_LINK_SPEED_100MBPS = 0x2,
 672         PHY_LINK_SPEED_1GBPS = 0x3,
 673         PHY_LINK_SPEED_10GBPS = 0x4
 674 };
 675
 676 struct be_cmd_resp_link_status {
 677         struct be_cmd_resp_hdr hdr;
 678         u8 physical_port;
 679         u8 mac_duplex;
 680         u8 mac_speed;
 681         u8 mac_fault;
 682         u8 mgmt_mac_duplex;
 683         u8 mgmt_mac_speed;
 684         u16 link_speed;
 685         u32 rsvd0;
 686 } __packed;
 687
 688 /******************** Port Identification ***************************/
 689 /*    Identifies the type of port attached to NIC     */
 690 struct be_cmd_req_port_type {
 691         struct be_cmd_req_hdr hdr;
 692         u32 page_num;
 693         u32 port;
 694 };
 695
 696 enum {
 697         TR_PAGE_A0 = 0xa0,
 698         TR_PAGE_A2 = 0xa2
 699 };
 700
 701 struct be_cmd_resp_port_type {
 702         struct be_cmd_resp_hdr hdr;
 703         u32 page_num;
 704         u32 port;
 705         struct data {
 706                 u8 identifier;
 707                 u8 identifier_ext;
 708                 u8 connector;
 709                 u8 transceiver[8];
 710                 u8 rsvd0[3];
 711                 u8 length_km;
 712                 u8 length_hm;
 713                 u8 length_om1;
 714                 u8 length_om2;
 715                 u8 length_cu;
 716                 u8 length_cu_m;
 717                 u8 vendor_name[16];
 718                 u8 rsvd;
 719                 u8 vendor_oui[3];
 720                 u8 vendor_pn[16];
 721                 u8 vendor_rev[4];
 722         } data;
 723 };
 724
 725 /******************** Get FW Version *******************/
 726 struct be_cmd_req_get_fw_version {
 727         struct be_cmd_req_hdr hdr;
 728         u8 rsvd0[FW_VER_LEN];
 729         u8 rsvd1[FW_VER_LEN];
 730 } __packed;
 731
 732 struct be_cmd_resp_get_fw_version {
 733         struct be_cmd_resp_hdr hdr;
 734         u8 firmware_version_string[FW_VER_LEN];
 735         u8 fw_on_flash_version_string[FW_VER_LEN];
 736 } __packed;
 737
 738 /******************** Set Flow Contrl *******************/
 739 struct be_cmd_req_set_flow_control {
 740         struct be_cmd_req_hdr hdr;
 741         u16 tx_flow_control;
 742         u16 rx_flow_control;
 743 } __packed;
 744
 745 /******************** Get Flow Contrl *******************/
 746 struct be_cmd_req_get_flow_control {
 747         struct be_cmd_req_hdr hdr;
 748         u32 rsvd;
 749 };
 750
 751 struct be_cmd_resp_get_flow_control {
 752         struct be_cmd_resp_hdr hdr;
 753         u16 tx_flow_control;
 754         u16 rx_flow_control;
 755 } __packed;
 756
 757 /******************** Modify EQ Delay *******************/
 758 struct be_cmd_req_modify_eq_delay {
 759         struct be_cmd_req_hdr hdr;
 760         u32 num_eq;
 761         struct {
 762                 u32 eq_id;
 763                 u32 phase;
 764                 u32 delay_multiplier;
 765         } delay[8];
 766 } __packed;
 767
 768 struct be_cmd_resp_modify_eq_delay {
 769         struct be_cmd_resp_hdr hdr;
 770         u32 rsvd0;
 771 } __packed;
 772
 773 /******************** Get FW Config *******************/
 774 #define BE_FUNCTION_CAPS_RSS                    0x2
 775 struct be_cmd_req_query_fw_cfg {
 776         struct be_cmd_req_hdr hdr;
 777         u32 rsvd[31];
 778 };
 779
 780 struct be_cmd_resp_query_fw_cfg {
 781         struct be_cmd_resp_hdr hdr;
 782         u32 be_config_number;
 783         u32 asic_revision;
 784         u32 phys_port;
 785         u32 function_mode;
 786         u32 rsvd[26];
 787         u32 function_caps;
 788 };
 789
 790 /******************** RSS Config *******************/
 791 /* RSS types */
 792 #define RSS_ENABLE_NONE                         0x0
 793 #define RSS_ENABLE_IPV4                         0x1
 794 #define RSS_ENABLE_TCP_IPV4                     0x2
 795 #define RSS_ENABLE_IPV6                         0x4
 796 #define RSS_ENABLE_TCP_IPV6                     0x8
 797
 798 struct be_cmd_req_rss_config {
 799         struct be_cmd_req_hdr hdr;
 800         u32 if_id;
 801         u16 enable_rss;
 802         u16 cpu_table_size_log2;
 803         u32 hash[10];
 804         u8 cpu_table[128];
 805         u8 flush;
 806         u8 rsvd0[3];
 807 };
 808
 809 /******************** Port Beacon ***************************/
 810
 811 #define BEACON_STATE_ENABLED            0x1
 812 #define BEACON_STATE_DISABLED           0x0
 813
 814 struct be_cmd_req_enable_disable_beacon {
 815         struct be_cmd_req_hdr hdr;
 816         u8  port_num;
 817         u8  beacon_state;
 818         u8  beacon_duration;
 819         u8  status_duration;
 820 } __packed;
 821
 822 struct be_cmd_resp_enable_disable_beacon {
 823         struct be_cmd_resp_hdr resp_hdr;
 824         u32 rsvd0;
 825 } __packed;
 826
 827 struct be_cmd_req_get_beacon_state {
 828         struct be_cmd_req_hdr hdr;
 829         u8  port_num;
 830         u8  rsvd0;
 831         u16 rsvd1;
 832 } __packed;
 833
 834 struct be_cmd_resp_get_beacon_state {
 835         struct be_cmd_resp_hdr resp_hdr;
 836         u8 beacon_state;
 837         u8 rsvd0[3];
 838 } __packed;
 839
 840 /****************** Firmware Flash ******************/
 841 struct flashrom_params {
 842         u32 op_code;
 843         u32 op_type;
 844         u32 data_buf_size;
 845         u32 offset;
 846         u8 data_buf[4];
 847 };
 848
 849 struct be_cmd_write_flashrom {
 850         struct be_cmd_req_hdr hdr;
 851         struct flashrom_params params;
 852 };
 853
 854 /************************ WOL *******************************/
 855 struct be_cmd_req_acpi_wol_magic_config{
 856         struct be_cmd_req_hdr hdr;
 857         u32 rsvd0[145];
 858         u8 magic_mac[6];
 859         u8 rsvd2[2];
 860 } __packed;
 861
 862 /********************** LoopBack test *********************/
 863 struct be_cmd_req_loopback_test {
 864         struct be_cmd_req_hdr hdr;
 865         u32 loopback_type;
 866         u32 num_pkts;
 867         u64 pattern;
 868         u32 src_port;
 869         u32 dest_port;
 870         u32 pkt_size;
 871 };
 872
 873 struct be_cmd_resp_loopback_test {
 874         struct be_cmd_resp_hdr resp_hdr;
 875         u32    status;
 876         u32    num_txfer;
 877         u32    num_rx;
 878         u32    miscomp_off;
 879         u32    ticks_compl;
 880 };
 881
 882 struct be_cmd_req_set_lmode {
 883         struct be_cmd_req_hdr hdr;
 884         u8 src_port;
 885         u8 dest_port;
 886         u8 loopback_type;
 887         u8 loopback_state;
 888 };
 889
 890 struct be_cmd_resp_set_lmode {
 891         struct be_cmd_resp_hdr resp_hdr;
 892         u8 rsvd0[4];
 893 };
 894
 895 /********************** DDR DMA test *********************/
 896 struct be_cmd_req_ddrdma_test {
 897         struct be_cmd_req_hdr hdr;
 898         u64 pattern;
 899         u32 byte_count;
 900         u32 rsvd0;
 901         u8  snd_buff[4096];
 902         u8  rsvd1[4096];
 903 };
 904
 905 struct be_cmd_resp_ddrdma_test {
 906         struct be_cmd_resp_hdr hdr;
 907         u64 pattern;
 908         u32 byte_cnt;
 909         u32 snd_err;
 910         u8  rsvd0[4096];
 911         u8  rcv_buff[4096];
 912 };
 913
 914 /*********************** SEEPROM Read ***********************/
 915
 916 #define BE_READ_SEEPROM_LEN 1024
 917 struct be_cmd_req_seeprom_read {
 918         struct be_cmd_req_hdr hdr;
 919         u8 rsvd0[BE_READ_SEEPROM_LEN];
 920 };
 921
 922 struct be_cmd_resp_seeprom_read {
 923         struct be_cmd_req_hdr hdr;
 924         u8 seeprom_data[BE_READ_SEEPROM_LEN];
 925 };
 926
 927 enum {
 928         PHY_TYPE_CX4_10GB = 0,
 929         PHY_TYPE_XFP_10GB,
 930         PHY_TYPE_SFP_1GB,
 931         PHY_TYPE_SFP_PLUS_10GB,
 932         PHY_TYPE_KR_10GB,
 933         PHY_TYPE_KX4_10GB,
 934         PHY_TYPE_BASET_10GB,
 935         PHY_TYPE_BASET_1GB,
 936         PHY_TYPE_DISABLED = 255
 937 };
 938
 939 struct be_cmd_req_get_phy_info {
 940         struct be_cmd_req_hdr hdr;
 941         u8 rsvd0[24];
 942 };
 943 struct be_cmd_resp_get_phy_info {
 944         struct be_cmd_req_hdr hdr;
 945         u16 phy_type;
 946         u16 interface_type;
 947         u32 misc_params;
 948         u32 future_use[4];
 949 };
 950
 951 /*********************** Set QOS ***********************/
 952
 953 #define BE_QOS_BITS_NIC                         1
 954
 955 struct be_cmd_req_set_qos {
 956         struct be_cmd_req_hdr hdr;
 957         u32 valid_bits;
 958         u32 max_bps_nic;
 959         u32 rsvd[7];
 960 };
 961
 962 struct be_cmd_resp_set_qos {
 963         struct be_cmd_resp_hdr hdr;
 964         u32 rsvd;
 965 };
 966
 967 extern int be_pci_fnum_get(struct be_adapter *adapter);
 968 extern int be_cmd_POST(struct be_adapter *adapter);
 969 extern int be_cmd_mac_addr_query(struct be_adapter *adapter, u8 *mac_addr,
 970                         u8 type, bool permanent, u32 if_handle);
 971 extern int be_cmd_pmac_add(struct be_adapter *adapter, u8 *mac_addr,
 972                         u32 if_id, u32 *pmac_id);
 973 extern int be_cmd_pmac_del(struct be_adapter *adapter, u32 if_id, u32 pmac_id);
 974 extern int be_cmd_if_create(struct be_adapter *adapter, u32 cap_flags,
 975                         u32 en_flags, u8 *mac, bool pmac_invalid,
 976                         u32 *if_handle, u32 *pmac_id, u32 domain);
 977 extern int be_cmd_if_destroy(struct be_adapter *adapter, u32 if_handle);
 978 extern int be_cmd_eq_create(struct be_adapter *adapter,
 979                         struct be_queue_info *eq, int eq_delay);
 980 extern int be_cmd_cq_create(struct be_adapter *adapter,
 981                         struct be_queue_info *cq, struct be_queue_info *eq,
 982                         bool sol_evts, bool no_delay,
 983                         int num_cqe_dma_coalesce);
 984 extern int be_cmd_mccq_create(struct be_adapter *adapter,
 985                         struct be_queue_info *mccq,
 986                         struct be_queue_info *cq);
 987 extern int be_cmd_txq_create(struct be_adapter *adapter,
 988                         struct be_queue_info *txq,
 989                         struct be_queue_info *cq);
 990 extern int be_cmd_rxq_create(struct be_adapter *adapter,
 991                         struct be_queue_info *rxq, u16 cq_id,
 992                         u16 frag_size, u16 max_frame_size, u32 if_id,
 993                         u32 rss, u8 *rss_id);
 994 extern int be_cmd_q_destroy(struct be_adapter *adapter, struct be_queue_info *q,
 995                         int type);
 996 extern int be_cmd_link_status_query(struct be_adapter *adapter,
 997                         bool *link_up, u8 *mac_speed, u16 *link_speed);
 998 extern int be_cmd_reset(struct be_adapter *adapter);
 999 extern int be_cmd_get_stats(struct be_adapter *adapter,
1000                         struct be_dma_mem *nonemb_cmd);
1001 extern int be_cmd_get_fw_ver(struct be_adapter *adapter, char *fw_ver);
1002
1003 extern int be_cmd_modify_eqd(struct be_adapter *adapter, u32 eq_id, u32 eqd);
1004 extern int be_cmd_vlan_config(struct be_adapter *adapter, u32 if_id,
1005                         u16 *vtag_array, u32 num, bool untagged,
1006                         bool promiscuous);
1007 extern int be_cmd_promiscuous_config(struct be_adapter *adapter,
1008                         u8 port_num, bool en);
1009 extern int be_cmd_multicast_set(struct be_adapter *adapter, u32 if_id,
1010                         struct net_device *netdev, struct be_dma_mem *mem);
1011 extern int be_cmd_set_flow_control(struct be_adapter *adapter,
1012                         u32 tx_fc, u32 rx_fc);
1013 extern int be_cmd_get_flow_control(struct be_adapter *adapter,
1014                         u32 *tx_fc, u32 *rx_fc);
1015 extern int be_cmd_query_fw_cfg(struct be_adapter *adapter,
1016                         u32 *port_num, u32 *function_mode, u32 *function_caps);
1017 extern int be_cmd_reset_function(struct be_adapter *adapter);
1018 extern int be_cmd_rss_config(struct be_adapter *adapter, u8 *rsstable,
1019                         u16 table_size);
1020 extern int be_process_mcc(struct be_adapter *adapter, int *status);
1021 extern int be_cmd_set_beacon_state(struct be_adapter *adapter,
1022                         u8 port_num, u8 beacon, u8 status, u8 state);
1023 extern int be_cmd_get_beacon_state(struct be_adapter *adapter,
1024                         u8 port_num, u32 *state);
1025 extern int be_cmd_write_flashrom(struct be_adapter *adapter,
1026                         struct be_dma_mem *cmd, u32 flash_oper,
1027                         u32 flash_opcode, u32 buf_size);
1028 int be_cmd_get_flash_crc(struct be_adapter *adapter, u8 *flashed_crc,
1029                                 int offset);
1030 extern int be_cmd_enable_magic_wol(struct be_adapter *adapter, u8 *mac,
1031                                 struct be_dma_mem *nonemb_cmd);
1032 extern int be_cmd_fw_init(struct be_adapter *adapter);
1033 extern int be_cmd_fw_clean(struct be_adapter *adapter);
1034 extern void be_async_mcc_enable(struct be_adapter *adapter);
1035 extern void be_async_mcc_disable(struct be_adapter *adapter);
1036 extern int be_cmd_loopback_test(struct be_adapter *adapter, u32 port_num,
1037                                 u32 loopback_type, u32 pkt_size,
1038                                 u32 num_pkts, u64 pattern);
1039 extern int be_cmd_ddr_dma_test(struct be_adapter *adapter, u64 pattern,
1040                         u32 byte_cnt, struct be_dma_mem *cmd);
1041 extern int be_cmd_get_seeprom_data(struct be_adapter *adapter,
1042                                 struct be_dma_mem *nonemb_cmd);
1043 extern int be_cmd_set_loopback(struct be_adapter *adapter, u8 port_num,
1044                                 u8 loopback_type, u8 enable);
1045 extern int be_cmd_get_phy_info(struct be_adapter *adapter,
1046                 struct be_dma_mem *cmd);
1047 extern int be_cmd_set_qos(struct be_adapter *adapter, u32 bps, u32 domain);
1048 extern void be_detect_dump_ue(struct be_adapter *adapter);
1049