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[PATCH] PPC44x EMAC driver: disable TX status deferral in half-duplex mode
[linux-2.6.git] / drivers / scsi / sata_mv.c
blobcd54244058b513d7d8c56b42c0da6ab1f8c66172
1 /*
2 * sata_mv.c - Marvell SATA support
3 *
4 * Copyright 2005: EMC Corporation, all rights reserved.
5 * Copyright 2005 Red Hat, Inc. All rights reserved.
6 *
7 * Please ALWAYS copy linux-ide@vger.kernel.org on emails.
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; version 2 of the License.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
21 *
22 */
23
24 #include <linux/kernel.h>
25 #include <linux/module.h>
26 #include <linux/pci.h>
27 #include <linux/init.h>
28 #include <linux/blkdev.h>
29 #include <linux/delay.h>
30 #include <linux/interrupt.h>
31 #include <linux/sched.h>
32 #include <linux/dma-mapping.h>
33 #include <linux/device.h>
34 #include <scsi/scsi_host.h>
35 #include <scsi/scsi_cmnd.h>
36 #include <linux/libata.h>
37 #include <asm/io.h>
38
39 #define DRV_NAME "sata_mv"
40 #define DRV_VERSION "0.5"
41
42 enum {
43 /* BAR's are enumerated in terms of pci_resource_start() terms */
44 MV_PRIMARY_BAR = 0, /* offset 0x10: memory space */
45 MV_IO_BAR = 2, /* offset 0x18: IO space */
46 MV_MISC_BAR = 3, /* offset 0x1c: FLASH, NVRAM, SRAM */
47
48 MV_MAJOR_REG_AREA_SZ = 0x10000, /* 64KB */
49 MV_MINOR_REG_AREA_SZ = 0x2000, /* 8KB */
50
51 MV_PCI_REG_BASE = 0,
52 MV_IRQ_COAL_REG_BASE = 0x18000, /* 6xxx part only */
53 MV_SATAHC0_REG_BASE = 0x20000,
54 MV_FLASH_CTL = 0x1046c,
55 MV_GPIO_PORT_CTL = 0x104f0,
56 MV_RESET_CFG = 0x180d8,
57
58 MV_PCI_REG_SZ = MV_MAJOR_REG_AREA_SZ,
59 MV_SATAHC_REG_SZ = MV_MAJOR_REG_AREA_SZ,
60 MV_SATAHC_ARBTR_REG_SZ = MV_MINOR_REG_AREA_SZ, /* arbiter */
61 MV_PORT_REG_SZ = MV_MINOR_REG_AREA_SZ,
62
63 MV_USE_Q_DEPTH = ATA_DEF_QUEUE,
64
65 MV_MAX_Q_DEPTH = 32,
66 MV_MAX_Q_DEPTH_MASK = MV_MAX_Q_DEPTH - 1,
67
68 /* CRQB needs alignment on a 1KB boundary. Size == 1KB
69 * CRPB needs alignment on a 256B boundary. Size == 256B
70 * SG count of 176 leads to MV_PORT_PRIV_DMA_SZ == 4KB
71 * ePRD (SG) entries need alignment on a 16B boundary. Size == 16B
72 */
73 MV_CRQB_Q_SZ = (32 * MV_MAX_Q_DEPTH),
74 MV_CRPB_Q_SZ = (8 * MV_MAX_Q_DEPTH),
75 MV_MAX_SG_CT = 176,
76 MV_SG_TBL_SZ = (16 * MV_MAX_SG_CT),
77 MV_PORT_PRIV_DMA_SZ = (MV_CRQB_Q_SZ + MV_CRPB_Q_SZ + MV_SG_TBL_SZ),
78
79 MV_PORTS_PER_HC = 4,
80 /* == (port / MV_PORTS_PER_HC) to determine HC from 0-7 port */
81 MV_PORT_HC_SHIFT = 2,
82 /* == (port % MV_PORTS_PER_HC) to determine hard port from 0-7 port */
83 MV_PORT_MASK = 3,
84
85 /* Host Flags */
86 MV_FLAG_DUAL_HC = (1 << 30), /* two SATA Host Controllers */
87 MV_FLAG_IRQ_COALESCE = (1 << 29), /* IRQ coalescing capability */
88 MV_COMMON_FLAGS = (ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
89 ATA_FLAG_SATA_RESET | ATA_FLAG_MMIO |
90 ATA_FLAG_NO_ATAPI),
91 MV_6XXX_FLAGS = MV_FLAG_IRQ_COALESCE,
92
93 CRQB_FLAG_READ = (1 << 0),
94 CRQB_TAG_SHIFT = 1,
95 CRQB_CMD_ADDR_SHIFT = 8,
96 CRQB_CMD_CS = (0x2 << 11),
97 CRQB_CMD_LAST = (1 << 15),
98
99 CRPB_FLAG_STATUS_SHIFT = 8,
100
101 EPRD_FLAG_END_OF_TBL = (1 << 31),
102
103 /* PCI interface registers */
104
105 PCI_COMMAND_OFS = 0xc00,
106
107 PCI_MAIN_CMD_STS_OFS = 0xd30,
108 STOP_PCI_MASTER = (1 << 2),
109 PCI_MASTER_EMPTY = (1 << 3),
110 GLOB_SFT_RST = (1 << 4),
111
112 MV_PCI_MODE = 0xd00,
113 MV_PCI_EXP_ROM_BAR_CTL = 0xd2c,
114 MV_PCI_DISC_TIMER = 0xd04,
115 MV_PCI_MSI_TRIGGER = 0xc38,
116 MV_PCI_SERR_MASK = 0xc28,
117 MV_PCI_XBAR_TMOUT = 0x1d04,
118 MV_PCI_ERR_LOW_ADDRESS = 0x1d40,
119 MV_PCI_ERR_HIGH_ADDRESS = 0x1d44,
120 MV_PCI_ERR_ATTRIBUTE = 0x1d48,
121 MV_PCI_ERR_COMMAND = 0x1d50,
122
123 PCI_IRQ_CAUSE_OFS = 0x1d58,
124 PCI_IRQ_MASK_OFS = 0x1d5c,
125 PCI_UNMASK_ALL_IRQS = 0x7fffff, /* bits 22-0 */
126
127 HC_MAIN_IRQ_CAUSE_OFS = 0x1d60,
128 HC_MAIN_IRQ_MASK_OFS = 0x1d64,
129 PORT0_ERR = (1 << 0), /* shift by port # */
130 PORT0_DONE = (1 << 1), /* shift by port # */
131 HC0_IRQ_PEND = 0x1ff, /* bits 0-8 = HC0's ports */
132 HC_SHIFT = 9, /* bits 9-17 = HC1's ports */
133 PCI_ERR = (1 << 18),
134 TRAN_LO_DONE = (1 << 19), /* 6xxx: IRQ coalescing */
135 TRAN_HI_DONE = (1 << 20), /* 6xxx: IRQ coalescing */
136 PORTS_0_7_COAL_DONE = (1 << 21), /* 6xxx: IRQ coalescing */
137 GPIO_INT = (1 << 22),
138 SELF_INT = (1 << 23),
139 TWSI_INT = (1 << 24),
140 HC_MAIN_RSVD = (0x7f << 25), /* bits 31-25 */
141 HC_MAIN_MASKED_IRQS = (TRAN_LO_DONE | TRAN_HI_DONE |
142 PORTS_0_7_COAL_DONE | GPIO_INT | TWSI_INT |
143 HC_MAIN_RSVD),
144
145 /* SATAHC registers */
146 HC_CFG_OFS = 0,
147
148 HC_IRQ_CAUSE_OFS = 0x14,
149 CRPB_DMA_DONE = (1 << 0), /* shift by port # */
150 HC_IRQ_COAL = (1 << 4), /* IRQ coalescing */
151 DEV_IRQ = (1 << 8), /* shift by port # */
152
153 /* Shadow block registers */
154 SHD_BLK_OFS = 0x100,
155 SHD_CTL_AST_OFS = 0x20, /* ofs from SHD_BLK_OFS */
156
157 /* SATA registers */
158 SATA_STATUS_OFS = 0x300, /* ctrl, err regs follow status */
159 SATA_ACTIVE_OFS = 0x350,
160 PHY_MODE3 = 0x310,
161 PHY_MODE4 = 0x314,
162 PHY_MODE2 = 0x330,
163 MV5_PHY_MODE = 0x74,
164 MV5_LT_MODE = 0x30,
165 MV5_PHY_CTL = 0x0C,
166 SATA_INTERFACE_CTL = 0x050,
167
168 MV_M2_PREAMP_MASK = 0x7e0,
169
170 /* Port registers */
171 EDMA_CFG_OFS = 0,
172 EDMA_CFG_Q_DEPTH = 0, /* queueing disabled */
173 EDMA_CFG_NCQ = (1 << 5),
174 EDMA_CFG_NCQ_GO_ON_ERR = (1 << 14), /* continue on error */
175 EDMA_CFG_RD_BRST_EXT = (1 << 11), /* read burst 512B */
176 EDMA_CFG_WR_BUFF_LEN = (1 << 13), /* write buffer 512B */
177
178 EDMA_ERR_IRQ_CAUSE_OFS = 0x8,
179 EDMA_ERR_IRQ_MASK_OFS = 0xc,
180 EDMA_ERR_D_PAR = (1 << 0),
181 EDMA_ERR_PRD_PAR = (1 << 1),
182 EDMA_ERR_DEV = (1 << 2),
183 EDMA_ERR_DEV_DCON = (1 << 3),
184 EDMA_ERR_DEV_CON = (1 << 4),
185 EDMA_ERR_SERR = (1 << 5),
186 EDMA_ERR_SELF_DIS = (1 << 7),
187 EDMA_ERR_BIST_ASYNC = (1 << 8),
188 EDMA_ERR_CRBQ_PAR = (1 << 9),
189 EDMA_ERR_CRPB_PAR = (1 << 10),
190 EDMA_ERR_INTRL_PAR = (1 << 11),
191 EDMA_ERR_IORDY = (1 << 12),
192 EDMA_ERR_LNK_CTRL_RX = (0xf << 13),
193 EDMA_ERR_LNK_CTRL_RX_2 = (1 << 15),
194 EDMA_ERR_LNK_DATA_RX = (0xf << 17),
195 EDMA_ERR_LNK_CTRL_TX = (0x1f << 21),
196 EDMA_ERR_LNK_DATA_TX = (0x1f << 26),
197 EDMA_ERR_TRANS_PROTO = (1 << 31),
198 EDMA_ERR_FATAL = (EDMA_ERR_D_PAR | EDMA_ERR_PRD_PAR |
199 EDMA_ERR_DEV_DCON | EDMA_ERR_CRBQ_PAR |
200 EDMA_ERR_CRPB_PAR | EDMA_ERR_INTRL_PAR |
201 EDMA_ERR_IORDY | EDMA_ERR_LNK_CTRL_RX_2 |
202 EDMA_ERR_LNK_DATA_RX |
203 EDMA_ERR_LNK_DATA_TX |
204 EDMA_ERR_TRANS_PROTO),
205
206 EDMA_REQ_Q_BASE_HI_OFS = 0x10,
207 EDMA_REQ_Q_IN_PTR_OFS = 0x14, /* also contains BASE_LO */
208
209 EDMA_REQ_Q_OUT_PTR_OFS = 0x18,
210 EDMA_REQ_Q_PTR_SHIFT = 5,
211
212 EDMA_RSP_Q_BASE_HI_OFS = 0x1c,
213 EDMA_RSP_Q_IN_PTR_OFS = 0x20,
214 EDMA_RSP_Q_OUT_PTR_OFS = 0x24, /* also contains BASE_LO */
215 EDMA_RSP_Q_PTR_SHIFT = 3,
216
217 EDMA_CMD_OFS = 0x28,
218 EDMA_EN = (1 << 0),
219 EDMA_DS = (1 << 1),
220 ATA_RST = (1 << 2),
221
222 EDMA_IORDY_TMOUT = 0x34,
223 EDMA_ARB_CFG = 0x38,
224
225 /* Host private flags (hp_flags) */
226 MV_HP_FLAG_MSI = (1 << 0),
227 MV_HP_ERRATA_50XXB0 = (1 << 1),
228 MV_HP_ERRATA_50XXB2 = (1 << 2),
229 MV_HP_ERRATA_60X1B2 = (1 << 3),
230 MV_HP_ERRATA_60X1C0 = (1 << 4),
231 MV_HP_50XX = (1 << 5),
232
233 /* Port private flags (pp_flags) */
234 MV_PP_FLAG_EDMA_EN = (1 << 0),
235 MV_PP_FLAG_EDMA_DS_ACT = (1 << 1),
236 };
237
238 #define IS_50XX(hpriv) ((hpriv)->hp_flags & MV_HP_50XX)
239 #define IS_60XX(hpriv) (((hpriv)->hp_flags & MV_HP_50XX) == 0)
240
241 enum {
242 /* Our DMA boundary is determined by an ePRD being unable to handle
243 * anything larger than 64KB
244 */
245 MV_DMA_BOUNDARY = 0xffffU,
246
247 EDMA_REQ_Q_BASE_LO_MASK = 0xfffffc00U,
248
249 EDMA_RSP_Q_BASE_LO_MASK = 0xffffff00U,
250 };
251
252 enum chip_type {
253 chip_504x,
254 chip_508x,
255 chip_5080,
256 chip_604x,
257 chip_608x,
258 };
259
260 /* Command ReQuest Block: 32B */
261 struct mv_crqb {
262 u32 sg_addr;
263 u32 sg_addr_hi;
264 u16 ctrl_flags;
265 u16 ata_cmd[11];
266 };
267
268 /* Command ResPonse Block: 8B */
269 struct mv_crpb {
270 u16 id;
271 u16 flags;
272 u32 tmstmp;
273 };
274
275 /* EDMA Physical Region Descriptor (ePRD); A.K.A. SG */
276 struct mv_sg {
277 u32 addr;
278 u32 flags_size;
279 u32 addr_hi;
280 u32 reserved;
281 };
282
283 struct mv_port_priv {
284 struct mv_crqb *crqb;
285 dma_addr_t crqb_dma;
286 struct mv_crpb *crpb;
287 dma_addr_t crpb_dma;
288 struct mv_sg *sg_tbl;
289 dma_addr_t sg_tbl_dma;
290
291 unsigned req_producer; /* cp of req_in_ptr */
292 unsigned rsp_consumer; /* cp of rsp_out_ptr */
293 u32 pp_flags;
294 };
295
296 struct mv_port_signal {
297 u32 amps;
298 u32 pre;
299 };
300
301 struct mv_host_priv;
302 struct mv_hw_ops {
303 void (*phy_errata)(struct mv_host_priv *hpriv, void __iomem *mmio,
304 unsigned int port);
305 void (*enable_leds)(struct mv_host_priv *hpriv, void __iomem *mmio);
306 void (*read_preamp)(struct mv_host_priv *hpriv, int idx,
307 void __iomem *mmio);
308 int (*reset_hc)(struct mv_host_priv *hpriv, void __iomem *mmio,
309 unsigned int n_hc);
310 void (*reset_flash)(struct mv_host_priv *hpriv, void __iomem *mmio);
311 void (*reset_bus)(struct pci_dev *pdev, void __iomem *mmio);
312 };
313
314 struct mv_host_priv {
315 u32 hp_flags;
316 struct mv_port_signal signal[8];
317 const struct mv_hw_ops *ops;
318 };
319
320 static void mv_irq_clear(struct ata_port *ap);
321 static u32 mv_scr_read(struct ata_port *ap, unsigned int sc_reg_in);
322 static void mv_scr_write(struct ata_port *ap, unsigned int sc_reg_in, u32 val);
323 static u32 mv5_scr_read(struct ata_port *ap, unsigned int sc_reg_in);
324 static void mv5_scr_write(struct ata_port *ap, unsigned int sc_reg_in, u32 val);
325 static void mv_phy_reset(struct ata_port *ap);
326 static void __mv_phy_reset(struct ata_port *ap, int can_sleep);
327 static void mv_host_stop(struct ata_host_set *host_set);
328 static int mv_port_start(struct ata_port *ap);
329 static void mv_port_stop(struct ata_port *ap);
330 static void mv_qc_prep(struct ata_queued_cmd *qc);
331 static int mv_qc_issue(struct ata_queued_cmd *qc);
332 static irqreturn_t mv_interrupt(int irq, void *dev_instance,
333 struct pt_regs *regs);
334 static void mv_eng_timeout(struct ata_port *ap);
335 static int mv_init_one(struct pci_dev *pdev, const struct pci_device_id *ent);
336
337 static void mv5_phy_errata(struct mv_host_priv *hpriv, void __iomem *mmio,
338 unsigned int port);
339 static void mv5_enable_leds(struct mv_host_priv *hpriv, void __iomem *mmio);
340 static void mv5_read_preamp(struct mv_host_priv *hpriv, int idx,
341 void __iomem *mmio);
342 static int mv5_reset_hc(struct mv_host_priv *hpriv, void __iomem *mmio,
343 unsigned int n_hc);
344 static void mv5_reset_flash(struct mv_host_priv *hpriv, void __iomem *mmio);
345 static void mv5_reset_bus(struct pci_dev *pdev, void __iomem *mmio);
346
347 static void mv6_phy_errata(struct mv_host_priv *hpriv, void __iomem *mmio,
348 unsigned int port);
349 static void mv6_enable_leds(struct mv_host_priv *hpriv, void __iomem *mmio);
350 static void mv6_read_preamp(struct mv_host_priv *hpriv, int idx,
351 void __iomem *mmio);
352 static int mv6_reset_hc(struct mv_host_priv *hpriv, void __iomem *mmio,
353 unsigned int n_hc);
354 static void mv6_reset_flash(struct mv_host_priv *hpriv, void __iomem *mmio);
355 static void mv_reset_pci_bus(struct pci_dev *pdev, void __iomem *mmio);
356 static void mv_channel_reset(struct mv_host_priv *hpriv, void __iomem *mmio,
357 unsigned int port_no);
358 static void mv_stop_and_reset(struct ata_port *ap);
359
360 static struct scsi_host_template mv_sht = {
361 .module = THIS_MODULE,
362 .name = DRV_NAME,
363 .ioctl = ata_scsi_ioctl,
364 .queuecommand = ata_scsi_queuecmd,
365 .eh_strategy_handler = ata_scsi_error,
366 .can_queue = MV_USE_Q_DEPTH,
367 .this_id = ATA_SHT_THIS_ID,
368 .sg_tablesize = MV_MAX_SG_CT / 2,
369 .max_sectors = ATA_MAX_SECTORS,
370 .cmd_per_lun = ATA_SHT_CMD_PER_LUN,
371 .emulated = ATA_SHT_EMULATED,
372 .use_clustering = ATA_SHT_USE_CLUSTERING,
373 .proc_name = DRV_NAME,
374 .dma_boundary = MV_DMA_BOUNDARY,
375 .slave_configure = ata_scsi_slave_config,
376 .bios_param = ata_std_bios_param,
377 };
378
379 static const struct ata_port_operations mv5_ops = {
380 .port_disable = ata_port_disable,
381
382 .tf_load = ata_tf_load,
383 .tf_read = ata_tf_read,
384 .check_status = ata_check_status,
385 .exec_command = ata_exec_command,
386 .dev_select = ata_std_dev_select,
387
388 .phy_reset = mv_phy_reset,
389
390 .qc_prep = mv_qc_prep,
391 .qc_issue = mv_qc_issue,
392
393 .eng_timeout = mv_eng_timeout,
394
395 .irq_handler = mv_interrupt,
396 .irq_clear = mv_irq_clear,
397
398 .scr_read = mv5_scr_read,
399 .scr_write = mv5_scr_write,
400
401 .port_start = mv_port_start,
402 .port_stop = mv_port_stop,
403 .host_stop = mv_host_stop,
404 };
405
406 static const struct ata_port_operations mv6_ops = {
407 .port_disable = ata_port_disable,
408
409 .tf_load = ata_tf_load,
410 .tf_read = ata_tf_read,
411 .check_status = ata_check_status,
412 .exec_command = ata_exec_command,
413 .dev_select = ata_std_dev_select,
414
415 .phy_reset = mv_phy_reset,
416
417 .qc_prep = mv_qc_prep,
418 .qc_issue = mv_qc_issue,
419
420 .eng_timeout = mv_eng_timeout,
421
422 .irq_handler = mv_interrupt,
423 .irq_clear = mv_irq_clear,
424
425 .scr_read = mv_scr_read,
426 .scr_write = mv_scr_write,
427
428 .port_start = mv_port_start,
429 .port_stop = mv_port_stop,
430 .host_stop = mv_host_stop,
431 };
432
433 static const struct ata_port_info mv_port_info[] = {
434 { /* chip_504x */
435 .sht = &mv_sht,
436 .host_flags = MV_COMMON_FLAGS,
437 .pio_mask = 0x1f, /* pio0-4 */
438 .udma_mask = 0x7f, /* udma0-6 */
439 .port_ops = &mv5_ops,
440 },
441 { /* chip_508x */
442 .sht = &mv_sht,
443 .host_flags = (MV_COMMON_FLAGS | MV_FLAG_DUAL_HC),
444 .pio_mask = 0x1f, /* pio0-4 */
445 .udma_mask = 0x7f, /* udma0-6 */
446 .port_ops = &mv5_ops,
447 },
448 { /* chip_5080 */
449 .sht = &mv_sht,
450 .host_flags = (MV_COMMON_FLAGS | MV_FLAG_DUAL_HC),
451 .pio_mask = 0x1f, /* pio0-4 */
452 .udma_mask = 0x7f, /* udma0-6 */
453 .port_ops = &mv5_ops,
454 },
455 { /* chip_604x */
456 .sht = &mv_sht,
457 .host_flags = (MV_COMMON_FLAGS | MV_6XXX_FLAGS),
458 .pio_mask = 0x1f, /* pio0-4 */
459 .udma_mask = 0x7f, /* udma0-6 */
460 .port_ops = &mv6_ops,
461 },
462 { /* chip_608x */
463 .sht = &mv_sht,
464 .host_flags = (MV_COMMON_FLAGS | MV_6XXX_FLAGS |
465 MV_FLAG_DUAL_HC),
466 .pio_mask = 0x1f, /* pio0-4 */
467 .udma_mask = 0x7f, /* udma0-6 */
468 .port_ops = &mv6_ops,
469 },
470 };
471
472 static const struct pci_device_id mv_pci_tbl[] = {
473 {PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x5040), 0, 0, chip_504x},
474 {PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x5041), 0, 0, chip_504x},
475 {PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x5080), 0, 0, chip_5080},
476 {PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x5081), 0, 0, chip_508x},
477
478 {PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x6040), 0, 0, chip_604x},
479 {PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x6041), 0, 0, chip_604x},
480 {PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x6080), 0, 0, chip_608x},
481 {PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x6081), 0, 0, chip_608x},
482
483 {PCI_DEVICE(PCI_VENDOR_ID_ADAPTEC2, 0x0241), 0, 0, chip_604x},
484 {} /* terminate list */
485 };
486
487 static struct pci_driver mv_pci_driver = {
488 .name = DRV_NAME,
489 .id_table = mv_pci_tbl,
490 .probe = mv_init_one,
491 .remove = ata_pci_remove_one,
492 };
493
494 static const struct mv_hw_ops mv5xxx_ops = {
495 .phy_errata = mv5_phy_errata,
496 .enable_leds = mv5_enable_leds,
497 .read_preamp = mv5_read_preamp,
498 .reset_hc = mv5_reset_hc,
499 .reset_flash = mv5_reset_flash,
500 .reset_bus = mv5_reset_bus,
501 };
502
503 static const struct mv_hw_ops mv6xxx_ops = {
504 .phy_errata = mv6_phy_errata,
505 .enable_leds = mv6_enable_leds,
506 .read_preamp = mv6_read_preamp,
507 .reset_hc = mv6_reset_hc,
508 .reset_flash = mv6_reset_flash,
509 .reset_bus = mv_reset_pci_bus,
510 };
511
512 /*
513 * Functions
514 */
515
516 static inline void writelfl(unsigned long data, void __iomem *addr)
517 {
518 writel(data, addr);
519 (void) readl(addr); /* flush to avoid PCI posted write */
520 }
521
522 static inline void __iomem *mv_hc_base(void __iomem *base, unsigned int hc)
523 {
524 return (base + MV_SATAHC0_REG_BASE + (hc * MV_SATAHC_REG_SZ));
525 }
526
527 static inline unsigned int mv_hc_from_port(unsigned int port)
528 {
529 return port >> MV_PORT_HC_SHIFT;
530 }
531
532 static inline unsigned int mv_hardport_from_port(unsigned int port)
533 {
534 return port & MV_PORT_MASK;
535 }
536
537 static inline void __iomem *mv_hc_base_from_port(void __iomem *base,
538 unsigned int port)
539 {
540 return mv_hc_base(base, mv_hc_from_port(port));
541 }
542
543 static inline void __iomem *mv_port_base(void __iomem *base, unsigned int port)
544 {
545 return mv_hc_base_from_port(base, port) +
546 MV_SATAHC_ARBTR_REG_SZ +
547 (mv_hardport_from_port(port) * MV_PORT_REG_SZ);
548 }
549
550 static inline void __iomem *mv_ap_base(struct ata_port *ap)
551 {
552 return mv_port_base(ap->host_set->mmio_base, ap->port_no);
553 }
554
555 static inline int mv_get_hc_count(unsigned long host_flags)
556 {
557 return ((host_flags & MV_FLAG_DUAL_HC) ? 2 : 1);
558 }
559
560 static void mv_irq_clear(struct ata_port *ap)
561 {
562 }
563
564 /**
565 * mv_start_dma - Enable eDMA engine
566 * @base: port base address
567 * @pp: port private data
568 *
569 * Verify the local cache of the eDMA state is accurate with an
570 * assert.
571 *
572 * LOCKING:
573 * Inherited from caller.
574 */
575 static void mv_start_dma(void __iomem *base, struct mv_port_priv *pp)
576 {
577 if (!(MV_PP_FLAG_EDMA_EN & pp->pp_flags)) {
578 writelfl(EDMA_EN, base + EDMA_CMD_OFS);
579 pp->pp_flags |= MV_PP_FLAG_EDMA_EN;
580 }
581 assert(EDMA_EN & readl(base + EDMA_CMD_OFS));
582 }
583
584 /**
585 * mv_stop_dma - Disable eDMA engine
586 * @ap: ATA channel to manipulate
587 *
588 * Verify the local cache of the eDMA state is accurate with an
589 * assert.
590 *
591 * LOCKING:
592 * Inherited from caller.
593 */
594 static void mv_stop_dma(struct ata_port *ap)
595 {
596 void __iomem *port_mmio = mv_ap_base(ap);
597 struct mv_port_priv *pp = ap->private_data;
598 u32 reg;
599 int i;
600
601 if (MV_PP_FLAG_EDMA_EN & pp->pp_flags) {
602 /* Disable EDMA if active. The disable bit auto clears.
603 */
604 writelfl(EDMA_DS, port_mmio + EDMA_CMD_OFS);
605 pp->pp_flags &= ~MV_PP_FLAG_EDMA_EN;
606 } else {
607 assert(!(EDMA_EN & readl(port_mmio + EDMA_CMD_OFS)));
608 }
609
610 /* now properly wait for the eDMA to stop */
611 for (i = 1000; i > 0; i--) {
612 reg = readl(port_mmio + EDMA_CMD_OFS);
613 if (!(EDMA_EN & reg)) {
614 break;
615 }
616 udelay(100);
617 }
618
619 if (EDMA_EN & reg) {
620 printk(KERN_ERR "ata%u: Unable to stop eDMA\n", ap->id);
621 /* FIXME: Consider doing a reset here to recover */
622 }
623 }
624
625 #ifdef ATA_DEBUG
626 static void mv_dump_mem(void __iomem *start, unsigned bytes)
627 {
628 int b, w;
629 for (b = 0; b < bytes; ) {
630 DPRINTK("%p: ", start + b);
631 for (w = 0; b < bytes && w < 4; w++) {
632 printk("%08x ",readl(start + b));
633 b += sizeof(u32);
634 }
635 printk("\n");
636 }
637 }
638 #endif
639
640 static void mv_dump_pci_cfg(struct pci_dev *pdev, unsigned bytes)
641 {
642 #ifdef ATA_DEBUG
643 int b, w;
644 u32 dw;
645 for (b = 0; b < bytes; ) {
646 DPRINTK("%02x: ", b);
647 for (w = 0; b < bytes && w < 4; w++) {
648 (void) pci_read_config_dword(pdev,b,&dw);
649 printk("%08x ",dw);
650 b += sizeof(u32);
651 }
652 printk("\n");
653 }
654 #endif
655 }
656 static void mv_dump_all_regs(void __iomem *mmio_base, int port,
657 struct pci_dev *pdev)
658 {
659 #ifdef ATA_DEBUG
660 void __iomem *hc_base = mv_hc_base(mmio_base,
661 port >> MV_PORT_HC_SHIFT);
662 void __iomem *port_base;
663 int start_port, num_ports, p, start_hc, num_hcs, hc;
664
665 if (0 > port) {
666 start_hc = start_port = 0;
667 num_ports = 8; /* shld be benign for 4 port devs */
668 num_hcs = 2;
669 } else {
670 start_hc = port >> MV_PORT_HC_SHIFT;
671 start_port = port;
672 num_ports = num_hcs = 1;
673 }
674 DPRINTK("All registers for port(s) %u-%u:\n", start_port,
675 num_ports > 1 ? num_ports - 1 : start_port);
676
677 if (NULL != pdev) {
678 DPRINTK("PCI config space regs:\n");
679 mv_dump_pci_cfg(pdev, 0x68);
680 }
681 DPRINTK("PCI regs:\n");
682 mv_dump_mem(mmio_base+0xc00, 0x3c);
683 mv_dump_mem(mmio_base+0xd00, 0x34);
684 mv_dump_mem(mmio_base+0xf00, 0x4);
685 mv_dump_mem(mmio_base+0x1d00, 0x6c);
686 for (hc = start_hc; hc < start_hc + num_hcs; hc++) {
687 hc_base = mv_hc_base(mmio_base, port >> MV_PORT_HC_SHIFT);
688 DPRINTK("HC regs (HC %i):\n", hc);
689 mv_dump_mem(hc_base, 0x1c);
690 }
691 for (p = start_port; p < start_port + num_ports; p++) {
692 port_base = mv_port_base(mmio_base, p);
693 DPRINTK("EDMA regs (port %i):\n",p);
694 mv_dump_mem(port_base, 0x54);
695 DPRINTK("SATA regs (port %i):\n",p);
696 mv_dump_mem(port_base+0x300, 0x60);
697 }
698 #endif
699 }
700
701 static unsigned int mv_scr_offset(unsigned int sc_reg_in)
702 {
703 unsigned int ofs;
704
705 switch (sc_reg_in) {
706 case SCR_STATUS:
707 case SCR_CONTROL:
708 case SCR_ERROR:
709 ofs = SATA_STATUS_OFS + (sc_reg_in * sizeof(u32));
710 break;
711 case SCR_ACTIVE:
712 ofs = SATA_ACTIVE_OFS; /* active is not with the others */
713 break;
714 default:
715 ofs = 0xffffffffU;
716 break;
717 }
718 return ofs;
719 }
720
721 static u32 mv_scr_read(struct ata_port *ap, unsigned int sc_reg_in)
722 {
723 unsigned int ofs = mv_scr_offset(sc_reg_in);
724
725 if (0xffffffffU != ofs) {
726 return readl(mv_ap_base(ap) + ofs);
727 } else {
728 return (u32) ofs;
729 }
730 }
731
732 static void mv_scr_write(struct ata_port *ap, unsigned int sc_reg_in, u32 val)
733 {
734 unsigned int ofs = mv_scr_offset(sc_reg_in);
735
736 if (0xffffffffU != ofs) {
737 writelfl(val, mv_ap_base(ap) + ofs);
738 }
739 }
740
741 /**
742 * mv_host_stop - Host specific cleanup/stop routine.
743 * @host_set: host data structure
744 *
745 * Disable ints, cleanup host memory, call general purpose
746 * host_stop.
747 *
748 * LOCKING:
749 * Inherited from caller.
750 */
751 static void mv_host_stop(struct ata_host_set *host_set)
752 {
753 struct mv_host_priv *hpriv = host_set->private_data;
754 struct pci_dev *pdev = to_pci_dev(host_set->dev);
755
756 if (hpriv->hp_flags & MV_HP_FLAG_MSI) {
757 pci_disable_msi(pdev);
758 } else {
759 pci_intx(pdev, 0);
760 }
761 kfree(hpriv);
762 ata_host_stop(host_set);
763 }
764
765 static inline void mv_priv_free(struct mv_port_priv *pp, struct device *dev)
766 {
767 dma_free_coherent(dev, MV_PORT_PRIV_DMA_SZ, pp->crpb, pp->crpb_dma);
768 }
769
770 /**
771 * mv_port_start - Port specific init/start routine.
772 * @ap: ATA channel to manipulate
773 *
774 * Allocate and point to DMA memory, init port private memory,
775 * zero indices.
776 *
777 * LOCKING:
778 * Inherited from caller.
779 */
780 static int mv_port_start(struct ata_port *ap)
781 {
782 struct device *dev = ap->host_set->dev;
783 struct mv_port_priv *pp;
784 void __iomem *port_mmio = mv_ap_base(ap);
785 void *mem;
786 dma_addr_t mem_dma;
787 int rc = -ENOMEM;
788
789 pp = kmalloc(sizeof(*pp), GFP_KERNEL);
790 if (!pp)
791 goto err_out;
792 memset(pp, 0, sizeof(*pp));
793
794 mem = dma_alloc_coherent(dev, MV_PORT_PRIV_DMA_SZ, &mem_dma,
795 GFP_KERNEL);
796 if (!mem)
797 goto err_out_pp;
798 memset(mem, 0, MV_PORT_PRIV_DMA_SZ);
799
800 rc = ata_pad_alloc(ap, dev);
801 if (rc)
802 goto err_out_priv;
803
804 /* First item in chunk of DMA memory:
805 * 32-slot command request table (CRQB), 32 bytes each in size
806 */
807 pp->crqb = mem;
808 pp->crqb_dma = mem_dma;
809 mem += MV_CRQB_Q_SZ;
810 mem_dma += MV_CRQB_Q_SZ;
811
812 /* Second item:
813 * 32-slot command response table (CRPB), 8 bytes each in size
814 */
815 pp->crpb = mem;
816 pp->crpb_dma = mem_dma;
817 mem += MV_CRPB_Q_SZ;
818 mem_dma += MV_CRPB_Q_SZ;
819
820 /* Third item:
821 * Table of scatter-gather descriptors (ePRD), 16 bytes each
822 */
823 pp->sg_tbl = mem;
824 pp->sg_tbl_dma = mem_dma;
825
826 writelfl(EDMA_CFG_Q_DEPTH | EDMA_CFG_RD_BRST_EXT |
827 EDMA_CFG_WR_BUFF_LEN, port_mmio + EDMA_CFG_OFS);
828
829 writel((pp->crqb_dma >> 16) >> 16, port_mmio + EDMA_REQ_Q_BASE_HI_OFS);
830 writelfl(pp->crqb_dma & EDMA_REQ_Q_BASE_LO_MASK,
831 port_mmio + EDMA_REQ_Q_IN_PTR_OFS);
832
833 writelfl(0, port_mmio + EDMA_REQ_Q_OUT_PTR_OFS);
834 writelfl(0, port_mmio + EDMA_RSP_Q_IN_PTR_OFS);
835
836 writel((pp->crpb_dma >> 16) >> 16, port_mmio + EDMA_RSP_Q_BASE_HI_OFS);
837 writelfl(pp->crpb_dma & EDMA_RSP_Q_BASE_LO_MASK,
838 port_mmio + EDMA_RSP_Q_OUT_PTR_OFS);
839
840 pp->req_producer = pp->rsp_consumer = 0;
841
842 /* Don't turn on EDMA here...do it before DMA commands only. Else
843 * we'll be unable to send non-data, PIO, etc due to restricted access
844 * to shadow regs.
845 */
846 ap->private_data = pp;
847 return 0;
848
849 err_out_priv:
850 mv_priv_free(pp, dev);
851 err_out_pp:
852 kfree(pp);
853 err_out:
854 return rc;
855 }
856
857 /**
858 * mv_port_stop - Port specific cleanup/stop routine.
859 * @ap: ATA channel to manipulate
860 *
861 * Stop DMA, cleanup port memory.
862 *
863 * LOCKING:
864 * This routine uses the host_set lock to protect the DMA stop.
865 */
866 static void mv_port_stop(struct ata_port *ap)
867 {
868 struct device *dev = ap->host_set->dev;
869 struct mv_port_priv *pp = ap->private_data;
870 unsigned long flags;
871
872 spin_lock_irqsave(&ap->host_set->lock, flags);
873 mv_stop_dma(ap);
874 spin_unlock_irqrestore(&ap->host_set->lock, flags);
875
876 ap->private_data = NULL;
877 ata_pad_free(ap, dev);
878 mv_priv_free(pp, dev);
879 kfree(pp);
880 }
881
882 /**
883 * mv_fill_sg - Fill out the Marvell ePRD (scatter gather) entries
884 * @qc: queued command whose SG list to source from
885 *
886 * Populate the SG list and mark the last entry.
887 *
888 * LOCKING:
889 * Inherited from caller.
890 */
891 static void mv_fill_sg(struct ata_queued_cmd *qc)
892 {
893 struct mv_port_priv *pp = qc->ap->private_data;
894 unsigned int i = 0;
895 struct scatterlist *sg;
896
897 ata_for_each_sg(sg, qc) {
898 dma_addr_t addr;
899 u32 sg_len, len, offset;
900
901 addr = sg_dma_address(sg);
902 sg_len = sg_dma_len(sg);
903
904 while (sg_len) {
905 offset = addr & MV_DMA_BOUNDARY;
906 len = sg_len;
907 if ((offset + sg_len) > 0x10000)
908 len = 0x10000 - offset;
909
910 pp->sg_tbl[i].addr = cpu_to_le32(addr & 0xffffffff);
911 pp->sg_tbl[i].addr_hi = cpu_to_le32((addr >> 16) >> 16);
912 pp->sg_tbl[i].flags_size = cpu_to_le32(len);
913
914 sg_len -= len;
915 addr += len;
916
917 if (!sg_len && ata_sg_is_last(sg, qc))
918 pp->sg_tbl[i].flags_size |= cpu_to_le32(EPRD_FLAG_END_OF_TBL);
919
920 i++;
921 }
922 }
923 }
924
925 static inline unsigned mv_inc_q_index(unsigned *index)
926 {
927 *index = (*index + 1) & MV_MAX_Q_DEPTH_MASK;
928 return *index;
929 }
930
931 static inline void mv_crqb_pack_cmd(u16 *cmdw, u8 data, u8 addr, unsigned last)
932 {
933 *cmdw = data | (addr << CRQB_CMD_ADDR_SHIFT) | CRQB_CMD_CS |
934 (last ? CRQB_CMD_LAST : 0);
935 }
936
937 /**
938 * mv_qc_prep - Host specific command preparation.
939 * @qc: queued command to prepare
940 *
941 * This routine simply redirects to the general purpose routine
942 * if command is not DMA. Else, it handles prep of the CRQB
943 * (command request block), does some sanity checking, and calls
944 * the SG load routine.
945 *
946 * LOCKING:
947 * Inherited from caller.
948 */
949 static void mv_qc_prep(struct ata_queued_cmd *qc)
950 {
951 struct ata_port *ap = qc->ap;
952 struct mv_port_priv *pp = ap->private_data;
953 u16 *cw;
954 struct ata_taskfile *tf;
955 u16 flags = 0;
956
957 if (ATA_PROT_DMA != qc->tf.protocol) {
958 return;
959 }
960
961 /* the req producer index should be the same as we remember it */
962 assert(((readl(mv_ap_base(qc->ap) + EDMA_REQ_Q_IN_PTR_OFS) >>
963 EDMA_REQ_Q_PTR_SHIFT) & MV_MAX_Q_DEPTH_MASK) ==
964 pp->req_producer);
965
966 /* Fill in command request block
967 */
968 if (!(qc->tf.flags & ATA_TFLAG_WRITE)) {
969 flags |= CRQB_FLAG_READ;
970 }
971 assert(MV_MAX_Q_DEPTH > qc->tag);
972 flags |= qc->tag << CRQB_TAG_SHIFT;
973
974 pp->crqb[pp->req_producer].sg_addr =
975 cpu_to_le32(pp->sg_tbl_dma & 0xffffffff);
976 pp->crqb[pp->req_producer].sg_addr_hi =
977 cpu_to_le32((pp->sg_tbl_dma >> 16) >> 16);
978 pp->crqb[pp->req_producer].ctrl_flags = cpu_to_le16(flags);
979
980 cw = &pp->crqb[pp->req_producer].ata_cmd[0];
981 tf = &qc->tf;
982
983 /* Sadly, the CRQB cannot accomodate all registers--there are
984 * only 11 bytes...so we must pick and choose required
985 * registers based on the command. So, we drop feature and
986 * hob_feature for [RW] DMA commands, but they are needed for
987 * NCQ. NCQ will drop hob_nsect.
988 */
989 switch (tf->command) {
990 case ATA_CMD_READ:
991 case ATA_CMD_READ_EXT:
992 case ATA_CMD_WRITE:
993 case ATA_CMD_WRITE_EXT:
994 mv_crqb_pack_cmd(cw++, tf->hob_nsect, ATA_REG_NSECT, 0);
995 break;
996 #ifdef LIBATA_NCQ /* FIXME: remove this line when NCQ added */
997 case ATA_CMD_FPDMA_READ:
998 case ATA_CMD_FPDMA_WRITE:
999 mv_crqb_pack_cmd(cw++, tf->hob_feature, ATA_REG_FEATURE, 0);
1000 mv_crqb_pack_cmd(cw++, tf->feature, ATA_REG_FEATURE, 0);
1001 break;
1002 #endif /* FIXME: remove this line when NCQ added */
1003 default:
1004 /* The only other commands EDMA supports in non-queued and
1005 * non-NCQ mode are: [RW] STREAM DMA and W DMA FUA EXT, none
1006 * of which are defined/used by Linux. If we get here, this
1007 * driver needs work.
1008 *
1009 * FIXME: modify libata to give qc_prep a return value and
1010 * return error here.
1011 */
1012 BUG_ON(tf->command);
1013 break;
1014 }
1015 mv_crqb_pack_cmd(cw++, tf->nsect, ATA_REG_NSECT, 0);
1016 mv_crqb_pack_cmd(cw++, tf->hob_lbal, ATA_REG_LBAL, 0);
1017 mv_crqb_pack_cmd(cw++, tf->lbal, ATA_REG_LBAL, 0);
1018 mv_crqb_pack_cmd(cw++, tf->hob_lbam, ATA_REG_LBAM, 0);
1019 mv_crqb_pack_cmd(cw++, tf->lbam, ATA_REG_LBAM, 0);
1020 mv_crqb_pack_cmd(cw++, tf->hob_lbah, ATA_REG_LBAH, 0);
1021 mv_crqb_pack_cmd(cw++, tf->lbah, ATA_REG_LBAH, 0);
1022 mv_crqb_pack_cmd(cw++, tf->device, ATA_REG_DEVICE, 0);
1023 mv_crqb_pack_cmd(cw++, tf->command, ATA_REG_CMD, 1); /* last */
1024
1025 if (!(qc->flags & ATA_QCFLAG_DMAMAP)) {
1026 return;
1027 }
1028 mv_fill_sg(qc);
1029 }
1030
1031 /**
1032 * mv_qc_issue - Initiate a command to the host
1033 * @qc: queued command to start
1034 *
1035 * This routine simply redirects to the general purpose routine
1036 * if command is not DMA. Else, it sanity checks our local
1037 * caches of the request producer/consumer indices then enables
1038 * DMA and bumps the request producer index.
1039 *
1040 * LOCKING:
1041 * Inherited from caller.
1042 */
1043 static int mv_qc_issue(struct ata_queued_cmd *qc)
1044 {
1045 void __iomem *port_mmio = mv_ap_base(qc->ap);
1046 struct mv_port_priv *pp = qc->ap->private_data;
1047 u32 in_ptr;
1048
1049 if (ATA_PROT_DMA != qc->tf.protocol) {
1050 /* We're about to send a non-EDMA capable command to the
1051 * port. Turn off EDMA so there won't be problems accessing
1052 * shadow block, etc registers.
1053 */
1054 mv_stop_dma(qc->ap);
1055 return ata_qc_issue_prot(qc);
1056 }
1057
1058 in_ptr = readl(port_mmio + EDMA_REQ_Q_IN_PTR_OFS);
1059
1060 /* the req producer index should be the same as we remember it */
1061 assert(((in_ptr >> EDMA_REQ_Q_PTR_SHIFT) & MV_MAX_Q_DEPTH_MASK) ==
1062 pp->req_producer);
1063 /* until we do queuing, the queue should be empty at this point */
1064 assert(((in_ptr >> EDMA_REQ_Q_PTR_SHIFT) & MV_MAX_Q_DEPTH_MASK) ==
1065 ((readl(port_mmio + EDMA_REQ_Q_OUT_PTR_OFS) >>
1066 EDMA_REQ_Q_PTR_SHIFT) & MV_MAX_Q_DEPTH_MASK));
1067
1068 mv_inc_q_index(&pp->req_producer); /* now incr producer index */
1069
1070 mv_start_dma(port_mmio, pp);
1071
1072 /* and write the request in pointer to kick the EDMA to life */
1073 in_ptr &= EDMA_REQ_Q_BASE_LO_MASK;
1074 in_ptr |= pp->req_producer << EDMA_REQ_Q_PTR_SHIFT;
1075 writelfl(in_ptr, port_mmio + EDMA_REQ_Q_IN_PTR_OFS);
1076
1077 return 0;
1078 }
1079
1080 /**
1081 * mv_get_crpb_status - get status from most recently completed cmd
1082 * @ap: ATA channel to manipulate
1083 *
1084 * This routine is for use when the port is in DMA mode, when it
1085 * will be using the CRPB (command response block) method of
1086 * returning command completion information. We assert indices
1087 * are good, grab status, and bump the response consumer index to
1088 * prove that we're up to date.
1089 *
1090 * LOCKING:
1091 * Inherited from caller.
1092 */
1093 static u8 mv_get_crpb_status(struct ata_port *ap)
1094 {
1095 void __iomem *port_mmio = mv_ap_base(ap);
1096 struct mv_port_priv *pp = ap->private_data;
1097 u32 out_ptr;
1098
1099 out_ptr = readl(port_mmio + EDMA_RSP_Q_OUT_PTR_OFS);
1100
1101 /* the response consumer index should be the same as we remember it */
1102 assert(((out_ptr >> EDMA_RSP_Q_PTR_SHIFT) & MV_MAX_Q_DEPTH_MASK) ==
1103 pp->rsp_consumer);
1104
1105 /* increment our consumer index... */
1106 pp->rsp_consumer = mv_inc_q_index(&pp->rsp_consumer);
1107
1108 /* and, until we do NCQ, there should only be 1 CRPB waiting */
1109 assert(((readl(port_mmio + EDMA_RSP_Q_IN_PTR_OFS) >>
1110 EDMA_RSP_Q_PTR_SHIFT) & MV_MAX_Q_DEPTH_MASK) ==
1111 pp->rsp_consumer);
1112
1113 /* write out our inc'd consumer index so EDMA knows we're caught up */
1114 out_ptr &= EDMA_RSP_Q_BASE_LO_MASK;
1115 out_ptr |= pp->rsp_consumer << EDMA_RSP_Q_PTR_SHIFT;
1116 writelfl(out_ptr, port_mmio + EDMA_RSP_Q_OUT_PTR_OFS);
1117
1118 /* Return ATA status register for completed CRPB */
1119 return (pp->crpb[pp->rsp_consumer].flags >> CRPB_FLAG_STATUS_SHIFT);
1120 }
1121
1122 /**
1123 * mv_err_intr - Handle error interrupts on the port
1124 * @ap: ATA channel to manipulate
1125 *
1126 * In most cases, just clear the interrupt and move on. However,
1127 * some cases require an eDMA reset, which is done right before
1128 * the COMRESET in mv_phy_reset(). The SERR case requires a
1129 * clear of pending errors in the SATA SERROR register. Finally,
1130 * if the port disabled DMA, update our cached copy to match.
1131 *
1132 * LOCKING:
1133 * Inherited from caller.
1134 */
1135 static void mv_err_intr(struct ata_port *ap)
1136 {
1137 void __iomem *port_mmio = mv_ap_base(ap);
1138 u32 edma_err_cause, serr = 0;
1139
1140 edma_err_cause = readl(port_mmio + EDMA_ERR_IRQ_CAUSE_OFS);
1141
1142 if (EDMA_ERR_SERR & edma_err_cause) {
1143 serr = scr_read(ap, SCR_ERROR);
1144 scr_write_flush(ap, SCR_ERROR, serr);
1145 }
1146 if (EDMA_ERR_SELF_DIS & edma_err_cause) {
1147 struct mv_port_priv *pp = ap->private_data;
1148 pp->pp_flags &= ~MV_PP_FLAG_EDMA_EN;
1149 }
1150 DPRINTK(KERN_ERR "ata%u: port error; EDMA err cause: 0x%08x "
1151 "SERR: 0x%08x\n", ap->id, edma_err_cause, serr);
1152
1153 /* Clear EDMA now that SERR cleanup done */
1154 writelfl(0, port_mmio + EDMA_ERR_IRQ_CAUSE_OFS);
1155
1156 /* check for fatal here and recover if needed */
1157 if (EDMA_ERR_FATAL & edma_err_cause) {
1158 mv_stop_and_reset(ap);
1159 }
1160 }
1161
1162 /**
1163 * mv_host_intr - Handle all interrupts on the given host controller
1164 * @host_set: host specific structure
1165 * @relevant: port error bits relevant to this host controller
1166 * @hc: which host controller we're to look at
1167 *
1168 * Read then write clear the HC interrupt status then walk each
1169 * port connected to the HC and see if it needs servicing. Port
1170 * success ints are reported in the HC interrupt status reg, the
1171 * port error ints are reported in the higher level main
1172 * interrupt status register and thus are passed in via the
1173 * 'relevant' argument.
1174 *
1175 * LOCKING:
1176 * Inherited from caller.
1177 */
1178 static void mv_host_intr(struct ata_host_set *host_set, u32 relevant,
1179 unsigned int hc)
1180 {
1181 void __iomem *mmio = host_set->mmio_base;
1182 void __iomem *hc_mmio = mv_hc_base(mmio, hc);
1183 struct ata_port *ap;
1184 struct ata_queued_cmd *qc;
1185 u32 hc_irq_cause;
1186 int shift, port, port0, hard_port, handled;
1187 unsigned int err_mask;
1188 u8 ata_status = 0;
1189
1190 if (hc == 0) {
1191 port0 = 0;
1192 } else {
1193 port0 = MV_PORTS_PER_HC;
1194 }
1195
1196 /* we'll need the HC success int register in most cases */
1197 hc_irq_cause = readl(hc_mmio + HC_IRQ_CAUSE_OFS);
1198 if (hc_irq_cause) {
1199 writelfl(~hc_irq_cause, hc_mmio + HC_IRQ_CAUSE_OFS);
1200 }
1201
1202 VPRINTK("ENTER, hc%u relevant=0x%08x HC IRQ cause=0x%08x\n",
1203 hc,relevant,hc_irq_cause);
1204
1205 for (port = port0; port < port0 + MV_PORTS_PER_HC; port++) {
1206 ap = host_set->ports[port];
1207 hard_port = port & MV_PORT_MASK; /* range 0-3 */
1208 handled = 0; /* ensure ata_status is set if handled++ */
1209
1210 if ((CRPB_DMA_DONE << hard_port) & hc_irq_cause) {
1211 /* new CRPB on the queue; just one at a time until NCQ
1212 */
1213 ata_status = mv_get_crpb_status(ap);
1214 handled++;
1215 } else if ((DEV_IRQ << hard_port) & hc_irq_cause) {
1216 /* received ATA IRQ; read the status reg to clear INTRQ
1217 */
1218 ata_status = readb((void __iomem *)
1219 ap->ioaddr.status_addr);
1220 handled++;
1221 }
1222
1223 if (ap &&
1224 (ap->flags & (ATA_FLAG_PORT_DISABLED | ATA_FLAG_NOINTR)))
1225 continue;
1226
1227 err_mask = ac_err_mask(ata_status);
1228
1229 shift = port << 1; /* (port * 2) */
1230 if (port >= MV_PORTS_PER_HC) {
1231 shift++; /* skip bit 8 in the HC Main IRQ reg */
1232 }
1233 if ((PORT0_ERR << shift) & relevant) {
1234 mv_err_intr(ap);
1235 err_mask |= AC_ERR_OTHER;
1236 handled++;
1237 }
1238
1239 if (handled && ap) {
1240 qc = ata_qc_from_tag(ap, ap->active_tag);
1241 if (NULL != qc) {
1242 VPRINTK("port %u IRQ found for qc, "
1243 "ata_status 0x%x\n", port,ata_status);
1244 /* mark qc status appropriately */
1245 if (!(qc->tf.ctl & ATA_NIEN)) {
1246 qc->err_mask |= err_mask;
1247 ata_qc_complete(qc);
1248 }
1249 }
1250 }
1251 }
1252 VPRINTK("EXIT\n");
1253 }
1254
1255 /**
1256 * mv_interrupt -
1257 * @irq: unused
1258 * @dev_instance: private data; in this case the host structure
1259 * @regs: unused
1260 *
1261 * Read the read only register to determine if any host
1262 * controllers have pending interrupts. If so, call lower level
1263 * routine to handle. Also check for PCI errors which are only
1264 * reported here.
1265 *
1266 * LOCKING:
1267 * This routine holds the host_set lock while processing pending
1268 * interrupts.
1269 */
1270 static irqreturn_t mv_interrupt(int irq, void *dev_instance,
1271 struct pt_regs *regs)
1272 {
1273 struct ata_host_set *host_set = dev_instance;
1274 unsigned int hc, handled = 0, n_hcs;
1275 void __iomem *mmio = host_set->mmio_base;
1276 u32 irq_stat;
1277
1278 irq_stat = readl(mmio + HC_MAIN_IRQ_CAUSE_OFS);
1279
1280 /* check the cases where we either have nothing pending or have read
1281 * a bogus register value which can indicate HW removal or PCI fault
1282 */
1283 if (!irq_stat || (0xffffffffU == irq_stat)) {
1284 return IRQ_NONE;
1285 }
1286
1287 n_hcs = mv_get_hc_count(host_set->ports[0]->flags);
1288 spin_lock(&host_set->lock);
1289
1290 for (hc = 0; hc < n_hcs; hc++) {
1291 u32 relevant = irq_stat & (HC0_IRQ_PEND << (hc * HC_SHIFT));
1292 if (relevant) {
1293 mv_host_intr(host_set, relevant, hc);
1294 handled++;
1295 }
1296 }
1297 if (PCI_ERR & irq_stat) {
1298 printk(KERN_ERR DRV_NAME ": PCI ERROR; PCI IRQ cause=0x%08x\n",
1299 readl(mmio + PCI_IRQ_CAUSE_OFS));
1300
1301 DPRINTK("All regs @ PCI error\n");
1302 mv_dump_all_regs(mmio, -1, to_pci_dev(host_set->dev));
1303
1304 writelfl(0, mmio + PCI_IRQ_CAUSE_OFS);
1305 handled++;
1306 }
1307 spin_unlock(&host_set->lock);
1308
1309 return IRQ_RETVAL(handled);
1310 }
1311
1312 static void __iomem *mv5_phy_base(void __iomem *mmio, unsigned int port)
1313 {
1314 void __iomem *hc_mmio = mv_hc_base_from_port(mmio, port);
1315 unsigned long ofs = (mv_hardport_from_port(port) + 1) * 0x100UL;
1316
1317 return hc_mmio + ofs;
1318 }
1319
1320 static unsigned int mv5_scr_offset(unsigned int sc_reg_in)
1321 {
1322 unsigned int ofs;
1323
1324 switch (sc_reg_in) {
1325 case SCR_STATUS:
1326 case SCR_ERROR:
1327 case SCR_CONTROL:
1328 ofs = sc_reg_in * sizeof(u32);
1329 break;
1330 default:
1331 ofs = 0xffffffffU;
1332 break;
1333 }
1334 return ofs;
1335 }
1336
1337 static u32 mv5_scr_read(struct ata_port *ap, unsigned int sc_reg_in)
1338 {
1339 void __iomem *mmio = mv5_phy_base(ap->host_set->mmio_base, ap->port_no);
1340 unsigned int ofs = mv5_scr_offset(sc_reg_in);
1341
1342 if (ofs != 0xffffffffU)
1343 return readl(mmio + ofs);
1344 else
1345 return (u32) ofs;
1346 }
1347
1348 static void mv5_scr_write(struct ata_port *ap, unsigned int sc_reg_in, u32 val)
1349 {
1350 void __iomem *mmio = mv5_phy_base(ap->host_set->mmio_base, ap->port_no);
1351 unsigned int ofs = mv5_scr_offset(sc_reg_in);
1352
1353 if (ofs != 0xffffffffU)
1354 writelfl(val, mmio + ofs);
1355 }
1356
1357 static void mv5_reset_bus(struct pci_dev *pdev, void __iomem *mmio)
1358 {
1359 u8 rev_id;
1360 int early_5080;
1361
1362 pci_read_config_byte(pdev, PCI_REVISION_ID, &rev_id);
1363
1364 early_5080 = (pdev->device == 0x5080) && (rev_id == 0);
1365
1366 if (!early_5080) {
1367 u32 tmp = readl(mmio + MV_PCI_EXP_ROM_BAR_CTL);
1368 tmp |= (1 << 0);
1369 writel(tmp, mmio + MV_PCI_EXP_ROM_BAR_CTL);
1370 }
1371
1372 mv_reset_pci_bus(pdev, mmio);
1373 }
1374
1375 static void mv5_reset_flash(struct mv_host_priv *hpriv, void __iomem *mmio)
1376 {
1377 writel(0x0fcfffff, mmio + MV_FLASH_CTL);
1378 }
1379
1380 static void mv5_read_preamp(struct mv_host_priv *hpriv, int idx,
1381 void __iomem *mmio)
1382 {
1383 void __iomem *phy_mmio = mv5_phy_base(mmio, idx);
1384 u32 tmp;
1385
1386 tmp = readl(phy_mmio + MV5_PHY_MODE);
1387
1388 hpriv->signal[idx].pre = tmp & 0x1800; /* bits 12:11 */
1389 hpriv->signal[idx].amps = tmp & 0xe0; /* bits 7:5 */
1390 }
1391
1392 static void mv5_enable_leds(struct mv_host_priv *hpriv, void __iomem *mmio)
1393 {
1394 u32 tmp;
1395
1396 writel(0, mmio + MV_GPIO_PORT_CTL);
1397
1398 /* FIXME: handle MV_HP_ERRATA_50XXB2 errata */
1399
1400 tmp = readl(mmio + MV_PCI_EXP_ROM_BAR_CTL);
1401 tmp |= ~(1 << 0);
1402 writel(tmp, mmio + MV_PCI_EXP_ROM_BAR_CTL);
1403 }
1404
1405 static void mv5_phy_errata(struct mv_host_priv *hpriv, void __iomem *mmio,
1406 unsigned int port)
1407 {
1408 void __iomem *phy_mmio = mv5_phy_base(mmio, port);
1409 const u32 mask = (1<<12) | (1<<11) | (1<<7) | (1<<6) | (1<<5);
1410 u32 tmp;
1411 int fix_apm_sq = (hpriv->hp_flags & MV_HP_ERRATA_50XXB0);
1412
1413 if (fix_apm_sq) {
1414 tmp = readl(phy_mmio + MV5_LT_MODE);
1415 tmp |= (1 << 19);
1416 writel(tmp, phy_mmio + MV5_LT_MODE);
1417
1418 tmp = readl(phy_mmio + MV5_PHY_CTL);
1419 tmp &= ~0x3;
1420 tmp |= 0x1;
1421 writel(tmp, phy_mmio + MV5_PHY_CTL);
1422 }
1423
1424 tmp = readl(phy_mmio + MV5_PHY_MODE);
1425 tmp &= ~mask;
1426 tmp |= hpriv->signal[port].pre;
1427 tmp |= hpriv->signal[port].amps;
1428 writel(tmp, phy_mmio + MV5_PHY_MODE);
1429 }
1430
1431
1432 #undef ZERO
1433 #define ZERO(reg) writel(0, port_mmio + (reg))
1434 static void mv5_reset_hc_port(struct mv_host_priv *hpriv, void __iomem *mmio,
1435 unsigned int port)
1436 {
1437 void __iomem *port_mmio = mv_port_base(mmio, port);
1438
1439 writelfl(EDMA_DS, port_mmio + EDMA_CMD_OFS);
1440
1441 mv_channel_reset(hpriv, mmio, port);
1442
1443 ZERO(0x028); /* command */
1444 writel(0x11f, port_mmio + EDMA_CFG_OFS);
1445 ZERO(0x004); /* timer */
1446 ZERO(0x008); /* irq err cause */
1447 ZERO(0x00c); /* irq err mask */
1448 ZERO(0x010); /* rq bah */
1449 ZERO(0x014); /* rq inp */
1450 ZERO(0x018); /* rq outp */
1451 ZERO(0x01c); /* respq bah */
1452 ZERO(0x024); /* respq outp */
1453 ZERO(0x020); /* respq inp */
1454 ZERO(0x02c); /* test control */
1455 writel(0xbc, port_mmio + EDMA_IORDY_TMOUT);
1456 }
1457 #undef ZERO
1458
1459 #define ZERO(reg) writel(0, hc_mmio + (reg))
1460 static void mv5_reset_one_hc(struct mv_host_priv *hpriv, void __iomem *mmio,
1461 unsigned int hc)
1462 {
1463 void __iomem *hc_mmio = mv_hc_base(mmio, hc);
1464 u32 tmp;
1465
1466 ZERO(0x00c);
1467 ZERO(0x010);
1468 ZERO(0x014);
1469 ZERO(0x018);
1470
1471 tmp = readl(hc_mmio + 0x20);
1472 tmp &= 0x1c1c1c1c;
1473 tmp |= 0x03030303;
1474 writel(tmp, hc_mmio + 0x20);
1475 }
1476 #undef ZERO
1477
1478 static int mv5_reset_hc(struct mv_host_priv *hpriv, void __iomem *mmio,
1479 unsigned int n_hc)
1480 {
1481 unsigned int hc, port;
1482
1483 for (hc = 0; hc < n_hc; hc++) {
1484 for (port = 0; port < MV_PORTS_PER_HC; port++)
1485 mv5_reset_hc_port(hpriv, mmio,
1486 (hc * MV_PORTS_PER_HC) + port);
1487
1488 mv5_reset_one_hc(hpriv, mmio, hc);
1489 }
1490
1491 return 0;
1492 }
1493
1494 #undef ZERO
1495 #define ZERO(reg) writel(0, mmio + (reg))
1496 static void mv_reset_pci_bus(struct pci_dev *pdev, void __iomem *mmio)
1497 {
1498 u32 tmp;
1499
1500 tmp = readl(mmio + MV_PCI_MODE);
1501 tmp &= 0xff00ffff;
1502 writel(tmp, mmio + MV_PCI_MODE);
1503
1504 ZERO(MV_PCI_DISC_TIMER);
1505 ZERO(MV_PCI_MSI_TRIGGER);
1506 writel(0x000100ff, mmio + MV_PCI_XBAR_TMOUT);
1507 ZERO(HC_MAIN_IRQ_MASK_OFS);
1508 ZERO(MV_PCI_SERR_MASK);
1509 ZERO(PCI_IRQ_CAUSE_OFS);
1510 ZERO(PCI_IRQ_MASK_OFS);
1511 ZERO(MV_PCI_ERR_LOW_ADDRESS);
1512 ZERO(MV_PCI_ERR_HIGH_ADDRESS);
1513 ZERO(MV_PCI_ERR_ATTRIBUTE);
1514 ZERO(MV_PCI_ERR_COMMAND);
1515 }
1516 #undef ZERO
1517
1518 static void mv6_reset_flash(struct mv_host_priv *hpriv, void __iomem *mmio)
1519 {
1520 u32 tmp;
1521
1522 mv5_reset_flash(hpriv, mmio);
1523
1524 tmp = readl(mmio + MV_GPIO_PORT_CTL);
1525 tmp &= 0x3;
1526 tmp |= (1 << 5) | (1 << 6);
1527 writel(tmp, mmio + MV_GPIO_PORT_CTL);
1528 }
1529
1530 /**
1531 * mv6_reset_hc - Perform the 6xxx global soft reset
1532 * @mmio: base address of the HBA
1533 *
1534 * This routine only applies to 6xxx parts.
1535 *
1536 * LOCKING:
1537 * Inherited from caller.
1538 */
1539 static int mv6_reset_hc(struct mv_host_priv *hpriv, void __iomem *mmio,
1540 unsigned int n_hc)
1541 {
1542 void __iomem *reg = mmio + PCI_MAIN_CMD_STS_OFS;
1543 int i, rc = 0;
1544 u32 t;
1545
1546 /* Following procedure defined in PCI "main command and status
1547 * register" table.
1548 */
1549 t = readl(reg);
1550 writel(t | STOP_PCI_MASTER, reg);
1551
1552 for (i = 0; i < 1000; i++) {
1553 udelay(1);
1554 t = readl(reg);
1555 if (PCI_MASTER_EMPTY & t) {
1556 break;
1557 }
1558 }
1559 if (!(PCI_MASTER_EMPTY & t)) {
1560 printk(KERN_ERR DRV_NAME ": PCI master won't flush\n");
1561 rc = 1;
1562 goto done;
1563 }
1564
1565 /* set reset */
1566 i = 5;
1567 do {
1568 writel(t | GLOB_SFT_RST, reg);
1569 t = readl(reg);
1570 udelay(1);
1571 } while (!(GLOB_SFT_RST & t) && (i-- > 0));
1572
1573 if (!(GLOB_SFT_RST & t)) {
1574 printk(KERN_ERR DRV_NAME ": can't set global reset\n");
1575 rc = 1;
1576 goto done;
1577 }
1578
1579 /* clear reset and *reenable the PCI master* (not mentioned in spec) */
1580 i = 5;
1581 do {
1582 writel(t & ~(GLOB_SFT_RST | STOP_PCI_MASTER), reg);
1583 t = readl(reg);
1584 udelay(1);
1585 } while ((GLOB_SFT_RST & t) && (i-- > 0));
1586
1587 if (GLOB_SFT_RST & t) {
1588 printk(KERN_ERR DRV_NAME ": can't clear global reset\n");
1589 rc = 1;
1590 }
1591 done:
1592 return rc;
1593 }
1594
1595 static void mv6_read_preamp(struct mv_host_priv *hpriv, int idx,
1596 void __iomem *mmio)
1597 {
1598 void __iomem *port_mmio;
1599 u32 tmp;
1600
1601 tmp = readl(mmio + MV_RESET_CFG);
1602 if ((tmp & (1 << 0)) == 0) {
1603 hpriv->signal[idx].amps = 0x7 << 8;
1604 hpriv->signal[idx].pre = 0x1 << 5;
1605 return;
1606 }
1607
1608 port_mmio = mv_port_base(mmio, idx);
1609 tmp = readl(port_mmio + PHY_MODE2);
1610
1611 hpriv->signal[idx].amps = tmp & 0x700; /* bits 10:8 */
1612 hpriv->signal[idx].pre = tmp & 0xe0; /* bits 7:5 */
1613 }
1614
1615 static void mv6_enable_leds(struct mv_host_priv *hpriv, void __iomem *mmio)
1616 {
1617 writel(0x00000060, mmio + MV_GPIO_PORT_CTL);
1618 }
1619
1620 static void mv6_phy_errata(struct mv_host_priv *hpriv, void __iomem *mmio,
1621 unsigned int port)
1622 {
1623 void __iomem *port_mmio = mv_port_base(mmio, port);
1624
1625 u32 hp_flags = hpriv->hp_flags;
1626 int fix_phy_mode2 =
1627 hp_flags & (MV_HP_ERRATA_60X1B2 | MV_HP_ERRATA_60X1C0);
1628 int fix_phy_mode4 =
1629 hp_flags & (MV_HP_ERRATA_60X1B2 | MV_HP_ERRATA_60X1C0);
1630 u32 m2, tmp;
1631
1632 if (fix_phy_mode2) {
1633 m2 = readl(port_mmio + PHY_MODE2);
1634 m2 &= ~(1 << 16);
1635 m2 |= (1 << 31);
1636 writel(m2, port_mmio + PHY_MODE2);
1637
1638 udelay(200);
1639
1640 m2 = readl(port_mmio + PHY_MODE2);
1641 m2 &= ~((1 << 16) | (1 << 31));
1642 writel(m2, port_mmio + PHY_MODE2);
1643
1644 udelay(200);
1645 }
1646
1647 /* who knows what this magic does */
1648 tmp = readl(port_mmio + PHY_MODE3);
1649 tmp &= ~0x7F800000;
1650 tmp |= 0x2A800000;
1651 writel(tmp, port_mmio + PHY_MODE3);
1652
1653 if (fix_phy_mode4) {
1654 u32 m4;
1655
1656 m4 = readl(port_mmio + PHY_MODE4);
1657
1658 if (hp_flags & MV_HP_ERRATA_60X1B2)
1659 tmp = readl(port_mmio + 0x310);
1660
1661 m4 = (m4 & ~(1 << 1)) | (1 << 0);
1662
1663 writel(m4, port_mmio + PHY_MODE4);
1664
1665 if (hp_flags & MV_HP_ERRATA_60X1B2)
1666 writel(tmp, port_mmio + 0x310);
1667 }
1668
1669 /* Revert values of pre-emphasis and signal amps to the saved ones */
1670 m2 = readl(port_mmio + PHY_MODE2);
1671
1672 m2 &= ~MV_M2_PREAMP_MASK;
1673 m2 |= hpriv->signal[port].amps;
1674 m2 |= hpriv->signal[port].pre;
1675 m2 &= ~(1 << 16);
1676
1677 writel(m2, port_mmio + PHY_MODE2);
1678 }
1679
1680 static void mv_channel_reset(struct mv_host_priv *hpriv, void __iomem *mmio,
1681 unsigned int port_no)
1682 {
1683 void __iomem *port_mmio = mv_port_base(mmio, port_no);
1684
1685 writelfl(ATA_RST, port_mmio + EDMA_CMD_OFS);
1686
1687 if (IS_60XX(hpriv)) {
1688 u32 ifctl = readl(port_mmio + SATA_INTERFACE_CTL);
1689 ifctl |= (1 << 12) | (1 << 7);
1690 writelfl(ifctl, port_mmio + SATA_INTERFACE_CTL);
1691 }
1692
1693 udelay(25); /* allow reset propagation */
1694
1695 /* Spec never mentions clearing the bit. Marvell's driver does
1696 * clear the bit, however.
1697 */
1698 writelfl(0, port_mmio + EDMA_CMD_OFS);
1699
1700 hpriv->ops->phy_errata(hpriv, mmio, port_no);
1701
1702 if (IS_50XX(hpriv))
1703 mdelay(1);
1704 }
1705
1706 static void mv_stop_and_reset(struct ata_port *ap)
1707 {
1708 struct mv_host_priv *hpriv = ap->host_set->private_data;
1709 void __iomem *mmio = ap->host_set->mmio_base;
1710
1711 mv_stop_dma(ap);
1712
1713 mv_channel_reset(hpriv, mmio, ap->port_no);
1714
1715 __mv_phy_reset(ap, 0);
1716 }
1717
1718 static inline void __msleep(unsigned int msec, int can_sleep)
1719 {
1720 if (can_sleep)
1721 msleep(msec);
1722 else
1723 mdelay(msec);
1724 }
1725
1726 /**
1727 * __mv_phy_reset - Perform eDMA reset followed by COMRESET
1728 * @ap: ATA channel to manipulate
1729 *
1730 * Part of this is taken from __sata_phy_reset and modified to
1731 * not sleep since this routine gets called from interrupt level.
1732 *
1733 * LOCKING:
1734 * Inherited from caller. This is coded to safe to call at
1735 * interrupt level, i.e. it does not sleep.
1736 */
1737 static void __mv_phy_reset(struct ata_port *ap, int can_sleep)
1738 {
1739 struct mv_port_priv *pp = ap->private_data;
1740 struct mv_host_priv *hpriv = ap->host_set->private_data;
1741 void __iomem *port_mmio = mv_ap_base(ap);
1742 struct ata_taskfile tf;
1743 struct ata_device *dev = &ap->device[0];
1744 unsigned long timeout;
1745 int retry = 5;
1746 u32 sstatus;
1747
1748 VPRINTK("ENTER, port %u, mmio 0x%p\n", ap->port_no, port_mmio);
1749
1750 DPRINTK("S-regs after ATA_RST: SStat 0x%08x SErr 0x%08x "
1751 "SCtrl 0x%08x\n", mv_scr_read(ap, SCR_STATUS),
1752 mv_scr_read(ap, SCR_ERROR), mv_scr_read(ap, SCR_CONTROL));
1753
1754 /* Issue COMRESET via SControl */
1755 comreset_retry:
1756 scr_write_flush(ap, SCR_CONTROL, 0x301);
1757 __msleep(1, can_sleep);
1758
1759 scr_write_flush(ap, SCR_CONTROL, 0x300);
1760 __msleep(20, can_sleep);
1761
1762 timeout = jiffies + msecs_to_jiffies(200);
1763 do {
1764 sstatus = scr_read(ap, SCR_STATUS) & 0x3;
1765 if ((sstatus == 3) || (sstatus == 0))
1766 break;
1767
1768 __msleep(1, can_sleep);
1769 } while (time_before(jiffies, timeout));
1770
1771 /* work around errata */
1772 if (IS_60XX(hpriv) &&
1773 (sstatus != 0x0) && (sstatus != 0x113) && (sstatus != 0x123) &&
1774 (retry-- > 0))
1775 goto comreset_retry;
1776
1777 DPRINTK("S-regs after PHY wake: SStat 0x%08x SErr 0x%08x "
1778 "SCtrl 0x%08x\n", mv_scr_read(ap, SCR_STATUS),
1779 mv_scr_read(ap, SCR_ERROR), mv_scr_read(ap, SCR_CONTROL));
1780
1781 if (sata_dev_present(ap)) {
1782 ata_port_probe(ap);
1783 } else {
1784 printk(KERN_INFO "ata%u: no device found (phy stat %08x)\n",
1785 ap->id, scr_read(ap, SCR_STATUS));
1786 ata_port_disable(ap);
1787 return;
1788 }
1789 ap->cbl = ATA_CBL_SATA;
1790
1791 /* even after SStatus reflects that device is ready,
1792 * it seems to take a while for link to be fully
1793 * established (and thus Status no longer 0x80/0x7F),
1794 * so we poll a bit for that, here.
1795 */
1796 retry = 20;
1797 while (1) {
1798 u8 drv_stat = ata_check_status(ap);
1799 if ((drv_stat != 0x80) && (drv_stat != 0x7f))
1800 break;
1801 __msleep(500, can_sleep);
1802 if (retry-- <= 0)
1803 break;
1804 }
1805
1806 tf.lbah = readb((void __iomem *) ap->ioaddr.lbah_addr);
1807 tf.lbam = readb((void __iomem *) ap->ioaddr.lbam_addr);
1808 tf.lbal = readb((void __iomem *) ap->ioaddr.lbal_addr);
1809 tf.nsect = readb((void __iomem *) ap->ioaddr.nsect_addr);
1810
1811 dev->class = ata_dev_classify(&tf);
1812 if (!ata_dev_present(dev)) {
1813 VPRINTK("Port disabled post-sig: No device present.\n");
1814 ata_port_disable(ap);
1815 }
1816
1817 writelfl(0, port_mmio + EDMA_ERR_IRQ_CAUSE_OFS);
1818
1819 pp->pp_flags &= ~MV_PP_FLAG_EDMA_EN;
1820
1821 VPRINTK("EXIT\n");
1822 }
1823
1824 static void mv_phy_reset(struct ata_port *ap)
1825 {
1826 __mv_phy_reset(ap, 1);
1827 }
1828
1829 /**
1830 * mv_eng_timeout - Routine called by libata when SCSI times out I/O
1831 * @ap: ATA channel to manipulate
1832 *
1833 * Intent is to clear all pending error conditions, reset the
1834 * chip/bus, fail the command, and move on.
1835 *
1836 * LOCKING:
1837 * This routine holds the host_set lock while failing the command.
1838 */
1839 static void mv_eng_timeout(struct ata_port *ap)
1840 {
1841 struct ata_queued_cmd *qc;
1842 unsigned long flags;
1843
1844 printk(KERN_ERR "ata%u: Entering mv_eng_timeout\n",ap->id);
1845 DPRINTK("All regs @ start of eng_timeout\n");
1846 mv_dump_all_regs(ap->host_set->mmio_base, ap->port_no,
1847 to_pci_dev(ap->host_set->dev));
1848
1849 qc = ata_qc_from_tag(ap, ap->active_tag);
1850 printk(KERN_ERR "mmio_base %p ap %p qc %p scsi_cmnd %p &cmnd %p\n",
1851 ap->host_set->mmio_base, ap, qc, qc->scsicmd,
1852 &qc->scsicmd->cmnd);
1853
1854 mv_err_intr(ap);
1855 mv_stop_and_reset(ap);
1856
1857 if (!qc) {
1858 printk(KERN_ERR "ata%u: BUG: timeout without command\n",
1859 ap->id);
1860 } else {
1861 /* hack alert! We cannot use the supplied completion
1862 * function from inside the ->eh_strategy_handler() thread.
1863 * libata is the only user of ->eh_strategy_handler() in
1864 * any kernel, so the default scsi_done() assumes it is
1865 * not being called from the SCSI EH.
1866 */
1867 spin_lock_irqsave(&ap->host_set->lock, flags);
1868 qc->scsidone = scsi_finish_command;
1869 qc->err_mask |= AC_ERR_OTHER;
1870 ata_qc_complete(qc);
1871 spin_unlock_irqrestore(&ap->host_set->lock, flags);
1872 }
1873 }
1874
1875 /**
1876 * mv_port_init - Perform some early initialization on a single port.
1877 * @port: libata data structure storing shadow register addresses
1878 * @port_mmio: base address of the port
1879 *
1880 * Initialize shadow register mmio addresses, clear outstanding
1881 * interrupts on the port, and unmask interrupts for the future
1882 * start of the port.
1883 *
1884 * LOCKING:
1885 * Inherited from caller.
1886 */
1887 static void mv_port_init(struct ata_ioports *port, void __iomem *port_mmio)
1888 {
1889 unsigned long shd_base = (unsigned long) port_mmio + SHD_BLK_OFS;
1890 unsigned serr_ofs;
1891
1892 /* PIO related setup
1893 */
1894 port->data_addr = shd_base + (sizeof(u32) * ATA_REG_DATA);
1895 port->error_addr =
1896 port->feature_addr = shd_base + (sizeof(u32) * ATA_REG_ERR);
1897 port->nsect_addr = shd_base + (sizeof(u32) * ATA_REG_NSECT);
1898 port->lbal_addr = shd_base + (sizeof(u32) * ATA_REG_LBAL);
1899 port->lbam_addr = shd_base + (sizeof(u32) * ATA_REG_LBAM);
1900 port->lbah_addr = shd_base + (sizeof(u32) * ATA_REG_LBAH);
1901 port->device_addr = shd_base + (sizeof(u32) * ATA_REG_DEVICE);
1902 port->status_addr =
1903 port->command_addr = shd_base + (sizeof(u32) * ATA_REG_STATUS);
1904 /* special case: control/altstatus doesn't have ATA_REG_ address */
1905 port->altstatus_addr = port->ctl_addr = shd_base + SHD_CTL_AST_OFS;
1906
1907 /* unused: */
1908 port->cmd_addr = port->bmdma_addr = port->scr_addr = 0;
1909
1910 /* Clear any currently outstanding port interrupt conditions */
1911 serr_ofs = mv_scr_offset(SCR_ERROR);
1912 writelfl(readl(port_mmio + serr_ofs), port_mmio + serr_ofs);
1913 writelfl(0, port_mmio + EDMA_ERR_IRQ_CAUSE_OFS);
1914
1915 /* unmask all EDMA error interrupts */
1916 writelfl(~0, port_mmio + EDMA_ERR_IRQ_MASK_OFS);
1917
1918 VPRINTK("EDMA cfg=0x%08x EDMA IRQ err cause/mask=0x%08x/0x%08x\n",
1919 readl(port_mmio + EDMA_CFG_OFS),
1920 readl(port_mmio + EDMA_ERR_IRQ_CAUSE_OFS),
1921 readl(port_mmio + EDMA_ERR_IRQ_MASK_OFS));
1922 }
1923
1924 static int mv_chip_id(struct pci_dev *pdev, struct mv_host_priv *hpriv,
1925 unsigned int board_idx)
1926 {
1927 u8 rev_id;
1928 u32 hp_flags = hpriv->hp_flags;
1929
1930 pci_read_config_byte(pdev, PCI_REVISION_ID, &rev_id);
1931
1932 switch(board_idx) {
1933 case chip_5080:
1934 hpriv->ops = &mv5xxx_ops;
1935 hp_flags |= MV_HP_50XX;
1936
1937 switch (rev_id) {
1938 case 0x1:
1939 hp_flags |= MV_HP_ERRATA_50XXB0;
1940 break;
1941 case 0x3:
1942 hp_flags |= MV_HP_ERRATA_50XXB2;
1943 break;
1944 default:
1945 dev_printk(KERN_WARNING, &pdev->dev,
1946 "Applying 50XXB2 workarounds to unknown rev\n");
1947 hp_flags |= MV_HP_ERRATA_50XXB2;
1948 break;
1949 }
1950 break;
1951
1952 case chip_504x:
1953 case chip_508x:
1954 hpriv->ops = &mv5xxx_ops;
1955 hp_flags |= MV_HP_50XX;
1956
1957 switch (rev_id) {
1958 case 0x0:
1959 hp_flags |= MV_HP_ERRATA_50XXB0;
1960 break;
1961 case 0x3:
1962 hp_flags |= MV_HP_ERRATA_50XXB2;
1963 break;
1964 default:
1965 dev_printk(KERN_WARNING, &pdev->dev,
1966 "Applying B2 workarounds to unknown rev\n");
1967 hp_flags |= MV_HP_ERRATA_50XXB2;
1968 break;
1969 }
1970 break;
1971
1972 case chip_604x:
1973 case chip_608x:
1974 hpriv->ops = &mv6xxx_ops;
1975
1976 switch (rev_id) {
1977 case 0x7:
1978 hp_flags |= MV_HP_ERRATA_60X1B2;
1979 break;
1980 case 0x9:
1981 hp_flags |= MV_HP_ERRATA_60X1C0;
1982 break;
1983 default:
1984 dev_printk(KERN_WARNING, &pdev->dev,
1985 "Applying B2 workarounds to unknown rev\n");
1986 hp_flags |= MV_HP_ERRATA_60X1B2;
1987 break;
1988 }
1989 break;
1990
1991 default:
1992 printk(KERN_ERR DRV_NAME ": BUG: invalid board index %u\n", board_idx);
1993 return 1;
1994 }
1995
1996 hpriv->hp_flags = hp_flags;
1997
1998 return 0;
1999 }
2000
2001 /**
2002 * mv_init_host - Perform some early initialization of the host.
2003 * @pdev: host PCI device
2004 * @probe_ent: early data struct representing the host
2005 *
2006 * If possible, do an early global reset of the host. Then do
2007 * our port init and clear/unmask all/relevant host interrupts.
2008 *
2009 * LOCKING:
2010 * Inherited from caller.
2011 */
2012 static int mv_init_host(struct pci_dev *pdev, struct ata_probe_ent *probe_ent,
2013 unsigned int board_idx)
2014 {
2015 int rc = 0, n_hc, port, hc;
2016 void __iomem *mmio = probe_ent->mmio_base;
2017 struct mv_host_priv *hpriv = probe_ent->private_data;
2018
2019 /* global interrupt mask */
2020 writel(0, mmio + HC_MAIN_IRQ_MASK_OFS);
2021
2022 rc = mv_chip_id(pdev, hpriv, board_idx);
2023 if (rc)
2024 goto done;
2025
2026 n_hc = mv_get_hc_count(probe_ent->host_flags);
2027 probe_ent->n_ports = MV_PORTS_PER_HC * n_hc;
2028
2029 for (port = 0; port < probe_ent->n_ports; port++)
2030 hpriv->ops->read_preamp(hpriv, port, mmio);
2031
2032 rc = hpriv->ops->reset_hc(hpriv, mmio, n_hc);
2033 if (rc)
2034 goto done;
2035
2036 hpriv->ops->reset_flash(hpriv, mmio);
2037 hpriv->ops->reset_bus(pdev, mmio);
2038 hpriv->ops->enable_leds(hpriv, mmio);
2039
2040 for (port = 0; port < probe_ent->n_ports; port++) {
2041 if (IS_60XX(hpriv)) {
2042 void __iomem *port_mmio = mv_port_base(mmio, port);
2043
2044 u32 ifctl = readl(port_mmio + SATA_INTERFACE_CTL);
2045 ifctl |= (1 << 12);
2046 writelfl(ifctl, port_mmio + SATA_INTERFACE_CTL);
2047 }
2048
2049 hpriv->ops->phy_errata(hpriv, mmio, port);
2050 }
2051
2052 for (port = 0; port < probe_ent->n_ports; port++) {
2053 void __iomem *port_mmio = mv_port_base(mmio, port);
2054 mv_port_init(&probe_ent->port[port], port_mmio);
2055 }
2056
2057 for (hc = 0; hc < n_hc; hc++) {
2058 void __iomem *hc_mmio = mv_hc_base(mmio, hc);
2059
2060 VPRINTK("HC%i: HC config=0x%08x HC IRQ cause "
2061 "(before clear)=0x%08x\n", hc,
2062 readl(hc_mmio + HC_CFG_OFS),
2063 readl(hc_mmio + HC_IRQ_CAUSE_OFS));
2064
2065 /* Clear any currently outstanding hc interrupt conditions */
2066 writelfl(0, hc_mmio + HC_IRQ_CAUSE_OFS);
2067 }
2068
2069 /* Clear any currently outstanding host interrupt conditions */
2070 writelfl(0, mmio + PCI_IRQ_CAUSE_OFS);
2071
2072 /* and unmask interrupt generation for host regs */
2073 writelfl(PCI_UNMASK_ALL_IRQS, mmio + PCI_IRQ_MASK_OFS);
2074 writelfl(~HC_MAIN_MASKED_IRQS, mmio + HC_MAIN_IRQ_MASK_OFS);
2075
2076 VPRINTK("HC MAIN IRQ cause/mask=0x%08x/0x%08x "
2077 "PCI int cause/mask=0x%08x/0x%08x\n",
2078 readl(mmio + HC_MAIN_IRQ_CAUSE_OFS),
2079 readl(mmio + HC_MAIN_IRQ_MASK_OFS),
2080 readl(mmio + PCI_IRQ_CAUSE_OFS),
2081 readl(mmio + PCI_IRQ_MASK_OFS));
2082
2083 done:
2084 return rc;
2085 }
2086
2087 /**
2088 * mv_print_info - Dump key info to kernel log for perusal.
2089 * @probe_ent: early data struct representing the host
2090 *
2091 * FIXME: complete this.
2092 *
2093 * LOCKING:
2094 * Inherited from caller.
2095 */
2096 static void mv_print_info(struct ata_probe_ent *probe_ent)
2097 {
2098 struct pci_dev *pdev = to_pci_dev(probe_ent->dev);
2099 struct mv_host_priv *hpriv = probe_ent->private_data;
2100 u8 rev_id, scc;
2101 const char *scc_s;
2102
2103 /* Use this to determine the HW stepping of the chip so we know
2104 * what errata to workaround
2105 */
2106 pci_read_config_byte(pdev, PCI_REVISION_ID, &rev_id);
2107
2108 pci_read_config_byte(pdev, PCI_CLASS_DEVICE, &scc);
2109 if (scc == 0)
2110 scc_s = "SCSI";
2111 else if (scc == 0x01)
2112 scc_s = "RAID";
2113 else
2114 scc_s = "unknown";
2115
2116 dev_printk(KERN_INFO, &pdev->dev,
2117 "%u slots %u ports %s mode IRQ via %s\n",
2118 (unsigned)MV_MAX_Q_DEPTH, probe_ent->n_ports,
2119 scc_s, (MV_HP_FLAG_MSI & hpriv->hp_flags) ? "MSI" : "INTx");
2120 }
2121
2122 /**
2123 * mv_init_one - handle a positive probe of a Marvell host
2124 * @pdev: PCI device found
2125 * @ent: PCI device ID entry for the matched host
2126 *
2127 * LOCKING:
2128 * Inherited from caller.
2129 */
2130 static int mv_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
2131 {
2132 static int printed_version = 0;
2133 struct ata_probe_ent *probe_ent = NULL;
2134 struct mv_host_priv *hpriv;
2135 unsigned int board_idx = (unsigned int)ent->driver_data;
2136 void __iomem *mmio_base;
2137 int pci_dev_busy = 0, rc;
2138
2139 if (!printed_version++)
2140 dev_printk(KERN_INFO, &pdev->dev, "version " DRV_VERSION "\n");
2141
2142 rc = pci_enable_device(pdev);
2143 if (rc) {
2144 return rc;
2145 }
2146
2147 rc = pci_request_regions(pdev, DRV_NAME);
2148 if (rc) {
2149 pci_dev_busy = 1;
2150 goto err_out;
2151 }
2152
2153 probe_ent = kmalloc(sizeof(*probe_ent), GFP_KERNEL);
2154 if (probe_ent == NULL) {
2155 rc = -ENOMEM;
2156 goto err_out_regions;
2157 }
2158
2159 memset(probe_ent, 0, sizeof(*probe_ent));
2160 probe_ent->dev = pci_dev_to_dev(pdev);
2161 INIT_LIST_HEAD(&probe_ent->node);
2162
2163 mmio_base = pci_iomap(pdev, MV_PRIMARY_BAR, 0);
2164 if (mmio_base == NULL) {
2165 rc = -ENOMEM;
2166 goto err_out_free_ent;
2167 }
2168
2169 hpriv = kmalloc(sizeof(*hpriv), GFP_KERNEL);
2170 if (!hpriv) {
2171 rc = -ENOMEM;
2172 goto err_out_iounmap;
2173 }
2174 memset(hpriv, 0, sizeof(*hpriv));
2175
2176 probe_ent->sht = mv_port_info[board_idx].sht;
2177 probe_ent->host_flags = mv_port_info[board_idx].host_flags;
2178 probe_ent->pio_mask = mv_port_info[board_idx].pio_mask;
2179 probe_ent->udma_mask = mv_port_info[board_idx].udma_mask;
2180 probe_ent->port_ops = mv_port_info[board_idx].port_ops;
2181
2182 probe_ent->irq = pdev->irq;
2183 probe_ent->irq_flags = SA_SHIRQ;
2184 probe_ent->mmio_base = mmio_base;
2185 probe_ent->private_data = hpriv;
2186
2187 /* initialize adapter */
2188 rc = mv_init_host(pdev, probe_ent, board_idx);
2189 if (rc) {
2190 goto err_out_hpriv;
2191 }
2192
2193 /* Enable interrupts */
2194 if (pci_enable_msi(pdev) == 0) {
2195 hpriv->hp_flags |= MV_HP_FLAG_MSI;
2196 } else {
2197 pci_intx(pdev, 1);
2198 }
2199
2200 mv_dump_pci_cfg(pdev, 0x68);
2201 mv_print_info(probe_ent);
2202
2203 if (ata_device_add(probe_ent) == 0) {
2204 rc = -ENODEV; /* No devices discovered */
2205 goto err_out_dev_add;
2206 }
2207
2208 kfree(probe_ent);
2209 return 0;
2210
2211 err_out_dev_add:
2212 if (MV_HP_FLAG_MSI & hpriv->hp_flags) {
2213 pci_disable_msi(pdev);
2214 } else {
2215 pci_intx(pdev, 0);
2216 }
2217 err_out_hpriv:
2218 kfree(hpriv);
2219 err_out_iounmap:
2220 pci_iounmap(pdev, mmio_base);
2221 err_out_free_ent:
2222 kfree(probe_ent);
2223 err_out_regions:
2224 pci_release_regions(pdev);
2225 err_out:
2226 if (!pci_dev_busy) {
2227 pci_disable_device(pdev);
2228 }
2229
2230 return rc;
2231 }
2232
2233 static int __init mv_init(void)
2234 {
2235 return pci_module_init(&mv_pci_driver);
2236 }
2237
2238 static void __exit mv_exit(void)
2239 {
2240 pci_unregister_driver(&mv_pci_driver);
2241 }
2242
2243 MODULE_AUTHOR("Brett Russ");
2244 MODULE_DESCRIPTION("SCSI low-level driver for Marvell SATA controllers");
2245 MODULE_LICENSE("GPL");
2246 MODULE_DEVICE_TABLE(pci, mv_pci_tbl);
2247 MODULE_VERSION(DRV_VERSION);
2248
2249 module_init(mv_init);
2250 module_exit(mv_exit);
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