drivers/usb/host/xhci.h

   1 /*
   2  * xHCI host controller driver
   3  *
   4  * Copyright (C) 2008 Intel Corp.
   5  *
   6  * Author: Sarah Sharp
   7  * Some code borrowed from the Linux EHCI driver.
   8  *
   9  * This program is free software; you can redistribute it and/or modify
  10  * it under the terms of the GNU General Public License version 2 as
  11  * published by the Free Software Foundation.
  12  *
  13  * This program is distributed in the hope that it will be useful, but
  14  * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  15  * or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  16  * for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software Foundation,
  20  * Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  21  */
  22
  23 #ifndef __LINUX_XHCI_HCD_H
  24 #define __LINUX_XHCI_HCD_H
  25
  26 #include <linux/usb.h>
  27 #include <linux/timer.h>
  28 #include <linux/kernel.h>
  29 #include <linux/usb/hcd.h>
  30
  31 /* Code sharing between pci-quirks and xhci hcd */
  32 #include        "xhci-ext-caps.h"
  33 #include "pci-quirks.h"
  34
  35 /* xHCI PCI Configuration Registers */
  36 #define XHCI_SBRN_OFFSET        (0x60)
  37
  38 /* Max number of USB devices for any host controller - limit in section 6.1 */
  39 #define MAX_HC_SLOTS            256
  40 /* Section 5.3.3 - MaxPorts */
  41 #define MAX_HC_PORTS            127
  42
  43 /*
  44  * xHCI register interface.
  45  * This corresponds to the eXtensible Host Controller Interface (xHCI)
  46  * Revision 0.95 specification
  47  */
  48
  49 /**
  50  * struct xhci_cap_regs - xHCI Host Controller Capability Registers.
  51  * @hc_capbase:         length of the capabilities register and HC version number
  52  * @hcs_params1:        HCSPARAMS1 - Structural Parameters 1
  53  * @hcs_params2:        HCSPARAMS2 - Structural Parameters 2
  54  * @hcs_params3:        HCSPARAMS3 - Structural Parameters 3
  55  * @hcc_params:         HCCPARAMS - Capability Parameters
  56  * @db_off:             DBOFF - Doorbell array offset
  57  * @run_regs_off:       RTSOFF - Runtime register space offset
  58  */
  59 struct xhci_cap_regs {
  60         __le32  hc_capbase;
  61         __le32  hcs_params1;
  62         __le32  hcs_params2;
  63         __le32  hcs_params3;
  64         __le32  hcc_params;
  65         __le32  db_off;
  66         __le32  run_regs_off;
  67         /* Reserved up to (CAPLENGTH - 0x1C) */
  68 };
  69
  70 /* hc_capbase bitmasks */
  71 /* bits 7:0 - how long is the Capabilities register */
  72 #define HC_LENGTH(p)            XHCI_HC_LENGTH(p)
  73 /* bits 31:16   */
  74 #define HC_VERSION(p)           (((p) >> 16) & 0xffff)
  75
  76 /* HCSPARAMS1 - hcs_params1 - bitmasks */
  77 /* bits 0:7, Max Device Slots */
  78 #define HCS_MAX_SLOTS(p)        (((p) >> 0) & 0xff)
  79 #define HCS_SLOTS_MASK          0xff
  80 /* bits 8:18, Max Interrupters */
  81 #define HCS_MAX_INTRS(p)        (((p) >> 8) & 0x7ff)
  82 /* bits 24:31, Max Ports - max value is 0x7F = 127 ports */
  83 #define HCS_MAX_PORTS(p)        (((p) >> 24) & 0x7f)
  84
  85 /* HCSPARAMS2 - hcs_params2 - bitmasks */
  86 /* bits 0:3, frames or uframes that SW needs to queue transactions
  87  * ahead of the HW to meet periodic deadlines */
  88 #define HCS_IST(p)              (((p) >> 0) & 0xf)
  89 /* bits 4:7, max number of Event Ring segments */
  90 #define HCS_ERST_MAX(p)         (((p) >> 4) & 0xf)
  91 /* bit 26 Scratchpad restore - for save/restore HW state - not used yet */
  92 /* bits 27:31 number of Scratchpad buffers SW must allocate for the HW */
  93 #define HCS_MAX_SCRATCHPAD(p)   (((p) >> 27) & 0x1f)
  94
  95 /* HCSPARAMS3 - hcs_params3 - bitmasks */
  96 /* bits 0:7, Max U1 to U0 latency for the roothub ports */
  97 #define HCS_U1_LATENCY(p)       (((p) >> 0) & 0xff)
  98 /* bits 16:31, Max U2 to U0 latency for the roothub ports */
  99 #define HCS_U2_LATENCY(p)       (((p) >> 16) & 0xffff)
 100
 101 /* HCCPARAMS - hcc_params - bitmasks */
 102 /* true: HC can use 64-bit address pointers */
 103 #define HCC_64BIT_ADDR(p)       ((p) & (1 << 0))
 104 /* true: HC can do bandwidth negotiation */
 105 #define HCC_BANDWIDTH_NEG(p)    ((p) & (1 << 1))
 106 /* true: HC uses 64-byte Device Context structures
 107  * FIXME 64-byte context structures aren't supported yet.
 108  */
 109 #define HCC_64BYTE_CONTEXT(p)   ((p) & (1 << 2))
 110 /* true: HC has port power switches */
 111 #define HCC_PPC(p)              ((p) & (1 << 3))
 112 /* true: HC has port indicators */
 113 #define HCS_INDICATOR(p)        ((p) & (1 << 4))
 114 /* true: HC has Light HC Reset Capability */
 115 #define HCC_LIGHT_RESET(p)      ((p) & (1 << 5))
 116 /* true: HC supports latency tolerance messaging */
 117 #define HCC_LTC(p)              ((p) & (1 << 6))
 118 /* true: no secondary Stream ID Support */
 119 #define HCC_NSS(p)              ((p) & (1 << 7))
 120 /* Max size for Primary Stream Arrays - 2^(n+1), where n is bits 12:15 */
 121 #define HCC_MAX_PSA(p)          (1 << ((((p) >> 12) & 0xf) + 1))
 122 /* Extended Capabilities pointer from PCI base - section 5.3.6 */
 123 #define HCC_EXT_CAPS(p)         XHCI_HCC_EXT_CAPS(p)
 124
 125 /* db_off bitmask - bits 0:1 reserved */
 126 #define DBOFF_MASK      (~0x3)
 127
 128 /* run_regs_off bitmask - bits 0:4 reserved */
 129 #define RTSOFF_MASK     (~0x1f)
 130
 131
 132 /* Number of registers per port */
 133 #define NUM_PORT_REGS   4
 134
 135 #define PORTSC          0
 136 #define PORTPMSC        1
 137 #define PORTLI          2
 138 #define PORTHLPMC       3
 139
 140 /**
 141  * struct xhci_op_regs - xHCI Host Controller Operational Registers.
 142  * @command:            USBCMD - xHC command register
 143  * @status:             USBSTS - xHC status register
 144  * @page_size:          This indicates the page size that the host controller
 145  *                      supports.  If bit n is set, the HC supports a page size
 146  *                      of 2^(n+12), up to a 128MB page size.
 147  *                      4K is the minimum page size.
 148  * @cmd_ring:           CRP - 64-bit Command Ring Pointer
 149  * @dcbaa_ptr:          DCBAAP - 64-bit Device Context Base Address Array Pointer
 150  * @config_reg:         CONFIG - Configure Register
 151  * @port_status_base:   PORTSCn - base address for Port Status and Control
 152  *                      Each port has a Port Status and Control register,
 153  *                      followed by a Port Power Management Status and Control
 154  *                      register, a Port Link Info register, and a reserved
 155  *                      register.
 156  * @port_power_base:    PORTPMSCn - base address for
 157  *                      Port Power Management Status and Control
 158  * @port_link_base:     PORTLIn - base address for Port Link Info (current
 159  *                      Link PM state and control) for USB 2.1 and USB 3.0
 160  *                      devices.
 161  */
 162 struct xhci_op_regs {
 163         __le32  command;
 164         __le32  status;
 165         __le32  page_size;
 166         __le32  reserved1;
 167         __le32  reserved2;
 168         __le32  dev_notification;
 169         __le64  cmd_ring;
 170         /* rsvd: offset 0x20-2F */
 171         __le32  reserved3[4];
 172         __le64  dcbaa_ptr;
 173         __le32  config_reg;
 174         /* rsvd: offset 0x3C-3FF */
 175         __le32  reserved4[241];
 176         /* port 1 registers, which serve as a base address for other ports */
 177         __le32  port_status_base;
 178         __le32  port_power_base;
 179         __le32  port_link_base;
 180         __le32  reserved5;
 181         /* registers for ports 2-255 */
 182         __le32  reserved6[NUM_PORT_REGS*254];
 183 };
 184
 185 /* USBCMD - USB command - command bitmasks */
 186 /* start/stop HC execution - do not write unless HC is halted*/
 187 #define CMD_RUN         XHCI_CMD_RUN
 188 /* Reset HC - resets internal HC state machine and all registers (except
 189  * PCI config regs).  HC does NOT drive a USB reset on the downstream ports.
 190  * The xHCI driver must reinitialize the xHC after setting this bit.
 191  */
 192 #define CMD_RESET       (1 << 1)
 193 /* Event Interrupt Enable - a '1' allows interrupts from the host controller */
 194 #define CMD_EIE         XHCI_CMD_EIE
 195 /* Host System Error Interrupt Enable - get out-of-band signal for HC errors */
 196 #define CMD_HSEIE       XHCI_CMD_HSEIE
 197 /* bits 4:6 are reserved (and should be preserved on writes). */
 198 /* light reset (port status stays unchanged) - reset completed when this is 0 */
 199 #define CMD_LRESET      (1 << 7)
 200 /* host controller save/restore state. */
 201 #define CMD_CSS         (1 << 8)
 202 #define CMD_CRS         (1 << 9)
 203 /* Enable Wrap Event - '1' means xHC generates an event when MFINDEX wraps. */
 204 #define CMD_EWE         XHCI_CMD_EWE
 205 /* MFINDEX power management - '1' means xHC can stop MFINDEX counter if all root
 206  * hubs are in U3 (selective suspend), disconnect, disabled, or powered-off.
 207  * '0' means the xHC can power it off if all ports are in the disconnect,
 208  * disabled, or powered-off state.
 209  */
 210 #define CMD_PM_INDEX    (1 << 11)
 211 /* bits 12:31 are reserved (and should be preserved on writes). */
 212
 213 /* IMAN - Interrupt Management Register */
 214 #define IMAN_IE         (1 << 1)
 215 #define IMAN_IP         (1 << 0)
 216
 217 /* USBSTS - USB status - status bitmasks */
 218 /* HC not running - set to 1 when run/stop bit is cleared. */
 219 #define STS_HALT        XHCI_STS_HALT
 220 /* serious error, e.g. PCI parity error.  The HC will clear the run/stop bit. */
 221 #define STS_FATAL       (1 << 2)
 222 /* event interrupt - clear this prior to clearing any IP flags in IR set*/
 223 #define STS_EINT        (1 << 3)
 224 /* port change detect */
 225 #define STS_PORT        (1 << 4)
 226 /* bits 5:7 reserved and zeroed */
 227 /* save state status - '1' means xHC is saving state */
 228 #define STS_SAVE        (1 << 8)
 229 /* restore state status - '1' means xHC is restoring state */
 230 #define STS_RESTORE     (1 << 9)
 231 /* true: save or restore error */
 232 #define STS_SRE         (1 << 10)
 233 /* true: Controller Not Ready to accept doorbell or op reg writes after reset */
 234 #define STS_CNR         XHCI_STS_CNR
 235 /* true: internal Host Controller Error - SW needs to reset and reinitialize */
 236 #define STS_HCE         (1 << 12)
 237 /* bits 13:31 reserved and should be preserved */
 238
 239 /*
 240  * DNCTRL - Device Notification Control Register - dev_notification bitmasks
 241  * Generate a device notification event when the HC sees a transaction with a
 242  * notification type that matches a bit set in this bit field.
 243  */
 244 #define DEV_NOTE_MASK           (0xffff)
 245 #define ENABLE_DEV_NOTE(x)      (1 << (x))
 246 /* Most of the device notification types should only be used for debug.
 247  * SW does need to pay attention to function wake notifications.
 248  */
 249 #define DEV_NOTE_FWAKE          ENABLE_DEV_NOTE(1)
 250
 251 /* CRCR - Command Ring Control Register - cmd_ring bitmasks */
 252 /* bit 0 is the command ring cycle state */
 253 /* stop ring operation after completion of the currently executing command */
 254 #define CMD_RING_PAUSE          (1 << 1)
 255 /* stop ring immediately - abort the currently executing command */
 256 #define CMD_RING_ABORT          (1 << 2)
 257 /* true: command ring is running */
 258 #define CMD_RING_RUNNING        (1 << 3)
 259 /* bits 4:5 reserved and should be preserved */
 260 /* Command Ring pointer - bit mask for the lower 32 bits. */
 261 #define CMD_RING_RSVD_BITS      (0x3f)
 262
 263 /* CONFIG - Configure Register - config_reg bitmasks */
 264 /* bits 0:7 - maximum number of device slots enabled (NumSlotsEn) */
 265 #define MAX_DEVS(p)     ((p) & 0xff)
 266 /* bits 8:31 - reserved and should be preserved */
 267
 268 /* PORTSC - Port Status and Control Register - port_status_base bitmasks */
 269 /* true: device connected */
 270 #define PORT_CONNECT    (1 << 0)
 271 /* true: port enabled */
 272 #define PORT_PE         (1 << 1)
 273 /* bit 2 reserved and zeroed */
 274 /* true: port has an over-current condition */
 275 #define PORT_OC         (1 << 3)
 276 /* true: port reset signaling asserted */
 277 #define PORT_RESET      (1 << 4)
 278 /* Port Link State - bits 5:8
 279  * A read gives the current link PM state of the port,
 280  * a write with Link State Write Strobe set sets the link state.
 281  */
 282 #define PORT_PLS_MASK   (0xf << 5)
 283 #define XDEV_U0         (0x0 << 5)
 284 #define XDEV_U2         (0x2 << 5)
 285 #define XDEV_U3         (0x3 << 5)
 286 #define XDEV_RESUME     (0xf << 5)
 287 /* true: port has power (see HCC_PPC) */
 288 #define PORT_POWER      (1 << 9)
 289 /* bits 10:13 indicate device speed:
 290  * 0 - undefined speed - port hasn't be initialized by a reset yet
 291  * 1 - full speed
 292  * 2 - low speed
 293  * 3 - high speed
 294  * 4 - super speed
 295  * 5-15 reserved
 296  */
 297 #define DEV_SPEED_MASK          (0xf << 10)
 298 #define XDEV_FS                 (0x1 << 10)
 299 #define XDEV_LS                 (0x2 << 10)
 300 #define XDEV_HS                 (0x3 << 10)
 301 #define XDEV_SS                 (0x4 << 10)
 302 #define DEV_UNDEFSPEED(p)       (((p) & DEV_SPEED_MASK) == (0x0<<10))
 303 #define DEV_FULLSPEED(p)        (((p) & DEV_SPEED_MASK) == XDEV_FS)
 304 #define DEV_LOWSPEED(p)         (((p) & DEV_SPEED_MASK) == XDEV_LS)
 305 #define DEV_HIGHSPEED(p)        (((p) & DEV_SPEED_MASK) == XDEV_HS)
 306 #define DEV_SUPERSPEED(p)       (((p) & DEV_SPEED_MASK) == XDEV_SS)
 307 /* Bits 20:23 in the Slot Context are the speed for the device */
 308 #define SLOT_SPEED_FS           (XDEV_FS << 10)
 309 #define SLOT_SPEED_LS           (XDEV_LS << 10)
 310 #define SLOT_SPEED_HS           (XDEV_HS << 10)
 311 #define SLOT_SPEED_SS           (XDEV_SS << 10)
 312 /* Port Indicator Control */
 313 #define PORT_LED_OFF    (0 << 14)
 314 #define PORT_LED_AMBER  (1 << 14)
 315 #define PORT_LED_GREEN  (2 << 14)
 316 #define PORT_LED_MASK   (3 << 14)
 317 /* Port Link State Write Strobe - set this when changing link state */
 318 #define PORT_LINK_STROBE        (1 << 16)
 319 /* true: connect status change */
 320 #define PORT_CSC        (1 << 17)
 321 /* true: port enable change */
 322 #define PORT_PEC        (1 << 18)
 323 /* true: warm reset for a USB 3.0 device is done.  A "hot" reset puts the port
 324  * into an enabled state, and the device into the default state.  A "warm" reset
 325  * also resets the link, forcing the device through the link training sequence.
 326  * SW can also look at the Port Reset register to see when warm reset is done.
 327  */
 328 #define PORT_WRC        (1 << 19)
 329 /* true: over-current change */
 330 #define PORT_OCC        (1 << 20)
 331 /* true: reset change - 1 to 0 transition of PORT_RESET */
 332 #define PORT_RC         (1 << 21)
 333 /* port link status change - set on some port link state transitions:
 334  *  Transition                          Reason
 335  *  ------------------------------------------------------------------------------
 336  *  - U3 to Resume                      Wakeup signaling from a device
 337  *  - Resume to Recovery to U0          USB 3.0 device resume
 338  *  - Resume to U0                      USB 2.0 device resume
 339  *  - U3 to Recovery to U0              Software resume of USB 3.0 device complete
 340  *  - U3 to U0                          Software resume of USB 2.0 device complete
 341  *  - U2 to U0                          L1 resume of USB 2.1 device complete
 342  *  - U0 to U0 (???)                    L1 entry rejection by USB 2.1 device
 343  *  - U0 to disabled                    L1 entry error with USB 2.1 device
 344  *  - Any state to inactive             Error on USB 3.0 port
 345  */
 346 #define PORT_PLC        (1 << 22)
 347 /* port configure error change - port failed to configure its link partner */
 348 #define PORT_CEC        (1 << 23)
 349 /* Cold Attach Status - xHC can set this bit to report device attached during
 350  * Sx state. Warm port reset should be perfomed to clear this bit and move port
 351  * to connected state.
 352  */
 353 #define PORT_CAS        (1 << 24)
 354 /* wake on connect (enable) */
 355 #define PORT_WKCONN_E   (1 << 25)
 356 /* wake on disconnect (enable) */
 357 #define PORT_WKDISC_E   (1 << 26)
 358 /* wake on over-current (enable) */
 359 #define PORT_WKOC_E     (1 << 27)
 360 /* bits 28:29 reserved */
 361 /* true: device is removable - for USB 3.0 roothub emulation */
 362 #define PORT_DEV_REMOVE (1 << 30)
 363 /* Initiate a warm port reset - complete when PORT_WRC is '1' */
 364 #define PORT_WR         (1 << 31)
 365
 366 /* We mark duplicate entries with -1 */
 367 #define DUPLICATE_ENTRY ((u8)(-1))
 368
 369 /* Port Power Management Status and Control - port_power_base bitmasks */
 370 /* Inactivity timer value for transitions into U1, in microseconds.
 371  * Timeout can be up to 127us.  0xFF means an infinite timeout.
 372  */
 373 #define PORT_U1_TIMEOUT(p)      ((p) & 0xff)
 374 #define PORT_U1_TIMEOUT_MASK    0xff
 375 /* Inactivity timer value for transitions into U2 */
 376 #define PORT_U2_TIMEOUT(p)      (((p) & 0xff) << 8)
 377 #define PORT_U2_TIMEOUT_MASK    (0xff << 8)
 378 /* Bits 24:31 for port testing */
 379
 380 /* USB2 Protocol PORTSPMSC */
 381 #define PORT_L1S_MASK           7
 382 #define PORT_L1S_SUCCESS        1
 383 #define PORT_RWE                (1 << 3)
 384 #define PORT_HIRD(p)            (((p) & 0xf) << 4)
 385 #define PORT_HIRD_MASK          (0xf << 4)
 386 #define PORT_L1DS_MASK          (0xff << 8)
 387 #define PORT_L1DS(p)            (((p) & 0xff) << 8)
 388 #define PORT_HLE                (1 << 16)
 389
 390
 391 /* USB2 Protocol PORTHLPMC */
 392 #define PORT_HIRDM(p)((p) & 3)
 393 #define PORT_L1_TIMEOUT(p)(((p) & 0xff) << 2)
 394 #define PORT_BESLD(p)(((p) & 0xf) << 10)
 395
 396 /* use 512 microseconds as USB2 LPM L1 default timeout. */
 397 #define XHCI_L1_TIMEOUT         512
 398
 399 /* Set default HIRD/BESL value to 4 (350/400us) for USB2 L1 LPM resume latency.
 400  * Safe to use with mixed HIRD and BESL systems (host and device) and is used
 401  * by other operating systems.
 402  *
 403  * XHCI 1.0 errata 8/14/12 Table 13 notes:
 404  * "Software should choose xHC BESL/BESLD field values that do not violate a
 405  * device's resume latency requirements,
 406  * e.g. not program values > '4' if BLC = '1' and a HIRD device is attached,
 407  * or not program values < '4' if BLC = '0' and a BESL device is attached.
 408  */
 409 #define XHCI_DEFAULT_BESL       4
 410
 411 /**
 412  * struct xhci_intr_reg - Interrupt Register Set
 413  * @irq_pending:        IMAN - Interrupt Management Register.  Used to enable
 414  *                      interrupts and check for pending interrupts.
 415  * @irq_control:        IMOD - Interrupt Moderation Register.
 416  *                      Used to throttle interrupts.
 417  * @erst_size:          Number of segments in the Event Ring Segment Table (ERST).
 418  * @erst_base:          ERST base address.
 419  * @erst_dequeue:       Event ring dequeue pointer.
 420  *
 421  * Each interrupter (defined by a MSI-X vector) has an event ring and an Event
 422  * Ring Segment Table (ERST) associated with it.  The event ring is comprised of
 423  * multiple segments of the same size.  The HC places events on the ring and
 424  * "updates the Cycle bit in the TRBs to indicate to software the current
 425  * position of the Enqueue Pointer." The HCD (Linux) processes those events and
 426  * updates the dequeue pointer.
 427  */
 428 struct xhci_intr_reg {
 429         __le32  irq_pending;
 430         __le32  irq_control;
 431         __le32  erst_size;
 432         __le32  rsvd;
 433         __le64  erst_base;
 434         __le64  erst_dequeue;
 435 };
 436
 437 /* irq_pending bitmasks */
 438 #define ER_IRQ_PENDING(p)       ((p) & 0x1)
 439 /* bits 2:31 need to be preserved */
 440 /* THIS IS BUGGY - FIXME - IP IS WRITE 1 TO CLEAR */
 441 #define ER_IRQ_CLEAR(p)         ((p) & 0xfffffffe)
 442 #define ER_IRQ_ENABLE(p)        ((ER_IRQ_CLEAR(p)) | 0x2)
 443 #define ER_IRQ_DISABLE(p)       ((ER_IRQ_CLEAR(p)) & ~(0x2))
 444
 445 /* irq_control bitmasks */
 446 /* Minimum interval between interrupts (in 250ns intervals).  The interval
 447  * between interrupts will be longer if there are no events on the event ring.
 448  * Default is 4000 (1 ms).
 449  */
 450 #define ER_IRQ_INTERVAL_MASK    (0xffff)
 451 /* Counter used to count down the time to the next interrupt - HW use only */
 452 #define ER_IRQ_COUNTER_MASK     (0xffff << 16)
 453
 454 /* erst_size bitmasks */
 455 /* Preserve bits 16:31 of erst_size */
 456 #define ERST_SIZE_MASK          (0xffff << 16)
 457
 458 /* erst_dequeue bitmasks */
 459 /* Dequeue ERST Segment Index (DESI) - Segment number (or alias)
 460  * where the current dequeue pointer lies.  This is an optional HW hint.
 461  */
 462 #define ERST_DESI_MASK          (0x7)
 463 /* Event Handler Busy (EHB) - is the event ring scheduled to be serviced by
 464  * a work queue (or delayed service routine)?
 465  */
 466 #define ERST_EHB                (1 << 3)
 467 #define ERST_PTR_MASK           (0xf)
 468
 469 /**
 470  * struct xhci_run_regs
 471  * @microframe_index:
 472  *              MFINDEX - current microframe number
 473  *
 474  * Section 5.5 Host Controller Runtime Registers:
 475  * "Software should read and write these registers using only Dword (32 bit)
 476  * or larger accesses"
 477  */
 478 struct xhci_run_regs {
 479         __le32                  microframe_index;
 480         __le32                  rsvd[7];
 481         struct xhci_intr_reg    ir_set[128];
 482 };
 483
 484 /**
 485  * struct doorbell_array
 486  *
 487  * Bits  0 -  7: Endpoint target
 488  * Bits  8 - 15: RsvdZ
 489  * Bits 16 - 31: Stream ID
 490  *
 491  * Section 5.6
 492  */
 493 struct xhci_doorbell_array {
 494         __le32  doorbell[256];
 495 };
 496
 497 #define DB_VALUE(ep, stream)    ((((ep) + 1) & 0xff) | ((stream) << 16))
 498 #define DB_VALUE_HOST           0x00000000
 499
 500 /**
 501  * struct xhci_protocol_caps
 502  * @revision:           major revision, minor revision, capability ID,
 503  *                      and next capability pointer.
 504  * @name_string:        Four ASCII characters to say which spec this xHC
 505  *                      follows, typically "USB ".
 506  * @port_info:          Port offset, count, and protocol-defined information.
 507  */
 508 struct xhci_protocol_caps {
 509         u32     revision;
 510         u32     name_string;
 511         u32     port_info;
 512 };
 513
 514 #define XHCI_EXT_PORT_MAJOR(x)  (((x) >> 24) & 0xff)
 515 #define XHCI_EXT_PORT_OFF(x)    ((x) & 0xff)
 516 #define XHCI_EXT_PORT_COUNT(x)  (((x) >> 8) & 0xff)
 517
 518 /**
 519  * struct xhci_container_ctx
 520  * @type: Type of context.  Used to calculated offsets to contained contexts.
 521  * @size: Size of the context data
 522  * @bytes: The raw context data given to HW
 523  * @dma: dma address of the bytes
 524  *
 525  * Represents either a Device or Input context.  Holds a pointer to the raw
 526  * memory used for the context (bytes) and dma address of it (dma).
 527  */
 528 struct xhci_container_ctx {
 529         unsigned type;
 530 #define XHCI_CTX_TYPE_DEVICE  0x1
 531 #define XHCI_CTX_TYPE_INPUT   0x2
 532
 533         int size;
 534
 535         u8 *bytes;
 536         dma_addr_t dma;
 537 };
 538
 539 /**
 540  * struct xhci_slot_ctx
 541  * @dev_info:   Route string, device speed, hub info, and last valid endpoint
 542  * @dev_info2:  Max exit latency for device number, root hub port number
 543  * @tt_info:    tt_info is used to construct split transaction tokens
 544  * @dev_state:  slot state and device address
 545  *
 546  * Slot Context - section 6.2.1.1.  This assumes the HC uses 32-byte context
 547  * structures.  If the HC uses 64-byte contexts, there is an additional 32 bytes
 548  * reserved at the end of the slot context for HC internal use.
 549  */
 550 struct xhci_slot_ctx {
 551         __le32  dev_info;
 552         __le32  dev_info2;
 553         __le32  tt_info;
 554         __le32  dev_state;
 555         /* offset 0x10 to 0x1f reserved for HC internal use */
 556         __le32  reserved[4];
 557 };
 558
 559 /* dev_info bitmasks */
 560 /* Route String - 0:19 */
 561 #define ROUTE_STRING_MASK       (0xfffff)
 562 /* Device speed - values defined by PORTSC Device Speed field - 20:23 */
 563 #define DEV_SPEED       (0xf << 20)
 564 /* bit 24 reserved */
 565 /* Is this LS/FS device connected through a HS hub? - bit 25 */
 566 #define DEV_MTT         (0x1 << 25)
 567 /* Set if the device is a hub - bit 26 */
 568 #define DEV_HUB         (0x1 << 26)
 569 /* Index of the last valid endpoint context in this device context - 27:31 */
 570 #define LAST_CTX_MASK   (0x1f << 27)
 571 #define LAST_CTX(p)     ((p) << 27)
 572 #define LAST_CTX_TO_EP_NUM(p)   (((p) >> 27) - 1)
 573 #define SLOT_FLAG       (1 << 0)
 574 #define EP0_FLAG        (1 << 1)
 575
 576 /* dev_info2 bitmasks */
 577 /* Max Exit Latency (ms) - worst case time to wake up all links in dev path */
 578 #define MAX_EXIT        (0xffff)
 579 /* Root hub port number that is needed to access the USB device */
 580 #define ROOT_HUB_PORT(p)        (((p) & 0xff) << 16)
 581 #define DEVINFO_TO_ROOT_HUB_PORT(p)     (((p) >> 16) & 0xff)
 582 /* Maximum number of ports under a hub device */
 583 #define XHCI_MAX_PORTS(p)       (((p) & 0xff) << 24)
 584
 585 /* tt_info bitmasks */
 586 /*
 587  * TT Hub Slot ID - for low or full speed devices attached to a high-speed hub
 588  * The Slot ID of the hub that isolates the high speed signaling from
 589  * this low or full-speed device.  '0' if attached to root hub port.
 590  */
 591 #define TT_SLOT         (0xff)
 592 /*
 593  * The number of the downstream facing port of the high-speed hub
 594  * '0' if the device is not low or full speed.
 595  */
 596 #define TT_PORT         (0xff << 8)
 597 #define TT_THINK_TIME(p)        (((p) & 0x3) << 16)
 598
 599 /* dev_state bitmasks */
 600 /* USB device address - assigned by the HC */
 601 #define DEV_ADDR_MASK   (0xff)
 602 /* bits 8:26 reserved */
 603 /* Slot state */
 604 #define SLOT_STATE      (0x1f << 27)
 605 #define GET_SLOT_STATE(p)       (((p) & (0x1f << 27)) >> 27)
 606
 607 #define SLOT_STATE_DISABLED     0
 608 #define SLOT_STATE_ENABLED      SLOT_STATE_DISABLED
 609 #define SLOT_STATE_DEFAULT      1
 610 #define SLOT_STATE_ADDRESSED    2
 611 #define SLOT_STATE_CONFIGURED   3
 612
 613 /**
 614  * struct xhci_ep_ctx
 615  * @ep_info:    endpoint state, streams, mult, and interval information.
 616  * @ep_info2:   information on endpoint type, max packet size, max burst size,
 617  *              error count, and whether the HC will force an event for all
 618  *              transactions.
 619  * @deq:        64-bit ring dequeue pointer address.  If the endpoint only
 620  *              defines one stream, this points to the endpoint transfer ring.
 621  *              Otherwise, it points to a stream context array, which has a
 622  *              ring pointer for each flow.
 623  * @tx_info:
 624  *              Average TRB lengths for the endpoint ring and
 625  *              max payload within an Endpoint Service Interval Time (ESIT).
 626  *
 627  * Endpoint Context - section 6.2.1.2.  This assumes the HC uses 32-byte context
 628  * structures.  If the HC uses 64-byte contexts, there is an additional 32 bytes
 629  * reserved at the end of the endpoint context for HC internal use.
 630  */
 631 struct xhci_ep_ctx {
 632         __le32  ep_info;
 633         __le32  ep_info2;
 634         __le64  deq;
 635         __le32  tx_info;
 636         /* offset 0x14 - 0x1f reserved for HC internal use */
 637         __le32  reserved[3];
 638 };
 639
 640 /* ep_info bitmasks */
 641 /*
 642  * Endpoint State - bits 0:2
 643  * 0 - disabled
 644  * 1 - running
 645  * 2 - halted due to halt condition - ok to manipulate endpoint ring
 646  * 3 - stopped
 647  * 4 - TRB error
 648  * 5-7 - reserved
 649  */
 650 #define EP_STATE_MASK           (0xf)
 651 #define EP_STATE_DISABLED       0
 652 #define EP_STATE_RUNNING        1
 653 #define EP_STATE_HALTED         2
 654 #define EP_STATE_STOPPED        3
 655 #define EP_STATE_ERROR          4
 656 /* Mult - Max number of burtst within an interval, in EP companion desc. */
 657 #define EP_MULT(p)              (((p) & 0x3) << 8)
 658 #define CTX_TO_EP_MULT(p)       (((p) >> 8) & 0x3)
 659 /* bits 10:14 are Max Primary Streams */
 660 /* bit 15 is Linear Stream Array */
 661 /* Interval - period between requests to an endpoint - 125u increments. */
 662 #define EP_INTERVAL(p)          (((p) & 0xff) << 16)
 663 #define EP_INTERVAL_TO_UFRAMES(p)               (1 << (((p) >> 16) & 0xff))
 664 #define CTX_TO_EP_INTERVAL(p)   (((p) >> 16) & 0xff)
 665 #define EP_MAXPSTREAMS_MASK     (0x1f << 10)
 666 #define EP_MAXPSTREAMS(p)       (((p) << 10) & EP_MAXPSTREAMS_MASK)
 667 /* Endpoint is set up with a Linear Stream Array (vs. Secondary Stream Array) */
 668 #define EP_HAS_LSA              (1 << 15)
 669
 670 /* ep_info2 bitmasks */
 671 /*
 672  * Force Event - generate transfer events for all TRBs for this endpoint
 673  * This will tell the HC to ignore the IOC and ISP flags (for debugging only).
 674  */
 675 #define FORCE_EVENT     (0x1)
 676 #define ERROR_COUNT(p)  (((p) & 0x3) << 1)
 677 #define CTX_TO_EP_TYPE(p)       (((p) >> 3) & 0x7)
 678 #define EP_TYPE(p)      ((p) << 3)
 679 #define ISOC_OUT_EP     1
 680 #define BULK_OUT_EP     2
 681 #define INT_OUT_EP      3
 682 #define CTRL_EP         4
 683 #define ISOC_IN_EP      5
 684 #define BULK_IN_EP      6
 685 #define INT_IN_EP       7
 686 /* bit 6 reserved */
 687 /* bit 7 is Host Initiate Disable - for disabling stream selection */
 688 #define MAX_BURST(p)    (((p)&0xff) << 8)
 689 #define CTX_TO_MAX_BURST(p)     (((p) >> 8) & 0xff)
 690 #define MAX_PACKET(p)   (((p)&0xffff) << 16)
 691 #define MAX_PACKET_MASK         (0xffff << 16)
 692 #define MAX_PACKET_DECODED(p)   (((p) >> 16) & 0xffff)
 693
 694 /* Get max packet size from ep desc. Bit 10..0 specify the max packet size.
 695  * USB2.0 spec 9.6.6.
 696  */
 697 #define GET_MAX_PACKET(p)       ((p) & 0x7ff)
 698
 699 /* tx_info bitmasks */
 700 #define AVG_TRB_LENGTH_FOR_EP(p)        ((p) & 0xffff)
 701 #define MAX_ESIT_PAYLOAD_FOR_EP(p)      (((p) & 0xffff) << 16)
 702 #define CTX_TO_MAX_ESIT_PAYLOAD(p)      (((p) >> 16) & 0xffff)
 703
 704 /* deq bitmasks */
 705 #define EP_CTX_CYCLE_MASK               (1 << 0)
 706
 707
 708 /**
 709  * struct xhci_input_control_context
 710  * Input control context; see section 6.2.5.
 711  *
 712  * @drop_context:       set the bit of the endpoint context you want to disable
 713  * @add_context:        set the bit of the endpoint context you want to enable
 714  */
 715 struct xhci_input_control_ctx {
 716         __le32  drop_flags;
 717         __le32  add_flags;
 718         __le32  rsvd2[6];
 719 };
 720
 721 #define EP_IS_ADDED(ctrl_ctx, i) \
 722         (le32_to_cpu(ctrl_ctx->add_flags) & (1 << (i + 1)))
 723 #define EP_IS_DROPPED(ctrl_ctx, i)       \
 724         (le32_to_cpu(ctrl_ctx->drop_flags) & (1 << (i + 1)))
 725
 726 /* Represents everything that is needed to issue a command on the command ring.
 727  * It's useful to pre-allocate these for commands that cannot fail due to
 728  * out-of-memory errors, like freeing streams.
 729  */
 730 struct xhci_command {
 731         /* Input context for changing device state */
 732         struct xhci_container_ctx       *in_ctx;
 733         u32                             status;
 734         /* If completion is null, no one is waiting on this command
 735          * and the structure can be freed after the command completes.
 736          */
 737         struct completion               *completion;
 738         union xhci_trb                  *command_trb;
 739         struct list_head                cmd_list;
 740 };
 741
 742 /* drop context bitmasks */
 743 #define DROP_EP(x)      (0x1 << x)
 744 /* add context bitmasks */
 745 #define ADD_EP(x)       (0x1 << x)
 746
 747 struct xhci_stream_ctx {
 748         /* 64-bit stream ring address, cycle state, and stream type */
 749         __le64  stream_ring;
 750         /* offset 0x14 - 0x1f reserved for HC internal use */
 751         __le32  reserved[2];
 752 };
 753
 754 /* Stream Context Types (section 6.4.1) - bits 3:1 of stream ctx deq ptr */
 755 #define SCT_FOR_CTX(p)          (((p) << 1) & 0x7)
 756 /* Secondary stream array type, dequeue pointer is to a transfer ring */
 757 #define SCT_SEC_TR              0
 758 /* Primary stream array type, dequeue pointer is to a transfer ring */
 759 #define SCT_PRI_TR              1
 760 /* Dequeue pointer is for a secondary stream array (SSA) with 8 entries */
 761 #define SCT_SSA_8               2
 762 #define SCT_SSA_16              3
 763 #define SCT_SSA_32              4
 764 #define SCT_SSA_64              5
 765 #define SCT_SSA_128             6
 766 #define SCT_SSA_256             7
 767
 768 /* Assume no secondary streams for now */
 769 struct xhci_stream_info {
 770         struct xhci_ring                **stream_rings;
 771         /* Number of streams, including stream 0 (which drivers can't use) */
 772         unsigned int                    num_streams;
 773         /* The stream context array may be bigger than
 774          * the number of streams the driver asked for
 775          */
 776         struct xhci_stream_ctx          *stream_ctx_array;
 777         unsigned int                    num_stream_ctxs;
 778         dma_addr_t                      ctx_array_dma;
 779         /* For mapping physical TRB addresses to segments in stream rings */
 780         struct radix_tree_root          trb_address_map;
 781         struct xhci_command             *free_streams_command;
 782 };
 783
 784 #define SMALL_STREAM_ARRAY_SIZE         256
 785 #define MEDIUM_STREAM_ARRAY_SIZE        1024
 786
 787 /* Some Intel xHCI host controllers need software to keep track of the bus
 788  * bandwidth.  Keep track of endpoint info here.  Each root port is allocated
 789  * the full bus bandwidth.  We must also treat TTs (including each port under a
 790  * multi-TT hub) as a separate bandwidth domain.  The direct memory interface
 791  * (DMI) also limits the total bandwidth (across all domains) that can be used.
 792  */
 793 struct xhci_bw_info {
 794         /* ep_interval is zero-based */
 795         unsigned int            ep_interval;
 796         /* mult and num_packets are one-based */
 797         unsigned int            mult;
 798         unsigned int            num_packets;
 799         unsigned int            max_packet_size;
 800         unsigned int            max_esit_payload;
 801         unsigned int            type;
 802 };
 803
 804 /* "Block" sizes in bytes the hardware uses for different device speeds.
 805  * The logic in this part of the hardware limits the number of bits the hardware
 806  * can use, so must represent bandwidth in a less precise manner to mimic what
 807  * the scheduler hardware computes.
 808  */
 809 #define FS_BLOCK        1
 810 #define HS_BLOCK        4
 811 #define SS_BLOCK        16
 812 #define DMI_BLOCK       32
 813
 814 /* Each device speed has a protocol overhead (CRC, bit stuffing, etc) associated
 815  * with each byte transferred.  SuperSpeed devices have an initial overhead to
 816  * set up bursts.  These are in blocks, see above.  LS overhead has already been
 817  * translated into FS blocks.
 818  */
 819 #define DMI_OVERHEAD 8
 820 #define DMI_OVERHEAD_BURST 4
 821 #define SS_OVERHEAD 8
 822 #define SS_OVERHEAD_BURST 32
 823 #define HS_OVERHEAD 26
 824 #define FS_OVERHEAD 20
 825 #define LS_OVERHEAD 128
 826 /* The TTs need to claim roughly twice as much bandwidth (94 bytes per
 827  * microframe ~= 24Mbps) of the HS bus as the devices can actually use because
 828  * of overhead associated with split transfers crossing microframe boundaries.
 829  * 31 blocks is pure protocol overhead.
 830  */
 831 #define TT_HS_OVERHEAD (31 + 94)
 832 #define TT_DMI_OVERHEAD (25 + 12)
 833
 834 /* Bandwidth limits in blocks */
 835 #define FS_BW_LIMIT             1285
 836 #define TT_BW_LIMIT             1320
 837 #define HS_BW_LIMIT             1607
 838 #define SS_BW_LIMIT_IN          3906
 839 #define DMI_BW_LIMIT_IN         3906
 840 #define SS_BW_LIMIT_OUT         3906
 841 #define DMI_BW_LIMIT_OUT        3906
 842
 843 /* Percentage of bus bandwidth reserved for non-periodic transfers */
 844 #define FS_BW_RESERVED          10
 845 #define HS_BW_RESERVED          20
 846 #define SS_BW_RESERVED          10
 847
 848 struct xhci_virt_ep {
 849         struct xhci_ring                *ring;
 850         /* Related to endpoints that are configured to use stream IDs only */
 851         struct xhci_stream_info         *stream_info;
 852         /* Temporary storage in case the configure endpoint command fails and we
 853          * have to restore the device state to the previous state
 854          */
 855         struct xhci_ring                *new_ring;
 856         unsigned int                    ep_state;
 857 #define SET_DEQ_PENDING         (1 << 0)
 858 #define EP_HALTED               (1 << 1)        /* For stall handling */
 859 #define EP_HALT_PENDING         (1 << 2)        /* For URB cancellation */
 860 /* Transitioning the endpoint to using streams, don't enqueue URBs */
 861 #define EP_GETTING_STREAMS      (1 << 3)
 862 #define EP_HAS_STREAMS          (1 << 4)
 863 /* Transitioning the endpoint to not using streams, don't enqueue URBs */
 864 #define EP_GETTING_NO_STREAMS   (1 << 5)
 865         /* ----  Related to URB cancellation ---- */
 866         struct list_head        cancelled_td_list;
 867         /* The TRB that was last reported in a stopped endpoint ring */
 868         union xhci_trb          *stopped_trb;
 869         struct xhci_td          *stopped_td;
 870         unsigned int            stopped_stream;
 871         /* Watchdog timer for stop endpoint command to cancel URBs */
 872         struct timer_list       stop_cmd_timer;
 873         int                     stop_cmds_pending;
 874         struct xhci_hcd         *xhci;
 875         /* Dequeue pointer and dequeue segment for a submitted Set TR Dequeue
 876          * command.  We'll need to update the ring's dequeue segment and dequeue
 877          * pointer after the command completes.
 878          */
 879         struct xhci_segment     *queued_deq_seg;
 880         union xhci_trb          *queued_deq_ptr;
 881         /*
 882          * Sometimes the xHC can not process isochronous endpoint ring quickly
 883          * enough, and it will miss some isoc tds on the ring and generate
 884          * a Missed Service Error Event.
 885          * Set skip flag when receive a Missed Service Error Event and
 886          * process the missed tds on the endpoint ring.
 887          */
 888         bool                    skip;
 889         /* Bandwidth checking storage */
 890         struct xhci_bw_info     bw_info;
 891         struct list_head        bw_endpoint_list;
 892 };
 893
 894 enum xhci_overhead_type {
 895         LS_OVERHEAD_TYPE = 0,
 896         FS_OVERHEAD_TYPE,
 897         HS_OVERHEAD_TYPE,
 898 };
 899
 900 struct xhci_interval_bw {
 901         unsigned int            num_packets;
 902         /* Sorted by max packet size.
 903          * Head of the list is the greatest max packet size.
 904          */
 905         struct list_head        endpoints;
 906         /* How many endpoints of each speed are present. */
 907         unsigned int            overhead[3];
 908 };
 909
 910 #define XHCI_MAX_INTERVAL       16
 911
 912 struct xhci_interval_bw_table {
 913         unsigned int            interval0_esit_payload;
 914         struct xhci_interval_bw interval_bw[XHCI_MAX_INTERVAL];
 915         /* Includes reserved bandwidth for async endpoints */
 916         unsigned int            bw_used;
 917         unsigned int            ss_bw_in;
 918         unsigned int            ss_bw_out;
 919 };
 920
 921
 922 struct xhci_virt_device {
 923         struct usb_device               *udev;
 924         /*
 925          * Commands to the hardware are passed an "input context" that
 926          * tells the hardware what to change in its data structures.
 927          * The hardware will return changes in an "output context" that
 928          * software must allocate for the hardware.  We need to keep
 929          * track of input and output contexts separately because
 930          * these commands might fail and we don't trust the hardware.
 931          */
 932         struct xhci_container_ctx       *out_ctx;
 933         /* Used for addressing devices and configuration changes */
 934         struct xhci_container_ctx       *in_ctx;
 935         /* Rings saved to ensure old alt settings can be re-instated */
 936         struct xhci_ring                **ring_cache;
 937         int                             num_rings_cached;
 938 #define XHCI_MAX_RINGS_CACHED   31
 939         struct xhci_virt_ep             eps[31];
 940         struct completion               cmd_completion;
 941         /* Status of the last command issued for this device */
 942         u32                             cmd_status;
 943         struct list_head                cmd_list;
 944         u8                              fake_port;
 945         u8                              real_port;
 946         struct xhci_interval_bw_table   *bw_table;
 947         struct xhci_tt_bw_info          *tt_info;
 948         /* The current max exit latency for the enabled USB3 link states. */
 949         u16                             current_mel;
 950 };
 951
 952 /*
 953  * For each roothub, keep track of the bandwidth information for each periodic
 954  * interval.
 955  *
 956  * If a high speed hub is attached to the roothub, each TT associated with that
 957  * hub is a separate bandwidth domain.  The interval information for the
 958  * endpoints on the devices under that TT will appear in the TT structure.
 959  */
 960 struct xhci_root_port_bw_info {
 961         struct list_head                tts;
 962         unsigned int                    num_active_tts;
 963         struct xhci_interval_bw_table   bw_table;
 964 };
 965
 966 struct xhci_tt_bw_info {
 967         struct list_head                tt_list;
 968         int                             slot_id;
 969         int                             ttport;
 970         struct xhci_interval_bw_table   bw_table;
 971         int                             active_eps;
 972 };
 973
 974
 975 /**
 976  * struct xhci_device_context_array
 977  * @dev_context_ptr     array of 64-bit DMA addresses for device contexts
 978  */
 979 struct xhci_device_context_array {
 980         /* 64-bit device addresses; we only write 32-bit addresses */
 981         __le64                  dev_context_ptrs[MAX_HC_SLOTS];
 982         /* private xHCD pointers */
 983         dma_addr_t      dma;
 984 };
 985 /* TODO: write function to set the 64-bit device DMA address */
 986 /*
 987  * TODO: change this to be dynamically sized at HC mem init time since the HC
 988  * might not be able to handle the maximum number of devices possible.
 989  */
 990
 991
 992 struct xhci_transfer_event {
 993         /* 64-bit buffer address, or immediate data */
 994         __le64  buffer;
 995         __le32  transfer_len;
 996         /* This field is interpreted differently based on the type of TRB */
 997         __le32  flags;
 998 };
 999
1000 /* Transfer event TRB length bit mask */
1001 /* bits 0:23 */
1002 #define EVENT_TRB_LEN(p)                ((p) & 0xffffff)
1003
1004 /** Transfer Event bit fields **/
1005 #define TRB_TO_EP_ID(p) (((p) >> 16) & 0x1f)
1006
1007 /* Completion Code - only applicable for some types of TRBs */
1008 #define COMP_CODE_MASK          (0xff << 24)
1009 #define GET_COMP_CODE(p)        (((p) & COMP_CODE_MASK) >> 24)
1010 #define COMP_SUCCESS    1
1011 /* Data Buffer Error */
1012 #define COMP_DB_ERR     2
1013 /* Babble Detected Error */
1014 #define COMP_BABBLE     3
1015 /* USB Transaction Error */
1016 #define COMP_TX_ERR     4
1017 /* TRB Error - some TRB field is invalid */
1018 #define COMP_TRB_ERR    5
1019 /* Stall Error - USB device is stalled */
1020 #define COMP_STALL      6
1021 /* Resource Error - HC doesn't have memory for that device configuration */
1022 #define COMP_ENOMEM     7
1023 /* Bandwidth Error - not enough room in schedule for this dev config */
1024 #define COMP_BW_ERR     8
1025 /* No Slots Available Error - HC ran out of device slots */
1026 #define COMP_ENOSLOTS   9
1027 /* Invalid Stream Type Error */
1028 #define COMP_STREAM_ERR 10
1029 /* Slot Not Enabled Error - doorbell rung for disabled device slot */
1030 #define COMP_EBADSLT    11
1031 /* Endpoint Not Enabled Error */
1032 #define COMP_EBADEP     12
1033 /* Short Packet */
1034 #define COMP_SHORT_TX   13
1035 /* Ring Underrun - doorbell rung for an empty isoc OUT ep ring */
1036 #define COMP_UNDERRUN   14
1037 /* Ring Overrun - isoc IN ep ring is empty when ep is scheduled to RX */
1038 #define COMP_OVERRUN    15
1039 /* Virtual Function Event Ring Full Error */
1040 #define COMP_VF_FULL    16
1041 /* Parameter Error - Context parameter is invalid */
1042 #define COMP_EINVAL     17
1043 /* Bandwidth Overrun Error - isoc ep exceeded its allocated bandwidth */
1044 #define COMP_BW_OVER    18
1045 /* Context State Error - illegal context state transition requested */
1046 #define COMP_CTX_STATE  19
1047 /* No Ping Response Error - HC didn't get PING_RESPONSE in time to TX */
1048 #define COMP_PING_ERR   20
1049 /* Event Ring is full */
1050 #define COMP_ER_FULL    21
1051 /* Incompatible Device Error */
1052 #define COMP_DEV_ERR    22
1053 /* Missed Service Error - HC couldn't service an isoc ep within interval */
1054 #define COMP_MISSED_INT 23
1055 /* Successfully stopped command ring */
1056 #define COMP_CMD_STOP   24
1057 /* Successfully aborted current command and stopped command ring */
1058 #define COMP_CMD_ABORT  25
1059 /* Stopped - transfer was terminated by a stop endpoint command */
1060 #define COMP_STOP       26
1061 /* Same as COMP_EP_STOPPED, but the transferred length in the event is invalid */
1062 #define COMP_STOP_INVAL 27
1063 /* Control Abort Error - Debug Capability - control pipe aborted */
1064 #define COMP_DBG_ABORT  28
1065 /* Max Exit Latency Too Large Error */
1066 #define COMP_MEL_ERR    29
1067 /* TRB type 30 reserved */
1068 /* Isoc Buffer Overrun - an isoc IN ep sent more data than could fit in TD */
1069 #define COMP_BUFF_OVER  31
1070 /* Event Lost Error - xHC has an "internal event overrun condition" */
1071 #define COMP_ISSUES     32
1072 /* Undefined Error - reported when other error codes don't apply */
1073 #define COMP_UNKNOWN    33
1074 /* Invalid Stream ID Error */
1075 #define COMP_STRID_ERR  34
1076 /* Secondary Bandwidth Error - may be returned by a Configure Endpoint cmd */
1077 #define COMP_2ND_BW_ERR 35
1078 /* Split Transaction Error */
1079 #define COMP_SPLIT_ERR  36
1080
1081 struct xhci_link_trb {
1082         /* 64-bit segment pointer*/
1083         __le64 segment_ptr;
1084         __le32 intr_target;
1085         __le32 control;
1086 };
1087
1088 /* control bitfields */
1089 #define LINK_TOGGLE     (0x1<<1)
1090
1091 /* Command completion event TRB */
1092 struct xhci_event_cmd {
1093         /* Pointer to command TRB, or the value passed by the event data trb */
1094         __le64 cmd_trb;
1095         __le32 status;
1096         __le32 flags;
1097 };
1098
1099 /* flags bitmasks */
1100 /* bits 16:23 are the virtual function ID */
1101 /* bits 24:31 are the slot ID */
1102 #define TRB_TO_SLOT_ID(p)       (((p) & (0xff<<24)) >> 24)
1103 #define SLOT_ID_FOR_TRB(p)      (((p) & 0xff) << 24)
1104
1105 /* Stop Endpoint TRB - ep_index to endpoint ID for this TRB */
1106 #define TRB_TO_EP_INDEX(p)              ((((p) & (0x1f << 16)) >> 16) - 1)
1107 #define EP_ID_FOR_TRB(p)                ((((p) + 1) & 0x1f) << 16)
1108
1109 #define SUSPEND_PORT_FOR_TRB(p)         (((p) & 1) << 23)
1110 #define TRB_TO_SUSPEND_PORT(p)          (((p) & (1 << 23)) >> 23)
1111 #define LAST_EP_INDEX                   30
1112
1113 /* Set TR Dequeue Pointer command TRB fields */
1114 #define TRB_TO_STREAM_ID(p)             ((((p) & (0xffff << 16)) >> 16))
1115 #define STREAM_ID_FOR_TRB(p)            ((((p)) & 0xffff) << 16)
1116
1117
1118 /* Port Status Change Event TRB fields */
1119 /* Port ID - bits 31:24 */
1120 #define GET_PORT_ID(p)          (((p) & (0xff << 24)) >> 24)
1121
1122 /* Normal TRB fields */
1123 /* transfer_len bitmasks - bits 0:16 */
1124 #define TRB_LEN(p)              ((p) & 0x1ffff)
1125 /* Interrupter Target - which MSI-X vector to target the completion event at */
1126 #define TRB_INTR_TARGET(p)      (((p) & 0x3ff) << 22)
1127 #define GET_INTR_TARGET(p)      (((p) >> 22) & 0x3ff)
1128 #define TRB_TBC(p)              (((p) & 0x3) << 7)
1129 #define TRB_TLBPC(p)            (((p) & 0xf) << 16)
1130
1131 /* Cycle bit - indicates TRB ownership by HC or HCD */
1132 #define TRB_CYCLE               (1<<0)
1133 /*
1134  * Force next event data TRB to be evaluated before task switch.
1135  * Used to pass OS data back after a TD completes.
1136  */
1137 #define TRB_ENT                 (1<<1)
1138 /* Interrupt on short packet */
1139 #define TRB_ISP                 (1<<2)
1140 /* Set PCIe no snoop attribute */
1141 #define TRB_NO_SNOOP            (1<<3)
1142 /* Chain multiple TRBs into a TD */
1143 #define TRB_CHAIN               (1<<4)
1144 /* Interrupt on completion */
1145 #define TRB_IOC                 (1<<5)
1146 /* The buffer pointer contains immediate data */
1147 #define TRB_IDT                 (1<<6)
1148
1149 /* Block Event Interrupt */
1150 #define TRB_BEI                 (1<<9)
1151
1152 /* Control transfer TRB specific fields */
1153 #define TRB_DIR_IN              (1<<16)
1154 #define TRB_TX_TYPE(p)          ((p) << 16)
1155 #define TRB_DATA_OUT            2
1156 #define TRB_DATA_IN             3
1157
1158 /* Isochronous TRB specific fields */
1159 #define TRB_SIA                 (1<<31)
1160
1161 struct xhci_generic_trb {
1162         __le32 field[4];
1163 };
1164
1165 union xhci_trb {
1166         struct xhci_link_trb            link;
1167         struct xhci_transfer_event      trans_event;
1168         struct xhci_event_cmd           event_cmd;
1169         struct xhci_generic_trb         generic;
1170 };
1171
1172 /* TRB bit mask */
1173 #define TRB_TYPE_BITMASK        (0xfc00)
1174 #define TRB_TYPE(p)             ((p) << 10)
1175 #define TRB_FIELD_TO_TYPE(p)    (((p) & TRB_TYPE_BITMASK) >> 10)
1176 /* TRB type IDs */
1177 /* bulk, interrupt, isoc scatter/gather, and control data stage */
1178 #define TRB_NORMAL              1
1179 /* setup stage for control transfers */
1180 #define TRB_SETUP               2
1181 /* data stage for control transfers */
1182 #define TRB_DATA                3
1183 /* status stage for control transfers */
1184 #define TRB_STATUS              4
1185 /* isoc transfers */
1186 #define TRB_ISOC                5
1187 /* TRB for linking ring segments */
1188 #define TRB_LINK                6
1189 #define TRB_EVENT_DATA          7
1190 /* Transfer Ring No-op (not for the command ring) */
1191 #define TRB_TR_NOOP             8
1192 /* Command TRBs */
1193 /* Enable Slot Command */
1194 #define TRB_ENABLE_SLOT         9
1195 /* Disable Slot Command */
1196 #define TRB_DISABLE_SLOT        10
1197 /* Address Device Command */
1198 #define TRB_ADDR_DEV            11
1199 /* Configure Endpoint Command */
1200 #define TRB_CONFIG_EP           12
1201 /* Evaluate Context Command */
1202 #define TRB_EVAL_CONTEXT        13
1203 /* Reset Endpoint Command */
1204 #define TRB_RESET_EP            14
1205 /* Stop Transfer Ring Command */
1206 #define TRB_STOP_RING           15
1207 /* Set Transfer Ring Dequeue Pointer Command */
1208 #define TRB_SET_DEQ             16
1209 /* Reset Device Command */
1210 #define TRB_RESET_DEV           17
1211 /* Force Event Command (opt) */
1212 #define TRB_FORCE_EVENT         18
1213 /* Negotiate Bandwidth Command (opt) */
1214 #define TRB_NEG_BANDWIDTH       19
1215 /* Set Latency Tolerance Value Command (opt) */
1216 #define TRB_SET_LT              20
1217 /* Get port bandwidth Command */
1218 #define TRB_GET_BW              21
1219 /* Force Header Command - generate a transaction or link management packet */
1220 #define TRB_FORCE_HEADER        22
1221 /* No-op Command - not for transfer rings */
1222 #define TRB_CMD_NOOP            23
1223 /* TRB IDs 24-31 reserved */
1224 /* Event TRBS */
1225 /* Transfer Event */
1226 #define TRB_TRANSFER            32
1227 /* Command Completion Event */
1228 #define TRB_COMPLETION          33
1229 /* Port Status Change Event */
1230 #define TRB_PORT_STATUS         34
1231 /* Bandwidth Request Event (opt) */
1232 #define TRB_BANDWIDTH_EVENT     35
1233 /* Doorbell Event (opt) */
1234 #define TRB_DOORBELL            36
1235 /* Host Controller Event */
1236 #define TRB_HC_EVENT            37
1237 /* Device Notification Event - device sent function wake notification */
1238 #define TRB_DEV_NOTE            38
1239 /* MFINDEX Wrap Event - microframe counter wrapped */
1240 #define TRB_MFINDEX_WRAP        39
1241 /* TRB IDs 40-47 reserved, 48-63 is vendor-defined */
1242
1243 /* Nec vendor-specific command completion event. */
1244 #define TRB_NEC_CMD_COMP        48
1245 /* Get NEC firmware revision. */
1246 #define TRB_NEC_GET_FW          49
1247
1248 #define TRB_TYPE_LINK(x)        (((x) & TRB_TYPE_BITMASK) == TRB_TYPE(TRB_LINK))
1249 /* Above, but for __le32 types -- can avoid work by swapping constants: */
1250 #define TRB_TYPE_LINK_LE32(x)   (((x) & cpu_to_le32(TRB_TYPE_BITMASK)) == \
1251                                  cpu_to_le32(TRB_TYPE(TRB_LINK)))
1252 #define TRB_TYPE_NOOP_LE32(x)   (((x) & cpu_to_le32(TRB_TYPE_BITMASK)) == \
1253                                  cpu_to_le32(TRB_TYPE(TRB_TR_NOOP)))
1254
1255 #define NEC_FW_MINOR(p)         (((p) >> 0) & 0xff)
1256 #define NEC_FW_MAJOR(p)         (((p) >> 8) & 0xff)
1257
1258 /*
1259  * TRBS_PER_SEGMENT must be a multiple of 4,
1260  * since the command ring is 64-byte aligned.
1261  * It must also be greater than 16.
1262  */
1263 #define TRBS_PER_SEGMENT        64
1264 /* Allow two commands + a link TRB, along with any reserved command TRBs */
1265 #define MAX_RSVD_CMD_TRBS       (TRBS_PER_SEGMENT - 3)
1266 #define TRB_SEGMENT_SIZE        (TRBS_PER_SEGMENT*16)
1267 #define TRB_SEGMENT_SHIFT       (ilog2(TRB_SEGMENT_SIZE))
1268 /* TRB buffer pointers can't cross 64KB boundaries */
1269 #define TRB_MAX_BUFF_SHIFT              16
1270 #define TRB_MAX_BUFF_SIZE       (1 << TRB_MAX_BUFF_SHIFT)
1271
1272 struct xhci_segment {
1273         union xhci_trb          *trbs;
1274         /* private to HCD */
1275         struct xhci_segment     *next;
1276         dma_addr_t              dma;
1277 };
1278
1279 struct xhci_td {
1280         struct list_head        td_list;
1281         struct list_head        cancelled_td_list;
1282         struct urb              *urb;
1283         struct xhci_segment     *start_seg;
1284         union xhci_trb          *first_trb;
1285         union xhci_trb          *last_trb;
1286 };
1287
1288 /* xHCI command default timeout value */
1289 #define XHCI_CMD_DEFAULT_TIMEOUT        (5 * HZ)
1290
1291 /* command descriptor */
1292 struct xhci_cd {
1293         struct list_head        cancel_cmd_list;
1294         struct xhci_command     *command;
1295         union xhci_trb          *cmd_trb;
1296 };
1297
1298 struct xhci_dequeue_state {
1299         struct xhci_segment *new_deq_seg;
1300         union xhci_trb *new_deq_ptr;
1301         int new_cycle_state;
1302 };
1303
1304 enum xhci_ring_type {
1305         TYPE_CTRL = 0,
1306         TYPE_ISOC,
1307         TYPE_BULK,
1308         TYPE_INTR,
1309         TYPE_STREAM,
1310         TYPE_COMMAND,
1311         TYPE_EVENT,
1312 };
1313
1314 struct xhci_ring {
1315         struct xhci_segment     *first_seg;
1316         struct xhci_segment     *last_seg;
1317         union  xhci_trb         *enqueue;
1318         struct xhci_segment     *enq_seg;
1319         unsigned int            enq_updates;
1320         union  xhci_trb         *dequeue;
1321         struct xhci_segment     *deq_seg;
1322         unsigned int            deq_updates;
1323         struct list_head        td_list;
1324         /*
1325          * Write the cycle state into the TRB cycle field to give ownership of
1326          * the TRB to the host controller (if we are the producer), or to check
1327          * if we own the TRB (if we are the consumer).  See section 4.9.1.
1328          */
1329         u32                     cycle_state;
1330         unsigned int            stream_id;
1331         unsigned int            num_segs;
1332         unsigned int            num_trbs_free;
1333         unsigned int            num_trbs_free_temp;
1334         enum xhci_ring_type     type;
1335         bool                    last_td_was_short;
1336 };
1337
1338 struct xhci_erst_entry {
1339         /* 64-bit event ring segment address */
1340         __le64  seg_addr;
1341         __le32  seg_size;
1342         /* Set to zero */
1343         __le32  rsvd;
1344 };
1345
1346 struct xhci_erst {
1347         struct xhci_erst_entry  *entries;
1348         unsigned int            num_entries;
1349         /* xhci->event_ring keeps track of segment dma addresses */
1350         dma_addr_t              erst_dma_addr;
1351         /* Num entries the ERST can contain */
1352         unsigned int            erst_size;
1353 };
1354
1355 struct xhci_scratchpad {
1356         u64 *sp_array;
1357         dma_addr_t sp_dma;
1358         void **sp_buffers;
1359         dma_addr_t *sp_dma_buffers;
1360 };
1361
1362 struct urb_priv {
1363         int     length;
1364         int     td_cnt;
1365         struct  xhci_td *td[0];
1366 };
1367
1368 /*
1369  * Each segment table entry is 4*32bits long.  1K seems like an ok size:
1370  * (1K bytes * 8bytes/bit) / (4*32 bits) = 64 segment entries in the table,
1371  * meaning 64 ring segments.
1372  * Initial allocated size of the ERST, in number of entries */
1373 #define ERST_NUM_SEGS   1
1374 /* Initial allocated size of the ERST, in number of entries */
1375 #define ERST_SIZE       64
1376 /* Initial number of event segment rings allocated */
1377 #define ERST_ENTRIES    1
1378 /* Poll every 60 seconds */
1379 #define POLL_TIMEOUT    60
1380 /* Stop endpoint command timeout (secs) for URB cancellation watchdog timer */
1381 #define XHCI_STOP_EP_CMD_TIMEOUT        5
1382 /* XXX: Make these module parameters */
1383
1384 struct s3_save {
1385         u32     command;
1386         u32     dev_nt;
1387         u64     dcbaa_ptr;
1388         u32     config_reg;
1389         u32     irq_pending;
1390         u32     irq_control;
1391         u32     erst_size;
1392         u64     erst_base;
1393         u64     erst_dequeue;
1394 };
1395
1396 /* Use for lpm */
1397 struct dev_info {
1398         u32                     dev_id;
1399         struct  list_head       list;
1400 };
1401
1402 struct xhci_bus_state {
1403         unsigned long           bus_suspended;
1404         unsigned long           next_statechange;
1405
1406         /* Port suspend arrays are indexed by the portnum of the fake roothub */
1407         /* ports suspend status arrays - max 31 ports for USB2, 15 for USB3 */
1408         u32                     port_c_suspend;
1409         u32                     suspended_ports;
1410         u32                     port_remote_wakeup;
1411         unsigned long           resume_done[USB_MAXCHILDREN];
1412         /* which ports have started to resume */
1413         unsigned long           resuming_ports;
1414         /* Which ports are waiting on RExit to U0 transition. */
1415         unsigned long           rexit_ports;
1416         struct completion       rexit_done[USB_MAXCHILDREN];
1417 };
1418
1419
1420 /*
1421  * It can take up to 20 ms to transition from RExit to U0 on the
1422  * Intel Lynx Point LP xHCI host.
1423  */
1424 #define XHCI_MAX_REXIT_TIMEOUT  (20 * 1000)
1425
1426 static inline unsigned int hcd_index(struct usb_hcd *hcd)
1427 {
1428         if (hcd->speed == HCD_USB3)
1429                 return 0;
1430         else
1431                 return 1;
1432 }
1433
1434 /* There is one xhci_hcd structure per controller */
1435 struct xhci_hcd {
1436         struct usb_hcd *main_hcd;
1437         struct usb_hcd *shared_hcd;
1438         /* glue to PCI and HCD framework */
1439         struct xhci_cap_regs __iomem *cap_regs;
1440         struct xhci_op_regs __iomem *op_regs;
1441         struct xhci_run_regs __iomem *run_regs;
1442         struct xhci_doorbell_array __iomem *dba;
1443         /* Our HCD's current interrupter register set */
1444         struct  xhci_intr_reg __iomem *ir_set;
1445
1446         /* Cached register copies of read-only HC data */
1447         __u32           hcs_params1;
1448         __u32           hcs_params2;
1449         __u32           hcs_params3;
1450         __u32           hcc_params;
1451
1452         spinlock_t      lock;
1453
1454         /* packed release number */
1455         u8              sbrn;
1456         u16             hci_version;
1457         u8              max_slots;
1458         u8              max_interrupters;
1459         u8              max_ports;
1460         u8              isoc_threshold;
1461         int             event_ring_max;
1462         int             addr_64;
1463         /* 4KB min, 128MB max */
1464         int             page_size;
1465         /* Valid values are 12 to 20, inclusive */
1466         int             page_shift;
1467         /* msi-x vectors */
1468         int             msix_count;
1469         struct msix_entry       *msix_entries;
1470         /* data structures */
1471         struct xhci_device_context_array *dcbaa;
1472         struct xhci_ring        *cmd_ring;
1473         unsigned int            cmd_ring_state;
1474 #define CMD_RING_STATE_RUNNING         (1 << 0)
1475 #define CMD_RING_STATE_ABORTED         (1 << 1)
1476 #define CMD_RING_STATE_STOPPED         (1 << 2)
1477         struct list_head        cancel_cmd_list;
1478         unsigned int            cmd_ring_reserved_trbs;
1479         struct xhci_ring        *event_ring;
1480         struct xhci_erst        erst;
1481         /* Scratchpad */
1482         struct xhci_scratchpad  *scratchpad;
1483         /* Store LPM test failed devices' information */
1484         struct list_head        lpm_failed_devs;
1485
1486         /* slot enabling and address device helpers */
1487         struct completion       addr_dev;
1488         int slot_id;
1489         /* For USB 3.0 LPM enable/disable. */
1490         struct xhci_command             *lpm_command;
1491         /* Internal mirror of the HW's dcbaa */
1492         struct xhci_virt_device *devs[MAX_HC_SLOTS];
1493         /* For keeping track of bandwidth domains per roothub. */
1494         struct xhci_root_port_bw_info   *rh_bw;
1495
1496         /* DMA pools */
1497         struct dma_pool *device_pool;
1498         struct dma_pool *segment_pool;
1499         struct dma_pool *small_streams_pool;
1500         struct dma_pool *medium_streams_pool;
1501
1502         /* Host controller watchdog timer structures */
1503         unsigned int            xhc_state;
1504
1505         u32                     command;
1506         struct s3_save          s3;
1507 /* Host controller is dying - not responding to commands. "I'm not dead yet!"
1508  *
1509  * xHC interrupts have been disabled and a watchdog timer will (or has already)
1510  * halt the xHCI host, and complete all URBs with an -ESHUTDOWN code.  Any code
1511  * that sees this status (other than the timer that set it) should stop touching
1512  * hardware immediately.  Interrupt handlers should return immediately when
1513  * they see this status (any time they drop and re-acquire xhci->lock).
1514  * xhci_urb_dequeue() should call usb_hcd_check_unlink_urb() and return without
1515  * putting the TD on the canceled list, etc.
1516  *
1517  * There are no reports of xHCI host controllers that display this issue.
1518  */
1519 #define XHCI_STATE_DYING        (1 << 0)
1520 #define XHCI_STATE_HALTED       (1 << 1)
1521         /* Statistics */
1522         int                     error_bitmask;
1523         unsigned int            quirks;
1524 #define XHCI_LINK_TRB_QUIRK     (1 << 0)
1525 #define XHCI_RESET_EP_QUIRK     (1 << 1)
1526 #define XHCI_NEC_HOST           (1 << 2)
1527 #define XHCI_AMD_PLL_FIX        (1 << 3)
1528 #define XHCI_SPURIOUS_SUCCESS   (1 << 4)
1529 /*
1530  * Certain Intel host controllers have a limit to the number of endpoint
1531  * contexts they can handle.  Ideally, they would signal that they can't handle
1532  * anymore endpoint contexts by returning a Resource Error for the Configure
1533  * Endpoint command, but they don't.  Instead they expect software to keep track
1534  * of the number of active endpoints for them, across configure endpoint
1535  * commands, reset device commands, disable slot commands, and address device
1536  * commands.
1537  */
1538 #define XHCI_EP_LIMIT_QUIRK     (1 << 5)
1539 #define XHCI_BROKEN_MSI         (1 << 6)
1540 #define XHCI_RESET_ON_RESUME    (1 << 7)
1541 #define XHCI_SW_BW_CHECKING     (1 << 8)
1542 #define XHCI_AMD_0x96_HOST      (1 << 9)
1543 #define XHCI_TRUST_TX_LENGTH    (1 << 10)
1544 #define XHCI_LPM_SUPPORT        (1 << 11)
1545 #define XHCI_INTEL_HOST         (1 << 12)
1546 #define XHCI_SPURIOUS_REBOOT    (1 << 13)
1547 #define XHCI_COMP_MODE_QUIRK    (1 << 14)
1548 #define XHCI_AVOID_BEI          (1 << 15)
1549 #define XHCI_PLAT               (1 << 16)
1550 #define XHCI_SLOW_SUSPEND       (1 << 17)
1551 #define XHCI_SPURIOUS_WAKEUP    (1 << 18)
1552         unsigned int            num_active_eps;
1553         unsigned int            limit_active_eps;
1554         /* There are two roothubs to keep track of bus suspend info for */
1555         struct xhci_bus_state   bus_state[2];
1556         /* Is each xHCI roothub port a USB 3.0, USB 2.0, or USB 1.1 port? */
1557         u8                      *port_array;
1558         /* Array of pointers to USB 3.0 PORTSC registers */
1559         __le32 __iomem          **usb3_ports;
1560         unsigned int            num_usb3_ports;
1561         /* Array of pointers to USB 2.0 PORTSC registers */
1562         __le32 __iomem          **usb2_ports;
1563         unsigned int            num_usb2_ports;
1564         /* support xHCI 0.96 spec USB2 software LPM */
1565         unsigned                sw_lpm_support:1;
1566         /* support xHCI 1.0 spec USB2 hardware LPM */
1567         unsigned                hw_lpm_support:1;
1568         /* cached usb2 extened protocol capabilites */
1569         u32                     *ext_caps;
1570         unsigned int            num_ext_caps;
1571         /* Compliance Mode Recovery Data */
1572         struct timer_list       comp_mode_recovery_timer;
1573         u32                     port_status_u0;
1574 /* Compliance Mode Timer Triggered every 2 seconds */
1575 #define COMP_MODE_RCVRY_MSECS 2000
1576 };
1577
1578 /* convert between an HCD pointer and the corresponding EHCI_HCD */
1579 static inline struct xhci_hcd *hcd_to_xhci(struct usb_hcd *hcd)
1580 {
1581         return *((struct xhci_hcd **) (hcd->hcd_priv));
1582 }
1583
1584 static inline struct usb_hcd *xhci_to_hcd(struct xhci_hcd *xhci)
1585 {
1586         return xhci->main_hcd;
1587 }
1588
1589 #define xhci_dbg(xhci, fmt, args...) \
1590         dev_dbg(xhci_to_hcd(xhci)->self.controller , fmt , ## args)
1591 #define xhci_err(xhci, fmt, args...) \
1592         dev_err(xhci_to_hcd(xhci)->self.controller , fmt , ## args)
1593 #define xhci_warn(xhci, fmt, args...) \
1594         dev_warn(xhci_to_hcd(xhci)->self.controller , fmt , ## args)
1595 #define xhci_warn_ratelimited(xhci, fmt, args...) \
1596         dev_warn_ratelimited(xhci_to_hcd(xhci)->self.controller , fmt , ## args)
1597
1598 /* TODO: copied from ehci.h - can be refactored? */
1599 /* xHCI spec says all registers are little endian */
1600 static inline unsigned int xhci_readl(const struct xhci_hcd *xhci,
1601                 __le32 __iomem *regs)
1602 {
1603         return readl(regs);
1604 }
1605 static inline void xhci_writel(struct xhci_hcd *xhci,
1606                 const unsigned int val, __le32 __iomem *regs)
1607 {
1608         writel(val, regs);
1609 }
1610
1611 /*
1612  * Registers should always be accessed with double word or quad word accesses.
1613  *
1614  * Some xHCI implementations may support 64-bit address pointers.  Registers
1615  * with 64-bit address pointers should be written to with dword accesses by
1616  * writing the low dword first (ptr[0]), then the high dword (ptr[1]) second.
1617  * xHCI implementations that do not support 64-bit address pointers will ignore
1618  * the high dword, and write order is irrelevant.
1619  */
1620 static inline u64 xhci_read_64(const struct xhci_hcd *xhci,
1621                 __le64 __iomem *regs)
1622 {
1623         __u32 __iomem *ptr = (__u32 __iomem *) regs;
1624         u64 val_lo = readl(ptr);
1625         u64 val_hi = readl(ptr + 1);
1626         return val_lo + (val_hi << 32);
1627 }
1628 static inline void xhci_write_64(struct xhci_hcd *xhci,
1629                                  const u64 val, __le64 __iomem *regs)
1630 {
1631         __u32 __iomem *ptr = (__u32 __iomem *) regs;
1632         u32 val_lo = lower_32_bits(val);
1633         u32 val_hi = upper_32_bits(val);
1634
1635         writel(val_lo, ptr);
1636         writel(val_hi, ptr + 1);
1637 }
1638
1639 static inline int xhci_link_trb_quirk(struct xhci_hcd *xhci)
1640 {
1641         return xhci->quirks & XHCI_LINK_TRB_QUIRK;
1642 }
1643
1644 /* xHCI debugging */
1645 void xhci_print_ir_set(struct xhci_hcd *xhci, int set_num);
1646 void xhci_print_registers(struct xhci_hcd *xhci);
1647 void xhci_dbg_regs(struct xhci_hcd *xhci);
1648 void xhci_print_run_regs(struct xhci_hcd *xhci);
1649 void xhci_print_trb_offsets(struct xhci_hcd *xhci, union xhci_trb *trb);
1650 void xhci_debug_trb(struct xhci_hcd *xhci, union xhci_trb *trb);
1651 void xhci_debug_segment(struct xhci_hcd *xhci, struct xhci_segment *seg);
1652 void xhci_debug_ring(struct xhci_hcd *xhci, struct xhci_ring *ring);
1653 void xhci_dbg_erst(struct xhci_hcd *xhci, struct xhci_erst *erst);
1654 void xhci_dbg_cmd_ptrs(struct xhci_hcd *xhci);
1655 void xhci_dbg_ring_ptrs(struct xhci_hcd *xhci, struct xhci_ring *ring);
1656 void xhci_dbg_ctx(struct xhci_hcd *xhci, struct xhci_container_ctx *ctx, unsigned int last_ep);
1657 char *xhci_get_slot_state(struct xhci_hcd *xhci,
1658                 struct xhci_container_ctx *ctx);
1659 void xhci_dbg_ep_rings(struct xhci_hcd *xhci,
1660                 unsigned int slot_id, unsigned int ep_index,
1661                 struct xhci_virt_ep *ep);
1662 void xhci_dbg_trace(struct xhci_hcd *xhci, void (*trace)(struct va_format *),
1663                         const char *fmt, ...);
1664
1665 /* xHCI memory management */
1666 void xhci_mem_cleanup(struct xhci_hcd *xhci);
1667 int xhci_mem_init(struct xhci_hcd *xhci, gfp_t flags);
1668 void xhci_free_virt_device(struct xhci_hcd *xhci, int slot_id);
1669 int xhci_alloc_virt_device(struct xhci_hcd *xhci, int slot_id, struct usb_device *udev, gfp_t flags);
1670 int xhci_setup_addressable_virt_dev(struct xhci_hcd *xhci, struct usb_device *udev);
1671 void xhci_copy_ep0_dequeue_into_input_ctx(struct xhci_hcd *xhci,
1672                 struct usb_device *udev);
1673 unsigned int xhci_get_endpoint_index(struct usb_endpoint_descriptor *desc);
1674 unsigned int xhci_get_endpoint_address(unsigned int ep_index);
1675 unsigned int xhci_get_endpoint_flag(struct usb_endpoint_descriptor *desc);
1676 unsigned int xhci_get_endpoint_flag_from_index(unsigned int ep_index);
1677 unsigned int xhci_last_valid_endpoint(u32 added_ctxs);
1678 void xhci_endpoint_zero(struct xhci_hcd *xhci, struct xhci_virt_device *virt_dev, struct usb_host_endpoint *ep);
1679 void xhci_drop_ep_from_interval_table(struct xhci_hcd *xhci,
1680                 struct xhci_bw_info *ep_bw,
1681                 struct xhci_interval_bw_table *bw_table,
1682                 struct usb_device *udev,
1683                 struct xhci_virt_ep *virt_ep,
1684                 struct xhci_tt_bw_info *tt_info);
1685 void xhci_update_tt_active_eps(struct xhci_hcd *xhci,
1686                 struct xhci_virt_device *virt_dev,
1687                 int old_active_eps);
1688 void xhci_clear_endpoint_bw_info(struct xhci_bw_info *bw_info);
1689 void xhci_update_bw_info(struct xhci_hcd *xhci,
1690                 struct xhci_container_ctx *in_ctx,
1691                 struct xhci_input_control_ctx *ctrl_ctx,
1692                 struct xhci_virt_device *virt_dev);
1693 void xhci_endpoint_copy(struct xhci_hcd *xhci,
1694                 struct xhci_container_ctx *in_ctx,
1695                 struct xhci_container_ctx *out_ctx,
1696                 unsigned int ep_index);
1697 void xhci_slot_copy(struct xhci_hcd *xhci,
1698                 struct xhci_container_ctx *in_ctx,
1699                 struct xhci_container_ctx *out_ctx);
1700 int xhci_endpoint_init(struct xhci_hcd *xhci, struct xhci_virt_device *virt_dev,
1701                 struct usb_device *udev, struct usb_host_endpoint *ep,
1702                 gfp_t mem_flags);
1703 void xhci_ring_free(struct xhci_hcd *xhci, struct xhci_ring *ring);
1704 int xhci_ring_expansion(struct xhci_hcd *xhci, struct xhci_ring *ring,
1705                                 unsigned int num_trbs, gfp_t flags);
1706 void xhci_free_or_cache_endpoint_ring(struct xhci_hcd *xhci,
1707                 struct xhci_virt_device *virt_dev,
1708                 unsigned int ep_index);
1709 struct xhci_stream_info *xhci_alloc_stream_info(struct xhci_hcd *xhci,
1710                 unsigned int num_stream_ctxs,
1711                 unsigned int num_streams, gfp_t flags);
1712 void xhci_free_stream_info(struct xhci_hcd *xhci,
1713                 struct xhci_stream_info *stream_info);
1714 void xhci_setup_streams_ep_input_ctx(struct xhci_hcd *xhci,
1715                 struct xhci_ep_ctx *ep_ctx,
1716                 struct xhci_stream_info *stream_info);
1717 void xhci_setup_no_streams_ep_input_ctx(struct xhci_hcd *xhci,
1718                 struct xhci_ep_ctx *ep_ctx,
1719                 struct xhci_virt_ep *ep);
1720 void xhci_free_device_endpoint_resources(struct xhci_hcd *xhci,
1721         struct xhci_virt_device *virt_dev, bool drop_control_ep);
1722 struct xhci_ring *xhci_dma_to_transfer_ring(
1723                 struct xhci_virt_ep *ep,
1724                 u64 address);
1725 struct xhci_ring *xhci_stream_id_to_ring(
1726                 struct xhci_virt_device *dev,
1727                 unsigned int ep_index,
1728                 unsigned int stream_id);
1729 struct xhci_command *xhci_alloc_command(struct xhci_hcd *xhci,
1730                 bool allocate_in_ctx, bool allocate_completion,
1731                 gfp_t mem_flags);
1732 void xhci_urb_free_priv(struct xhci_hcd *xhci, struct urb_priv *urb_priv);
1733 void xhci_free_command(struct xhci_hcd *xhci,
1734                 struct xhci_command *command);
1735
1736 #ifdef CONFIG_PCI
1737 /* xHCI PCI glue */
1738 int xhci_register_pci(void);
1739 void xhci_unregister_pci(void);
1740 #else
1741 static inline int xhci_register_pci(void) { return 0; }
1742 static inline void xhci_unregister_pci(void) {}
1743 #endif
1744
1745 #if defined(CONFIG_USB_XHCI_PLATFORM) \
1746         || defined(CONFIG_USB_XHCI_PLATFORM_MODULE)
1747 int xhci_register_plat(void);
1748 void xhci_unregister_plat(void);
1749 #else
1750 static inline int xhci_register_plat(void)
1751 { return 0; }
1752 static inline void xhci_unregister_plat(void)
1753 {  }
1754 #endif
1755
1756 /* xHCI host controller glue */
1757 typedef void (*xhci_get_quirks_t)(struct device *, struct xhci_hcd *);
1758 int xhci_handshake(struct xhci_hcd *xhci, void __iomem *ptr,
1759                 u32 mask, u32 done, int usec);
1760 void xhci_quiesce(struct xhci_hcd *xhci);
1761 int xhci_halt(struct xhci_hcd *xhci);
1762 int xhci_reset(struct xhci_hcd *xhci);
1763 int xhci_init(struct usb_hcd *hcd);
1764 int xhci_run(struct usb_hcd *hcd);
1765 void xhci_stop(struct usb_hcd *hcd);
1766 void xhci_shutdown(struct usb_hcd *hcd);
1767 int xhci_gen_setup(struct usb_hcd *hcd, xhci_get_quirks_t get_quirks);
1768
1769 #ifdef  CONFIG_PM
1770 int xhci_suspend(struct xhci_hcd *xhci);
1771 int xhci_resume(struct xhci_hcd *xhci, bool hibernated);
1772 #else
1773 #define xhci_suspend    NULL
1774 #define xhci_resume     NULL
1775 #endif
1776
1777 int xhci_get_frame(struct usb_hcd *hcd);
1778 irqreturn_t xhci_irq(struct usb_hcd *hcd);
1779 irqreturn_t xhci_msi_irq(int irq, void *hcd);
1780 int xhci_alloc_dev(struct usb_hcd *hcd, struct usb_device *udev);
1781 void xhci_free_dev(struct usb_hcd *hcd, struct usb_device *udev);
1782 int xhci_alloc_tt_info(struct xhci_hcd *xhci,
1783                 struct xhci_virt_device *virt_dev,
1784                 struct usb_device *hdev,
1785                 struct usb_tt *tt, gfp_t mem_flags);
1786 int xhci_alloc_streams(struct usb_hcd *hcd, struct usb_device *udev,
1787                 struct usb_host_endpoint **eps, unsigned int num_eps,
1788                 unsigned int num_streams, gfp_t mem_flags);
1789 int xhci_free_streams(struct usb_hcd *hcd, struct usb_device *udev,
1790                 struct usb_host_endpoint **eps, unsigned int num_eps,
1791                 gfp_t mem_flags);
1792 int xhci_address_device(struct usb_hcd *hcd, struct usb_device *udev);
1793 int xhci_update_device(struct usb_hcd *hcd, struct usb_device *udev);
1794 int xhci_set_usb2_hardware_lpm(struct usb_hcd *hcd,
1795                                 struct usb_device *udev, int enable);
1796 int xhci_update_hub_device(struct usb_hcd *hcd, struct usb_device *hdev,
1797                         struct usb_tt *tt, gfp_t mem_flags);
1798 int xhci_urb_enqueue(struct usb_hcd *hcd, struct urb *urb, gfp_t mem_flags);
1799 int xhci_urb_dequeue(struct usb_hcd *hcd, struct urb *urb, int status);
1800 int xhci_add_endpoint(struct usb_hcd *hcd, struct usb_device *udev, struct usb_host_endpoint *ep);
1801 int xhci_drop_endpoint(struct usb_hcd *hcd, struct usb_device *udev, struct usb_host_endpoint *ep);
1802 void xhci_endpoint_reset(struct usb_hcd *hcd, struct usb_host_endpoint *ep);
1803 int xhci_discover_or_reset_device(struct usb_hcd *hcd, struct usb_device *udev);
1804 int xhci_check_bandwidth(struct usb_hcd *hcd, struct usb_device *udev);
1805 void xhci_reset_bandwidth(struct usb_hcd *hcd, struct usb_device *udev);
1806
1807 /* xHCI ring, segment, TRB, and TD functions */
1808 dma_addr_t xhci_trb_virt_to_dma(struct xhci_segment *seg, union xhci_trb *trb);
1809 struct xhci_segment *trb_in_td(struct xhci_segment *start_seg,
1810                 union xhci_trb *start_trb, union xhci_trb *end_trb,
1811                 dma_addr_t suspect_dma);
1812 int xhci_is_vendor_info_code(struct xhci_hcd *xhci, unsigned int trb_comp_code);
1813 void xhci_ring_cmd_db(struct xhci_hcd *xhci);
1814 int xhci_queue_slot_control(struct xhci_hcd *xhci, u32 trb_type, u32 slot_id);
1815 int xhci_queue_address_device(struct xhci_hcd *xhci, dma_addr_t in_ctx_ptr,
1816                 u32 slot_id);
1817 int xhci_queue_vendor_command(struct xhci_hcd *xhci,
1818                 u32 field1, u32 field2, u32 field3, u32 field4);
1819 int xhci_queue_stop_endpoint(struct xhci_hcd *xhci, int slot_id,
1820                 unsigned int ep_index, int suspend);
1821 int xhci_queue_ctrl_tx(struct xhci_hcd *xhci, gfp_t mem_flags, struct urb *urb,
1822                 int slot_id, unsigned int ep_index);
1823 int xhci_queue_bulk_tx(struct xhci_hcd *xhci, gfp_t mem_flags, struct urb *urb,
1824                 int slot_id, unsigned int ep_index);
1825 int xhci_queue_intr_tx(struct xhci_hcd *xhci, gfp_t mem_flags, struct urb *urb,
1826                 int slot_id, unsigned int ep_index);
1827 int xhci_queue_isoc_tx_prepare(struct xhci_hcd *xhci, gfp_t mem_flags,
1828                 struct urb *urb, int slot_id, unsigned int ep_index);
1829 int xhci_queue_configure_endpoint(struct xhci_hcd *xhci, dma_addr_t in_ctx_ptr,
1830                 u32 slot_id, bool command_must_succeed);
1831 int xhci_queue_evaluate_context(struct xhci_hcd *xhci, dma_addr_t in_ctx_ptr,
1832                 u32 slot_id, bool command_must_succeed);
1833 int xhci_queue_reset_ep(struct xhci_hcd *xhci, int slot_id,
1834                 unsigned int ep_index);
1835 int xhci_queue_reset_device(struct xhci_hcd *xhci, u32 slot_id);
1836 void xhci_find_new_dequeue_state(struct xhci_hcd *xhci,
1837                 unsigned int slot_id, unsigned int ep_index,
1838                 unsigned int stream_id, struct xhci_td *cur_td,
1839                 struct xhci_dequeue_state *state);
1840 void xhci_queue_new_dequeue_state(struct xhci_hcd *xhci,
1841                 unsigned int slot_id, unsigned int ep_index,
1842                 unsigned int stream_id,
1843                 struct xhci_dequeue_state *deq_state);
1844 void xhci_cleanup_stalled_ring(struct xhci_hcd *xhci,
1845                 struct usb_device *udev, unsigned int ep_index);
1846 void xhci_queue_config_ep_quirk(struct xhci_hcd *xhci,
1847                 unsigned int slot_id, unsigned int ep_index,
1848                 struct xhci_dequeue_state *deq_state);
1849 void xhci_stop_endpoint_command_watchdog(unsigned long arg);
1850 int xhci_cancel_cmd(struct xhci_hcd *xhci, struct xhci_command *command,
1851                 union xhci_trb *cmd_trb);
1852 void xhci_ring_ep_doorbell(struct xhci_hcd *xhci, unsigned int slot_id,
1853                 unsigned int ep_index, unsigned int stream_id);
1854 union xhci_trb *xhci_find_next_enqueue(struct xhci_ring *ring);
1855
1856 /* xHCI roothub code */
1857 void xhci_set_link_state(struct xhci_hcd *xhci, __le32 __iomem **port_array,
1858                                 int port_id, u32 link_state);
1859 int xhci_enable_usb3_lpm_timeout(struct usb_hcd *hcd,
1860                         struct usb_device *udev, enum usb3_link_state state);
1861 int xhci_disable_usb3_lpm_timeout(struct usb_hcd *hcd,
1862                         struct usb_device *udev, enum usb3_link_state state);
1863 void xhci_test_and_clear_bit(struct xhci_hcd *xhci, __le32 __iomem **port_array,
1864                                 int port_id, u32 port_bit);
1865 int xhci_hub_control(struct usb_hcd *hcd, u16 typeReq, u16 wValue, u16 wIndex,
1866                 char *buf, u16 wLength);
1867 int xhci_hub_status_data(struct usb_hcd *hcd, char *buf);
1868 int xhci_find_raw_port_number(struct usb_hcd *hcd, int port1);
1869
1870 #ifdef CONFIG_PM
1871 int xhci_bus_suspend(struct usb_hcd *hcd);
1872 int xhci_bus_resume(struct usb_hcd *hcd);
1873 #else
1874 #define xhci_bus_suspend        NULL
1875 #define xhci_bus_resume         NULL
1876 #endif  /* CONFIG_PM */
1877
1878 u32 xhci_port_state_to_neutral(u32 state);
1879 int xhci_find_slot_id_by_port(struct usb_hcd *hcd, struct xhci_hcd *xhci,
1880                 u16 port);
1881 void xhci_ring_device(struct xhci_hcd *xhci, int slot_id);
1882
1883 /* xHCI contexts */
1884 struct xhci_input_control_ctx *xhci_get_input_control_ctx(struct xhci_hcd *xhci, struct xhci_container_ctx *ctx);
1885 struct xhci_slot_ctx *xhci_get_slot_ctx(struct xhci_hcd *xhci, struct xhci_container_ctx *ctx);
1886 struct xhci_ep_ctx *xhci_get_ep_ctx(struct xhci_hcd *xhci, struct xhci_container_ctx *ctx, unsigned int ep_index);
1887
1888 /* xHCI quirks */
1889 bool xhci_compliance_mode_recovery_timer_quirk_check(void);
1890
1891 #endif /* __LINUX_XHCI_HCD_H */