arch/metag/include/asm/cache.h

   1 #ifndef __ASM_METAG_CACHE_H
   2 #define __ASM_METAG_CACHE_H
   3
   4 /* L1 cache line size (64 bytes) */
   5 #define L1_CACHE_SHIFT          6
   6 #define L1_CACHE_BYTES          (1 << L1_CACHE_SHIFT)
   7
   8 /* Meta requires large data items to be 8 byte aligned. */
   9 #define ARCH_SLAB_MINALIGN      8
  10
  11 /*
  12  * With an L2 cache, we may invalidate dirty lines, so we need to ensure DMA
  13  * buffers have cache line alignment.
  14  */
  15 #ifdef CONFIG_METAG_L2C
  16 #define ARCH_DMA_MINALIGN       L1_CACHE_BYTES
  17 #else
  18 #define ARCH_DMA_MINALIGN       8
  19 #endif
  20
  21 #define __read_mostly __attribute__((__section__(".data..read_mostly")))
  22
  23 #endif