3 * Copyright (C) 2013 Texas Instruments Incorporated
5 * Interconnects common for AM335x and AM43x
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation version 2.
11 * This program is distributed "as is" WITHOUT ANY WARRANTY of any
12 * kind, whether express or implied; without even the implied warranty
13 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
17 #include <linux/sizes.h>
18 #include "omap_hwmod.h"
19 #include "omap_hwmod_33xx_43xx_common_data.h"
22 struct omap_hwmod_ocp_if am33xx_mpu__l3_main
= {
23 .master
= &am33xx_mpu_hwmod
,
24 .slave
= &am33xx_l3_main_hwmod
,
25 .clk
= "dpll_mpu_m2_ck",
30 struct omap_hwmod_ocp_if am33xx_l3_main__l3_s
= {
31 .master
= &am33xx_l3_main_hwmod
,
32 .slave
= &am33xx_l3_s_hwmod
,
34 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
37 /* l3 s -> l4 per/ls */
38 struct omap_hwmod_ocp_if am33xx_l3_s__l4_ls
= {
39 .master
= &am33xx_l3_s_hwmod
,
40 .slave
= &am33xx_l4_ls_hwmod
,
42 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
46 struct omap_hwmod_ocp_if am33xx_l3_s__l4_wkup
= {
47 .master
= &am33xx_l3_s_hwmod
,
48 .slave
= &am33xx_l4_wkup_hwmod
,
50 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
53 /* l3 main -> l3 instr */
54 struct omap_hwmod_ocp_if am33xx_l3_main__l3_instr
= {
55 .master
= &am33xx_l3_main_hwmod
,
56 .slave
= &am33xx_l3_instr_hwmod
,
58 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
62 struct omap_hwmod_ocp_if am33xx_mpu__prcm
= {
63 .master
= &am33xx_mpu_hwmod
,
64 .slave
= &am33xx_prcm_hwmod
,
65 .clk
= "dpll_mpu_m2_ck",
66 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
70 struct omap_hwmod_ocp_if am33xx_l3_s__l3_main
= {
71 .master
= &am33xx_l3_s_hwmod
,
72 .slave
= &am33xx_l3_main_hwmod
,
74 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
77 /* pru-icss -> l3 main */
78 struct omap_hwmod_ocp_if am33xx_pruss__l3_main
= {
79 .master
= &am33xx_pruss_hwmod
,
80 .slave
= &am33xx_l3_main_hwmod
,
82 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
86 struct omap_hwmod_ocp_if am33xx_gfx__l3_main
= {
87 .master
= &am33xx_gfx_hwmod
,
88 .slave
= &am33xx_l3_main_hwmod
,
89 .clk
= "dpll_core_m4_ck",
90 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
94 struct omap_hwmod_ocp_if am33xx_l3_main__gfx
= {
95 .master
= &am33xx_l3_main_hwmod
,
96 .slave
= &am33xx_gfx_hwmod
,
97 .clk
= "dpll_core_m4_ck",
98 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
102 struct omap_hwmod_ocp_if am33xx_l4_wkup__rtc
= {
103 .master
= &am33xx_l4_wkup_hwmod
,
104 .slave
= &am33xx_rtc_hwmod
,
105 .clk
= "clkdiv32k_ick",
106 .user
= OCP_USER_MPU
,
109 /* l4 per/ls -> DCAN0 */
110 struct omap_hwmod_ocp_if am33xx_l4_per__dcan0
= {
111 .master
= &am33xx_l4_ls_hwmod
,
112 .slave
= &am33xx_dcan0_hwmod
,
114 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
117 /* l4 per/ls -> DCAN1 */
118 struct omap_hwmod_ocp_if am33xx_l4_per__dcan1
= {
119 .master
= &am33xx_l4_ls_hwmod
,
120 .slave
= &am33xx_dcan1_hwmod
,
122 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
125 /* l4 per/ls -> GPIO2 */
126 struct omap_hwmod_ocp_if am33xx_l4_per__gpio1
= {
127 .master
= &am33xx_l4_ls_hwmod
,
128 .slave
= &am33xx_gpio1_hwmod
,
130 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
133 /* l4 per/ls -> gpio3 */
134 struct omap_hwmod_ocp_if am33xx_l4_per__gpio2
= {
135 .master
= &am33xx_l4_ls_hwmod
,
136 .slave
= &am33xx_gpio2_hwmod
,
138 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
141 /* l4 per/ls -> gpio4 */
142 struct omap_hwmod_ocp_if am33xx_l4_per__gpio3
= {
143 .master
= &am33xx_l4_ls_hwmod
,
144 .slave
= &am33xx_gpio3_hwmod
,
146 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
149 struct omap_hwmod_ocp_if am33xx_cpgmac0__mdio
= {
150 .master
= &am33xx_cpgmac0_hwmod
,
151 .slave
= &am33xx_mdio_hwmod
,
152 .user
= OCP_USER_MPU
,
155 static struct omap_hwmod_addr_space am33xx_elm_addr_space
[] = {
157 .pa_start
= 0x48080000,
158 .pa_end
= 0x48080000 + SZ_8K
- 1,
159 .flags
= ADDR_TYPE_RT
164 struct omap_hwmod_ocp_if am33xx_l4_ls__elm
= {
165 .master
= &am33xx_l4_ls_hwmod
,
166 .slave
= &am33xx_elm_hwmod
,
168 .addr
= am33xx_elm_addr_space
,
169 .user
= OCP_USER_MPU
,
172 static struct omap_hwmod_addr_space am33xx_epwmss0_addr_space
[] = {
174 .pa_start
= 0x48300000,
175 .pa_end
= 0x48300000 + SZ_16
- 1,
176 .flags
= ADDR_TYPE_RT
181 struct omap_hwmod_ocp_if am33xx_l4_ls__epwmss0
= {
182 .master
= &am33xx_l4_ls_hwmod
,
183 .slave
= &am33xx_epwmss0_hwmod
,
185 .addr
= am33xx_epwmss0_addr_space
,
186 .user
= OCP_USER_MPU
,
189 struct omap_hwmod_ocp_if am33xx_epwmss0__ecap0
= {
190 .master
= &am33xx_epwmss0_hwmod
,
191 .slave
= &am33xx_ecap0_hwmod
,
193 .user
= OCP_USER_MPU
,
196 struct omap_hwmod_ocp_if am33xx_epwmss0__eqep0
= {
197 .master
= &am33xx_epwmss0_hwmod
,
198 .slave
= &am33xx_eqep0_hwmod
,
200 .user
= OCP_USER_MPU
,
203 struct omap_hwmod_ocp_if am33xx_epwmss0__ehrpwm0
= {
204 .master
= &am33xx_epwmss0_hwmod
,
205 .slave
= &am33xx_ehrpwm0_hwmod
,
207 .user
= OCP_USER_MPU
,
211 static struct omap_hwmod_addr_space am33xx_epwmss1_addr_space
[] = {
213 .pa_start
= 0x48302000,
214 .pa_end
= 0x48302000 + SZ_16
- 1,
215 .flags
= ADDR_TYPE_RT
220 struct omap_hwmod_ocp_if am33xx_l4_ls__epwmss1
= {
221 .master
= &am33xx_l4_ls_hwmod
,
222 .slave
= &am33xx_epwmss1_hwmod
,
224 .addr
= am33xx_epwmss1_addr_space
,
225 .user
= OCP_USER_MPU
,
228 struct omap_hwmod_ocp_if am33xx_epwmss1__ecap1
= {
229 .master
= &am33xx_epwmss1_hwmod
,
230 .slave
= &am33xx_ecap1_hwmod
,
232 .user
= OCP_USER_MPU
,
235 struct omap_hwmod_ocp_if am33xx_epwmss1__eqep1
= {
236 .master
= &am33xx_epwmss1_hwmod
,
237 .slave
= &am33xx_eqep1_hwmod
,
239 .user
= OCP_USER_MPU
,
242 struct omap_hwmod_ocp_if am33xx_epwmss1__ehrpwm1
= {
243 .master
= &am33xx_epwmss1_hwmod
,
244 .slave
= &am33xx_ehrpwm1_hwmod
,
246 .user
= OCP_USER_MPU
,
249 static struct omap_hwmod_addr_space am33xx_epwmss2_addr_space
[] = {
251 .pa_start
= 0x48304000,
252 .pa_end
= 0x48304000 + SZ_16
- 1,
253 .flags
= ADDR_TYPE_RT
258 struct omap_hwmod_ocp_if am33xx_l4_ls__epwmss2
= {
259 .master
= &am33xx_l4_ls_hwmod
,
260 .slave
= &am33xx_epwmss2_hwmod
,
262 .addr
= am33xx_epwmss2_addr_space
,
263 .user
= OCP_USER_MPU
,
266 struct omap_hwmod_ocp_if am33xx_epwmss2__ecap2
= {
267 .master
= &am33xx_epwmss2_hwmod
,
268 .slave
= &am33xx_ecap2_hwmod
,
270 .user
= OCP_USER_MPU
,
273 struct omap_hwmod_ocp_if am33xx_epwmss2__eqep2
= {
274 .master
= &am33xx_epwmss2_hwmod
,
275 .slave
= &am33xx_eqep2_hwmod
,
277 .user
= OCP_USER_MPU
,
280 struct omap_hwmod_ocp_if am33xx_epwmss2__ehrpwm2
= {
281 .master
= &am33xx_epwmss2_hwmod
,
282 .slave
= &am33xx_ehrpwm2_hwmod
,
284 .user
= OCP_USER_MPU
,
287 /* l3s cfg -> gpmc */
288 static struct omap_hwmod_addr_space am33xx_gpmc_addr_space
[] = {
290 .pa_start
= 0x50000000,
291 .pa_end
= 0x50000000 + SZ_8K
- 1,
292 .flags
= ADDR_TYPE_RT
,
297 struct omap_hwmod_ocp_if am33xx_l3_s__gpmc
= {
298 .master
= &am33xx_l3_s_hwmod
,
299 .slave
= &am33xx_gpmc_hwmod
,
301 .addr
= am33xx_gpmc_addr_space
,
302 .user
= OCP_USER_MPU
,
306 struct omap_hwmod_ocp_if am33xx_l4_per__i2c2
= {
307 .master
= &am33xx_l4_ls_hwmod
,
308 .slave
= &am33xx_i2c2_hwmod
,
310 .user
= OCP_USER_MPU
,
313 struct omap_hwmod_ocp_if am33xx_l4_per__i2c3
= {
314 .master
= &am33xx_l4_ls_hwmod
,
315 .slave
= &am33xx_i2c3_hwmod
,
317 .user
= OCP_USER_MPU
,
320 static struct omap_hwmod_addr_space am33xx_mailbox_addrs
[] = {
322 .pa_start
= 0x480C8000,
323 .pa_end
= 0x480C8000 + (SZ_4K
- 1),
324 .flags
= ADDR_TYPE_RT
329 /* l4 ls -> mailbox */
330 struct omap_hwmod_ocp_if am33xx_l4_per__mailbox
= {
331 .master
= &am33xx_l4_ls_hwmod
,
332 .slave
= &am33xx_mailbox_hwmod
,
334 .addr
= am33xx_mailbox_addrs
,
335 .user
= OCP_USER_MPU
,
338 /* l4 ls -> spinlock */
339 struct omap_hwmod_ocp_if am33xx_l4_ls__spinlock
= {
340 .master
= &am33xx_l4_ls_hwmod
,
341 .slave
= &am33xx_spinlock_hwmod
,
343 .user
= OCP_USER_MPU
,
346 /* l4 ls -> mcasp0 */
347 static struct omap_hwmod_addr_space am33xx_mcasp0_addr_space
[] = {
349 .pa_start
= 0x48038000,
350 .pa_end
= 0x48038000 + SZ_8K
- 1,
351 .flags
= ADDR_TYPE_RT
356 struct omap_hwmod_ocp_if am33xx_l4_ls__mcasp0
= {
357 .master
= &am33xx_l4_ls_hwmod
,
358 .slave
= &am33xx_mcasp0_hwmod
,
360 .addr
= am33xx_mcasp0_addr_space
,
361 .user
= OCP_USER_MPU
,
364 /* l4 ls -> mcasp1 */
365 static struct omap_hwmod_addr_space am33xx_mcasp1_addr_space
[] = {
367 .pa_start
= 0x4803C000,
368 .pa_end
= 0x4803C000 + SZ_8K
- 1,
369 .flags
= ADDR_TYPE_RT
374 struct omap_hwmod_ocp_if am33xx_l4_ls__mcasp1
= {
375 .master
= &am33xx_l4_ls_hwmod
,
376 .slave
= &am33xx_mcasp1_hwmod
,
378 .addr
= am33xx_mcasp1_addr_space
,
379 .user
= OCP_USER_MPU
,
383 static struct omap_hwmod_addr_space am33xx_mmc0_addr_space
[] = {
385 .pa_start
= 0x48060100,
386 .pa_end
= 0x48060100 + SZ_4K
- 1,
387 .flags
= ADDR_TYPE_RT
,
392 struct omap_hwmod_ocp_if am33xx_l4_ls__mmc0
= {
393 .master
= &am33xx_l4_ls_hwmod
,
394 .slave
= &am33xx_mmc0_hwmod
,
396 .addr
= am33xx_mmc0_addr_space
,
397 .user
= OCP_USER_MPU
,
401 static struct omap_hwmod_addr_space am33xx_mmc1_addr_space
[] = {
403 .pa_start
= 0x481d8100,
404 .pa_end
= 0x481d8100 + SZ_4K
- 1,
405 .flags
= ADDR_TYPE_RT
,
410 struct omap_hwmod_ocp_if am33xx_l4_ls__mmc1
= {
411 .master
= &am33xx_l4_ls_hwmod
,
412 .slave
= &am33xx_mmc1_hwmod
,
414 .addr
= am33xx_mmc1_addr_space
,
415 .user
= OCP_USER_MPU
,
419 static struct omap_hwmod_addr_space am33xx_mmc2_addr_space
[] = {
421 .pa_start
= 0x47810100,
422 .pa_end
= 0x47810100 + SZ_64K
- 1,
423 .flags
= ADDR_TYPE_RT
,
428 struct omap_hwmod_ocp_if am33xx_l3_s__mmc2
= {
429 .master
= &am33xx_l3_s_hwmod
,
430 .slave
= &am33xx_mmc2_hwmod
,
432 .addr
= am33xx_mmc2_addr_space
,
433 .user
= OCP_USER_MPU
,
436 /* l4 ls -> mcspi0 */
437 struct omap_hwmod_ocp_if am33xx_l4_ls__mcspi0
= {
438 .master
= &am33xx_l4_ls_hwmod
,
439 .slave
= &am33xx_spi0_hwmod
,
441 .user
= OCP_USER_MPU
,
444 /* l4 ls -> mcspi1 */
445 struct omap_hwmod_ocp_if am33xx_l4_ls__mcspi1
= {
446 .master
= &am33xx_l4_ls_hwmod
,
447 .slave
= &am33xx_spi1_hwmod
,
449 .user
= OCP_USER_MPU
,
452 /* l4 per -> timer2 */
453 struct omap_hwmod_ocp_if am33xx_l4_ls__timer2
= {
454 .master
= &am33xx_l4_ls_hwmod
,
455 .slave
= &am33xx_timer2_hwmod
,
457 .user
= OCP_USER_MPU
,
460 /* l4 per -> timer3 */
461 struct omap_hwmod_ocp_if am33xx_l4_ls__timer3
= {
462 .master
= &am33xx_l4_ls_hwmod
,
463 .slave
= &am33xx_timer3_hwmod
,
465 .user
= OCP_USER_MPU
,
468 /* l4 per -> timer4 */
469 struct omap_hwmod_ocp_if am33xx_l4_ls__timer4
= {
470 .master
= &am33xx_l4_ls_hwmod
,
471 .slave
= &am33xx_timer4_hwmod
,
473 .user
= OCP_USER_MPU
,
476 /* l4 per -> timer5 */
477 struct omap_hwmod_ocp_if am33xx_l4_ls__timer5
= {
478 .master
= &am33xx_l4_ls_hwmod
,
479 .slave
= &am33xx_timer5_hwmod
,
481 .user
= OCP_USER_MPU
,
484 /* l4 per -> timer6 */
485 struct omap_hwmod_ocp_if am33xx_l4_ls__timer6
= {
486 .master
= &am33xx_l4_ls_hwmod
,
487 .slave
= &am33xx_timer6_hwmod
,
489 .user
= OCP_USER_MPU
,
492 /* l4 per -> timer7 */
493 struct omap_hwmod_ocp_if am33xx_l4_ls__timer7
= {
494 .master
= &am33xx_l4_ls_hwmod
,
495 .slave
= &am33xx_timer7_hwmod
,
497 .user
= OCP_USER_MPU
,
500 /* l3 main -> tpcc */
501 struct omap_hwmod_ocp_if am33xx_l3_main__tpcc
= {
502 .master
= &am33xx_l3_main_hwmod
,
503 .slave
= &am33xx_tpcc_hwmod
,
505 .user
= OCP_USER_MPU
,
508 /* l3 main -> tpcc0 */
509 static struct omap_hwmod_addr_space am33xx_tptc0_addr_space
[] = {
511 .pa_start
= 0x49800000,
512 .pa_end
= 0x49800000 + SZ_8K
- 1,
513 .flags
= ADDR_TYPE_RT
,
518 struct omap_hwmod_ocp_if am33xx_l3_main__tptc0
= {
519 .master
= &am33xx_l3_main_hwmod
,
520 .slave
= &am33xx_tptc0_hwmod
,
522 .addr
= am33xx_tptc0_addr_space
,
523 .user
= OCP_USER_MPU
,
526 /* l3 main -> tpcc1 */
527 static struct omap_hwmod_addr_space am33xx_tptc1_addr_space
[] = {
529 .pa_start
= 0x49900000,
530 .pa_end
= 0x49900000 + SZ_8K
- 1,
531 .flags
= ADDR_TYPE_RT
,
536 struct omap_hwmod_ocp_if am33xx_l3_main__tptc1
= {
537 .master
= &am33xx_l3_main_hwmod
,
538 .slave
= &am33xx_tptc1_hwmod
,
540 .addr
= am33xx_tptc1_addr_space
,
541 .user
= OCP_USER_MPU
,
544 /* l3 main -> tpcc2 */
545 static struct omap_hwmod_addr_space am33xx_tptc2_addr_space
[] = {
547 .pa_start
= 0x49a00000,
548 .pa_end
= 0x49a00000 + SZ_8K
- 1,
549 .flags
= ADDR_TYPE_RT
,
554 struct omap_hwmod_ocp_if am33xx_l3_main__tptc2
= {
555 .master
= &am33xx_l3_main_hwmod
,
556 .slave
= &am33xx_tptc2_hwmod
,
558 .addr
= am33xx_tptc2_addr_space
,
559 .user
= OCP_USER_MPU
,
563 struct omap_hwmod_ocp_if am33xx_l4_ls__uart2
= {
564 .master
= &am33xx_l4_ls_hwmod
,
565 .slave
= &am33xx_uart2_hwmod
,
567 .user
= OCP_USER_MPU
,
571 struct omap_hwmod_ocp_if am33xx_l4_ls__uart3
= {
572 .master
= &am33xx_l4_ls_hwmod
,
573 .slave
= &am33xx_uart3_hwmod
,
575 .user
= OCP_USER_MPU
,
579 struct omap_hwmod_ocp_if am33xx_l4_ls__uart4
= {
580 .master
= &am33xx_l4_ls_hwmod
,
581 .slave
= &am33xx_uart4_hwmod
,
583 .user
= OCP_USER_MPU
,
587 struct omap_hwmod_ocp_if am33xx_l4_ls__uart5
= {
588 .master
= &am33xx_l4_ls_hwmod
,
589 .slave
= &am33xx_uart5_hwmod
,
591 .user
= OCP_USER_MPU
,
595 struct omap_hwmod_ocp_if am33xx_l4_ls__uart6
= {
596 .master
= &am33xx_l4_ls_hwmod
,
597 .slave
= &am33xx_uart6_hwmod
,
599 .user
= OCP_USER_MPU
,
602 /* l3 main -> ocmc */
603 struct omap_hwmod_ocp_if am33xx_l3_main__ocmc
= {
604 .master
= &am33xx_l3_main_hwmod
,
605 .slave
= &am33xx_ocmcram_hwmod
,
606 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
609 /* l3 main -> sha0 HIB2 */
610 static struct omap_hwmod_addr_space am33xx_sha0_addrs
[] = {
612 .pa_start
= 0x53100000,
613 .pa_end
= 0x53100000 + SZ_512
- 1,
614 .flags
= ADDR_TYPE_RT
619 struct omap_hwmod_ocp_if am33xx_l3_main__sha0
= {
620 .master
= &am33xx_l3_main_hwmod
,
621 .slave
= &am33xx_sha0_hwmod
,
623 .addr
= am33xx_sha0_addrs
,
624 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
627 /* l3 main -> AES0 HIB2 */
628 static struct omap_hwmod_addr_space am33xx_aes0_addrs
[] = {
630 .pa_start
= 0x53500000,
631 .pa_end
= 0x53500000 + SZ_1M
- 1,
632 .flags
= ADDR_TYPE_RT
637 struct omap_hwmod_ocp_if am33xx_l3_main__aes0
= {
638 .master
= &am33xx_l3_main_hwmod
,
639 .slave
= &am33xx_aes0_hwmod
,
641 .addr
= am33xx_aes0_addrs
,
642 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,