arch/arm/mach-omap2/gpmc-nand.c

   1 /*
   2  * gpmc-nand.c
   3  *
   4  * Copyright (C) 2009 Texas Instruments
   5  * Vimal Singh <vimalsingh@ti.com>
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License version 2 as
   9  * published by the Free Software Foundation.
  10  */
  11
  12 #include <linux/kernel.h>
  13 #include <linux/platform_device.h>
  14 #include <linux/io.h>
  15 #include <linux/mtd/nand.h>
  16 #include <linux/platform_data/mtd-nand-omap2.h>
  17
  18 #include <asm/mach/flash.h>
  19
  20 #include "gpmc.h"
  21 #include "soc.h"
  22 #include "gpmc-nand.h"
  23
  24 /* minimum size for IO mapping */
  25 #define NAND_IO_SIZE    4
  26
  27 static struct resource gpmc_nand_resource[] = {
  28         {
  29                 .flags          = IORESOURCE_MEM,
  30         },
  31         {
  32                 .flags          = IORESOURCE_IRQ,
  33         },
  34         {
  35                 .flags          = IORESOURCE_IRQ,
  36         },
  37 };
  38
  39 static struct platform_device gpmc_nand_device = {
  40         .name           = "omap2-nand",
  41         .id             = 0,
  42         .num_resources  = ARRAY_SIZE(gpmc_nand_resource),
  43         .resource       = gpmc_nand_resource,
  44 };
  45
  46 static bool gpmc_hwecc_bch_capable(enum omap_ecc ecc_opt)
  47 {
  48         /* support only OMAP3 class */
  49         if (!cpu_is_omap34xx() && !soc_is_am33xx()) {
  50                 pr_err("BCH ecc is not supported on this CPU\n");
  51                 return 0;
  52         }
  53
  54         /*
  55          * For now, assume 4-bit mode is only supported on OMAP3630 ES1.x, x>=1
  56          * and AM33xx derivates. Other chips may be added if confirmed to work.
  57          */
  58         if ((ecc_opt == OMAP_ECC_BCH4_CODE_HW) &&
  59             (!cpu_is_omap3630() || (GET_OMAP_REVISION() == 0)) &&
  60             (!soc_is_am33xx())) {
  61                 pr_err("BCH 4-bit mode is not supported on this CPU\n");
  62                 return 0;
  63         }
  64
  65         return 1;
  66 }
  67
  68 int gpmc_nand_init(struct omap_nand_platform_data *gpmc_nand_data,
  69                    struct gpmc_timings *gpmc_t)
  70 {
  71         int err = 0;
  72         struct gpmc_settings s;
  73         struct device *dev = &gpmc_nand_device.dev;
  74
  75         memset(&s, 0, sizeof(struct gpmc_settings));
  76
  77         gpmc_nand_device.dev.platform_data = gpmc_nand_data;
  78
  79         err = gpmc_cs_request(gpmc_nand_data->cs, NAND_IO_SIZE,
  80                                 (unsigned long *)&gpmc_nand_resource[0].start);
  81         if (err < 0) {
  82                 dev_err(dev, "Cannot request GPMC CS %d, error %d\n",
  83                         gpmc_nand_data->cs, err);
  84                 return err;
  85         }
  86
  87         gpmc_nand_resource[0].end = gpmc_nand_resource[0].start +
  88                                                         NAND_IO_SIZE - 1;
  89
  90         gpmc_nand_resource[1].start =
  91                                 gpmc_get_client_irq(GPMC_IRQ_FIFOEVENTENABLE);
  92         gpmc_nand_resource[2].start =
  93                                 gpmc_get_client_irq(GPMC_IRQ_COUNT_EVENT);
  94
  95         if (gpmc_t) {
  96                 err = gpmc_cs_set_timings(gpmc_nand_data->cs, gpmc_t);
  97                 if (err < 0) {
  98                         dev_err(dev, "Unable to set gpmc timings: %d\n", err);
  99                         return err;
 100                 }
 101
 102                 if (gpmc_nand_data->of_node) {
 103                         gpmc_read_settings_dt(gpmc_nand_data->of_node, &s);
 104                 } else {
 105                         /* Enable RD PIN Monitoring Reg */
 106                         if (gpmc_nand_data->dev_ready) {
 107                                 s.wait_on_read = true;
 108                                 s.wait_on_write = true;
 109                         }
 110                 }
 111
 112                 s.device_nand = true;
 113
 114                 if (gpmc_nand_data->devsize == NAND_BUSWIDTH_16)
 115                         s.device_width = GPMC_DEVWIDTH_16BIT;
 116                 else
 117                         s.device_width = GPMC_DEVWIDTH_8BIT;
 118
 119                 err = gpmc_cs_program_settings(gpmc_nand_data->cs, &s);
 120                 if (err < 0)
 121                         goto out_free_cs;
 122
 123                 err = gpmc_configure(GPMC_CONFIG_WP, 0);
 124                 if (err < 0)
 125                         goto out_free_cs;
 126         }
 127
 128         gpmc_update_nand_reg(&gpmc_nand_data->reg, gpmc_nand_data->cs);
 129
 130         if (!gpmc_hwecc_bch_capable(gpmc_nand_data->ecc_opt))
 131                 return -EINVAL;
 132
 133         err = platform_device_register(&gpmc_nand_device);
 134         if (err < 0) {
 135                 dev_err(dev, "Unable to register NAND device\n");
 136                 goto out_free_cs;
 137         }
 138
 139         return 0;
 140
 141 out_free_cs:
 142         gpmc_cs_free(gpmc_nand_data->cs);
 143
 144         return err;
 145 }