2 * Copyright (C) 2005 - 2009 ServerEngines
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License version 2
7 * as published by the Free Software Foundation. The full GNU General
8 * Public License is included in this distribution in the file called COPYING.
10 * Contact Information:
11 * linux-drivers@serverengines.com
14 * 209 N. Fair Oaks Ave
21 #include <linux/pci.h>
22 #include <linux/etherdevice.h>
23 #include <linux/version.h>
24 #include <linux/delay.h>
28 #include <linux/if_vlan.h>
29 #include <linux/workqueue.h>
30 #include <linux/interrupt.h>
31 #include <linux/firmware.h>
35 #define DRV_VER "2.101.346u"
36 #define DRV_NAME "be2net"
37 #define BE_NAME "ServerEngines BladeEngine2 10Gbps NIC"
38 #define BE3_NAME "ServerEngines BladeEngine3 10Gbps NIC"
39 #define OC_NAME "Emulex OneConnect 10Gbps NIC"
40 #define OC_NAME1 "Emulex OneConnect 10Gbps NIC (be3)"
41 #define DRV_DESC BE_NAME "Driver"
43 #define BE_VENDOR_ID 0x19a2
44 #define BE_DEVICE_ID1 0x211
45 #define BE_DEVICE_ID2 0x221
46 #define OC_DEVICE_ID1 0x700
47 #define OC_DEVICE_ID2 0x701
48 #define OC_DEVICE_ID3 0x710
50 static inline char *nic_name(struct pci_dev
*pdev
)
52 switch (pdev
->device
) {
65 /* Number of bytes of an RX frame that are copied to skb->data */
67 #define BE_MAX_JUMBO_FRAME_SIZE 9018
68 #define BE_MIN_MTU 256
70 #define BE_NUM_VLANS_SUPPORTED 64
72 #define BE_MAX_TX_FRAG_COUNT 30
74 #define EVNT_Q_LEN 1024
76 #define TX_CQ_LEN 1024
77 #define RX_Q_LEN 1024 /* Does not support any other value */
78 #define RX_CQ_LEN 1024
79 #define MCC_Q_LEN 128 /* total size not to exceed 8 pages */
80 #define MCC_CQ_LEN 256
82 #define BE_NAPI_WEIGHT 64
83 #define MAX_RX_POST BE_NAPI_WEIGHT /* Frags posted at a time */
84 #define RX_FRAGS_REFILL_WM (RX_Q_LEN - MAX_RX_POST)
94 struct be_queue_info
{
95 struct be_dma_mem dma_mem
;
97 u16 entry_size
; /* Size of an element in the queue */
101 atomic_t used
; /* Number of valid elements in the queue */
104 static inline u32
MODULO(u16 val
, u16 limit
)
106 BUG_ON(limit
& (limit
- 1));
107 return val
& (limit
- 1);
110 static inline void index_adv(u16
*index
, u16 val
, u16 limit
)
112 *index
= MODULO((*index
+ val
), limit
);
115 static inline void index_inc(u16
*index
, u16 limit
)
117 *index
= MODULO((*index
+ 1), limit
);
120 static inline void *queue_head_node(struct be_queue_info
*q
)
122 return q
->dma_mem
.va
+ q
->head
* q
->entry_size
;
125 static inline void *queue_tail_node(struct be_queue_info
*q
)
127 return q
->dma_mem
.va
+ q
->tail
* q
->entry_size
;
130 static inline void queue_head_inc(struct be_queue_info
*q
)
132 index_inc(&q
->head
, q
->len
);
135 static inline void queue_tail_inc(struct be_queue_info
*q
)
137 index_inc(&q
->tail
, q
->len
);
141 struct be_queue_info q
;
144 /* Adaptive interrupt coalescing (AIC) info */
146 u16 min_eqd
; /* in usecs */
147 u16 max_eqd
; /* in usecs */
148 u16 cur_eqd
; /* in usecs */
150 struct napi_struct napi
;
154 struct be_queue_info q
;
155 struct be_queue_info cq
;
158 struct be_drvr_stats
{
159 u32 be_tx_reqs
; /* number of TX requests initiated */
160 u32 be_tx_stops
; /* number of times TX Q was stopped */
161 u32 be_fwd_reqs
; /* number of send reqs through forwarding i/f */
162 u32 be_tx_wrbs
; /* number of tx WRBs used */
163 u32 be_tx_events
; /* number of tx completion events */
164 u32 be_tx_compl
; /* number of tx completion entries processed */
167 u64 be_tx_bytes_prev
;
170 u32 cache_barrier
[16];
172 u32 be_ethrx_post_fail
;/* number of ethrx buffer alloc failures */
173 u32 be_rx_polls
; /* number of times NAPI called poll function */
174 u32 be_rx_events
; /* number of ucast rx completion events */
175 u32 be_rx_compl
; /* number of rx completion entries processed */
178 u64 be_rx_bytes_prev
;
180 /* number of non ether type II frames dropped where
181 * frame len > length field of Mac Hdr */
182 u32 be_802_3_dropped_frames
;
183 /* number of non ether type II frames malformed where
184 * in frame len < length field of Mac Hdr */
185 u32 be_802_3_malformed_frames
;
186 u32 be_rxcp_err
; /* Num rx completion entries w/ err set. */
187 ulong rx_fps_jiffies
; /* jiffies at last FPS calc */
189 u32 be_prev_rx_frags
;
190 u32 be_rx_fps
; /* Rx frags per second */
193 struct be_stats_obj
{
194 struct be_drvr_stats drvr_stats
;
195 struct be_dma_mem cmd
;
199 struct be_queue_info q
;
200 struct be_queue_info cq
;
201 /* Remember the skbs that were transmitted */
202 struct sk_buff
*sent_skb_list
[TX_Q_LEN
];
205 /* Struct to remember the pages posted for rx frags */
206 struct be_rx_page_info
{
214 struct be_queue_info q
;
215 struct be_queue_info cq
;
216 struct be_rx_page_info page_info_tbl
[RX_Q_LEN
];
219 #define BE_NUM_MSIX_VECTORS 2 /* 1 each for Tx and Rx */
221 struct pci_dev
*pdev
;
222 struct net_device
*netdev
;
225 u8 __iomem
*db
; /* Door Bell */
226 u8 __iomem
*pcicfg
; /* PCI config space */
228 spinlock_t mbox_lock
; /* For serializing mbox cmds to BE card */
229 struct be_dma_mem mbox_mem
;
230 /* Mbox mem is adjusted to align to 16 bytes. The allocated addr
231 * is stored for freeing purpose */
232 struct be_dma_mem mbox_mem_alloced
;
234 struct be_mcc_obj mcc_obj
;
235 spinlock_t mcc_lock
; /* For serializing mcc cmds to BE card */
236 spinlock_t mcc_cq_lock
;
238 struct msix_entry msix_entries
[BE_NUM_MSIX_VECTORS
];
243 struct be_eq_obj tx_eq
;
244 struct be_tx_obj tx_obj
;
246 u32 cache_line_break
[8];
249 struct be_eq_obj rx_eq
;
250 struct be_rx_obj rx_obj
;
251 u32 big_page_size
; /* Compounded page size shared by rx wrbs */
252 bool rx_post_starved
; /* Zero rx frags have been posted to BE */
254 struct vlan_group
*vlan_grp
;
256 u8 vlan_tag
[VLAN_GROUP_ARRAY_LEN
];
257 struct be_dma_mem mc_cmd_mem
;
259 struct be_stats_obj stats
;
260 /* Work queue used to perform periodic tasks like getting statistics */
261 struct delayed_work work
;
263 /* Ethtool knobs and info */
264 bool rx_csum
; /* BE card must perform rx-checksumming */
265 char fw_ver
[FW_VER_LEN
];
266 u32 if_handle
; /* Used to configure filtering */
267 u32 pmac_id
; /* MAC addr handle used by BE card */
274 u32 rx_fc
; /* Rx flow control */
275 u32 tx_fc
; /* Tx flow control */
280 extern const struct ethtool_ops be_ethtool_ops
;
282 #define drvr_stats(adapter) (&adapter->stats.drvr_stats)
284 static inline unsigned int be_pci_func(struct be_adapter
*adapter
)
286 return PCI_FUNC(adapter
->pdev
->devfn
);
289 #define BE_SET_NETDEV_OPS(netdev, ops) (netdev->netdev_ops = ops)
291 #define PAGE_SHIFT_4K 12
292 #define PAGE_SIZE_4K (1 << PAGE_SHIFT_4K)
294 /* Returns number of pages spanned by the data starting at the given addr */
295 #define PAGES_4K_SPANNED(_address, size) \
296 ((u32)((((size_t)(_address) & (PAGE_SIZE_4K - 1)) + \
297 (size) + (PAGE_SIZE_4K - 1)) >> PAGE_SHIFT_4K))
299 /* Byte offset into the page corresponding to given address */
300 #define OFFSET_IN_PAGE(addr) \
301 ((size_t)(addr) & (PAGE_SIZE_4K-1))
303 /* Returns bit offset within a DWORD of a bitfield */
304 #define AMAP_BIT_OFFSET(_struct, field) \
305 (((size_t)&(((_struct *)0)->field))%32)
307 /* Returns the bit mask of the field that is NOT shifted into location. */
308 static inline u32
amap_mask(u32 bitsize
)
310 return (bitsize
== 32 ? 0xFFFFFFFF : (1 << bitsize
) - 1);
314 amap_set(void *ptr
, u32 dw_offset
, u32 mask
, u32 offset
, u32 value
)
316 u32
*dw
= (u32
*) ptr
+ dw_offset
;
317 *dw
&= ~(mask
<< offset
);
318 *dw
|= (mask
& value
) << offset
;
321 #define AMAP_SET_BITS(_struct, field, ptr, val) \
323 offsetof(_struct, field)/32, \
324 amap_mask(sizeof(((_struct *)0)->field)), \
325 AMAP_BIT_OFFSET(_struct, field), \
328 static inline u32
amap_get(void *ptr
, u32 dw_offset
, u32 mask
, u32 offset
)
330 u32
*dw
= (u32
*) ptr
;
331 return mask
& (*(dw
+ dw_offset
) >> offset
);
334 #define AMAP_GET_BITS(_struct, field, ptr) \
336 offsetof(_struct, field)/32, \
337 amap_mask(sizeof(((_struct *)0)->field)), \
338 AMAP_BIT_OFFSET(_struct, field))
340 #define be_dws_cpu_to_le(wrb, len) swap_dws(wrb, len)
341 #define be_dws_le_to_cpu(wrb, len) swap_dws(wrb, len)
342 static inline void swap_dws(void *wrb
, int len
)
348 *dw
= cpu_to_le32(*dw
);
352 #endif /* __BIG_ENDIAN */
355 static inline u8
is_tcp_pkt(struct sk_buff
*skb
)
359 if (ip_hdr(skb
)->version
== 4)
360 val
= (ip_hdr(skb
)->protocol
== IPPROTO_TCP
);
361 else if (ip_hdr(skb
)->version
== 6)
362 val
= (ipv6_hdr(skb
)->nexthdr
== NEXTHDR_TCP
);
367 static inline u8
is_udp_pkt(struct sk_buff
*skb
)
371 if (ip_hdr(skb
)->version
== 4)
372 val
= (ip_hdr(skb
)->protocol
== IPPROTO_UDP
);
373 else if (ip_hdr(skb
)->version
== 6)
374 val
= (ipv6_hdr(skb
)->nexthdr
== NEXTHDR_UDP
);
379 extern void be_cq_notify(struct be_adapter
*adapter
, u16 qid
, bool arm
,
381 extern void be_link_status_update(struct be_adapter
*adapter
, bool link_up
);
382 extern void netdev_stats_update(struct be_adapter
*adapter
);
383 extern int be_load_fw(struct be_adapter
*adapter
, u8
*func
);