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[SCSI] qla2xxx: Prevent enabling target mode for unsupported HBAs.
[linux-2.6.git] / drivers / scsi / qla2xxx / qla_def.h
blob5c42c9162026c8eca2ed764b4ab4e75508d2db6d
1 /*
2 * QLogic Fibre Channel HBA Driver
3 * Copyright (c) 2003-2012 QLogic Corporation
4 *
5 * See LICENSE.qla2xxx for copyright and licensing details.
6 */
7 #ifndef __QLA_DEF_H
8 #define __QLA_DEF_H
9
10 #include <linux/kernel.h>
11 #include <linux/init.h>
12 #include <linux/types.h>
13 #include <linux/module.h>
14 #include <linux/list.h>
15 #include <linux/pci.h>
16 #include <linux/dma-mapping.h>
17 #include <linux/sched.h>
18 #include <linux/slab.h>
19 #include <linux/dmapool.h>
20 #include <linux/mempool.h>
21 #include <linux/spinlock.h>
22 #include <linux/completion.h>
23 #include <linux/interrupt.h>
24 #include <linux/workqueue.h>
25 #include <linux/firmware.h>
26 #include <linux/aer.h>
27 #include <linux/mutex.h>
28
29 #include <scsi/scsi.h>
30 #include <scsi/scsi_host.h>
31 #include <scsi/scsi_device.h>
32 #include <scsi/scsi_cmnd.h>
33 #include <scsi/scsi_transport_fc.h>
34 #include <scsi/scsi_bsg_fc.h>
35
36 #include "qla_bsg.h"
37 #include "qla_nx.h"
38 #define QLA2XXX_DRIVER_NAME "qla2xxx"
39 #define QLA2XXX_APIDEV "ql2xapidev"
40
41 /*
42 * We have MAILBOX_REGISTER_COUNT sized arrays in a few places,
43 * but that's fine as we don't look at the last 24 ones for
44 * ISP2100 HBAs.
45 */
46 #define MAILBOX_REGISTER_COUNT_2100 8
47 #define MAILBOX_REGISTER_COUNT_2200 24
48 #define MAILBOX_REGISTER_COUNT 32
49
50 #define QLA2200A_RISC_ROM_VER 4
51 #define FPM_2300 6
52 #define FPM_2310 7
53
54 #include "qla_settings.h"
55
56 /*
57 * Data bit definitions
58 */
59 #define BIT_0 0x1
60 #define BIT_1 0x2
61 #define BIT_2 0x4
62 #define BIT_3 0x8
63 #define BIT_4 0x10
64 #define BIT_5 0x20
65 #define BIT_6 0x40
66 #define BIT_7 0x80
67 #define BIT_8 0x100
68 #define BIT_9 0x200
69 #define BIT_10 0x400
70 #define BIT_11 0x800
71 #define BIT_12 0x1000
72 #define BIT_13 0x2000
73 #define BIT_14 0x4000
74 #define BIT_15 0x8000
75 #define BIT_16 0x10000
76 #define BIT_17 0x20000
77 #define BIT_18 0x40000
78 #define BIT_19 0x80000
79 #define BIT_20 0x100000
80 #define BIT_21 0x200000
81 #define BIT_22 0x400000
82 #define BIT_23 0x800000
83 #define BIT_24 0x1000000
84 #define BIT_25 0x2000000
85 #define BIT_26 0x4000000
86 #define BIT_27 0x8000000
87 #define BIT_28 0x10000000
88 #define BIT_29 0x20000000
89 #define BIT_30 0x40000000
90 #define BIT_31 0x80000000
91
92 #define LSB(x) ((uint8_t)(x))
93 #define MSB(x) ((uint8_t)((uint16_t)(x) >> 8))
94
95 #define LSW(x) ((uint16_t)(x))
96 #define MSW(x) ((uint16_t)((uint32_t)(x) >> 16))
97
98 #define LSD(x) ((uint32_t)((uint64_t)(x)))
99 #define MSD(x) ((uint32_t)((((uint64_t)(x)) >> 16) >> 16))
100
101 #define MAKE_HANDLE(x, y) ((uint32_t)((((uint32_t)(x)) << 16) | (uint32_t)(y)))
102
103 /*
104 * I/O register
105 */
106
107 #define RD_REG_BYTE(addr) readb(addr)
108 #define RD_REG_WORD(addr) readw(addr)
109 #define RD_REG_DWORD(addr) readl(addr)
110 #define RD_REG_BYTE_RELAXED(addr) readb_relaxed(addr)
111 #define RD_REG_WORD_RELAXED(addr) readw_relaxed(addr)
112 #define RD_REG_DWORD_RELAXED(addr) readl_relaxed(addr)
113 #define WRT_REG_BYTE(addr, data) writeb(data,addr)
114 #define WRT_REG_WORD(addr, data) writew(data,addr)
115 #define WRT_REG_DWORD(addr, data) writel(data,addr)
116
117 /*
118 * ISP83XX specific remote register addresses
119 */
120 #define QLA83XX_LED_PORT0 0x00201320
121 #define QLA83XX_LED_PORT1 0x00201328
122 #define QLA83XX_IDC_DEV_STATE 0x22102384
123 #define QLA83XX_IDC_MAJOR_VERSION 0x22102380
124 #define QLA83XX_IDC_MINOR_VERSION 0x22102398
125 #define QLA83XX_IDC_DRV_PRESENCE 0x22102388
126 #define QLA83XX_IDC_DRIVER_ACK 0x2210238c
127 #define QLA83XX_IDC_CONTROL 0x22102390
128 #define QLA83XX_IDC_AUDIT 0x22102394
129 #define QLA83XX_IDC_LOCK_RECOVERY 0x2210239c
130 #define QLA83XX_DRIVER_LOCKID 0x22102104
131 #define QLA83XX_DRIVER_LOCK 0x8111c028
132 #define QLA83XX_DRIVER_UNLOCK 0x8111c02c
133 #define QLA83XX_FLASH_LOCKID 0x22102100
134 #define QLA83XX_FLASH_LOCK 0x8111c010
135 #define QLA83XX_FLASH_UNLOCK 0x8111c014
136 #define QLA83XX_DEV_PARTINFO1 0x221023e0
137 #define QLA83XX_DEV_PARTINFO2 0x221023e4
138 #define QLA83XX_FW_HEARTBEAT 0x221020b0
139 #define QLA83XX_PEG_HALT_STATUS1 0x221020a8
140 #define QLA83XX_PEG_HALT_STATUS2 0x221020ac
141
142 /* 83XX: Macros defining 8200 AEN Reason codes */
143 #define IDC_DEVICE_STATE_CHANGE BIT_0
144 #define IDC_PEG_HALT_STATUS_CHANGE BIT_1
145 #define IDC_NIC_FW_REPORTED_FAILURE BIT_2
146 #define IDC_HEARTBEAT_FAILURE BIT_3
147
148 /* 83XX: Macros defining 8200 AEN Error-levels */
149 #define ERR_LEVEL_NON_FATAL 0x1
150 #define ERR_LEVEL_RECOVERABLE_FATAL 0x2
151 #define ERR_LEVEL_UNRECOVERABLE_FATAL 0x4
152
153 /* 83XX: Macros for IDC Version */
154 #define QLA83XX_SUPP_IDC_MAJOR_VERSION 0x01
155 #define QLA83XX_SUPP_IDC_MINOR_VERSION 0x0
156
157 /* 83XX: Macros for scheduling dpc tasks */
158 #define QLA83XX_NIC_CORE_RESET 0x1
159 #define QLA83XX_IDC_STATE_HANDLER 0x2
160 #define QLA83XX_NIC_CORE_UNRECOVERABLE 0x3
161
162 /* 83XX: Macros for defining IDC-Control bits */
163 #define QLA83XX_IDC_RESET_DISABLED BIT_0
164 #define QLA83XX_IDC_GRACEFUL_RESET BIT_1
165
166 /* 83XX: Macros for different timeouts */
167 #define QLA83XX_IDC_INITIALIZATION_TIMEOUT 30
168 #define QLA83XX_IDC_RESET_ACK_TIMEOUT 10
169 #define QLA83XX_MAX_LOCK_RECOVERY_WAIT (2 * HZ)
170
171 /* 83XX: Macros for defining class in DEV-Partition Info register */
172 #define QLA83XX_CLASS_TYPE_NONE 0x0
173 #define QLA83XX_CLASS_TYPE_NIC 0x1
174 #define QLA83XX_CLASS_TYPE_FCOE 0x2
175 #define QLA83XX_CLASS_TYPE_ISCSI 0x3
176
177 /* 83XX: Macros for IDC Lock-Recovery stages */
178 #define IDC_LOCK_RECOVERY_STAGE1 0x1 /* Stage1: Intent for
179 * lock-recovery
180 */
181 #define IDC_LOCK_RECOVERY_STAGE2 0x2 /* Stage2: Perform lock-recovery */
182
183 /* 83XX: Macros for IDC Audit type */
184 #define IDC_AUDIT_TIMESTAMP 0x0 /* IDC-AUDIT: Record timestamp of
185 * dev-state change to NEED-RESET
186 * or NEED-QUIESCENT
187 */
188 #define IDC_AUDIT_COMPLETION 0x1 /* IDC-AUDIT: Record duration of
189 * reset-recovery completion is
190 * second
191 */
192
193 /*
194 * The ISP2312 v2 chip cannot access the FLASH/GPIO registers via MMIO in an
195 * 133Mhz slot.
196 */
197 #define RD_REG_WORD_PIO(addr) (inw((unsigned long)addr))
198 #define WRT_REG_WORD_PIO(addr, data) (outw(data,(unsigned long)addr))
199
200 /*
201 * Fibre Channel device definitions.
202 */
203 #define WWN_SIZE 8 /* Size of WWPN, WWN & WWNN */
204 #define MAX_FIBRE_DEVICES_2100 512
205 #define MAX_FIBRE_DEVICES_2400 2048
206 #define MAX_FIBRE_DEVICES_LOOP 128
207 #define MAX_FIBRE_DEVICES_MAX MAX_FIBRE_DEVICES_2400
208 #define LOOPID_MAP_SIZE (ha->max_fibre_devices)
209 #define MAX_FIBRE_LUNS 0xFFFF
210 #define MAX_HOST_COUNT 16
211
212 /*
213 * Host adapter default definitions.
214 */
215 #define MAX_BUSES 1 /* We only have one bus today */
216 #define MIN_LUNS 8
217 #define MAX_LUNS MAX_FIBRE_LUNS
218 #define MAX_CMDS_PER_LUN 255
219
220 /*
221 * Fibre Channel device definitions.
222 */
223 #define SNS_LAST_LOOP_ID_2100 0xfe
224 #define SNS_LAST_LOOP_ID_2300 0x7ff
225
226 #define LAST_LOCAL_LOOP_ID 0x7d
227 #define SNS_FL_PORT 0x7e
228 #define FABRIC_CONTROLLER 0x7f
229 #define SIMPLE_NAME_SERVER 0x80
230 #define SNS_FIRST_LOOP_ID 0x81
231 #define MANAGEMENT_SERVER 0xfe
232 #define BROADCAST 0xff
233
234 /*
235 * There is no correspondence between an N-PORT id and an AL_PA. Therefore the
236 * valid range of an N-PORT id is 0 through 0x7ef.
237 */
238 #define NPH_LAST_HANDLE 0x7ef
239 #define NPH_MGMT_SERVER 0x7fa /* FFFFFA */
240 #define NPH_SNS 0x7fc /* FFFFFC */
241 #define NPH_FABRIC_CONTROLLER 0x7fd /* FFFFFD */
242 #define NPH_F_PORT 0x7fe /* FFFFFE */
243 #define NPH_IP_BROADCAST 0x7ff /* FFFFFF */
244
245 #define MAX_CMDSZ 16 /* SCSI maximum CDB size. */
246 #include "qla_fw.h"
247
248 /*
249 * Timeout timer counts in seconds
250 */
251 #define PORT_RETRY_TIME 1
252 #define LOOP_DOWN_TIMEOUT 60
253 #define LOOP_DOWN_TIME 255 /* 240 */
254 #define LOOP_DOWN_RESET (LOOP_DOWN_TIME - 30)
255
256 #define DEFAULT_OUTSTANDING_COMMANDS 1024
257 #define MIN_OUTSTANDING_COMMANDS 128
258
259 /* ISP request and response entry counts (37-65535) */
260 #define REQUEST_ENTRY_CNT_2100 128 /* Number of request entries. */
261 #define REQUEST_ENTRY_CNT_2200 2048 /* Number of request entries. */
262 #define REQUEST_ENTRY_CNT_24XX 2048 /* Number of request entries. */
263 #define RESPONSE_ENTRY_CNT_2100 64 /* Number of response entries.*/
264 #define RESPONSE_ENTRY_CNT_2300 512 /* Number of response entries.*/
265 #define RESPONSE_ENTRY_CNT_MQ 128 /* Number of response entries.*/
266 #define ATIO_ENTRY_CNT_24XX 4096 /* Number of ATIO entries. */
267
268 struct req_que;
269
270 /*
271 * (sd.h is not exported, hence local inclusion)
272 * Data Integrity Field tuple.
273 */
274 struct sd_dif_tuple {
275 __be16 guard_tag; /* Checksum */
276 __be16 app_tag; /* Opaque storage */
277 __be32 ref_tag; /* Target LBA or indirect LBA */
278 };
279
280 /*
281 * SCSI Request Block
282 */
283 struct srb_cmd {
284 struct scsi_cmnd *cmd; /* Linux SCSI command pkt */
285 uint32_t request_sense_length;
286 uint8_t *request_sense_ptr;
287 void *ctx;
288 };
289
290 /*
291 * SRB flag definitions
292 */
293 #define SRB_DMA_VALID BIT_0 /* Command sent to ISP */
294 #define SRB_FCP_CMND_DMA_VALID BIT_12 /* DIF: DSD List valid */
295 #define SRB_CRC_CTX_DMA_VALID BIT_2 /* DIF: context DMA valid */
296 #define SRB_CRC_PROT_DMA_VALID BIT_4 /* DIF: prot DMA valid */
297 #define SRB_CRC_CTX_DSD_VALID BIT_5 /* DIF: dsd_list valid */
298
299 /* To identify if a srb is of T10-CRC type. @sp => srb_t pointer */
300 #define IS_PROT_IO(sp) (sp->flags & SRB_CRC_CTX_DSD_VALID)
301
302 /*
303 * SRB extensions.
304 */
305 struct srb_iocb {
306 union {
307 struct {
308 uint16_t flags;
309 #define SRB_LOGIN_RETRIED BIT_0
310 #define SRB_LOGIN_COND_PLOGI BIT_1
311 #define SRB_LOGIN_SKIP_PRLI BIT_2
312 uint16_t data[2];
313 } logio;
314 struct {
315 /*
316 * Values for flags field below are as
317 * defined in tsk_mgmt_entry struct
318 * for control_flags field in qla_fw.h.
319 */
320 uint32_t flags;
321 uint32_t lun;
322 uint32_t data;
323 } tmf;
324 } u;
325
326 struct timer_list timer;
327 void (*timeout)(void *);
328 };
329
330 /* Values for srb_ctx type */
331 #define SRB_LOGIN_CMD 1
332 #define SRB_LOGOUT_CMD 2
333 #define SRB_ELS_CMD_RPT 3
334 #define SRB_ELS_CMD_HST 4
335 #define SRB_CT_CMD 5
336 #define SRB_ADISC_CMD 6
337 #define SRB_TM_CMD 7
338 #define SRB_SCSI_CMD 8
339 #define SRB_BIDI_CMD 9
340
341 typedef struct srb {
342 atomic_t ref_count;
343 struct fc_port *fcport;
344 uint32_t handle;
345 uint16_t flags;
346 uint16_t type;
347 char *name;
348 int iocbs;
349 union {
350 struct srb_iocb iocb_cmd;
351 struct fc_bsg_job *bsg_job;
352 struct srb_cmd scmd;
353 } u;
354 void (*done)(void *, void *, int);
355 void (*free)(void *, void *);
356 } srb_t;
357
358 #define GET_CMD_SP(sp) (sp->u.scmd.cmd)
359 #define SET_CMD_SP(sp, cmd) (sp->u.scmd.cmd = cmd)
360 #define GET_CMD_CTX_SP(sp) (sp->u.scmd.ctx)
361
362 #define GET_CMD_SENSE_LEN(sp) \
363 (sp->u.scmd.request_sense_length)
364 #define SET_CMD_SENSE_LEN(sp, len) \
365 (sp->u.scmd.request_sense_length = len)
366 #define GET_CMD_SENSE_PTR(sp) \
367 (sp->u.scmd.request_sense_ptr)
368 #define SET_CMD_SENSE_PTR(sp, ptr) \
369 (sp->u.scmd.request_sense_ptr = ptr)
370
371 struct msg_echo_lb {
372 dma_addr_t send_dma;
373 dma_addr_t rcv_dma;
374 uint16_t req_sg_cnt;
375 uint16_t rsp_sg_cnt;
376 uint16_t options;
377 uint32_t transfer_size;
378 };
379
380 /*
381 * ISP I/O Register Set structure definitions.
382 */
383 struct device_reg_2xxx {
384 uint16_t flash_address; /* Flash BIOS address */
385 uint16_t flash_data; /* Flash BIOS data */
386 uint16_t unused_1[1]; /* Gap */
387 uint16_t ctrl_status; /* Control/Status */
388 #define CSR_FLASH_64K_BANK BIT_3 /* Flash upper 64K bank select */
389 #define CSR_FLASH_ENABLE BIT_1 /* Flash BIOS Read/Write enable */
390 #define CSR_ISP_SOFT_RESET BIT_0 /* ISP soft reset */
391
392 uint16_t ictrl; /* Interrupt control */
393 #define ICR_EN_INT BIT_15 /* ISP enable interrupts. */
394 #define ICR_EN_RISC BIT_3 /* ISP enable RISC interrupts. */
395
396 uint16_t istatus; /* Interrupt status */
397 #define ISR_RISC_INT BIT_3 /* RISC interrupt */
398
399 uint16_t semaphore; /* Semaphore */
400 uint16_t nvram; /* NVRAM register. */
401 #define NVR_DESELECT 0
402 #define NVR_BUSY BIT_15
403 #define NVR_WRT_ENABLE BIT_14 /* Write enable */
404 #define NVR_PR_ENABLE BIT_13 /* Protection register enable */
405 #define NVR_DATA_IN BIT_3
406 #define NVR_DATA_OUT BIT_2
407 #define NVR_SELECT BIT_1
408 #define NVR_CLOCK BIT_0
409
410 #define NVR_WAIT_CNT 20000
411
412 union {
413 struct {
414 uint16_t mailbox0;
415 uint16_t mailbox1;
416 uint16_t mailbox2;
417 uint16_t mailbox3;
418 uint16_t mailbox4;
419 uint16_t mailbox5;
420 uint16_t mailbox6;
421 uint16_t mailbox7;
422 uint16_t unused_2[59]; /* Gap */
423 } __attribute__((packed)) isp2100;
424 struct {
425 /* Request Queue */
426 uint16_t req_q_in; /* In-Pointer */
427 uint16_t req_q_out; /* Out-Pointer */
428 /* Response Queue */
429 uint16_t rsp_q_in; /* In-Pointer */
430 uint16_t rsp_q_out; /* Out-Pointer */
431
432 /* RISC to Host Status */
433 uint32_t host_status;
434 #define HSR_RISC_INT BIT_15 /* RISC interrupt */
435 #define HSR_RISC_PAUSED BIT_8 /* RISC Paused */
436
437 /* Host to Host Semaphore */
438 uint16_t host_semaphore;
439 uint16_t unused_3[17]; /* Gap */
440 uint16_t mailbox0;
441 uint16_t mailbox1;
442 uint16_t mailbox2;
443 uint16_t mailbox3;
444 uint16_t mailbox4;
445 uint16_t mailbox5;
446 uint16_t mailbox6;
447 uint16_t mailbox7;
448 uint16_t mailbox8;
449 uint16_t mailbox9;
450 uint16_t mailbox10;
451 uint16_t mailbox11;
452 uint16_t mailbox12;
453 uint16_t mailbox13;
454 uint16_t mailbox14;
455 uint16_t mailbox15;
456 uint16_t mailbox16;
457 uint16_t mailbox17;
458 uint16_t mailbox18;
459 uint16_t mailbox19;
460 uint16_t mailbox20;
461 uint16_t mailbox21;
462 uint16_t mailbox22;
463 uint16_t mailbox23;
464 uint16_t mailbox24;
465 uint16_t mailbox25;
466 uint16_t mailbox26;
467 uint16_t mailbox27;
468 uint16_t mailbox28;
469 uint16_t mailbox29;
470 uint16_t mailbox30;
471 uint16_t mailbox31;
472 uint16_t fb_cmd;
473 uint16_t unused_4[10]; /* Gap */
474 } __attribute__((packed)) isp2300;
475 } u;
476
477 uint16_t fpm_diag_config;
478 uint16_t unused_5[0x4]; /* Gap */
479 uint16_t risc_hw;
480 uint16_t unused_5_1; /* Gap */
481 uint16_t pcr; /* Processor Control Register. */
482 uint16_t unused_6[0x5]; /* Gap */
483 uint16_t mctr; /* Memory Configuration and Timing. */
484 uint16_t unused_7[0x3]; /* Gap */
485 uint16_t fb_cmd_2100; /* Unused on 23XX */
486 uint16_t unused_8[0x3]; /* Gap */
487 uint16_t hccr; /* Host command & control register. */
488 #define HCCR_HOST_INT BIT_7 /* Host interrupt bit */
489 #define HCCR_RISC_PAUSE BIT_5 /* Pause mode bit */
490 /* HCCR commands */
491 #define HCCR_RESET_RISC 0x1000 /* Reset RISC */
492 #define HCCR_PAUSE_RISC 0x2000 /* Pause RISC */
493 #define HCCR_RELEASE_RISC 0x3000 /* Release RISC from reset. */
494 #define HCCR_SET_HOST_INT 0x5000 /* Set host interrupt */
495 #define HCCR_CLR_HOST_INT 0x6000 /* Clear HOST interrupt */
496 #define HCCR_CLR_RISC_INT 0x7000 /* Clear RISC interrupt */
497 #define HCCR_DISABLE_PARITY_PAUSE 0x4001 /* Disable parity error RISC pause. */
498 #define HCCR_ENABLE_PARITY 0xA000 /* Enable PARITY interrupt */
499
500 uint16_t unused_9[5]; /* Gap */
501 uint16_t gpiod; /* GPIO Data register. */
502 uint16_t gpioe; /* GPIO Enable register. */
503 #define GPIO_LED_MASK 0x00C0
504 #define GPIO_LED_GREEN_OFF_AMBER_OFF 0x0000
505 #define GPIO_LED_GREEN_ON_AMBER_OFF 0x0040
506 #define GPIO_LED_GREEN_OFF_AMBER_ON 0x0080
507 #define GPIO_LED_GREEN_ON_AMBER_ON 0x00C0
508 #define GPIO_LED_ALL_OFF 0x0000
509 #define GPIO_LED_RED_ON_OTHER_OFF 0x0001 /* isp2322 */
510 #define GPIO_LED_RGA_ON 0x00C1 /* isp2322: red green amber */
511
512 union {
513 struct {
514 uint16_t unused_10[8]; /* Gap */
515 uint16_t mailbox8;
516 uint16_t mailbox9;
517 uint16_t mailbox10;
518 uint16_t mailbox11;
519 uint16_t mailbox12;
520 uint16_t mailbox13;
521 uint16_t mailbox14;
522 uint16_t mailbox15;
523 uint16_t mailbox16;
524 uint16_t mailbox17;
525 uint16_t mailbox18;
526 uint16_t mailbox19;
527 uint16_t mailbox20;
528 uint16_t mailbox21;
529 uint16_t mailbox22;
530 uint16_t mailbox23; /* Also probe reg. */
531 } __attribute__((packed)) isp2200;
532 } u_end;
533 };
534
535 struct device_reg_25xxmq {
536 uint32_t req_q_in;
537 uint32_t req_q_out;
538 uint32_t rsp_q_in;
539 uint32_t rsp_q_out;
540 uint32_t atio_q_in;
541 uint32_t atio_q_out;
542 };
543
544 typedef union {
545 struct device_reg_2xxx isp;
546 struct device_reg_24xx isp24;
547 struct device_reg_25xxmq isp25mq;
548 struct device_reg_82xx isp82;
549 } device_reg_t;
550
551 #define ISP_REQ_Q_IN(ha, reg) \
552 (IS_QLA2100(ha) || IS_QLA2200(ha) ? \
553 &(reg)->u.isp2100.mailbox4 : \
554 &(reg)->u.isp2300.req_q_in)
555 #define ISP_REQ_Q_OUT(ha, reg) \
556 (IS_QLA2100(ha) || IS_QLA2200(ha) ? \
557 &(reg)->u.isp2100.mailbox4 : \
558 &(reg)->u.isp2300.req_q_out)
559 #define ISP_RSP_Q_IN(ha, reg) \
560 (IS_QLA2100(ha) || IS_QLA2200(ha) ? \
561 &(reg)->u.isp2100.mailbox5 : \
562 &(reg)->u.isp2300.rsp_q_in)
563 #define ISP_RSP_Q_OUT(ha, reg) \
564 (IS_QLA2100(ha) || IS_QLA2200(ha) ? \
565 &(reg)->u.isp2100.mailbox5 : \
566 &(reg)->u.isp2300.rsp_q_out)
567
568 #define ISP_ATIO_Q_IN(vha) (vha->hw->tgt.atio_q_in)
569 #define ISP_ATIO_Q_OUT(vha) (vha->hw->tgt.atio_q_out)
570
571 #define MAILBOX_REG(ha, reg, num) \
572 (IS_QLA2100(ha) || IS_QLA2200(ha) ? \
573 (num < 8 ? \
574 &(reg)->u.isp2100.mailbox0 + (num) : \
575 &(reg)->u_end.isp2200.mailbox8 + (num) - 8) : \
576 &(reg)->u.isp2300.mailbox0 + (num))
577 #define RD_MAILBOX_REG(ha, reg, num) \
578 RD_REG_WORD(MAILBOX_REG(ha, reg, num))
579 #define WRT_MAILBOX_REG(ha, reg, num, data) \
580 WRT_REG_WORD(MAILBOX_REG(ha, reg, num), data)
581
582 #define FB_CMD_REG(ha, reg) \
583 (IS_QLA2100(ha) || IS_QLA2200(ha) ? \
584 &(reg)->fb_cmd_2100 : \
585 &(reg)->u.isp2300.fb_cmd)
586 #define RD_FB_CMD_REG(ha, reg) \
587 RD_REG_WORD(FB_CMD_REG(ha, reg))
588 #define WRT_FB_CMD_REG(ha, reg, data) \
589 WRT_REG_WORD(FB_CMD_REG(ha, reg), data)
590
591 typedef struct {
592 uint32_t out_mb; /* outbound from driver */
593 uint32_t in_mb; /* Incoming from RISC */
594 uint16_t mb[MAILBOX_REGISTER_COUNT];
595 long buf_size;
596 void *bufp;
597 uint32_t tov;
598 uint8_t flags;
599 #define MBX_DMA_IN BIT_0
600 #define MBX_DMA_OUT BIT_1
601 #define IOCTL_CMD BIT_2
602 } mbx_cmd_t;
603
604 #define MBX_TOV_SECONDS 30
605
606 /*
607 * ISP product identification definitions in mailboxes after reset.
608 */
609 #define PROD_ID_1 0x4953
610 #define PROD_ID_2 0x0000
611 #define PROD_ID_2a 0x5020
612 #define PROD_ID_3 0x2020
613
614 /*
615 * ISP mailbox Self-Test status codes
616 */
617 #define MBS_FRM_ALIVE 0 /* Firmware Alive. */
618 #define MBS_CHKSUM_ERR 1 /* Checksum Error. */
619 #define MBS_BUSY 4 /* Busy. */
620
621 /*
622 * ISP mailbox command complete status codes
623 */
624 #define MBS_COMMAND_COMPLETE 0x4000
625 #define MBS_INVALID_COMMAND 0x4001
626 #define MBS_HOST_INTERFACE_ERROR 0x4002
627 #define MBS_TEST_FAILED 0x4003
628 #define MBS_COMMAND_ERROR 0x4005
629 #define MBS_COMMAND_PARAMETER_ERROR 0x4006
630 #define MBS_PORT_ID_USED 0x4007
631 #define MBS_LOOP_ID_USED 0x4008
632 #define MBS_ALL_IDS_IN_USE 0x4009
633 #define MBS_NOT_LOGGED_IN 0x400A
634 #define MBS_LINK_DOWN_ERROR 0x400B
635 #define MBS_DIAG_ECHO_TEST_ERROR 0x400C
636
637 /*
638 * ISP mailbox asynchronous event status codes
639 */
640 #define MBA_ASYNC_EVENT 0x8000 /* Asynchronous event. */
641 #define MBA_RESET 0x8001 /* Reset Detected. */
642 #define MBA_SYSTEM_ERR 0x8002 /* System Error. */
643 #define MBA_REQ_TRANSFER_ERR 0x8003 /* Request Transfer Error. */
644 #define MBA_RSP_TRANSFER_ERR 0x8004 /* Response Transfer Error. */
645 #define MBA_WAKEUP_THRES 0x8005 /* Request Queue Wake-up. */
646 #define MBA_LIP_OCCURRED 0x8010 /* Loop Initialization Procedure */
647 /* occurred. */
648 #define MBA_LOOP_UP 0x8011 /* FC Loop UP. */
649 #define MBA_LOOP_DOWN 0x8012 /* FC Loop Down. */
650 #define MBA_LIP_RESET 0x8013 /* LIP reset occurred. */
651 #define MBA_PORT_UPDATE 0x8014 /* Port Database update. */
652 #define MBA_RSCN_UPDATE 0x8015 /* Register State Chg Notification. */
653 #define MBA_LIP_F8 0x8016 /* Received a LIP F8. */
654 #define MBA_LOOP_INIT_ERR 0x8017 /* Loop Initialization Error. */
655 #define MBA_FABRIC_AUTH_REQ 0x801b /* Fabric Authentication Required. */
656 #define MBA_SCSI_COMPLETION 0x8020 /* SCSI Command Complete. */
657 #define MBA_CTIO_COMPLETION 0x8021 /* CTIO Complete. */
658 #define MBA_IP_COMPLETION 0x8022 /* IP Transmit Command Complete. */
659 #define MBA_IP_RECEIVE 0x8023 /* IP Received. */
660 #define MBA_IP_BROADCAST 0x8024 /* IP Broadcast Received. */
661 #define MBA_IP_LOW_WATER_MARK 0x8025 /* IP Low Water Mark reached. */
662 #define MBA_IP_RCV_BUFFER_EMPTY 0x8026 /* IP receive buffer queue empty. */
663 #define MBA_IP_HDR_DATA_SPLIT 0x8027 /* IP header/data splitting feature */
664 /* used. */
665 #define MBA_TRACE_NOTIFICATION 0x8028 /* Trace/Diagnostic notification. */
666 #define MBA_POINT_TO_POINT 0x8030 /* Point to point mode. */
667 #define MBA_CMPLT_1_16BIT 0x8031 /* Completion 1 16bit IOSB. */
668 #define MBA_CMPLT_2_16BIT 0x8032 /* Completion 2 16bit IOSB. */
669 #define MBA_CMPLT_3_16BIT 0x8033 /* Completion 3 16bit IOSB. */
670 #define MBA_CMPLT_4_16BIT 0x8034 /* Completion 4 16bit IOSB. */
671 #define MBA_CMPLT_5_16BIT 0x8035 /* Completion 5 16bit IOSB. */
672 #define MBA_CHG_IN_CONNECTION 0x8036 /* Change in connection mode. */
673 #define MBA_RIO_RESPONSE 0x8040 /* RIO response queue update. */
674 #define MBA_ZIO_RESPONSE 0x8040 /* ZIO response queue update. */
675 #define MBA_CMPLT_2_32BIT 0x8042 /* Completion 2 32bit IOSB. */
676 #define MBA_BYPASS_NOTIFICATION 0x8043 /* Auto bypass notification. */
677 #define MBA_DISCARD_RND_FRAME 0x8048 /* discard RND frame due to error. */
678 #define MBA_REJECTED_FCP_CMD 0x8049 /* rejected FCP_CMD. */
679
680 /* 83XX FCoE specific */
681 #define MBA_IDC_AEN 0x8200 /* FCoE: NIC Core state change AEN */
682
683 /* Interrupt type codes */
684 #define INTR_ROM_MB_SUCCESS 0x1
685 #define INTR_ROM_MB_FAILED 0x2
686 #define INTR_MB_SUCCESS 0x10
687 #define INTR_MB_FAILED 0x11
688 #define INTR_ASYNC_EVENT 0x12
689 #define INTR_RSP_QUE_UPDATE 0x13
690 #define INTR_RSP_QUE_UPDATE_83XX 0x14
691 #define INTR_ATIO_QUE_UPDATE 0x1C
692 #define INTR_ATIO_RSP_QUE_UPDATE 0x1D
693
694 /* ISP mailbox loopback echo diagnostic error code */
695 #define MBS_LB_RESET 0x17
696 /*
697 * Firmware options 1, 2, 3.
698 */
699 #define FO1_AE_ON_LIPF8 BIT_0
700 #define FO1_AE_ALL_LIP_RESET BIT_1
701 #define FO1_CTIO_RETRY BIT_3
702 #define FO1_DISABLE_LIP_F7_SW BIT_4
703 #define FO1_DISABLE_100MS_LOS_WAIT BIT_5
704 #define FO1_DISABLE_GPIO6_7 BIT_6 /* LED bits */
705 #define FO1_AE_ON_LOOP_INIT_ERR BIT_7
706 #define FO1_SET_EMPHASIS_SWING BIT_8
707 #define FO1_AE_AUTO_BYPASS BIT_9
708 #define FO1_ENABLE_PURE_IOCB BIT_10
709 #define FO1_AE_PLOGI_RJT BIT_11
710 #define FO1_ENABLE_ABORT_SEQUENCE BIT_12
711 #define FO1_AE_QUEUE_FULL BIT_13
712
713 #define FO2_ENABLE_ATIO_TYPE_3 BIT_0
714 #define FO2_REV_LOOPBACK BIT_1
715
716 #define FO3_ENABLE_EMERG_IOCB BIT_0
717 #define FO3_AE_RND_ERROR BIT_1
718
719 /* 24XX additional firmware options */
720 #define ADD_FO_COUNT 3
721 #define ADD_FO1_DISABLE_GPIO_LED_CTRL BIT_6 /* LED bits */
722 #define ADD_FO1_ENABLE_PUREX_IOCB BIT_10
723
724 #define ADD_FO2_ENABLE_SEL_CLS2 BIT_5
725
726 #define ADD_FO3_NO_ABT_ON_LINK_DOWN BIT_14
727
728 /*
729 * ISP mailbox commands
730 */
731 #define MBC_LOAD_RAM 1 /* Load RAM. */
732 #define MBC_EXECUTE_FIRMWARE 2 /* Execute firmware. */
733 #define MBC_WRITE_RAM_WORD 4 /* Write RAM word. */
734 #define MBC_READ_RAM_WORD 5 /* Read RAM word. */
735 #define MBC_MAILBOX_REGISTER_TEST 6 /* Wrap incoming mailboxes */
736 #define MBC_VERIFY_CHECKSUM 7 /* Verify checksum. */
737 #define MBC_GET_FIRMWARE_VERSION 8 /* Get firmware revision. */
738 #define MBC_LOAD_RISC_RAM 9 /* Load RAM command. */
739 #define MBC_DUMP_RISC_RAM 0xa /* Dump RAM command. */
740 #define MBC_LOAD_RISC_RAM_EXTENDED 0xb /* Load RAM extended. */
741 #define MBC_DUMP_RISC_RAM_EXTENDED 0xc /* Dump RAM extended. */
742 #define MBC_WRITE_RAM_WORD_EXTENDED 0xd /* Write RAM word extended */
743 #define MBC_READ_RAM_EXTENDED 0xf /* Read RAM extended. */
744 #define MBC_IOCB_COMMAND 0x12 /* Execute IOCB command. */
745 #define MBC_STOP_FIRMWARE 0x14 /* Stop firmware. */
746 #define MBC_ABORT_COMMAND 0x15 /* Abort IOCB command. */
747 #define MBC_ABORT_DEVICE 0x16 /* Abort device (ID/LUN). */
748 #define MBC_ABORT_TARGET 0x17 /* Abort target (ID). */
749 #define MBC_RESET 0x18 /* Reset. */
750 #define MBC_GET_ADAPTER_LOOP_ID 0x20 /* Get loop id of ISP2200. */
751 #define MBC_GET_RETRY_COUNT 0x22 /* Get f/w retry cnt/delay. */
752 #define MBC_DISABLE_VI 0x24 /* Disable VI operation. */
753 #define MBC_ENABLE_VI 0x25 /* Enable VI operation. */
754 #define MBC_GET_FIRMWARE_OPTION 0x28 /* Get Firmware Options. */
755 #define MBC_SET_FIRMWARE_OPTION 0x38 /* Set Firmware Options. */
756 #define MBC_LOOP_PORT_BYPASS 0x40 /* Loop Port Bypass. */
757 #define MBC_LOOP_PORT_ENABLE 0x41 /* Loop Port Enable. */
758 #define MBC_GET_RESOURCE_COUNTS 0x42 /* Get Resource Counts. */
759 #define MBC_NON_PARTICIPATE 0x43 /* Non-Participating Mode. */
760 #define MBC_DIAGNOSTIC_ECHO 0x44 /* Diagnostic echo. */
761 #define MBC_DIAGNOSTIC_LOOP_BACK 0x45 /* Diagnostic loop back. */
762 #define MBC_ONLINE_SELF_TEST 0x46 /* Online self-test. */
763 #define MBC_ENHANCED_GET_PORT_DATABASE 0x47 /* Get port database + login */
764 #define MBC_CONFIGURE_VF 0x4b /* Configure VFs */
765 #define MBC_RESET_LINK_STATUS 0x52 /* Reset Link Error Status */
766 #define MBC_IOCB_COMMAND_A64 0x54 /* Execute IOCB command (64) */
767 #define MBC_PORT_LOGOUT 0x56 /* Port Logout request */
768 #define MBC_SEND_RNID_ELS 0x57 /* Send RNID ELS request */
769 #define MBC_SET_RNID_PARAMS 0x59 /* Set RNID parameters */
770 #define MBC_GET_RNID_PARAMS 0x5a /* Data Rate */
771 #define MBC_DATA_RATE 0x5d /* Get RNID parameters */
772 #define MBC_INITIALIZE_FIRMWARE 0x60 /* Initialize firmware */
773 #define MBC_INITIATE_LIP 0x62 /* Initiate Loop */
774 /* Initialization Procedure */
775 #define MBC_GET_FC_AL_POSITION_MAP 0x63 /* Get FC_AL Position Map. */
776 #define MBC_GET_PORT_DATABASE 0x64 /* Get Port Database. */
777 #define MBC_CLEAR_ACA 0x65 /* Clear ACA. */
778 #define MBC_TARGET_RESET 0x66 /* Target Reset. */
779 #define MBC_CLEAR_TASK_SET 0x67 /* Clear Task Set. */
780 #define MBC_ABORT_TASK_SET 0x68 /* Abort Task Set. */
781 #define MBC_GET_FIRMWARE_STATE 0x69 /* Get firmware state. */
782 #define MBC_GET_PORT_NAME 0x6a /* Get port name. */
783 #define MBC_GET_LINK_STATUS 0x6b /* Get port link status. */
784 #define MBC_LIP_RESET 0x6c /* LIP reset. */
785 #define MBC_SEND_SNS_COMMAND 0x6e /* Send Simple Name Server */
786 /* commandd. */
787 #define MBC_LOGIN_FABRIC_PORT 0x6f /* Login fabric port. */
788 #define MBC_SEND_CHANGE_REQUEST 0x70 /* Send Change Request. */
789 #define MBC_LOGOUT_FABRIC_PORT 0x71 /* Logout fabric port. */
790 #define MBC_LIP_FULL_LOGIN 0x72 /* Full login LIP. */
791 #define MBC_LOGIN_LOOP_PORT 0x74 /* Login Loop Port. */
792 #define MBC_PORT_NODE_NAME_LIST 0x75 /* Get port/node name list. */
793 #define MBC_INITIALIZE_RECEIVE_QUEUE 0x77 /* Initialize receive queue */
794 #define MBC_UNLOAD_IP 0x79 /* Shutdown IP */
795 #define MBC_GET_ID_LIST 0x7C /* Get Port ID list. */
796 #define MBC_SEND_LFA_COMMAND 0x7D /* Send Loop Fabric Address */
797 #define MBC_LUN_RESET 0x7E /* Send LUN reset */
798
799 /*
800 * ISP24xx mailbox commands
801 */
802 #define MBC_SERDES_PARAMS 0x10 /* Serdes Tx Parameters. */
803 #define MBC_GET_IOCB_STATUS 0x12 /* Get IOCB status command. */
804 #define MBC_PORT_PARAMS 0x1A /* Port iDMA Parameters. */
805 #define MBC_GET_TIMEOUT_PARAMS 0x22 /* Get FW timeouts. */
806 #define MBC_TRACE_CONTROL 0x27 /* Trace control command. */
807 #define MBC_GEN_SYSTEM_ERROR 0x2a /* Generate System Error. */
808 #define MBC_WRITE_SFP 0x30 /* Write SFP Data. */
809 #define MBC_READ_SFP 0x31 /* Read SFP Data. */
810 #define MBC_SET_TIMEOUT_PARAMS 0x32 /* Set FW timeouts. */
811 #define MBC_MID_INITIALIZE_FIRMWARE 0x48 /* MID Initialize firmware. */
812 #define MBC_MID_GET_VP_DATABASE 0x49 /* MID Get VP Database. */
813 #define MBC_MID_GET_VP_ENTRY 0x4a /* MID Get VP Entry. */
814 #define MBC_HOST_MEMORY_COPY 0x53 /* Host Memory Copy. */
815 #define MBC_SEND_RNFT_ELS 0x5e /* Send RNFT ELS request */
816 #define MBC_GET_LINK_PRIV_STATS 0x6d /* Get link & private data. */
817 #define MBC_SET_VENDOR_ID 0x76 /* Set Vendor ID. */
818 #define MBC_PORT_RESET 0x120 /* Port Reset */
819 #define MBC_SET_PORT_CONFIG 0x122 /* Set port configuration */
820 #define MBC_GET_PORT_CONFIG 0x123 /* Get port configuration */
821
822 /*
823 * ISP81xx mailbox commands
824 */
825 #define MBC_WRITE_MPI_REGISTER 0x01 /* Write MPI Register. */
826
827 /* Firmware return data sizes */
828 #define FCAL_MAP_SIZE 128
829
830 /* Mailbox bit definitions for out_mb and in_mb */
831 #define MBX_31 BIT_31
832 #define MBX_30 BIT_30
833 #define MBX_29 BIT_29
834 #define MBX_28 BIT_28
835 #define MBX_27 BIT_27
836 #define MBX_26 BIT_26
837 #define MBX_25 BIT_25
838 #define MBX_24 BIT_24
839 #define MBX_23 BIT_23
840 #define MBX_22 BIT_22
841 #define MBX_21 BIT_21
842 #define MBX_20 BIT_20
843 #define MBX_19 BIT_19
844 #define MBX_18 BIT_18
845 #define MBX_17 BIT_17
846 #define MBX_16 BIT_16
847 #define MBX_15 BIT_15
848 #define MBX_14 BIT_14
849 #define MBX_13 BIT_13
850 #define MBX_12 BIT_12
851 #define MBX_11 BIT_11
852 #define MBX_10 BIT_10
853 #define MBX_9 BIT_9
854 #define MBX_8 BIT_8
855 #define MBX_7 BIT_7
856 #define MBX_6 BIT_6
857 #define MBX_5 BIT_5
858 #define MBX_4 BIT_4
859 #define MBX_3 BIT_3
860 #define MBX_2 BIT_2
861 #define MBX_1 BIT_1
862 #define MBX_0 BIT_0
863
864 /*
865 * Firmware state codes from get firmware state mailbox command
866 */
867 #define FSTATE_CONFIG_WAIT 0
868 #define FSTATE_WAIT_AL_PA 1
869 #define FSTATE_WAIT_LOGIN 2
870 #define FSTATE_READY 3
871 #define FSTATE_LOSS_OF_SYNC 4
872 #define FSTATE_ERROR 5
873 #define FSTATE_REINIT 6
874 #define FSTATE_NON_PART 7
875
876 #define FSTATE_CONFIG_CORRECT 0
877 #define FSTATE_P2P_RCV_LIP 1
878 #define FSTATE_P2P_CHOOSE_LOOP 2
879 #define FSTATE_P2P_RCV_UNIDEN_LIP 3
880 #define FSTATE_FATAL_ERROR 4
881 #define FSTATE_LOOP_BACK_CONN 5
882
883 /*
884 * Port Database structure definition
885 * Little endian except where noted.
886 */
887 #define PORT_DATABASE_SIZE 128 /* bytes */
888 typedef struct {
889 uint8_t options;
890 uint8_t control;
891 uint8_t master_state;
892 uint8_t slave_state;
893 uint8_t reserved[2];
894 uint8_t hard_address;
895 uint8_t reserved_1;
896 uint8_t port_id[4];
897 uint8_t node_name[WWN_SIZE];
898 uint8_t port_name[WWN_SIZE];
899 uint16_t execution_throttle;
900 uint16_t execution_count;
901 uint8_t reset_count;
902 uint8_t reserved_2;
903 uint16_t resource_allocation;
904 uint16_t current_allocation;
905 uint16_t queue_head;
906 uint16_t queue_tail;
907 uint16_t transmit_execution_list_next;
908 uint16_t transmit_execution_list_previous;
909 uint16_t common_features;
910 uint16_t total_concurrent_sequences;
911 uint16_t RO_by_information_category;
912 uint8_t recipient;
913 uint8_t initiator;
914 uint16_t receive_data_size;
915 uint16_t concurrent_sequences;
916 uint16_t open_sequences_per_exchange;
917 uint16_t lun_abort_flags;
918 uint16_t lun_stop_flags;
919 uint16_t stop_queue_head;
920 uint16_t stop_queue_tail;
921 uint16_t port_retry_timer;
922 uint16_t next_sequence_id;
923 uint16_t frame_count;
924 uint16_t PRLI_payload_length;
925 uint8_t prli_svc_param_word_0[2]; /* Big endian */
926 /* Bits 15-0 of word 0 */
927 uint8_t prli_svc_param_word_3[2]; /* Big endian */
928 /* Bits 15-0 of word 3 */
929 uint16_t loop_id;
930 uint16_t extended_lun_info_list_pointer;
931 uint16_t extended_lun_stop_list_pointer;
932 } port_database_t;
933
934 /*
935 * Port database slave/master states
936 */
937 #define PD_STATE_DISCOVERY 0
938 #define PD_STATE_WAIT_DISCOVERY_ACK 1
939 #define PD_STATE_PORT_LOGIN 2
940 #define PD_STATE_WAIT_PORT_LOGIN_ACK 3
941 #define PD_STATE_PROCESS_LOGIN 4
942 #define PD_STATE_WAIT_PROCESS_LOGIN_ACK 5
943 #define PD_STATE_PORT_LOGGED_IN 6
944 #define PD_STATE_PORT_UNAVAILABLE 7
945 #define PD_STATE_PROCESS_LOGOUT 8
946 #define PD_STATE_WAIT_PROCESS_LOGOUT_ACK 9
947 #define PD_STATE_PORT_LOGOUT 10
948 #define PD_STATE_WAIT_PORT_LOGOUT_ACK 11
949
950
951 #define QLA_ZIO_MODE_6 (BIT_2 | BIT_1)
952 #define QLA_ZIO_DISABLED 0
953 #define QLA_ZIO_DEFAULT_TIMER 2
954
955 /*
956 * ISP Initialization Control Block.
957 * Little endian except where noted.
958 */
959 #define ICB_VERSION 1
960 typedef struct {
961 uint8_t version;
962 uint8_t reserved_1;
963
964 /*
965 * LSB BIT 0 = Enable Hard Loop Id
966 * LSB BIT 1 = Enable Fairness
967 * LSB BIT 2 = Enable Full-Duplex
968 * LSB BIT 3 = Enable Fast Posting
969 * LSB BIT 4 = Enable Target Mode
970 * LSB BIT 5 = Disable Initiator Mode
971 * LSB BIT 6 = Enable ADISC
972 * LSB BIT 7 = Enable Target Inquiry Data
973 *
974 * MSB BIT 0 = Enable PDBC Notify
975 * MSB BIT 1 = Non Participating LIP
976 * MSB BIT 2 = Descending Loop ID Search
977 * MSB BIT 3 = Acquire Loop ID in LIPA
978 * MSB BIT 4 = Stop PortQ on Full Status
979 * MSB BIT 5 = Full Login after LIP
980 * MSB BIT 6 = Node Name Option
981 * MSB BIT 7 = Ext IFWCB enable bit
982 */
983 uint8_t firmware_options[2];
984
985 uint16_t frame_payload_size;
986 uint16_t max_iocb_allocation;
987 uint16_t execution_throttle;
988 uint8_t retry_count;
989 uint8_t retry_delay; /* unused */
990 uint8_t port_name[WWN_SIZE]; /* Big endian. */
991 uint16_t hard_address;
992 uint8_t inquiry_data;
993 uint8_t login_timeout;
994 uint8_t node_name[WWN_SIZE]; /* Big endian. */
995
996 uint16_t request_q_outpointer;
997 uint16_t response_q_inpointer;
998 uint16_t request_q_length;
999 uint16_t response_q_length;
1000 uint32_t request_q_address[2];
1001 uint32_t response_q_address[2];
1002
1003 uint16_t lun_enables;
1004 uint8_t command_resource_count;
1005 uint8_t immediate_notify_resource_count;
1006 uint16_t timeout;
1007 uint8_t reserved_2[2];
1008
1009 /*
1010 * LSB BIT 0 = Timer Operation mode bit 0
1011 * LSB BIT 1 = Timer Operation mode bit 1
1012 * LSB BIT 2 = Timer Operation mode bit 2
1013 * LSB BIT 3 = Timer Operation mode bit 3
1014 * LSB BIT 4 = Init Config Mode bit 0
1015 * LSB BIT 5 = Init Config Mode bit 1
1016 * LSB BIT 6 = Init Config Mode bit 2
1017 * LSB BIT 7 = Enable Non part on LIHA failure
1018 *
1019 * MSB BIT 0 = Enable class 2
1020 * MSB BIT 1 = Enable ACK0
1021 * MSB BIT 2 =
1022 * MSB BIT 3 =
1023 * MSB BIT 4 = FC Tape Enable
1024 * MSB BIT 5 = Enable FC Confirm
1025 * MSB BIT 6 = Enable command queuing in target mode
1026 * MSB BIT 7 = No Logo On Link Down
1027 */
1028 uint8_t add_firmware_options[2];
1029
1030 uint8_t response_accumulation_timer;
1031 uint8_t interrupt_delay_timer;
1032
1033 /*
1034 * LSB BIT 0 = Enable Read xfr_rdy
1035 * LSB BIT 1 = Soft ID only
1036 * LSB BIT 2 =
1037 * LSB BIT 3 =
1038 * LSB BIT 4 = FCP RSP Payload [0]
1039 * LSB BIT 5 = FCP RSP Payload [1] / Sbus enable - 2200
1040 * LSB BIT 6 = Enable Out-of-Order frame handling
1041 * LSB BIT 7 = Disable Automatic PLOGI on Local Loop
1042 *
1043 * MSB BIT 0 = Sbus enable - 2300
1044 * MSB BIT 1 =
1045 * MSB BIT 2 =
1046 * MSB BIT 3 =
1047 * MSB BIT 4 = LED mode
1048 * MSB BIT 5 = enable 50 ohm termination
1049 * MSB BIT 6 = Data Rate (2300 only)
1050 * MSB BIT 7 = Data Rate (2300 only)
1051 */
1052 uint8_t special_options[2];
1053
1054 uint8_t reserved_3[26];
1055 } init_cb_t;
1056
1057 /*
1058 * Get Link Status mailbox command return buffer.
1059 */
1060 #define GLSO_SEND_RPS BIT_0
1061 #define GLSO_USE_DID BIT_3
1062
1063 struct link_statistics {
1064 uint32_t link_fail_cnt;
1065 uint32_t loss_sync_cnt;
1066 uint32_t loss_sig_cnt;
1067 uint32_t prim_seq_err_cnt;
1068 uint32_t inval_xmit_word_cnt;
1069 uint32_t inval_crc_cnt;
1070 uint32_t lip_cnt;
1071 uint32_t unused1[0x1a];
1072 uint32_t tx_frames;
1073 uint32_t rx_frames;
1074 uint32_t dumped_frames;
1075 uint32_t unused2[2];
1076 uint32_t nos_rcvd;
1077 };
1078
1079 /*
1080 * NVRAM Command values.
1081 */
1082 #define NV_START_BIT BIT_2
1083 #define NV_WRITE_OP (BIT_26+BIT_24)
1084 #define NV_READ_OP (BIT_26+BIT_25)
1085 #define NV_ERASE_OP (BIT_26+BIT_25+BIT_24)
1086 #define NV_MASK_OP (BIT_26+BIT_25+BIT_24)
1087 #define NV_DELAY_COUNT 10
1088
1089 /*
1090 * QLogic ISP2100, ISP2200 and ISP2300 NVRAM structure definition.
1091 */
1092 typedef struct {
1093 /*
1094 * NVRAM header
1095 */
1096 uint8_t id[4];
1097 uint8_t nvram_version;
1098 uint8_t reserved_0;
1099
1100 /*
1101 * NVRAM RISC parameter block
1102 */
1103 uint8_t parameter_block_version;
1104 uint8_t reserved_1;
1105
1106 /*
1107 * LSB BIT 0 = Enable Hard Loop Id
1108 * LSB BIT 1 = Enable Fairness
1109 * LSB BIT 2 = Enable Full-Duplex
1110 * LSB BIT 3 = Enable Fast Posting
1111 * LSB BIT 4 = Enable Target Mode
1112 * LSB BIT 5 = Disable Initiator Mode
1113 * LSB BIT 6 = Enable ADISC
1114 * LSB BIT 7 = Enable Target Inquiry Data
1115 *
1116 * MSB BIT 0 = Enable PDBC Notify
1117 * MSB BIT 1 = Non Participating LIP
1118 * MSB BIT 2 = Descending Loop ID Search
1119 * MSB BIT 3 = Acquire Loop ID in LIPA
1120 * MSB BIT 4 = Stop PortQ on Full Status
1121 * MSB BIT 5 = Full Login after LIP
1122 * MSB BIT 6 = Node Name Option
1123 * MSB BIT 7 = Ext IFWCB enable bit
1124 */
1125 uint8_t firmware_options[2];
1126
1127 uint16_t frame_payload_size;
1128 uint16_t max_iocb_allocation;
1129 uint16_t execution_throttle;
1130 uint8_t retry_count;
1131 uint8_t retry_delay; /* unused */
1132 uint8_t port_name[WWN_SIZE]; /* Big endian. */
1133 uint16_t hard_address;
1134 uint8_t inquiry_data;
1135 uint8_t login_timeout;
1136 uint8_t node_name[WWN_SIZE]; /* Big endian. */
1137
1138 /*
1139 * LSB BIT 0 = Timer Operation mode bit 0
1140 * LSB BIT 1 = Timer Operation mode bit 1
1141 * LSB BIT 2 = Timer Operation mode bit 2
1142 * LSB BIT 3 = Timer Operation mode bit 3
1143 * LSB BIT 4 = Init Config Mode bit 0
1144 * LSB BIT 5 = Init Config Mode bit 1
1145 * LSB BIT 6 = Init Config Mode bit 2
1146 * LSB BIT 7 = Enable Non part on LIHA failure
1147 *
1148 * MSB BIT 0 = Enable class 2
1149 * MSB BIT 1 = Enable ACK0
1150 * MSB BIT 2 =
1151 * MSB BIT 3 =
1152 * MSB BIT 4 = FC Tape Enable
1153 * MSB BIT 5 = Enable FC Confirm
1154 * MSB BIT 6 = Enable command queuing in target mode
1155 * MSB BIT 7 = No Logo On Link Down
1156 */
1157 uint8_t add_firmware_options[2];
1158
1159 uint8_t response_accumulation_timer;
1160 uint8_t interrupt_delay_timer;
1161
1162 /*
1163 * LSB BIT 0 = Enable Read xfr_rdy
1164 * LSB BIT 1 = Soft ID only
1165 * LSB BIT 2 =
1166 * LSB BIT 3 =
1167 * LSB BIT 4 = FCP RSP Payload [0]
1168 * LSB BIT 5 = FCP RSP Payload [1] / Sbus enable - 2200
1169 * LSB BIT 6 = Enable Out-of-Order frame handling
1170 * LSB BIT 7 = Disable Automatic PLOGI on Local Loop
1171 *
1172 * MSB BIT 0 = Sbus enable - 2300
1173 * MSB BIT 1 =
1174 * MSB BIT 2 =
1175 * MSB BIT 3 =
1176 * MSB BIT 4 = LED mode
1177 * MSB BIT 5 = enable 50 ohm termination
1178 * MSB BIT 6 = Data Rate (2300 only)
1179 * MSB BIT 7 = Data Rate (2300 only)
1180 */
1181 uint8_t special_options[2];
1182
1183 /* Reserved for expanded RISC parameter block */
1184 uint8_t reserved_2[22];
1185
1186 /*
1187 * LSB BIT 0 = Tx Sensitivity 1G bit 0
1188 * LSB BIT 1 = Tx Sensitivity 1G bit 1
1189 * LSB BIT 2 = Tx Sensitivity 1G bit 2
1190 * LSB BIT 3 = Tx Sensitivity 1G bit 3
1191 * LSB BIT 4 = Rx Sensitivity 1G bit 0
1192 * LSB BIT 5 = Rx Sensitivity 1G bit 1
1193 * LSB BIT 6 = Rx Sensitivity 1G bit 2
1194 * LSB BIT 7 = Rx Sensitivity 1G bit 3
1195 *
1196 * MSB BIT 0 = Tx Sensitivity 2G bit 0
1197 * MSB BIT 1 = Tx Sensitivity 2G bit 1
1198 * MSB BIT 2 = Tx Sensitivity 2G bit 2
1199 * MSB BIT 3 = Tx Sensitivity 2G bit 3
1200 * MSB BIT 4 = Rx Sensitivity 2G bit 0
1201 * MSB BIT 5 = Rx Sensitivity 2G bit 1
1202 * MSB BIT 6 = Rx Sensitivity 2G bit 2
1203 * MSB BIT 7 = Rx Sensitivity 2G bit 3
1204 *
1205 * LSB BIT 0 = Output Swing 1G bit 0
1206 * LSB BIT 1 = Output Swing 1G bit 1
1207 * LSB BIT 2 = Output Swing 1G bit 2
1208 * LSB BIT 3 = Output Emphasis 1G bit 0
1209 * LSB BIT 4 = Output Emphasis 1G bit 1
1210 * LSB BIT 5 = Output Swing 2G bit 0
1211 * LSB BIT 6 = Output Swing 2G bit 1
1212 * LSB BIT 7 = Output Swing 2G bit 2
1213 *
1214 * MSB BIT 0 = Output Emphasis 2G bit 0
1215 * MSB BIT 1 = Output Emphasis 2G bit 1
1216 * MSB BIT 2 = Output Enable
1217 * MSB BIT 3 =
1218 * MSB BIT 4 =
1219 * MSB BIT 5 =
1220 * MSB BIT 6 =
1221 * MSB BIT 7 =
1222 */
1223 uint8_t seriallink_options[4];
1224
1225 /*
1226 * NVRAM host parameter block
1227 *
1228 * LSB BIT 0 = Enable spinup delay
1229 * LSB BIT 1 = Disable BIOS
1230 * LSB BIT 2 = Enable Memory Map BIOS
1231 * LSB BIT 3 = Enable Selectable Boot
1232 * LSB BIT 4 = Disable RISC code load
1233 * LSB BIT 5 = Set cache line size 1
1234 * LSB BIT 6 = PCI Parity Disable
1235 * LSB BIT 7 = Enable extended logging
1236 *
1237 * MSB BIT 0 = Enable 64bit addressing
1238 * MSB BIT 1 = Enable lip reset
1239 * MSB BIT 2 = Enable lip full login
1240 * MSB BIT 3 = Enable target reset
1241 * MSB BIT 4 = Enable database storage
1242 * MSB BIT 5 = Enable cache flush read
1243 * MSB BIT 6 = Enable database load
1244 * MSB BIT 7 = Enable alternate WWN
1245 */
1246 uint8_t host_p[2];
1247
1248 uint8_t boot_node_name[WWN_SIZE];
1249 uint8_t boot_lun_number;
1250 uint8_t reset_delay;
1251 uint8_t port_down_retry_count;
1252 uint8_t boot_id_number;
1253 uint16_t max_luns_per_target;
1254 uint8_t fcode_boot_port_name[WWN_SIZE];
1255 uint8_t alternate_port_name[WWN_SIZE];
1256 uint8_t alternate_node_name[WWN_SIZE];
1257
1258 /*
1259 * BIT 0 = Selective Login
1260 * BIT 1 = Alt-Boot Enable
1261 * BIT 2 =
1262 * BIT 3 = Boot Order List
1263 * BIT 4 =
1264 * BIT 5 = Selective LUN
1265 * BIT 6 =
1266 * BIT 7 = unused
1267 */
1268 uint8_t efi_parameters;
1269
1270 uint8_t link_down_timeout;
1271
1272 uint8_t adapter_id[16];
1273
1274 uint8_t alt1_boot_node_name[WWN_SIZE];
1275 uint16_t alt1_boot_lun_number;
1276 uint8_t alt2_boot_node_name[WWN_SIZE];
1277 uint16_t alt2_boot_lun_number;
1278 uint8_t alt3_boot_node_name[WWN_SIZE];
1279 uint16_t alt3_boot_lun_number;
1280 uint8_t alt4_boot_node_name[WWN_SIZE];
1281 uint16_t alt4_boot_lun_number;
1282 uint8_t alt5_boot_node_name[WWN_SIZE];
1283 uint16_t alt5_boot_lun_number;
1284 uint8_t alt6_boot_node_name[WWN_SIZE];
1285 uint16_t alt6_boot_lun_number;
1286 uint8_t alt7_boot_node_name[WWN_SIZE];
1287 uint16_t alt7_boot_lun_number;
1288
1289 uint8_t reserved_3[2];
1290
1291 /* Offset 200-215 : Model Number */
1292 uint8_t model_number[16];
1293
1294 /* OEM related items */
1295 uint8_t oem_specific[16];
1296
1297 /*
1298 * NVRAM Adapter Features offset 232-239
1299 *
1300 * LSB BIT 0 = External GBIC
1301 * LSB BIT 1 = Risc RAM parity
1302 * LSB BIT 2 = Buffer Plus Module
1303 * LSB BIT 3 = Multi Chip Adapter
1304 * LSB BIT 4 = Internal connector
1305 * LSB BIT 5 =
1306 * LSB BIT 6 =
1307 * LSB BIT 7 =
1308 *
1309 * MSB BIT 0 =
1310 * MSB BIT 1 =
1311 * MSB BIT 2 =
1312 * MSB BIT 3 =
1313 * MSB BIT 4 =
1314 * MSB BIT 5 =
1315 * MSB BIT 6 =
1316 * MSB BIT 7 =
1317 */
1318 uint8_t adapter_features[2];
1319
1320 uint8_t reserved_4[16];
1321
1322 /* Subsystem vendor ID for ISP2200 */
1323 uint16_t subsystem_vendor_id_2200;
1324
1325 /* Subsystem device ID for ISP2200 */
1326 uint16_t subsystem_device_id_2200;
1327
1328 uint8_t reserved_5;
1329 uint8_t checksum;
1330 } nvram_t;
1331
1332 /*
1333 * ISP queue - response queue entry definition.
1334 */
1335 typedef struct {
1336 uint8_t entry_type; /* Entry type. */
1337 uint8_t entry_count; /* Entry count. */
1338 uint8_t sys_define; /* System defined. */
1339 uint8_t entry_status; /* Entry Status. */
1340 uint32_t handle; /* System defined handle */
1341 uint8_t data[52];
1342 uint32_t signature;
1343 #define RESPONSE_PROCESSED 0xDEADDEAD /* Signature */
1344 } response_t;
1345
1346 /*
1347 * ISP queue - ATIO queue entry definition.
1348 */
1349 struct atio {
1350 uint8_t entry_type; /* Entry type. */
1351 uint8_t entry_count; /* Entry count. */
1352 uint8_t data[58];
1353 uint32_t signature;
1354 #define ATIO_PROCESSED 0xDEADDEAD /* Signature */
1355 };
1356
1357 typedef union {
1358 uint16_t extended;
1359 struct {
1360 uint8_t reserved;
1361 uint8_t standard;
1362 } id;
1363 } target_id_t;
1364
1365 #define SET_TARGET_ID(ha, to, from) \
1366 do { \
1367 if (HAS_EXTENDED_IDS(ha)) \
1368 to.extended = cpu_to_le16(from); \
1369 else \
1370 to.id.standard = (uint8_t)from; \
1371 } while (0)
1372
1373 /*
1374 * ISP queue - command entry structure definition.
1375 */
1376 #define COMMAND_TYPE 0x11 /* Command entry */
1377 typedef struct {
1378 uint8_t entry_type; /* Entry type. */
1379 uint8_t entry_count; /* Entry count. */
1380 uint8_t sys_define; /* System defined. */
1381 uint8_t entry_status; /* Entry Status. */
1382 uint32_t handle; /* System handle. */
1383 target_id_t target; /* SCSI ID */
1384 uint16_t lun; /* SCSI LUN */
1385 uint16_t control_flags; /* Control flags. */
1386 #define CF_WRITE BIT_6
1387 #define CF_READ BIT_5
1388 #define CF_SIMPLE_TAG BIT_3
1389 #define CF_ORDERED_TAG BIT_2
1390 #define CF_HEAD_TAG BIT_1
1391 uint16_t reserved_1;
1392 uint16_t timeout; /* Command timeout. */
1393 uint16_t dseg_count; /* Data segment count. */
1394 uint8_t scsi_cdb[MAX_CMDSZ]; /* SCSI command words. */
1395 uint32_t byte_count; /* Total byte count. */
1396 uint32_t dseg_0_address; /* Data segment 0 address. */
1397 uint32_t dseg_0_length; /* Data segment 0 length. */
1398 uint32_t dseg_1_address; /* Data segment 1 address. */
1399 uint32_t dseg_1_length; /* Data segment 1 length. */
1400 uint32_t dseg_2_address; /* Data segment 2 address. */
1401 uint32_t dseg_2_length; /* Data segment 2 length. */
1402 } cmd_entry_t;
1403
1404 /*
1405 * ISP queue - 64-Bit addressing, command entry structure definition.
1406 */
1407 #define COMMAND_A64_TYPE 0x19 /* Command A64 entry */
1408 typedef struct {
1409 uint8_t entry_type; /* Entry type. */
1410 uint8_t entry_count; /* Entry count. */
1411 uint8_t sys_define; /* System defined. */
1412 uint8_t entry_status; /* Entry Status. */
1413 uint32_t handle; /* System handle. */
1414 target_id_t target; /* SCSI ID */
1415 uint16_t lun; /* SCSI LUN */
1416 uint16_t control_flags; /* Control flags. */
1417 uint16_t reserved_1;
1418 uint16_t timeout; /* Command timeout. */
1419 uint16_t dseg_count; /* Data segment count. */
1420 uint8_t scsi_cdb[MAX_CMDSZ]; /* SCSI command words. */
1421 uint32_t byte_count; /* Total byte count. */
1422 uint32_t dseg_0_address[2]; /* Data segment 0 address. */
1423 uint32_t dseg_0_length; /* Data segment 0 length. */
1424 uint32_t dseg_1_address[2]; /* Data segment 1 address. */
1425 uint32_t dseg_1_length; /* Data segment 1 length. */
1426 } cmd_a64_entry_t, request_t;
1427
1428 /*
1429 * ISP queue - continuation entry structure definition.
1430 */
1431 #define CONTINUE_TYPE 0x02 /* Continuation entry. */
1432 typedef struct {
1433 uint8_t entry_type; /* Entry type. */
1434 uint8_t entry_count; /* Entry count. */
1435 uint8_t sys_define; /* System defined. */
1436 uint8_t entry_status; /* Entry Status. */
1437 uint32_t reserved;
1438 uint32_t dseg_0_address; /* Data segment 0 address. */
1439 uint32_t dseg_0_length; /* Data segment 0 length. */
1440 uint32_t dseg_1_address; /* Data segment 1 address. */
1441 uint32_t dseg_1_length; /* Data segment 1 length. */
1442 uint32_t dseg_2_address; /* Data segment 2 address. */
1443 uint32_t dseg_2_length; /* Data segment 2 length. */
1444 uint32_t dseg_3_address; /* Data segment 3 address. */
1445 uint32_t dseg_3_length; /* Data segment 3 length. */
1446 uint32_t dseg_4_address; /* Data segment 4 address. */
1447 uint32_t dseg_4_length; /* Data segment 4 length. */
1448 uint32_t dseg_5_address; /* Data segment 5 address. */
1449 uint32_t dseg_5_length; /* Data segment 5 length. */
1450 uint32_t dseg_6_address; /* Data segment 6 address. */
1451 uint32_t dseg_6_length; /* Data segment 6 length. */
1452 } cont_entry_t;
1453
1454 /*
1455 * ISP queue - 64-Bit addressing, continuation entry structure definition.
1456 */
1457 #define CONTINUE_A64_TYPE 0x0A /* Continuation A64 entry. */
1458 typedef struct {
1459 uint8_t entry_type; /* Entry type. */
1460 uint8_t entry_count; /* Entry count. */
1461 uint8_t sys_define; /* System defined. */
1462 uint8_t entry_status; /* Entry Status. */
1463 uint32_t dseg_0_address[2]; /* Data segment 0 address. */
1464 uint32_t dseg_0_length; /* Data segment 0 length. */
1465 uint32_t dseg_1_address[2]; /* Data segment 1 address. */
1466 uint32_t dseg_1_length; /* Data segment 1 length. */
1467 uint32_t dseg_2_address [2]; /* Data segment 2 address. */
1468 uint32_t dseg_2_length; /* Data segment 2 length. */
1469 uint32_t dseg_3_address[2]; /* Data segment 3 address. */
1470 uint32_t dseg_3_length; /* Data segment 3 length. */
1471 uint32_t dseg_4_address[2]; /* Data segment 4 address. */
1472 uint32_t dseg_4_length; /* Data segment 4 length. */
1473 } cont_a64_entry_t;
1474
1475 #define PO_MODE_DIF_INSERT 0
1476 #define PO_MODE_DIF_REMOVE 1
1477 #define PO_MODE_DIF_PASS 2
1478 #define PO_MODE_DIF_REPLACE 3
1479 #define PO_MODE_DIF_TCP_CKSUM 6
1480 #define PO_ENABLE_DIF_BUNDLING BIT_8
1481 #define PO_ENABLE_INCR_GUARD_SEED BIT_3
1482 #define PO_DISABLE_INCR_REF_TAG BIT_5
1483 #define PO_DISABLE_GUARD_CHECK BIT_4
1484 /*
1485 * ISP queue - 64-Bit addressing, continuation crc entry structure definition.
1486 */
1487 struct crc_context {
1488 uint32_t handle; /* System handle. */
1489 uint32_t ref_tag;
1490 uint16_t app_tag;
1491 uint8_t ref_tag_mask[4]; /* Validation/Replacement Mask*/
1492 uint8_t app_tag_mask[2]; /* Validation/Replacement Mask*/
1493 uint16_t guard_seed; /* Initial Guard Seed */
1494 uint16_t prot_opts; /* Requested Data Protection Mode */
1495 uint16_t blk_size; /* Data size in bytes */
1496 uint16_t runt_blk_guard; /* Guard value for runt block (tape
1497 * only) */
1498 uint32_t byte_count; /* Total byte count/ total data
1499 * transfer count */
1500 union {
1501 struct {
1502 uint32_t reserved_1;
1503 uint16_t reserved_2;
1504 uint16_t reserved_3;
1505 uint32_t reserved_4;
1506 uint32_t data_address[2];
1507 uint32_t data_length;
1508 uint32_t reserved_5[2];
1509 uint32_t reserved_6;
1510 } nobundling;
1511 struct {
1512 uint32_t dif_byte_count; /* Total DIF byte
1513 * count */
1514 uint16_t reserved_1;
1515 uint16_t dseg_count; /* Data segment count */
1516 uint32_t reserved_2;
1517 uint32_t data_address[2];
1518 uint32_t data_length;
1519 uint32_t dif_address[2];
1520 uint32_t dif_length; /* Data segment 0
1521 * length */
1522 } bundling;
1523 } u;
1524
1525 struct fcp_cmnd fcp_cmnd;
1526 dma_addr_t crc_ctx_dma;
1527 /* List of DMA context transfers */
1528 struct list_head dsd_list;
1529
1530 /* This structure should not exceed 512 bytes */
1531 };
1532
1533 #define CRC_CONTEXT_LEN_FW (offsetof(struct crc_context, fcp_cmnd.lun))
1534 #define CRC_CONTEXT_FCPCMND_OFF (offsetof(struct crc_context, fcp_cmnd.lun))
1535
1536 /*
1537 * ISP queue - status entry structure definition.
1538 */
1539 #define STATUS_TYPE 0x03 /* Status entry. */
1540 typedef struct {
1541 uint8_t entry_type; /* Entry type. */
1542 uint8_t entry_count; /* Entry count. */
1543 uint8_t sys_define; /* System defined. */
1544 uint8_t entry_status; /* Entry Status. */
1545 uint32_t handle; /* System handle. */
1546 uint16_t scsi_status; /* SCSI status. */
1547 uint16_t comp_status; /* Completion status. */
1548 uint16_t state_flags; /* State flags. */
1549 uint16_t status_flags; /* Status flags. */
1550 uint16_t rsp_info_len; /* Response Info Length. */
1551 uint16_t req_sense_length; /* Request sense data length. */
1552 uint32_t residual_length; /* Residual transfer length. */
1553 uint8_t rsp_info[8]; /* FCP response information. */
1554 uint8_t req_sense_data[32]; /* Request sense data. */
1555 } sts_entry_t;
1556
1557 /*
1558 * Status entry entry status
1559 */
1560 #define RF_RQ_DMA_ERROR BIT_6 /* Request Queue DMA error. */
1561 #define RF_INV_E_ORDER BIT_5 /* Invalid entry order. */
1562 #define RF_INV_E_COUNT BIT_4 /* Invalid entry count. */
1563 #define RF_INV_E_PARAM BIT_3 /* Invalid entry parameter. */
1564 #define RF_INV_E_TYPE BIT_2 /* Invalid entry type. */
1565 #define RF_BUSY BIT_1 /* Busy */
1566 #define RF_MASK (RF_RQ_DMA_ERROR | RF_INV_E_ORDER | RF_INV_E_COUNT | \
1567 RF_INV_E_PARAM | RF_INV_E_TYPE | RF_BUSY)
1568 #define RF_MASK_24XX (RF_INV_E_ORDER | RF_INV_E_COUNT | RF_INV_E_PARAM | \
1569 RF_INV_E_TYPE)
1570
1571 /*
1572 * Status entry SCSI status bit definitions.
1573 */
1574 #define SS_MASK 0xfff /* Reserved bits BIT_12-BIT_15*/
1575 #define SS_RESIDUAL_UNDER BIT_11
1576 #define SS_RESIDUAL_OVER BIT_10
1577 #define SS_SENSE_LEN_VALID BIT_9
1578 #define SS_RESPONSE_INFO_LEN_VALID BIT_8
1579
1580 #define SS_RESERVE_CONFLICT (BIT_4 | BIT_3)
1581 #define SS_BUSY_CONDITION BIT_3
1582 #define SS_CONDITION_MET BIT_2
1583 #define SS_CHECK_CONDITION BIT_1
1584
1585 /*
1586 * Status entry completion status
1587 */
1588 #define CS_COMPLETE 0x0 /* No errors */
1589 #define CS_INCOMPLETE 0x1 /* Incomplete transfer of cmd. */
1590 #define CS_DMA 0x2 /* A DMA direction error. */
1591 #define CS_TRANSPORT 0x3 /* Transport error. */
1592 #define CS_RESET 0x4 /* SCSI bus reset occurred */
1593 #define CS_ABORTED 0x5 /* System aborted command. */
1594 #define CS_TIMEOUT 0x6 /* Timeout error. */
1595 #define CS_DATA_OVERRUN 0x7 /* Data overrun. */
1596 #define CS_DIF_ERROR 0xC /* DIF error detected */
1597
1598 #define CS_DATA_UNDERRUN 0x15 /* Data Underrun. */
1599 #define CS_QUEUE_FULL 0x1C /* Queue Full. */
1600 #define CS_PORT_UNAVAILABLE 0x28 /* Port unavailable */
1601 /* (selection timeout) */
1602 #define CS_PORT_LOGGED_OUT 0x29 /* Port Logged Out */
1603 #define CS_PORT_CONFIG_CHG 0x2A /* Port Configuration Changed */
1604 #define CS_PORT_BUSY 0x2B /* Port Busy */
1605 #define CS_COMPLETE_CHKCOND 0x30 /* Error? */
1606 #define CS_BAD_PAYLOAD 0x80 /* Driver defined */
1607 #define CS_UNKNOWN 0x81 /* Driver defined */
1608 #define CS_RETRY 0x82 /* Driver defined */
1609 #define CS_LOOP_DOWN_ABORT 0x83 /* Driver defined */
1610
1611 #define CS_BIDIR_RD_OVERRUN 0x700
1612 #define CS_BIDIR_RD_WR_OVERRUN 0x707
1613 #define CS_BIDIR_RD_OVERRUN_WR_UNDERRUN 0x715
1614 #define CS_BIDIR_RD_UNDERRUN 0x1500
1615 #define CS_BIDIR_RD_UNDERRUN_WR_OVERRUN 0x1507
1616 #define CS_BIDIR_RD_WR_UNDERRUN 0x1515
1617 #define CS_BIDIR_DMA 0x200
1618 /*
1619 * Status entry status flags
1620 */
1621 #define SF_ABTS_TERMINATED BIT_10
1622 #define SF_LOGOUT_SENT BIT_13
1623
1624 /*
1625 * ISP queue - status continuation entry structure definition.
1626 */
1627 #define STATUS_CONT_TYPE 0x10 /* Status continuation entry. */
1628 typedef struct {
1629 uint8_t entry_type; /* Entry type. */
1630 uint8_t entry_count; /* Entry count. */
1631 uint8_t sys_define; /* System defined. */
1632 uint8_t entry_status; /* Entry Status. */
1633 uint8_t data[60]; /* data */
1634 } sts_cont_entry_t;
1635
1636 /*
1637 * ISP queue - RIO Type 1 status entry (32 bit I/O entry handles)
1638 * structure definition.
1639 */
1640 #define STATUS_TYPE_21 0x21 /* Status entry. */
1641 typedef struct {
1642 uint8_t entry_type; /* Entry type. */
1643 uint8_t entry_count; /* Entry count. */
1644 uint8_t handle_count; /* Handle count. */
1645 uint8_t entry_status; /* Entry Status. */
1646 uint32_t handle[15]; /* System handles. */
1647 } sts21_entry_t;
1648
1649 /*
1650 * ISP queue - RIO Type 2 status entry (16 bit I/O entry handles)
1651 * structure definition.
1652 */
1653 #define STATUS_TYPE_22 0x22 /* Status entry. */
1654 typedef struct {
1655 uint8_t entry_type; /* Entry type. */
1656 uint8_t entry_count; /* Entry count. */
1657 uint8_t handle_count; /* Handle count. */
1658 uint8_t entry_status; /* Entry Status. */
1659 uint16_t handle[30]; /* System handles. */
1660 } sts22_entry_t;
1661
1662 /*
1663 * ISP queue - marker entry structure definition.
1664 */
1665 #define MARKER_TYPE 0x04 /* Marker entry. */
1666 typedef struct {
1667 uint8_t entry_type; /* Entry type. */
1668 uint8_t entry_count; /* Entry count. */
1669 uint8_t handle_count; /* Handle count. */
1670 uint8_t entry_status; /* Entry Status. */
1671 uint32_t sys_define_2; /* System defined. */
1672 target_id_t target; /* SCSI ID */
1673 uint8_t modifier; /* Modifier (7-0). */
1674 #define MK_SYNC_ID_LUN 0 /* Synchronize ID/LUN */
1675 #define MK_SYNC_ID 1 /* Synchronize ID */
1676 #define MK_SYNC_ALL 2 /* Synchronize all ID/LUN */
1677 #define MK_SYNC_LIP 3 /* Synchronize all ID/LUN, */
1678 /* clear port changed, */
1679 /* use sequence number. */
1680 uint8_t reserved_1;
1681 uint16_t sequence_number; /* Sequence number of event */
1682 uint16_t lun; /* SCSI LUN */
1683 uint8_t reserved_2[48];
1684 } mrk_entry_t;
1685
1686 /*
1687 * ISP queue - Management Server entry structure definition.
1688 */
1689 #define MS_IOCB_TYPE 0x29 /* Management Server IOCB entry */
1690 typedef struct {
1691 uint8_t entry_type; /* Entry type. */
1692 uint8_t entry_count; /* Entry count. */
1693 uint8_t handle_count; /* Handle count. */
1694 uint8_t entry_status; /* Entry Status. */
1695 uint32_t handle1; /* System handle. */
1696 target_id_t loop_id;
1697 uint16_t status;
1698 uint16_t control_flags; /* Control flags. */
1699 uint16_t reserved2;
1700 uint16_t timeout;
1701 uint16_t cmd_dsd_count;
1702 uint16_t total_dsd_count;
1703 uint8_t type;
1704 uint8_t r_ctl;
1705 uint16_t rx_id;
1706 uint16_t reserved3;
1707 uint32_t handle2;
1708 uint32_t rsp_bytecount;
1709 uint32_t req_bytecount;
1710 uint32_t dseg_req_address[2]; /* Data segment 0 address. */
1711 uint32_t dseg_req_length; /* Data segment 0 length. */
1712 uint32_t dseg_rsp_address[2]; /* Data segment 1 address. */
1713 uint32_t dseg_rsp_length; /* Data segment 1 length. */
1714 } ms_iocb_entry_t;
1715
1716
1717 /*
1718 * ISP queue - Mailbox Command entry structure definition.
1719 */
1720 #define MBX_IOCB_TYPE 0x39
1721 struct mbx_entry {
1722 uint8_t entry_type;
1723 uint8_t entry_count;
1724 uint8_t sys_define1;
1725 /* Use sys_define1 for source type */
1726 #define SOURCE_SCSI 0x00
1727 #define SOURCE_IP 0x01
1728 #define SOURCE_VI 0x02
1729 #define SOURCE_SCTP 0x03
1730 #define SOURCE_MP 0x04
1731 #define SOURCE_MPIOCTL 0x05
1732 #define SOURCE_ASYNC_IOCB 0x07
1733
1734 uint8_t entry_status;
1735
1736 uint32_t handle;
1737 target_id_t loop_id;
1738
1739 uint16_t status;
1740 uint16_t state_flags;
1741 uint16_t status_flags;
1742
1743 uint32_t sys_define2[2];
1744
1745 uint16_t mb0;
1746 uint16_t mb1;
1747 uint16_t mb2;
1748 uint16_t mb3;
1749 uint16_t mb6;
1750 uint16_t mb7;
1751 uint16_t mb9;
1752 uint16_t mb10;
1753 uint32_t reserved_2[2];
1754 uint8_t node_name[WWN_SIZE];
1755 uint8_t port_name[WWN_SIZE];
1756 };
1757
1758 /*
1759 * ISP request and response queue entry sizes
1760 */
1761 #define RESPONSE_ENTRY_SIZE (sizeof(response_t))
1762 #define REQUEST_ENTRY_SIZE (sizeof(request_t))
1763
1764
1765 /*
1766 * 24 bit port ID type definition.
1767 */
1768 typedef union {
1769 uint32_t b24 : 24;
1770
1771 struct {
1772 #ifdef __BIG_ENDIAN
1773 uint8_t domain;
1774 uint8_t area;
1775 uint8_t al_pa;
1776 #elif defined(__LITTLE_ENDIAN)
1777 uint8_t al_pa;
1778 uint8_t area;
1779 uint8_t domain;
1780 #else
1781 #error "__BIG_ENDIAN or __LITTLE_ENDIAN must be defined!"
1782 #endif
1783 uint8_t rsvd_1;
1784 } b;
1785 } port_id_t;
1786 #define INVALID_PORT_ID 0xFFFFFF
1787
1788 /*
1789 * Switch info gathering structure.
1790 */
1791 typedef struct {
1792 port_id_t d_id;
1793 uint8_t node_name[WWN_SIZE];
1794 uint8_t port_name[WWN_SIZE];
1795 uint8_t fabric_port_name[WWN_SIZE];
1796 uint16_t fp_speed;
1797 uint8_t fc4_type;
1798 } sw_info_t;
1799
1800 /* FCP-4 types */
1801 #define FC4_TYPE_FCP_SCSI 0x08
1802 #define FC4_TYPE_OTHER 0x0
1803 #define FC4_TYPE_UNKNOWN 0xff
1804
1805 /*
1806 * Fibre channel port type.
1807 */
1808 typedef enum {
1809 FCT_UNKNOWN,
1810 FCT_RSCN,
1811 FCT_SWITCH,
1812 FCT_BROADCAST,
1813 FCT_INITIATOR,
1814 FCT_TARGET
1815 } fc_port_type_t;
1816
1817 /*
1818 * Fibre channel port structure.
1819 */
1820 typedef struct fc_port {
1821 struct list_head list;
1822 struct scsi_qla_host *vha;
1823
1824 uint8_t node_name[WWN_SIZE];
1825 uint8_t port_name[WWN_SIZE];
1826 port_id_t d_id;
1827 uint16_t loop_id;
1828 uint16_t old_loop_id;
1829
1830 uint8_t fcp_prio;
1831
1832 uint8_t fabric_port_name[WWN_SIZE];
1833 uint16_t fp_speed;
1834
1835 fc_port_type_t port_type;
1836
1837 atomic_t state;
1838 uint32_t flags;
1839
1840 int login_retry;
1841
1842 struct fc_rport *rport, *drport;
1843 u32 supported_classes;
1844
1845 uint8_t fc4_type;
1846 uint8_t scan_state;
1847 } fc_port_t;
1848
1849 #define QLA_FCPORT_SCAN_NONE 0
1850 #define QLA_FCPORT_SCAN_FOUND 1
1851
1852 /*
1853 * Fibre channel port/lun states.
1854 */
1855 #define FCS_UNCONFIGURED 1
1856 #define FCS_DEVICE_DEAD 2
1857 #define FCS_DEVICE_LOST 3
1858 #define FCS_ONLINE 4
1859
1860 static const char * const port_state_str[] = {
1861 "Unknown",
1862 "UNCONFIGURED",
1863 "DEAD",
1864 "LOST",
1865 "ONLINE"
1866 };
1867
1868 /*
1869 * FC port flags.
1870 */
1871 #define FCF_FABRIC_DEVICE BIT_0
1872 #define FCF_LOGIN_NEEDED BIT_1
1873 #define FCF_FCP2_DEVICE BIT_2
1874 #define FCF_ASYNC_SENT BIT_3
1875 #define FCF_CONF_COMP_SUPPORTED BIT_4
1876
1877 /* No loop ID flag. */
1878 #define FC_NO_LOOP_ID 0x1000
1879
1880 /*
1881 * FC-CT interface
1882 *
1883 * NOTE: All structures are big-endian in form.
1884 */
1885
1886 #define CT_REJECT_RESPONSE 0x8001
1887 #define CT_ACCEPT_RESPONSE 0x8002
1888 #define CT_REASON_INVALID_COMMAND_CODE 0x01
1889 #define CT_REASON_CANNOT_PERFORM 0x09
1890 #define CT_REASON_COMMAND_UNSUPPORTED 0x0b
1891 #define CT_EXPL_ALREADY_REGISTERED 0x10
1892
1893 #define NS_N_PORT_TYPE 0x01
1894 #define NS_NL_PORT_TYPE 0x02
1895 #define NS_NX_PORT_TYPE 0x7F
1896
1897 #define GA_NXT_CMD 0x100
1898 #define GA_NXT_REQ_SIZE (16 + 4)
1899 #define GA_NXT_RSP_SIZE (16 + 620)
1900
1901 #define GID_PT_CMD 0x1A1
1902 #define GID_PT_REQ_SIZE (16 + 4)
1903
1904 #define GPN_ID_CMD 0x112
1905 #define GPN_ID_REQ_SIZE (16 + 4)
1906 #define GPN_ID_RSP_SIZE (16 + 8)
1907
1908 #define GNN_ID_CMD 0x113
1909 #define GNN_ID_REQ_SIZE (16 + 4)
1910 #define GNN_ID_RSP_SIZE (16 + 8)
1911
1912 #define GFT_ID_CMD 0x117
1913 #define GFT_ID_REQ_SIZE (16 + 4)
1914 #define GFT_ID_RSP_SIZE (16 + 32)
1915
1916 #define RFT_ID_CMD 0x217
1917 #define RFT_ID_REQ_SIZE (16 + 4 + 32)
1918 #define RFT_ID_RSP_SIZE 16
1919
1920 #define RFF_ID_CMD 0x21F
1921 #define RFF_ID_REQ_SIZE (16 + 4 + 2 + 1 + 1)
1922 #define RFF_ID_RSP_SIZE 16
1923
1924 #define RNN_ID_CMD 0x213
1925 #define RNN_ID_REQ_SIZE (16 + 4 + 8)
1926 #define RNN_ID_RSP_SIZE 16
1927
1928 #define RSNN_NN_CMD 0x239
1929 #define RSNN_NN_REQ_SIZE (16 + 8 + 1 + 255)
1930 #define RSNN_NN_RSP_SIZE 16
1931
1932 #define GFPN_ID_CMD 0x11C
1933 #define GFPN_ID_REQ_SIZE (16 + 4)
1934 #define GFPN_ID_RSP_SIZE (16 + 8)
1935
1936 #define GPSC_CMD 0x127
1937 #define GPSC_REQ_SIZE (16 + 8)
1938 #define GPSC_RSP_SIZE (16 + 2 + 2)
1939
1940 #define GFF_ID_CMD 0x011F
1941 #define GFF_ID_REQ_SIZE (16 + 4)
1942 #define GFF_ID_RSP_SIZE (16 + 128)
1943
1944 /*
1945 * HBA attribute types.
1946 */
1947 #define FDMI_HBA_ATTR_COUNT 9
1948 #define FDMI_HBA_NODE_NAME 1
1949 #define FDMI_HBA_MANUFACTURER 2
1950 #define FDMI_HBA_SERIAL_NUMBER 3
1951 #define FDMI_HBA_MODEL 4
1952 #define FDMI_HBA_MODEL_DESCRIPTION 5
1953 #define FDMI_HBA_HARDWARE_VERSION 6
1954 #define FDMI_HBA_DRIVER_VERSION 7
1955 #define FDMI_HBA_OPTION_ROM_VERSION 8
1956 #define FDMI_HBA_FIRMWARE_VERSION 9
1957 #define FDMI_HBA_OS_NAME_AND_VERSION 0xa
1958 #define FDMI_HBA_MAXIMUM_CT_PAYLOAD_LENGTH 0xb
1959
1960 struct ct_fdmi_hba_attr {
1961 uint16_t type;
1962 uint16_t len;
1963 union {
1964 uint8_t node_name[WWN_SIZE];
1965 uint8_t manufacturer[32];
1966 uint8_t serial_num[8];
1967 uint8_t model[16];
1968 uint8_t model_desc[80];
1969 uint8_t hw_version[16];
1970 uint8_t driver_version[32];
1971 uint8_t orom_version[16];
1972 uint8_t fw_version[16];
1973 uint8_t os_version[128];
1974 uint8_t max_ct_len[4];
1975 } a;
1976 };
1977
1978 struct ct_fdmi_hba_attributes {
1979 uint32_t count;
1980 struct ct_fdmi_hba_attr entry[FDMI_HBA_ATTR_COUNT];
1981 };
1982
1983 /*
1984 * Port attribute types.
1985 */
1986 #define FDMI_PORT_ATTR_COUNT 6
1987 #define FDMI_PORT_FC4_TYPES 1
1988 #define FDMI_PORT_SUPPORT_SPEED 2
1989 #define FDMI_PORT_CURRENT_SPEED 3
1990 #define FDMI_PORT_MAX_FRAME_SIZE 4
1991 #define FDMI_PORT_OS_DEVICE_NAME 5
1992 #define FDMI_PORT_HOST_NAME 6
1993
1994 #define FDMI_PORT_SPEED_1GB 0x1
1995 #define FDMI_PORT_SPEED_2GB 0x2
1996 #define FDMI_PORT_SPEED_10GB 0x4
1997 #define FDMI_PORT_SPEED_4GB 0x8
1998 #define FDMI_PORT_SPEED_8GB 0x10
1999 #define FDMI_PORT_SPEED_16GB 0x20
2000 #define FDMI_PORT_SPEED_UNKNOWN 0x8000
2001
2002 struct ct_fdmi_port_attr {
2003 uint16_t type;
2004 uint16_t len;
2005 union {
2006 uint8_t fc4_types[32];
2007 uint32_t sup_speed;
2008 uint32_t cur_speed;
2009 uint32_t max_frame_size;
2010 uint8_t os_dev_name[32];
2011 uint8_t host_name[32];
2012 } a;
2013 };
2014
2015 /*
2016 * Port Attribute Block.
2017 */
2018 struct ct_fdmi_port_attributes {
2019 uint32_t count;
2020 struct ct_fdmi_port_attr entry[FDMI_PORT_ATTR_COUNT];
2021 };
2022
2023 /* FDMI definitions. */
2024 #define GRHL_CMD 0x100
2025 #define GHAT_CMD 0x101
2026 #define GRPL_CMD 0x102
2027 #define GPAT_CMD 0x110
2028
2029 #define RHBA_CMD 0x200
2030 #define RHBA_RSP_SIZE 16
2031
2032 #define RHAT_CMD 0x201
2033 #define RPRT_CMD 0x210
2034
2035 #define RPA_CMD 0x211
2036 #define RPA_RSP_SIZE 16
2037
2038 #define DHBA_CMD 0x300
2039 #define DHBA_REQ_SIZE (16 + 8)
2040 #define DHBA_RSP_SIZE 16
2041
2042 #define DHAT_CMD 0x301
2043 #define DPRT_CMD 0x310
2044 #define DPA_CMD 0x311
2045
2046 /* CT command header -- request/response common fields */
2047 struct ct_cmd_hdr {
2048 uint8_t revision;
2049 uint8_t in_id[3];
2050 uint8_t gs_type;
2051 uint8_t gs_subtype;
2052 uint8_t options;
2053 uint8_t reserved;
2054 };
2055
2056 /* CT command request */
2057 struct ct_sns_req {
2058 struct ct_cmd_hdr header;
2059 uint16_t command;
2060 uint16_t max_rsp_size;
2061 uint8_t fragment_id;
2062 uint8_t reserved[3];
2063
2064 union {
2065 /* GA_NXT, GPN_ID, GNN_ID, GFT_ID, GFPN_ID */
2066 struct {
2067 uint8_t reserved;
2068 uint8_t port_id[3];
2069 } port_id;
2070
2071 struct {
2072 uint8_t port_type;
2073 uint8_t domain;
2074 uint8_t area;
2075 uint8_t reserved;
2076 } gid_pt;
2077
2078 struct {
2079 uint8_t reserved;
2080 uint8_t port_id[3];
2081 uint8_t fc4_types[32];
2082 } rft_id;
2083
2084 struct {
2085 uint8_t reserved;
2086 uint8_t port_id[3];
2087 uint16_t reserved2;
2088 uint8_t fc4_feature;
2089 uint8_t fc4_type;
2090 } rff_id;
2091
2092 struct {
2093 uint8_t reserved;
2094 uint8_t port_id[3];
2095 uint8_t node_name[8];
2096 } rnn_id;
2097
2098 struct {
2099 uint8_t node_name[8];
2100 uint8_t name_len;
2101 uint8_t sym_node_name[255];
2102 } rsnn_nn;
2103
2104 struct {
2105 uint8_t hba_indentifier[8];
2106 } ghat;
2107
2108 struct {
2109 uint8_t hba_identifier[8];
2110 uint32_t entry_count;
2111 uint8_t port_name[8];
2112 struct ct_fdmi_hba_attributes attrs;
2113 } rhba;
2114
2115 struct {
2116 uint8_t hba_identifier[8];
2117 struct ct_fdmi_hba_attributes attrs;
2118 } rhat;
2119
2120 struct {
2121 uint8_t port_name[8];
2122 struct ct_fdmi_port_attributes attrs;
2123 } rpa;
2124
2125 struct {
2126 uint8_t port_name[8];
2127 } dhba;
2128
2129 struct {
2130 uint8_t port_name[8];
2131 } dhat;
2132
2133 struct {
2134 uint8_t port_name[8];
2135 } dprt;
2136
2137 struct {
2138 uint8_t port_name[8];
2139 } dpa;
2140
2141 struct {
2142 uint8_t port_name[8];
2143 } gpsc;
2144
2145 struct {
2146 uint8_t reserved;
2147 uint8_t port_name[3];
2148 } gff_id;
2149 } req;
2150 };
2151
2152 /* CT command response header */
2153 struct ct_rsp_hdr {
2154 struct ct_cmd_hdr header;
2155 uint16_t response;
2156 uint16_t residual;
2157 uint8_t fragment_id;
2158 uint8_t reason_code;
2159 uint8_t explanation_code;
2160 uint8_t vendor_unique;
2161 };
2162
2163 struct ct_sns_gid_pt_data {
2164 uint8_t control_byte;
2165 uint8_t port_id[3];
2166 };
2167
2168 struct ct_sns_rsp {
2169 struct ct_rsp_hdr header;
2170
2171 union {
2172 struct {
2173 uint8_t port_type;
2174 uint8_t port_id[3];
2175 uint8_t port_name[8];
2176 uint8_t sym_port_name_len;
2177 uint8_t sym_port_name[255];
2178 uint8_t node_name[8];
2179 uint8_t sym_node_name_len;
2180 uint8_t sym_node_name[255];
2181 uint8_t init_proc_assoc[8];
2182 uint8_t node_ip_addr[16];
2183 uint8_t class_of_service[4];
2184 uint8_t fc4_types[32];
2185 uint8_t ip_address[16];
2186 uint8_t fabric_port_name[8];
2187 uint8_t reserved;
2188 uint8_t hard_address[3];
2189 } ga_nxt;
2190
2191 struct {
2192 /* Assume the largest number of targets for the union */
2193 struct ct_sns_gid_pt_data
2194 entries[MAX_FIBRE_DEVICES_MAX];
2195 } gid_pt;
2196
2197 struct {
2198 uint8_t port_name[8];
2199 } gpn_id;
2200
2201 struct {
2202 uint8_t node_name[8];
2203 } gnn_id;
2204
2205 struct {
2206 uint8_t fc4_types[32];
2207 } gft_id;
2208
2209 struct {
2210 uint32_t entry_count;
2211 uint8_t port_name[8];
2212 struct ct_fdmi_hba_attributes attrs;
2213 } ghat;
2214
2215 struct {
2216 uint8_t port_name[8];
2217 } gfpn_id;
2218
2219 struct {
2220 uint16_t speeds;
2221 uint16_t speed;
2222 } gpsc;
2223
2224 #define GFF_FCP_SCSI_OFFSET 7
2225 struct {
2226 uint8_t fc4_features[128];
2227 } gff_id;
2228 } rsp;
2229 };
2230
2231 struct ct_sns_pkt {
2232 union {
2233 struct ct_sns_req req;
2234 struct ct_sns_rsp rsp;
2235 } p;
2236 };
2237
2238 /*
2239 * SNS command structures -- for 2200 compatibility.
2240 */
2241 #define RFT_ID_SNS_SCMD_LEN 22
2242 #define RFT_ID_SNS_CMD_SIZE 60
2243 #define RFT_ID_SNS_DATA_SIZE 16
2244
2245 #define RNN_ID_SNS_SCMD_LEN 10
2246 #define RNN_ID_SNS_CMD_SIZE 36
2247 #define RNN_ID_SNS_DATA_SIZE 16
2248
2249 #define GA_NXT_SNS_SCMD_LEN 6
2250 #define GA_NXT_SNS_CMD_SIZE 28
2251 #define GA_NXT_SNS_DATA_SIZE (620 + 16)
2252
2253 #define GID_PT_SNS_SCMD_LEN 6
2254 #define GID_PT_SNS_CMD_SIZE 28
2255 /*
2256 * Assume MAX_FIBRE_DEVICES_2100 as these defines are only used with older
2257 * adapters.
2258 */
2259 #define GID_PT_SNS_DATA_SIZE (MAX_FIBRE_DEVICES_2100 * 4 + 16)
2260
2261 #define GPN_ID_SNS_SCMD_LEN 6
2262 #define GPN_ID_SNS_CMD_SIZE 28
2263 #define GPN_ID_SNS_DATA_SIZE (8 + 16)
2264
2265 #define GNN_ID_SNS_SCMD_LEN 6
2266 #define GNN_ID_SNS_CMD_SIZE 28
2267 #define GNN_ID_SNS_DATA_SIZE (8 + 16)
2268
2269 struct sns_cmd_pkt {
2270 union {
2271 struct {
2272 uint16_t buffer_length;
2273 uint16_t reserved_1;
2274 uint32_t buffer_address[2];
2275 uint16_t subcommand_length;
2276 uint16_t reserved_2;
2277 uint16_t subcommand;
2278 uint16_t size;
2279 uint32_t reserved_3;
2280 uint8_t param[36];
2281 } cmd;
2282
2283 uint8_t rft_data[RFT_ID_SNS_DATA_SIZE];
2284 uint8_t rnn_data[RNN_ID_SNS_DATA_SIZE];
2285 uint8_t gan_data[GA_NXT_SNS_DATA_SIZE];
2286 uint8_t gid_data[GID_PT_SNS_DATA_SIZE];
2287 uint8_t gpn_data[GPN_ID_SNS_DATA_SIZE];
2288 uint8_t gnn_data[GNN_ID_SNS_DATA_SIZE];
2289 } p;
2290 };
2291
2292 struct fw_blob {
2293 char *name;
2294 uint32_t segs[4];
2295 const struct firmware *fw;
2296 };
2297
2298 /* Return data from MBC_GET_ID_LIST call. */
2299 struct gid_list_info {
2300 uint8_t al_pa;
2301 uint8_t area;
2302 uint8_t domain;
2303 uint8_t loop_id_2100; /* ISP2100/ISP2200 -- 4 bytes. */
2304 uint16_t loop_id; /* ISP23XX -- 6 bytes. */
2305 uint16_t reserved_1; /* ISP24XX -- 8 bytes. */
2306 };
2307
2308 /* NPIV */
2309 typedef struct vport_info {
2310 uint8_t port_name[WWN_SIZE];
2311 uint8_t node_name[WWN_SIZE];
2312 int vp_id;
2313 uint16_t loop_id;
2314 unsigned long host_no;
2315 uint8_t port_id[3];
2316 int loop_state;
2317 } vport_info_t;
2318
2319 typedef struct vport_params {
2320 uint8_t port_name[WWN_SIZE];
2321 uint8_t node_name[WWN_SIZE];
2322 uint32_t options;
2323 #define VP_OPTS_RETRY_ENABLE BIT_0
2324 #define VP_OPTS_VP_DISABLE BIT_1
2325 } vport_params_t;
2326
2327 /* NPIV - return codes of VP create and modify */
2328 #define VP_RET_CODE_OK 0
2329 #define VP_RET_CODE_FATAL 1
2330 #define VP_RET_CODE_WRONG_ID 2
2331 #define VP_RET_CODE_WWPN 3
2332 #define VP_RET_CODE_RESOURCES 4
2333 #define VP_RET_CODE_NO_MEM 5
2334 #define VP_RET_CODE_NOT_FOUND 6
2335
2336 struct qla_hw_data;
2337 struct rsp_que;
2338 /*
2339 * ISP operations
2340 */
2341 struct isp_operations {
2342
2343 int (*pci_config) (struct scsi_qla_host *);
2344 void (*reset_chip) (struct scsi_qla_host *);
2345 int (*chip_diag) (struct scsi_qla_host *);
2346 void (*config_rings) (struct scsi_qla_host *);
2347 void (*reset_adapter) (struct scsi_qla_host *);
2348 int (*nvram_config) (struct scsi_qla_host *);
2349 void (*update_fw_options) (struct scsi_qla_host *);
2350 int (*load_risc) (struct scsi_qla_host *, uint32_t *);
2351
2352 char * (*pci_info_str) (struct scsi_qla_host *, char *);
2353 char * (*fw_version_str) (struct scsi_qla_host *, char *);
2354
2355 irq_handler_t intr_handler;
2356 void (*enable_intrs) (struct qla_hw_data *);
2357 void (*disable_intrs) (struct qla_hw_data *);
2358
2359 int (*abort_command) (srb_t *);
2360 int (*target_reset) (struct fc_port *, unsigned int, int);
2361 int (*lun_reset) (struct fc_port *, unsigned int, int);
2362 int (*fabric_login) (struct scsi_qla_host *, uint16_t, uint8_t,
2363 uint8_t, uint8_t, uint16_t *, uint8_t);
2364 int (*fabric_logout) (struct scsi_qla_host *, uint16_t, uint8_t,
2365 uint8_t, uint8_t);
2366
2367 uint16_t (*calc_req_entries) (uint16_t);
2368 void (*build_iocbs) (srb_t *, cmd_entry_t *, uint16_t);
2369 void * (*prep_ms_iocb) (struct scsi_qla_host *, uint32_t, uint32_t);
2370 void * (*prep_ms_fdmi_iocb) (struct scsi_qla_host *, uint32_t,
2371 uint32_t);
2372
2373 uint8_t * (*read_nvram) (struct scsi_qla_host *, uint8_t *,
2374 uint32_t, uint32_t);
2375 int (*write_nvram) (struct scsi_qla_host *, uint8_t *, uint32_t,
2376 uint32_t);
2377
2378 void (*fw_dump) (struct scsi_qla_host *, int);
2379
2380 int (*beacon_on) (struct scsi_qla_host *);
2381 int (*beacon_off) (struct scsi_qla_host *);
2382 void (*beacon_blink) (struct scsi_qla_host *);
2383
2384 uint8_t * (*read_optrom) (struct scsi_qla_host *, uint8_t *,
2385 uint32_t, uint32_t);
2386 int (*write_optrom) (struct scsi_qla_host *, uint8_t *, uint32_t,
2387 uint32_t);
2388
2389 int (*get_flash_version) (struct scsi_qla_host *, void *);
2390 int (*start_scsi) (srb_t *);
2391 int (*abort_isp) (struct scsi_qla_host *);
2392 int (*iospace_config)(struct qla_hw_data*);
2393 };
2394
2395 /* MSI-X Support *************************************************************/
2396
2397 #define QLA_MSIX_CHIP_REV_24XX 3
2398 #define QLA_MSIX_FW_MODE(m) (((m) & (BIT_7|BIT_8|BIT_9)) >> 7)
2399 #define QLA_MSIX_FW_MODE_1(m) (QLA_MSIX_FW_MODE(m) == 1)
2400
2401 #define QLA_MSIX_DEFAULT 0x00
2402 #define QLA_MSIX_RSP_Q 0x01
2403
2404 #define QLA_MIDX_DEFAULT 0
2405 #define QLA_MIDX_RSP_Q 1
2406 #define QLA_PCI_MSIX_CONTROL 0xa2
2407 #define QLA_83XX_PCI_MSIX_CONTROL 0x92
2408
2409 struct scsi_qla_host;
2410
2411 struct qla_msix_entry {
2412 int have_irq;
2413 uint32_t vector;
2414 uint16_t entry;
2415 struct rsp_que *rsp;
2416 };
2417
2418 #define WATCH_INTERVAL 1 /* number of seconds */
2419
2420 /* Work events. */
2421 enum qla_work_type {
2422 QLA_EVT_AEN,
2423 QLA_EVT_IDC_ACK,
2424 QLA_EVT_ASYNC_LOGIN,
2425 QLA_EVT_ASYNC_LOGIN_DONE,
2426 QLA_EVT_ASYNC_LOGOUT,
2427 QLA_EVT_ASYNC_LOGOUT_DONE,
2428 QLA_EVT_ASYNC_ADISC,
2429 QLA_EVT_ASYNC_ADISC_DONE,
2430 QLA_EVT_UEVENT,
2431 };
2432
2433
2434 struct qla_work_evt {
2435 struct list_head list;
2436 enum qla_work_type type;
2437 u32 flags;
2438 #define QLA_EVT_FLAG_FREE 0x1
2439
2440 union {
2441 struct {
2442 enum fc_host_event_code code;
2443 u32 data;
2444 } aen;
2445 struct {
2446 #define QLA_IDC_ACK_REGS 7
2447 uint16_t mb[QLA_IDC_ACK_REGS];
2448 } idc_ack;
2449 struct {
2450 struct fc_port *fcport;
2451 #define QLA_LOGIO_LOGIN_RETRIED BIT_0
2452 u16 data[2];
2453 } logio;
2454 struct {
2455 u32 code;
2456 #define QLA_UEVENT_CODE_FW_DUMP 0
2457 } uevent;
2458 } u;
2459 };
2460
2461 struct qla_chip_state_84xx {
2462 struct list_head list;
2463 struct kref kref;
2464
2465 void *bus;
2466 spinlock_t access_lock;
2467 struct mutex fw_update_mutex;
2468 uint32_t fw_update;
2469 uint32_t op_fw_version;
2470 uint32_t op_fw_size;
2471 uint32_t op_fw_seq_size;
2472 uint32_t diag_fw_version;
2473 uint32_t gold_fw_version;
2474 };
2475
2476 struct qla_statistics {
2477 uint32_t total_isp_aborts;
2478 uint64_t input_bytes;
2479 uint64_t output_bytes;
2480 };
2481
2482 struct bidi_statistics {
2483 unsigned long long io_count;
2484 unsigned long long transfer_bytes;
2485 };
2486
2487 /* Multi queue support */
2488 #define MBC_INITIALIZE_MULTIQ 0x1f
2489 #define QLA_QUE_PAGE 0X1000
2490 #define QLA_MQ_SIZE 32
2491 #define QLA_MAX_QUEUES 256
2492 #define ISP_QUE_REG(ha, id) \
2493 ((ha->mqenable || IS_QLA83XX(ha)) ? \
2494 ((device_reg_t __iomem *)(ha->mqiobase) +\
2495 (QLA_QUE_PAGE * id)) :\
2496 ((device_reg_t __iomem *)(ha->iobase)))
2497 #define QLA_REQ_QUE_ID(tag) \
2498 ((tag < QLA_MAX_QUEUES && tag > 0) ? tag : 0)
2499 #define QLA_DEFAULT_QUE_QOS 5
2500 #define QLA_PRECONFIG_VPORTS 32
2501 #define QLA_MAX_VPORTS_QLA24XX 128
2502 #define QLA_MAX_VPORTS_QLA25XX 256
2503 /* Response queue data structure */
2504 struct rsp_que {
2505 dma_addr_t dma;
2506 response_t *ring;
2507 response_t *ring_ptr;
2508 uint32_t __iomem *rsp_q_in; /* FWI2-capable only. */
2509 uint32_t __iomem *rsp_q_out;
2510 uint16_t ring_index;
2511 uint16_t out_ptr;
2512 uint16_t length;
2513 uint16_t options;
2514 uint16_t rid;
2515 uint16_t id;
2516 uint16_t vp_idx;
2517 struct qla_hw_data *hw;
2518 struct qla_msix_entry *msix;
2519 struct req_que *req;
2520 srb_t *status_srb; /* status continuation entry */
2521 struct work_struct q_work;
2522 };
2523
2524 /* Request queue data structure */
2525 struct req_que {
2526 dma_addr_t dma;
2527 request_t *ring;
2528 request_t *ring_ptr;
2529 uint32_t __iomem *req_q_in; /* FWI2-capable only. */
2530 uint32_t __iomem *req_q_out;
2531 uint16_t ring_index;
2532 uint16_t in_ptr;
2533 uint16_t cnt;
2534 uint16_t length;
2535 uint16_t options;
2536 uint16_t rid;
2537 uint16_t id;
2538 uint16_t qos;
2539 uint16_t vp_idx;
2540 struct rsp_que *rsp;
2541 srb_t **outstanding_cmds;
2542 uint32_t current_outstanding_cmd;
2543 uint16_t num_outstanding_cmds;
2544 #define MAX_Q_DEPTH 32
2545 int max_q_depth;
2546 };
2547
2548 /* Place holder for FW buffer parameters */
2549 struct qlfc_fw {
2550 void *fw_buf;
2551 dma_addr_t fw_dma;
2552 uint32_t len;
2553 };
2554
2555 struct qlt_hw_data {
2556 /* Protected by hw lock */
2557 uint32_t enable_class_2:1;
2558 uint32_t enable_explicit_conf:1;
2559 uint32_t ini_mode_force_reverse:1;
2560 uint32_t node_name_set:1;
2561
2562 dma_addr_t atio_dma; /* Physical address. */
2563 struct atio *atio_ring; /* Base virtual address */
2564 struct atio *atio_ring_ptr; /* Current address. */
2565 uint16_t atio_ring_index; /* Current index. */
2566 uint16_t atio_q_length;
2567 uint32_t __iomem *atio_q_in;
2568 uint32_t __iomem *atio_q_out;
2569
2570 void *target_lport_ptr;
2571 struct qla_tgt_func_tmpl *tgt_ops;
2572 struct qla_tgt *qla_tgt;
2573 struct qla_tgt_cmd *cmds[DEFAULT_OUTSTANDING_COMMANDS];
2574 uint16_t current_handle;
2575
2576 struct qla_tgt_vp_map *tgt_vp_map;
2577 struct mutex tgt_mutex;
2578 struct mutex tgt_host_action_mutex;
2579
2580 int saved_set;
2581 uint16_t saved_exchange_count;
2582 uint32_t saved_firmware_options_1;
2583 uint32_t saved_firmware_options_2;
2584 uint32_t saved_firmware_options_3;
2585 uint8_t saved_firmware_options[2];
2586 uint8_t saved_add_firmware_options[2];
2587
2588 uint8_t tgt_node_name[WWN_SIZE];
2589 };
2590
2591 /*
2592 * Qlogic host adapter specific data structure.
2593 */
2594 struct qla_hw_data {
2595 struct pci_dev *pdev;
2596 /* SRB cache. */
2597 #define SRB_MIN_REQ 128
2598 mempool_t *srb_mempool;
2599
2600 volatile struct {
2601 uint32_t mbox_int :1;
2602 uint32_t mbox_busy :1;
2603 uint32_t disable_risc_code_load :1;
2604 uint32_t enable_64bit_addressing :1;
2605 uint32_t enable_lip_reset :1;
2606 uint32_t enable_target_reset :1;
2607 uint32_t enable_lip_full_login :1;
2608 uint32_t enable_led_scheme :1;
2609
2610 uint32_t msi_enabled :1;
2611 uint32_t msix_enabled :1;
2612 uint32_t disable_serdes :1;
2613 uint32_t gpsc_supported :1;
2614 uint32_t npiv_supported :1;
2615 uint32_t pci_channel_io_perm_failure :1;
2616 uint32_t fce_enabled :1;
2617 uint32_t fac_supported :1;
2618
2619 uint32_t chip_reset_done :1;
2620 uint32_t port0 :1;
2621 uint32_t running_gold_fw :1;
2622 uint32_t eeh_busy :1;
2623 uint32_t cpu_affinity_enabled :1;
2624 uint32_t disable_msix_handshake :1;
2625 uint32_t fcp_prio_enabled :1;
2626 uint32_t isp82xx_fw_hung:1;
2627 uint32_t nic_core_hung:1;
2628
2629 uint32_t quiesce_owner:1;
2630 uint32_t thermal_supported:1;
2631 uint32_t nic_core_reset_hdlr_active:1;
2632 uint32_t nic_core_reset_owner:1;
2633 uint32_t isp82xx_no_md_cap:1;
2634 uint32_t host_shutting_down:1;
2635 uint32_t idc_compl_status:1;
2636 /* 32 bits */
2637 } flags;
2638
2639 /* This spinlock is used to protect "io transactions", you must
2640 * acquire it before doing any IO to the card, eg with RD_REG*() and
2641 * WRT_REG*() for the duration of your entire commandtransaction.
2642 *
2643 * This spinlock is of lower priority than the io request lock.
2644 */
2645
2646 spinlock_t hardware_lock ____cacheline_aligned;
2647 int bars;
2648 int mem_only;
2649 device_reg_t __iomem *iobase; /* Base I/O address */
2650 resource_size_t pio_address;
2651
2652 #define MIN_IOBASE_LEN 0x100
2653 /* Multi queue data structs */
2654 device_reg_t __iomem *mqiobase;
2655 device_reg_t __iomem *msixbase;
2656 uint16_t msix_count;
2657 uint8_t mqenable;
2658 struct req_que **req_q_map;
2659 struct rsp_que **rsp_q_map;
2660 unsigned long req_qid_map[(QLA_MAX_QUEUES / 8) / sizeof(unsigned long)];
2661 unsigned long rsp_qid_map[(QLA_MAX_QUEUES / 8) / sizeof(unsigned long)];
2662 uint8_t max_req_queues;
2663 uint8_t max_rsp_queues;
2664 struct qla_npiv_entry *npiv_info;
2665 uint16_t nvram_npiv_size;
2666
2667 uint16_t switch_cap;
2668 #define FLOGI_SEQ_DEL BIT_8
2669 #define FLOGI_MID_SUPPORT BIT_10
2670 #define FLOGI_VSAN_SUPPORT BIT_12
2671 #define FLOGI_SP_SUPPORT BIT_13
2672
2673 uint8_t port_no; /* Physical port of adapter */
2674
2675 /* Timeout timers. */
2676 uint8_t loop_down_abort_time; /* port down timer */
2677 atomic_t loop_down_timer; /* loop down timer */
2678 uint8_t link_down_timeout; /* link down timeout */
2679 uint16_t max_loop_id;
2680 uint16_t max_fibre_devices; /* Maximum number of targets */
2681
2682 uint16_t fb_rev;
2683 uint16_t min_external_loopid; /* First external loop Id */
2684
2685 #define PORT_SPEED_UNKNOWN 0xFFFF
2686 #define PORT_SPEED_1GB 0x00
2687 #define PORT_SPEED_2GB 0x01
2688 #define PORT_SPEED_4GB 0x03
2689 #define PORT_SPEED_8GB 0x04
2690 #define PORT_SPEED_16GB 0x05
2691 #define PORT_SPEED_10GB 0x13
2692 uint16_t link_data_rate; /* F/W operating speed */
2693
2694 uint8_t current_topology;
2695 uint8_t prev_topology;
2696 #define ISP_CFG_NL 1
2697 #define ISP_CFG_N 2
2698 #define ISP_CFG_FL 4
2699 #define ISP_CFG_F 8
2700
2701 uint8_t operating_mode; /* F/W operating mode */
2702 #define LOOP 0
2703 #define P2P 1
2704 #define LOOP_P2P 2
2705 #define P2P_LOOP 3
2706 uint8_t interrupts_on;
2707 uint32_t isp_abort_cnt;
2708
2709 #define PCI_DEVICE_ID_QLOGIC_ISP2532 0x2532
2710 #define PCI_DEVICE_ID_QLOGIC_ISP8432 0x8432
2711 #define PCI_DEVICE_ID_QLOGIC_ISP8001 0x8001
2712 #define PCI_DEVICE_ID_QLOGIC_ISP8031 0x8031
2713 #define PCI_DEVICE_ID_QLOGIC_ISP2031 0x2031
2714 uint32_t device_type;
2715 #define DT_ISP2100 BIT_0
2716 #define DT_ISP2200 BIT_1
2717 #define DT_ISP2300 BIT_2
2718 #define DT_ISP2312 BIT_3
2719 #define DT_ISP2322 BIT_4
2720 #define DT_ISP6312 BIT_5
2721 #define DT_ISP6322 BIT_6
2722 #define DT_ISP2422 BIT_7
2723 #define DT_ISP2432 BIT_8
2724 #define DT_ISP5422 BIT_9
2725 #define DT_ISP5432 BIT_10
2726 #define DT_ISP2532 BIT_11
2727 #define DT_ISP8432 BIT_12
2728 #define DT_ISP8001 BIT_13
2729 #define DT_ISP8021 BIT_14
2730 #define DT_ISP2031 BIT_15
2731 #define DT_ISP8031 BIT_16
2732 #define DT_ISP_LAST (DT_ISP8031 << 1)
2733
2734 #define DT_T10_PI BIT_25
2735 #define DT_IIDMA BIT_26
2736 #define DT_FWI2 BIT_27
2737 #define DT_ZIO_SUPPORTED BIT_28
2738 #define DT_OEM_001 BIT_29
2739 #define DT_ISP2200A BIT_30
2740 #define DT_EXTENDED_IDS BIT_31
2741 #define DT_MASK(ha) ((ha)->device_type & (DT_ISP_LAST - 1))
2742 #define IS_QLA2100(ha) (DT_MASK(ha) & DT_ISP2100)
2743 #define IS_QLA2200(ha) (DT_MASK(ha) & DT_ISP2200)
2744 #define IS_QLA2300(ha) (DT_MASK(ha) & DT_ISP2300)
2745 #define IS_QLA2312(ha) (DT_MASK(ha) & DT_ISP2312)
2746 #define IS_QLA2322(ha) (DT_MASK(ha) & DT_ISP2322)
2747 #define IS_QLA6312(ha) (DT_MASK(ha) & DT_ISP6312)
2748 #define IS_QLA6322(ha) (DT_MASK(ha) & DT_ISP6322)
2749 #define IS_QLA2422(ha) (DT_MASK(ha) & DT_ISP2422)
2750 #define IS_QLA2432(ha) (DT_MASK(ha) & DT_ISP2432)
2751 #define IS_QLA5422(ha) (DT_MASK(ha) & DT_ISP5422)
2752 #define IS_QLA5432(ha) (DT_MASK(ha) & DT_ISP5432)
2753 #define IS_QLA2532(ha) (DT_MASK(ha) & DT_ISP2532)
2754 #define IS_QLA8432(ha) (DT_MASK(ha) & DT_ISP8432)
2755 #define IS_QLA8001(ha) (DT_MASK(ha) & DT_ISP8001)
2756 #define IS_QLA81XX(ha) (IS_QLA8001(ha))
2757 #define IS_QLA82XX(ha) (DT_MASK(ha) & DT_ISP8021)
2758 #define IS_QLA2031(ha) (DT_MASK(ha) & DT_ISP2031)
2759 #define IS_QLA8031(ha) (DT_MASK(ha) & DT_ISP8031)
2760
2761 #define IS_QLA23XX(ha) (IS_QLA2300(ha) || IS_QLA2312(ha) || IS_QLA2322(ha) || \
2762 IS_QLA6312(ha) || IS_QLA6322(ha))
2763 #define IS_QLA24XX(ha) (IS_QLA2422(ha) || IS_QLA2432(ha))
2764 #define IS_QLA54XX(ha) (IS_QLA5422(ha) || IS_QLA5432(ha))
2765 #define IS_QLA25XX(ha) (IS_QLA2532(ha))
2766 #define IS_QLA83XX(ha) (IS_QLA2031(ha) || IS_QLA8031(ha))
2767 #define IS_QLA84XX(ha) (IS_QLA8432(ha))
2768 #define IS_QLA24XX_TYPE(ha) (IS_QLA24XX(ha) || IS_QLA54XX(ha) || \
2769 IS_QLA84XX(ha))
2770 #define IS_CNA_CAPABLE(ha) (IS_QLA81XX(ha) || IS_QLA82XX(ha) || \
2771 IS_QLA8031(ha))
2772 #define IS_QLA2XXX_MIDTYPE(ha) (IS_QLA24XX(ha) || IS_QLA84XX(ha) || \
2773 IS_QLA25XX(ha) || IS_QLA81XX(ha) || \
2774 IS_QLA82XX(ha) || IS_QLA83XX(ha))
2775 #define IS_MSIX_NACK_CAPABLE(ha) (IS_QLA81XX(ha) || IS_QLA83XX(ha))
2776 #define IS_NOPOLLING_TYPE(ha) ((IS_QLA25XX(ha) || IS_QLA81XX(ha) || \
2777 IS_QLA83XX(ha)) && (ha)->flags.msix_enabled)
2778 #define IS_FAC_REQUIRED(ha) (IS_QLA81XX(ha) || IS_QLA83XX(ha))
2779 #define IS_NOCACHE_VPD_TYPE(ha) (IS_QLA81XX(ha) || IS_QLA83XX(ha))
2780 #define IS_ALOGIO_CAPABLE(ha) (IS_QLA23XX(ha) || IS_FWI2_CAPABLE(ha))
2781
2782 #define IS_T10_PI_CAPABLE(ha) ((ha)->device_type & DT_T10_PI)
2783 #define IS_IIDMA_CAPABLE(ha) ((ha)->device_type & DT_IIDMA)
2784 #define IS_FWI2_CAPABLE(ha) ((ha)->device_type & DT_FWI2)
2785 #define IS_ZIO_SUPPORTED(ha) ((ha)->device_type & DT_ZIO_SUPPORTED)
2786 #define IS_OEM_001(ha) ((ha)->device_type & DT_OEM_001)
2787 #define HAS_EXTENDED_IDS(ha) ((ha)->device_type & DT_EXTENDED_IDS)
2788 #define IS_CT6_SUPPORTED(ha) ((ha)->device_type & DT_CT6_SUPPORTED)
2789 #define IS_MQUE_CAPABLE(ha) ((ha)->mqenable || IS_QLA83XX(ha))
2790 #define IS_BIDI_CAPABLE(ha) ((IS_QLA25XX(ha) || IS_QLA2031(ha)))
2791 /* Bit 21 of fw_attributes decides the MCTP capabilities */
2792 #define IS_MCTP_CAPABLE(ha) (IS_QLA2031(ha) && \
2793 ((ha)->fw_attributes_ext[0] & BIT_0))
2794 #define IS_PI_UNINIT_CAPABLE(ha) (IS_QLA83XX(ha))
2795 #define IS_PI_IPGUARD_CAPABLE(ha) (IS_QLA83XX(ha))
2796 #define IS_PI_DIFB_DIX0_CAPABLE(ha) (0)
2797 #define IS_PI_SPLIT_DET_CAPABLE_HBA(ha) (IS_QLA83XX(ha))
2798 #define IS_PI_SPLIT_DET_CAPABLE(ha) (IS_PI_SPLIT_DET_CAPABLE_HBA(ha) && \
2799 (((ha)->fw_attributes_h << 16 | (ha)->fw_attributes) & BIT_22))
2800 #define IS_ATIO_MSIX_CAPABLE(ha) (IS_QLA83XX(ha))
2801 #define IS_TGT_MODE_CAPABLE(ha) (ha->tgt.atio_q_length)
2802
2803 /* HBA serial number */
2804 uint8_t serial0;
2805 uint8_t serial1;
2806 uint8_t serial2;
2807
2808 /* NVRAM configuration data */
2809 #define MAX_NVRAM_SIZE 4096
2810 #define VPD_OFFSET MAX_NVRAM_SIZE / 2
2811 uint16_t nvram_size;
2812 uint16_t nvram_base;
2813 void *nvram;
2814 uint16_t vpd_size;
2815 uint16_t vpd_base;
2816 void *vpd;
2817
2818 uint16_t loop_reset_delay;
2819 uint8_t retry_count;
2820 uint8_t login_timeout;
2821 uint16_t r_a_tov;
2822 int port_down_retry_count;
2823 uint8_t mbx_count;
2824
2825 uint32_t login_retry_count;
2826 /* SNS command interfaces. */
2827 ms_iocb_entry_t *ms_iocb;
2828 dma_addr_t ms_iocb_dma;
2829 struct ct_sns_pkt *ct_sns;
2830 dma_addr_t ct_sns_dma;
2831 /* SNS command interfaces for 2200. */
2832 struct sns_cmd_pkt *sns_cmd;
2833 dma_addr_t sns_cmd_dma;
2834
2835 #define SFP_DEV_SIZE 256
2836 #define SFP_BLOCK_SIZE 64
2837 void *sfp_data;
2838 dma_addr_t sfp_data_dma;
2839
2840 #define XGMAC_DATA_SIZE 4096
2841 void *xgmac_data;
2842 dma_addr_t xgmac_data_dma;
2843
2844 #define DCBX_TLV_DATA_SIZE 4096
2845 void *dcbx_tlv;
2846 dma_addr_t dcbx_tlv_dma;
2847
2848 struct task_struct *dpc_thread;
2849 uint8_t dpc_active; /* DPC routine is active */
2850
2851 dma_addr_t gid_list_dma;
2852 struct gid_list_info *gid_list;
2853 int gid_list_info_size;
2854
2855 /* Small DMA pool allocations -- maximum 256 bytes in length. */
2856 #define DMA_POOL_SIZE 256
2857 struct dma_pool *s_dma_pool;
2858
2859 dma_addr_t init_cb_dma;
2860 init_cb_t *init_cb;
2861 int init_cb_size;
2862 dma_addr_t ex_init_cb_dma;
2863 struct ex_init_cb_81xx *ex_init_cb;
2864
2865 void *async_pd;
2866 dma_addr_t async_pd_dma;
2867
2868 void *swl;
2869
2870 /* These are used by mailbox operations. */
2871 volatile uint16_t mailbox_out[MAILBOX_REGISTER_COUNT];
2872
2873 mbx_cmd_t *mcp;
2874 unsigned long mbx_cmd_flags;
2875 #define MBX_INTERRUPT 1
2876 #define MBX_INTR_WAIT 2
2877 #define MBX_UPDATE_FLASH_ACTIVE 3
2878
2879 struct mutex vport_lock; /* Virtual port synchronization */
2880 spinlock_t vport_slock; /* order is hardware_lock, then vport_slock */
2881 struct completion mbx_cmd_comp; /* Serialize mbx access */
2882 struct completion mbx_intr_comp; /* Used for completion notification */
2883 struct completion dcbx_comp; /* For set port config notification */
2884 int notify_dcbx_comp;
2885 struct mutex selflogin_lock;
2886
2887 /* Basic firmware related information. */
2888 uint16_t fw_major_version;
2889 uint16_t fw_minor_version;
2890 uint16_t fw_subminor_version;
2891 uint16_t fw_attributes;
2892 uint16_t fw_attributes_h;
2893 uint16_t fw_attributes_ext[2];
2894 uint32_t fw_memory_size;
2895 uint32_t fw_transfer_size;
2896 uint32_t fw_srisc_address;
2897 #define RISC_START_ADDRESS_2100 0x1000
2898 #define RISC_START_ADDRESS_2300 0x800
2899 #define RISC_START_ADDRESS_2400 0x100000
2900 uint16_t fw_xcb_count;
2901 uint16_t fw_iocb_count;
2902
2903 uint16_t fw_options[16]; /* slots: 1,2,3,10,11 */
2904 uint8_t fw_seriallink_options[4];
2905 uint16_t fw_seriallink_options24[4];
2906
2907 uint8_t mpi_version[3];
2908 uint32_t mpi_capabilities;
2909 uint8_t phy_version[3];
2910
2911 /* Firmware dump information. */
2912 struct qla2xxx_fw_dump *fw_dump;
2913 uint32_t fw_dump_len;
2914 int fw_dumped;
2915 int fw_dump_reading;
2916 dma_addr_t eft_dma;
2917 void *eft;
2918 /* Current size of mctp dump is 0x086064 bytes */
2919 #define MCTP_DUMP_SIZE 0x086064
2920 dma_addr_t mctp_dump_dma;
2921 void *mctp_dump;
2922 int mctp_dumped;
2923 int mctp_dump_reading;
2924 uint32_t chain_offset;
2925 struct dentry *dfs_dir;
2926 struct dentry *dfs_fce;
2927 dma_addr_t fce_dma;
2928 void *fce;
2929 uint32_t fce_bufs;
2930 uint16_t fce_mb[8];
2931 uint64_t fce_wr, fce_rd;
2932 struct mutex fce_mutex;
2933
2934 uint32_t pci_attr;
2935 uint16_t chip_revision;
2936
2937 uint16_t product_id[4];
2938
2939 uint8_t model_number[16+1];
2940 #define BINZERO "\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0"
2941 char model_desc[80];
2942 uint8_t adapter_id[16+1];
2943
2944 /* Option ROM information. */
2945 char *optrom_buffer;
2946 uint32_t optrom_size;
2947 int optrom_state;
2948 #define QLA_SWAITING 0
2949 #define QLA_SREADING 1
2950 #define QLA_SWRITING 2
2951 uint32_t optrom_region_start;
2952 uint32_t optrom_region_size;
2953
2954 /* PCI expansion ROM image information. */
2955 #define ROM_CODE_TYPE_BIOS 0
2956 #define ROM_CODE_TYPE_FCODE 1
2957 #define ROM_CODE_TYPE_EFI 3
2958 uint8_t bios_revision[2];
2959 uint8_t efi_revision[2];
2960 uint8_t fcode_revision[16];
2961 uint32_t fw_revision[4];
2962
2963 uint32_t gold_fw_version[4];
2964
2965 /* Offsets for flash/nvram access (set to ~0 if not used). */
2966 uint32_t flash_conf_off;
2967 uint32_t flash_data_off;
2968 uint32_t nvram_conf_off;
2969 uint32_t nvram_data_off;
2970
2971 uint32_t fdt_wrt_disable;
2972 uint32_t fdt_erase_cmd;
2973 uint32_t fdt_block_size;
2974 uint32_t fdt_unprotect_sec_cmd;
2975 uint32_t fdt_protect_sec_cmd;
2976
2977 uint32_t flt_region_flt;
2978 uint32_t flt_region_fdt;
2979 uint32_t flt_region_boot;
2980 uint32_t flt_region_fw;
2981 uint32_t flt_region_vpd_nvram;
2982 uint32_t flt_region_vpd;
2983 uint32_t flt_region_nvram;
2984 uint32_t flt_region_npiv_conf;
2985 uint32_t flt_region_gold_fw;
2986 uint32_t flt_region_fcp_prio;
2987 uint32_t flt_region_bootload;
2988
2989 /* Needed for BEACON */
2990 uint16_t beacon_blink_led;
2991 uint8_t beacon_color_state;
2992 #define QLA_LED_GRN_ON 0x01
2993 #define QLA_LED_YLW_ON 0x02
2994 #define QLA_LED_ABR_ON 0x04
2995 #define QLA_LED_ALL_ON 0x07 /* yellow, green, amber. */
2996 /* ISP2322: red, green, amber. */
2997 uint16_t zio_mode;
2998 uint16_t zio_timer;
2999
3000 struct qla_msix_entry *msix_entries;
3001
3002 struct list_head vp_list; /* list of VP */
3003 unsigned long vp_idx_map[(MAX_MULTI_ID_FABRIC / 8) /
3004 sizeof(unsigned long)];
3005 uint16_t num_vhosts; /* number of vports created */
3006 uint16_t num_vsans; /* number of vsan created */
3007 uint16_t max_npiv_vports; /* 63 or 125 per topoloty */
3008 int cur_vport_count;
3009
3010 struct qla_chip_state_84xx *cs84xx;
3011 struct isp_operations *isp_ops;
3012 struct workqueue_struct *wq;
3013 struct qlfc_fw fw_buf;
3014
3015 /* FCP_CMND priority support */
3016 struct qla_fcp_prio_cfg *fcp_prio_cfg;
3017
3018 struct dma_pool *dl_dma_pool;
3019 #define DSD_LIST_DMA_POOL_SIZE 512
3020
3021 struct dma_pool *fcp_cmnd_dma_pool;
3022 mempool_t *ctx_mempool;
3023 #define FCP_CMND_DMA_POOL_SIZE 512
3024
3025 unsigned long nx_pcibase; /* Base I/O address */
3026 uint8_t *nxdb_rd_ptr; /* Doorbell read pointer */
3027 unsigned long nxdb_wr_ptr; /* Door bell write pointer */
3028
3029 uint32_t crb_win;
3030 uint32_t curr_window;
3031 uint32_t ddr_mn_window;
3032 unsigned long mn_win_crb;
3033 unsigned long ms_win_crb;
3034 int qdr_sn_window;
3035 uint32_t fcoe_dev_init_timeout;
3036 uint32_t fcoe_reset_timeout;
3037 rwlock_t hw_lock;
3038 uint16_t portnum; /* port number */
3039 int link_width;
3040 struct fw_blob *hablob;
3041 struct qla82xx_legacy_intr_set nx_legacy_intr;
3042
3043 uint16_t gbl_dsd_inuse;
3044 uint16_t gbl_dsd_avail;
3045 struct list_head gbl_dsd_list;
3046 #define NUM_DSD_CHAIN 4096
3047
3048 uint8_t fw_type;
3049 __le32 file_prd_off; /* File firmware product offset */
3050
3051 uint32_t md_template_size;
3052 void *md_tmplt_hdr;
3053 dma_addr_t md_tmplt_hdr_dma;
3054 void *md_dump;
3055 uint32_t md_dump_size;
3056
3057 void *loop_id_map;
3058
3059 /* QLA83XX IDC specific fields */
3060 uint32_t idc_audit_ts;
3061
3062 /* DPC low-priority workqueue */
3063 struct workqueue_struct *dpc_lp_wq;
3064 struct work_struct idc_aen;
3065 /* DPC high-priority workqueue */
3066 struct workqueue_struct *dpc_hp_wq;
3067 struct work_struct nic_core_reset;
3068 struct work_struct idc_state_handler;
3069 struct work_struct nic_core_unrecoverable;
3070
3071 #define HOST_QUEUE_RAMPDOWN_INTERVAL (60 * HZ)
3072 #define HOST_QUEUE_RAMPUP_INTERVAL (30 * HZ)
3073 unsigned long host_last_rampdown_time;
3074 unsigned long host_last_rampup_time;
3075 int cfg_lun_q_depth;
3076
3077 struct qlt_hw_data tgt;
3078 };
3079
3080 /*
3081 * Qlogic scsi host structure
3082 */
3083 typedef struct scsi_qla_host {
3084 struct list_head list;
3085 struct list_head vp_fcports; /* list of fcports */
3086 struct list_head work_list;
3087 spinlock_t work_lock;
3088
3089 /* Commonly used flags and state information. */
3090 struct Scsi_Host *host;
3091 unsigned long host_no;
3092 uint8_t host_str[16];
3093
3094 volatile struct {
3095 uint32_t init_done :1;
3096 uint32_t online :1;
3097 uint32_t reset_active :1;
3098
3099 uint32_t management_server_logged_in :1;
3100 uint32_t process_response_queue :1;
3101 uint32_t difdix_supported:1;
3102 uint32_t delete_progress:1;
3103 } flags;
3104
3105 atomic_t loop_state;
3106 #define LOOP_TIMEOUT 1
3107 #define LOOP_DOWN 2
3108 #define LOOP_UP 3
3109 #define LOOP_UPDATE 4
3110 #define LOOP_READY 5
3111 #define LOOP_DEAD 6
3112
3113 unsigned long dpc_flags;
3114 #define RESET_MARKER_NEEDED 0 /* Send marker to ISP. */
3115 #define RESET_ACTIVE 1
3116 #define ISP_ABORT_NEEDED 2 /* Initiate ISP abort. */
3117 #define ABORT_ISP_ACTIVE 3 /* ISP abort in progress. */
3118 #define LOOP_RESYNC_NEEDED 4 /* Device Resync needed. */
3119 #define LOOP_RESYNC_ACTIVE 5
3120 #define LOCAL_LOOP_UPDATE 6 /* Perform a local loop update. */
3121 #define RSCN_UPDATE 7 /* Perform an RSCN update. */
3122 #define RELOGIN_NEEDED 8
3123 #define REGISTER_FC4_NEEDED 9 /* SNS FC4 registration required. */
3124 #define ISP_ABORT_RETRY 10 /* ISP aborted. */
3125 #define BEACON_BLINK_NEEDED 11
3126 #define REGISTER_FDMI_NEEDED 12
3127 #define FCPORT_UPDATE_NEEDED 13
3128 #define VP_DPC_NEEDED 14 /* wake up for VP dpc handling */
3129 #define UNLOADING 15
3130 #define NPIV_CONFIG_NEEDED 16
3131 #define ISP_UNRECOVERABLE 17
3132 #define FCOE_CTX_RESET_NEEDED 18 /* Initiate FCoE context reset */
3133 #define MPI_RESET_NEEDED 19 /* Initiate MPI FW reset */
3134 #define ISP_QUIESCE_NEEDED 20 /* Driver need some quiescence */
3135 #define SCR_PENDING 21 /* SCR in target mode */
3136 #define HOST_RAMP_DOWN_QUEUE_DEPTH 22
3137 #define HOST_RAMP_UP_QUEUE_DEPTH 23
3138
3139 uint32_t device_flags;
3140 #define SWITCH_FOUND BIT_0
3141 #define DFLG_NO_CABLE BIT_1
3142 #define DFLG_DEV_FAILED BIT_5
3143
3144 /* ISP configuration data. */
3145 uint16_t loop_id; /* Host adapter loop id */
3146 uint16_t self_login_loop_id; /* host adapter loop id
3147 * get it on self login
3148 */
3149 fc_port_t bidir_fcport; /* fcport used for bidir cmnds
3150 * no need of allocating it for
3151 * each command
3152 */
3153
3154 port_id_t d_id; /* Host adapter port id */
3155 uint8_t marker_needed;
3156 uint16_t mgmt_svr_loop_id;
3157
3158
3159
3160 /* Timeout timers. */
3161 uint8_t loop_down_abort_time; /* port down timer */
3162 atomic_t loop_down_timer; /* loop down timer */
3163 uint8_t link_down_timeout; /* link down timeout */
3164
3165 uint32_t timer_active;
3166 struct timer_list timer;
3167
3168 uint8_t node_name[WWN_SIZE];
3169 uint8_t port_name[WWN_SIZE];
3170 uint8_t fabric_node_name[WWN_SIZE];
3171
3172 uint16_t fcoe_vlan_id;
3173 uint16_t fcoe_fcf_idx;
3174 uint8_t fcoe_vn_port_mac[6];
3175
3176 uint32_t vp_abort_cnt;
3177
3178 struct fc_vport *fc_vport; /* holds fc_vport * for each vport */
3179 uint16_t vp_idx; /* vport ID */
3180
3181 unsigned long vp_flags;
3182 #define VP_IDX_ACQUIRED 0 /* bit no 0 */
3183 #define VP_CREATE_NEEDED 1
3184 #define VP_BIND_NEEDED 2
3185 #define VP_DELETE_NEEDED 3
3186 #define VP_SCR_NEEDED 4 /* State Change Request registration */
3187 atomic_t vp_state;
3188 #define VP_OFFLINE 0
3189 #define VP_ACTIVE 1
3190 #define VP_FAILED 2
3191 // #define VP_DISABLE 3
3192 uint16_t vp_err_state;
3193 uint16_t vp_prev_err_state;
3194 #define VP_ERR_UNKWN 0
3195 #define VP_ERR_PORTDWN 1
3196 #define VP_ERR_FAB_UNSUPPORTED 2
3197 #define VP_ERR_FAB_NORESOURCES 3
3198 #define VP_ERR_FAB_LOGOUT 4
3199 #define VP_ERR_ADAP_NORESOURCES 5
3200 struct qla_hw_data *hw;
3201 struct req_que *req;
3202 int fw_heartbeat_counter;
3203 int seconds_since_last_heartbeat;
3204 struct fc_host_statistics fc_host_stat;
3205 struct qla_statistics qla_stats;
3206 struct bidi_statistics bidi_stats;
3207
3208 atomic_t vref_count;
3209 } scsi_qla_host_t;
3210
3211 #define SET_VP_IDX 1
3212 #define SET_AL_PA 2
3213 #define RESET_VP_IDX 3
3214 #define RESET_AL_PA 4
3215 struct qla_tgt_vp_map {
3216 uint8_t idx;
3217 scsi_qla_host_t *vha;
3218 };
3219
3220 /*
3221 * Macros to help code, maintain, etc.
3222 */
3223 #define LOOP_TRANSITION(ha) \
3224 (test_bit(ISP_ABORT_NEEDED, &ha->dpc_flags) || \
3225 test_bit(LOOP_RESYNC_NEEDED, &ha->dpc_flags) || \
3226 atomic_read(&ha->loop_state) == LOOP_DOWN)
3227
3228 #define QLA_VHA_MARK_BUSY(__vha, __bail) do { \
3229 atomic_inc(&__vha->vref_count); \
3230 mb(); \
3231 if (__vha->flags.delete_progress) { \
3232 atomic_dec(&__vha->vref_count); \
3233 __bail = 1; \
3234 } else { \
3235 __bail = 0; \
3236 } \
3237 } while (0)
3238
3239 #define QLA_VHA_MARK_NOT_BUSY(__vha) do { \
3240 atomic_dec(&__vha->vref_count); \
3241 } while (0)
3242
3243 /*
3244 * qla2x00 local function return status codes
3245 */
3246 #define MBS_MASK 0x3fff
3247
3248 #define QLA_SUCCESS (MBS_COMMAND_COMPLETE & MBS_MASK)
3249 #define QLA_INVALID_COMMAND (MBS_INVALID_COMMAND & MBS_MASK)
3250 #define QLA_INTERFACE_ERROR (MBS_HOST_INTERFACE_ERROR & MBS_MASK)
3251 #define QLA_TEST_FAILED (MBS_TEST_FAILED & MBS_MASK)
3252 #define QLA_COMMAND_ERROR (MBS_COMMAND_ERROR & MBS_MASK)
3253 #define QLA_PARAMETER_ERROR (MBS_COMMAND_PARAMETER_ERROR & MBS_MASK)
3254 #define QLA_PORT_ID_USED (MBS_PORT_ID_USED & MBS_MASK)
3255 #define QLA_LOOP_ID_USED (MBS_LOOP_ID_USED & MBS_MASK)
3256 #define QLA_ALL_IDS_IN_USE (MBS_ALL_IDS_IN_USE & MBS_MASK)
3257 #define QLA_NOT_LOGGED_IN (MBS_NOT_LOGGED_IN & MBS_MASK)
3258
3259 #define QLA_FUNCTION_TIMEOUT 0x100
3260 #define QLA_FUNCTION_PARAMETER_ERROR 0x101
3261 #define QLA_FUNCTION_FAILED 0x102
3262 #define QLA_MEMORY_ALLOC_FAILED 0x103
3263 #define QLA_LOCK_TIMEOUT 0x104
3264 #define QLA_ABORTED 0x105
3265 #define QLA_SUSPENDED 0x106
3266 #define QLA_BUSY 0x107
3267 #define QLA_ALREADY_REGISTERED 0x109
3268
3269 #define NVRAM_DELAY() udelay(10)
3270
3271 /*
3272 * Flash support definitions
3273 */
3274 #define OPTROM_SIZE_2300 0x20000
3275 #define OPTROM_SIZE_2322 0x100000
3276 #define OPTROM_SIZE_24XX 0x100000
3277 #define OPTROM_SIZE_25XX 0x200000
3278 #define OPTROM_SIZE_81XX 0x400000
3279 #define OPTROM_SIZE_82XX 0x800000
3280 #define OPTROM_SIZE_83XX 0x1000000
3281
3282 #define OPTROM_BURST_SIZE 0x1000
3283 #define OPTROM_BURST_DWORDS (OPTROM_BURST_SIZE / 4)
3284
3285 #define QLA_DSDS_PER_IOCB 37
3286
3287 #define CMD_SP(Cmnd) ((Cmnd)->SCp.ptr)
3288
3289 #define QLA_SG_ALL 1024
3290
3291 enum nexus_wait_type {
3292 WAIT_HOST = 0,
3293 WAIT_TARGET,
3294 WAIT_LUN,
3295 };
3296
3297 #include "qla_gbl.h"
3298 #include "qla_dbg.h"
3299 #include "qla_inline.h"
3300 #endif
Linus' kernel tree