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staging: gma500: cleanup the SDVO messages
[linux-2.6.git] / drivers / staging / gma500 / psb_drv.c
blob8978ed657857bbd7d07731eacb65e5170423c74d
1 /**************************************************************************
2 * Copyright (c) 2007, Intel Corporation.
3 * All Rights Reserved.
4 * Copyright (c) 2008, Tungsten Graphics, Inc. Cedar Park, TX., USA.
5 * All Rights Reserved.
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms and conditions of the GNU General Public License,
9 * version 2, as published by the Free Software Foundation.
10 *
11 * This program is distributed in the hope it will be useful, but WITHOUT
12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 * more details.
15 *
16 * You should have received a copy of the GNU General Public License along with
17 * this program; if not, write to the Free Software Foundation, Inc.,
18 * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
19 *
20 **************************************************************************/
21
22 #include <drm/drmP.h>
23 #include <drm/drm.h>
24 #include "psb_drm.h"
25 #include "psb_drv.h"
26 #include "psb_fb.h"
27 #include "psb_reg.h"
28 #include "psb_intel_reg.h"
29 #include "psb_intel_bios.h"
30 #include <drm/drm_pciids.h>
31 #include "psb_powermgmt.h"
32 #include <linux/cpu.h>
33 #include <linux/notifier.h>
34 #include <linux/spinlock.h>
35 #include <linux/pm_runtime.h>
36 #include <acpi/video.h>
37
38 int drm_psb_debug;
39 static int drm_psb_trap_pagefaults;
40
41 int drm_psb_no_fb;
42
43 static int psb_probe(struct pci_dev *pdev, const struct pci_device_id *ent);
44
45 MODULE_PARM_DESC(debug, "Enable debug output");
46 MODULE_PARM_DESC(no_fb, "Disable FBdev");
47 MODULE_PARM_DESC(trap_pagefaults, "Error and reset on MMU pagefaults");
48 module_param_named(debug, drm_psb_debug, int, 0600);
49 module_param_named(no_fb, drm_psb_no_fb, int, 0600);
50 module_param_named(trap_pagefaults, drm_psb_trap_pagefaults, int, 0600);
51
52
53 static struct pci_device_id pciidlist[] = {
54 { 0x8086, 0x8108, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PSB_8108 },
55 { 0x8086, 0x8109, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PSB_8109 },
56 { 0x8086, 0x4100, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MRST_4100},
57 { 0x8086, 0x4101, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MRST_4100},
58 { 0x8086, 0x4102, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MRST_4100},
59 { 0x8086, 0x4103, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MRST_4100},
60 { 0x8086, 0x4104, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MRST_4100},
61 { 0x8086, 0x4105, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MRST_4100},
62 { 0x8086, 0x4106, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MRST_4100},
63 { 0x8086, 0x4107, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MRST_4100},
64 { 0, 0, 0}
65 };
66 MODULE_DEVICE_TABLE(pci, pciidlist);
67
68 /*
69 * Standard IOCTLs.
70 */
71
72 #define DRM_IOCTL_PSB_KMS_OFF \
73 DRM_IO(DRM_PSB_KMS_OFF + DRM_COMMAND_BASE)
74 #define DRM_IOCTL_PSB_KMS_ON \
75 DRM_IO(DRM_PSB_KMS_ON + DRM_COMMAND_BASE)
76 #define DRM_IOCTL_PSB_VT_LEAVE \
77 DRM_IO(DRM_PSB_VT_LEAVE + DRM_COMMAND_BASE)
78 #define DRM_IOCTL_PSB_VT_ENTER \
79 DRM_IO(DRM_PSB_VT_ENTER + DRM_COMMAND_BASE)
80 #define DRM_IOCTL_PSB_SIZES \
81 DRM_IOR(DRM_PSB_SIZES + DRM_COMMAND_BASE, \
82 struct drm_psb_sizes_arg)
83 #define DRM_IOCTL_PSB_FUSE_REG \
84 DRM_IOWR(DRM_PSB_FUSE_REG + DRM_COMMAND_BASE, uint32_t)
85 #define DRM_IOCTL_PSB_DC_STATE \
86 DRM_IOW(DRM_PSB_DC_STATE + DRM_COMMAND_BASE, \
87 struct drm_psb_dc_state_arg)
88 #define DRM_IOCTL_PSB_ADB \
89 DRM_IOWR(DRM_PSB_ADB + DRM_COMMAND_BASE, uint32_t)
90 #define DRM_IOCTL_PSB_MODE_OPERATION \
91 DRM_IOWR(DRM_PSB_MODE_OPERATION + DRM_COMMAND_BASE, \
92 struct drm_psb_mode_operation_arg)
93 #define DRM_IOCTL_PSB_STOLEN_MEMORY \
94 DRM_IOWR(DRM_PSB_STOLEN_MEMORY + DRM_COMMAND_BASE, \
95 struct drm_psb_stolen_memory_arg)
96 #define DRM_IOCTL_PSB_REGISTER_RW \
97 DRM_IOWR(DRM_PSB_REGISTER_RW + DRM_COMMAND_BASE, \
98 struct drm_psb_register_rw_arg)
99 #define DRM_IOCTL_PSB_GTT_MAP \
100 DRM_IOWR(DRM_PSB_GTT_MAP + DRM_COMMAND_BASE, \
101 struct psb_gtt_mapping_arg)
102 #define DRM_IOCTL_PSB_GTT_UNMAP \
103 DRM_IOW(DRM_PSB_GTT_UNMAP + DRM_COMMAND_BASE, \
104 struct psb_gtt_mapping_arg)
105 #define DRM_IOCTL_PSB_UPDATE_GUARD \
106 DRM_IOWR(DRM_PSB_UPDATE_GUARD + DRM_COMMAND_BASE, \
107 uint32_t)
108 #define DRM_IOCTL_PSB_DPST \
109 DRM_IOWR(DRM_PSB_DPST + DRM_COMMAND_BASE, \
110 uint32_t)
111 #define DRM_IOCTL_PSB_GAMMA \
112 DRM_IOWR(DRM_PSB_GAMMA + DRM_COMMAND_BASE, \
113 struct drm_psb_dpst_lut_arg)
114 #define DRM_IOCTL_PSB_DPST_BL \
115 DRM_IOWR(DRM_PSB_DPST_BL + DRM_COMMAND_BASE, \
116 uint32_t)
117 #define DRM_IOCTL_PSB_GET_PIPE_FROM_CRTC_ID \
118 DRM_IOWR(DRM_PSB_GET_PIPE_FROM_CRTC_ID + DRM_COMMAND_BASE, \
119 struct drm_psb_get_pipe_from_crtc_id_arg)
120
121 #define DRM_IOCTL_PSB_KMS_OFF DRM_IO(DRM_PSB_KMS_OFF + DRM_COMMAND_BASE)
122 #define DRM_IOCTL_PSB_KMS_ON DRM_IO(DRM_PSB_KMS_ON + DRM_COMMAND_BASE)
123
124 static int psb_vt_leave_ioctl(struct drm_device *dev, void *data,
125 struct drm_file *file_priv);
126 static int psb_vt_enter_ioctl(struct drm_device *dev, void *data,
127 struct drm_file *file_priv);
128 static int psb_sizes_ioctl(struct drm_device *dev, void *data,
129 struct drm_file *file_priv);
130 static int psb_dc_state_ioctl(struct drm_device *dev, void * data,
131 struct drm_file *file_priv);
132 static int psb_adb_ioctl(struct drm_device *dev, void *data,
133 struct drm_file *file_priv);
134 static int psb_mode_operation_ioctl(struct drm_device *dev, void *data,
135 struct drm_file *file_priv);
136 static int psb_stolen_memory_ioctl(struct drm_device *dev, void *data,
137 struct drm_file *file_priv);
138 static int psb_register_rw_ioctl(struct drm_device *dev, void *data,
139 struct drm_file *file_priv);
140 static int psb_dpst_ioctl(struct drm_device *dev, void *data,
141 struct drm_file *file_priv);
142 static int psb_gamma_ioctl(struct drm_device *dev, void *data,
143 struct drm_file *file_priv);
144 static int psb_dpst_bl_ioctl(struct drm_device *dev, void *data,
145 struct drm_file *file_priv);
146
147 #define PSB_IOCTL_DEF(ioctl, func, flags) \
148 [DRM_IOCTL_NR(ioctl) - DRM_COMMAND_BASE] = {ioctl, flags, func}
149
150 static struct drm_ioctl_desc psb_ioctls[] = {
151 PSB_IOCTL_DEF(DRM_IOCTL_PSB_KMS_OFF, psbfb_kms_off_ioctl,
152 DRM_ROOT_ONLY),
153 PSB_IOCTL_DEF(DRM_IOCTL_PSB_KMS_ON,
154 psbfb_kms_on_ioctl,
155 DRM_ROOT_ONLY),
156 PSB_IOCTL_DEF(DRM_IOCTL_PSB_VT_LEAVE, psb_vt_leave_ioctl,
157 DRM_ROOT_ONLY),
158 PSB_IOCTL_DEF(DRM_IOCTL_PSB_VT_ENTER,
159 psb_vt_enter_ioctl,
160 DRM_ROOT_ONLY),
161 PSB_IOCTL_DEF(DRM_IOCTL_PSB_SIZES, psb_sizes_ioctl, DRM_AUTH),
162 PSB_IOCTL_DEF(DRM_IOCTL_PSB_DC_STATE, psb_dc_state_ioctl, DRM_AUTH),
163 PSB_IOCTL_DEF(DRM_IOCTL_PSB_ADB, psb_adb_ioctl, DRM_AUTH),
164 PSB_IOCTL_DEF(DRM_IOCTL_PSB_MODE_OPERATION, psb_mode_operation_ioctl,
165 DRM_AUTH),
166 PSB_IOCTL_DEF(DRM_IOCTL_PSB_STOLEN_MEMORY, psb_stolen_memory_ioctl,
167 DRM_AUTH),
168 PSB_IOCTL_DEF(DRM_IOCTL_PSB_REGISTER_RW, psb_register_rw_ioctl,
169 DRM_AUTH),
170 PSB_IOCTL_DEF(DRM_IOCTL_PSB_GTT_MAP,
171 psb_gtt_map_meminfo_ioctl,
172 DRM_AUTH),
173 PSB_IOCTL_DEF(DRM_IOCTL_PSB_GTT_UNMAP,
174 psb_gtt_unmap_meminfo_ioctl,
175 DRM_AUTH),
176 PSB_IOCTL_DEF(DRM_IOCTL_PSB_DPST, psb_dpst_ioctl, DRM_AUTH),
177 PSB_IOCTL_DEF(DRM_IOCTL_PSB_GAMMA, psb_gamma_ioctl, DRM_AUTH),
178 PSB_IOCTL_DEF(DRM_IOCTL_PSB_DPST_BL, psb_dpst_bl_ioctl, DRM_AUTH),
179 PSB_IOCTL_DEF(DRM_IOCTL_PSB_GET_PIPE_FROM_CRTC_ID,
180 psb_intel_get_pipe_from_crtc_id, 0),
181
182 };
183
184 static void psb_lastclose(struct drm_device *dev)
185 {
186 return;
187 }
188
189 static void psb_do_takedown(struct drm_device *dev)
190 {
191 /* FIXME: do we need to clean up the gtt here ? */
192 }
193
194 void mrst_get_fuse_settings(struct drm_device *dev)
195 {
196 struct drm_psb_private *dev_priv = dev->dev_private;
197 struct pci_dev *pci_root = pci_get_bus_and_slot(0, 0);
198 uint32_t fuse_value = 0;
199 uint32_t fuse_value_tmp = 0;
200
201 #define FB_REG06 0xD0810600
202 #define FB_MIPI_DISABLE (1 << 11)
203 #define FB_REG09 0xD0810900
204 #define FB_REG09 0xD0810900
205 #define FB_SKU_MASK 0x7000
206 #define FB_SKU_SHIFT 12
207 #define FB_SKU_100 0
208 #define FB_SKU_100L 1
209 #define FB_SKU_83 2
210 pci_write_config_dword(pci_root, 0xD0, FB_REG06);
211 pci_read_config_dword(pci_root, 0xD4, &fuse_value);
212
213 dev_priv->iLVDS_enable = fuse_value & FB_MIPI_DISABLE;
214
215 DRM_INFO("internal display is %s\n",
216 dev_priv->iLVDS_enable ? "LVDS display" : "MIPI display");
217
218 /*prevent Runtime suspend at start*/
219 if (dev_priv->iLVDS_enable) {
220 dev_priv->is_lvds_on = true;
221 dev_priv->is_mipi_on = false;
222 }
223 else {
224 dev_priv->is_mipi_on = true;
225 dev_priv->is_lvds_on = false;
226 }
227
228 dev_priv->video_device_fuse = fuse_value;
229
230 pci_write_config_dword(pci_root, 0xD0, FB_REG09);
231 pci_read_config_dword(pci_root, 0xD4, &fuse_value);
232
233 DRM_INFO("SKU values is 0x%x. \n", fuse_value);
234 fuse_value_tmp = (fuse_value & FB_SKU_MASK) >> FB_SKU_SHIFT;
235
236 dev_priv->fuse_reg_value = fuse_value;
237
238 switch (fuse_value_tmp) {
239 case FB_SKU_100:
240 dev_priv->core_freq = 200;
241 break;
242 case FB_SKU_100L:
243 dev_priv->core_freq = 100;
244 break;
245 case FB_SKU_83:
246 dev_priv->core_freq = 166;
247 break;
248 default:
249 DRM_ERROR("Invalid SKU values, SKU value = 0x%08x\n", fuse_value_tmp);
250 dev_priv->core_freq = 0;
251 }
252 DRM_INFO("LNC core clk is %dMHz.\n", dev_priv->core_freq);
253 pci_dev_put(pci_root);
254 }
255
256 void mid_get_pci_revID (struct drm_psb_private *dev_priv)
257 {
258 uint32_t platform_rev_id = 0;
259 struct pci_dev *pci_gfx_root = pci_get_bus_and_slot(0, PCI_DEVFN(2, 0));
260
261 /*get the revison ID, B0:D2:F0;0x08 */
262 pci_read_config_dword(pci_gfx_root, 0x08, &platform_rev_id);
263 dev_priv->platform_rev_id = (uint8_t) platform_rev_id;
264 pci_dev_put(pci_gfx_root);
265 PSB_DEBUG_ENTRY("platform_rev_id is %x\n", dev_priv->platform_rev_id);
266 }
267
268 void mrst_get_vbt_data(struct drm_psb_private *dev_priv)
269 {
270 struct mrst_vbt *vbt = &dev_priv->vbt_data;
271 u32 platform_config_address;
272 u16 new_size;
273 u8 *vbt_virtual;
274 u8 bpi;
275 u8 number_desc = 0;
276 struct mrst_timing_info *dp_ti = &dev_priv->gct_data.DTD;
277 struct gct_r10_timing_info ti;
278 void *pGCT;
279 struct pci_dev *pci_gfx_root = pci_get_bus_and_slot(0, PCI_DEVFN(2, 0));
280
281 /*get the address of the platform config vbt, B0:D2:F0;0xFC */
282 pci_read_config_dword(pci_gfx_root, 0xFC, &platform_config_address);
283 pci_dev_put(pci_gfx_root);
284 DRM_INFO("drm platform config address is %x\n",
285 platform_config_address);
286
287 /* check for platform config address == 0. */
288 /* this means fw doesn't support vbt */
289
290 if (platform_config_address == 0) {
291 vbt->size = 0;
292 return;
293 }
294
295 /* get the virtual address of the vbt */
296 vbt_virtual = ioremap(platform_config_address, sizeof(*vbt));
297
298 memcpy(vbt, vbt_virtual, sizeof(*vbt));
299 iounmap(vbt_virtual); /* Free virtual address space */
300
301 printk(KERN_ALERT "GCT revision is %x\n", vbt->revision);
302
303 switch (vbt->revision) {
304 case 0:
305 vbt->mrst_gct = NULL;
306 vbt->mrst_gct = \
307 ioremap(platform_config_address + sizeof(*vbt) - 4,
308 vbt->size - sizeof(*vbt) + 4);
309 pGCT = vbt->mrst_gct;
310 bpi = ((struct mrst_gct_v1 *)pGCT)->PD.BootPanelIndex;
311 dev_priv->gct_data.bpi = bpi;
312 dev_priv->gct_data.pt =
313 ((struct mrst_gct_v1 *)pGCT)->PD.PanelType;
314 memcpy(&dev_priv->gct_data.DTD,
315 &((struct mrst_gct_v1 *)pGCT)->panel[bpi].DTD,
316 sizeof(struct mrst_timing_info));
317 dev_priv->gct_data.Panel_Port_Control =
318 ((struct mrst_gct_v1 *)pGCT)->panel[bpi].Panel_Port_Control;
319 dev_priv->gct_data.Panel_MIPI_Display_Descriptor =
320 ((struct mrst_gct_v1 *)pGCT)->panel[bpi].Panel_MIPI_Display_Descriptor;
321 break;
322 case 1:
323 vbt->mrst_gct = NULL;
324 vbt->mrst_gct = \
325 ioremap(platform_config_address + sizeof(*vbt) - 4,
326 vbt->size - sizeof(*vbt) + 4);
327 pGCT = vbt->mrst_gct;
328 bpi = ((struct mrst_gct_v2 *)pGCT)->PD.BootPanelIndex;
329 dev_priv->gct_data.bpi = bpi;
330 dev_priv->gct_data.pt =
331 ((struct mrst_gct_v2 *)pGCT)->PD.PanelType;
332 memcpy(&dev_priv->gct_data.DTD,
333 &((struct mrst_gct_v2 *)pGCT)->panel[bpi].DTD,
334 sizeof(struct mrst_timing_info));
335 dev_priv->gct_data.Panel_Port_Control =
336 ((struct mrst_gct_v2 *)pGCT)->panel[bpi].Panel_Port_Control;
337 dev_priv->gct_data.Panel_MIPI_Display_Descriptor =
338 ((struct mrst_gct_v2 *)pGCT)->panel[bpi].Panel_MIPI_Display_Descriptor;
339 break;
340 case 0x10:
341 /*header definition changed from rev 01 (v2) to rev 10h. */
342 /*so, some values have changed location*/
343 new_size = vbt->checksum; /*checksum contains lo size byte*/
344 /*LSB of mrst_gct contains hi size byte*/
345 new_size |= ((0xff & (unsigned int)vbt->mrst_gct)) << 8;
346
347 vbt->checksum = vbt->size; /*size contains the checksum*/
348 if (new_size > 0xff)
349 vbt->size = 0xff; /*restrict size to 255*/
350 else
351 vbt->size = new_size;
352
353 /* number of descriptors defined in the GCT */
354 number_desc = ((0xff00 & (unsigned int)vbt->mrst_gct)) >> 8;
355 bpi = ((0xff0000 & (unsigned int)vbt->mrst_gct)) >> 16;
356 vbt->mrst_gct = NULL;
357 vbt->mrst_gct = \
358 ioremap(platform_config_address + GCT_R10_HEADER_SIZE,
359 GCT_R10_DISPLAY_DESC_SIZE * number_desc);
360 pGCT = vbt->mrst_gct;
361 pGCT = (u8 *)pGCT + (bpi*GCT_R10_DISPLAY_DESC_SIZE);
362 dev_priv->gct_data.bpi = bpi; /*save boot panel id*/
363
364 /*copy the GCT display timings into a temp structure*/
365 memcpy(&ti, pGCT, sizeof(struct gct_r10_timing_info));
366
367 /*now copy the temp struct into the dev_priv->gct_data*/
368 dp_ti->pixel_clock = ti.pixel_clock;
369 dp_ti->hactive_hi = ti.hactive_hi;
370 dp_ti->hactive_lo = ti.hactive_lo;
371 dp_ti->hblank_hi = ti.hblank_hi;
372 dp_ti->hblank_lo = ti.hblank_lo;
373 dp_ti->hsync_offset_hi = ti.hsync_offset_hi;
374 dp_ti->hsync_offset_lo = ti.hsync_offset_lo;
375 dp_ti->hsync_pulse_width_hi = ti.hsync_pulse_width_hi;
376 dp_ti->hsync_pulse_width_lo = ti.hsync_pulse_width_lo;
377 dp_ti->vactive_hi = ti.vactive_hi;
378 dp_ti->vactive_lo = ti.vactive_lo;
379 dp_ti->vblank_hi = ti.vblank_hi;
380 dp_ti->vblank_lo = ti.vblank_lo;
381 dp_ti->vsync_offset_hi = ti.vsync_offset_hi;
382 dp_ti->vsync_offset_lo = ti.vsync_offset_lo;
383 dp_ti->vsync_pulse_width_hi = ti.vsync_pulse_width_hi;
384 dp_ti->vsync_pulse_width_lo = ti.vsync_pulse_width_lo;
385
386 /*mov the MIPI_Display_Descriptor data from GCT to dev priv*/
387 dev_priv->gct_data.Panel_MIPI_Display_Descriptor =
388 *((u8 *)pGCT + 0x0d);
389 dev_priv->gct_data.Panel_MIPI_Display_Descriptor |=
390 (*((u8 *)pGCT + 0x0e)) << 8;
391 break;
392 default:
393 printk(KERN_ERR "Unknown revision of GCT!\n");
394 vbt->size = 0;
395 }
396 }
397
398 static void psb_get_core_freq(struct drm_device *dev)
399 {
400 uint32_t clock;
401 struct pci_dev *pci_root = pci_get_bus_and_slot(0, 0);
402 struct drm_psb_private *dev_priv = dev->dev_private;
403
404 /*pci_write_config_dword(pci_root, 0xD4, 0x00C32004);*/
405 /*pci_write_config_dword(pci_root, 0xD0, 0xE0033000);*/
406
407 pci_write_config_dword(pci_root, 0xD0, 0xD0050300);
408 pci_read_config_dword(pci_root, 0xD4, &clock);
409 pci_dev_put(pci_root);
410
411 switch (clock & 0x07) {
412 case 0:
413 dev_priv->core_freq = 100;
414 break;
415 case 1:
416 dev_priv->core_freq = 133;
417 break;
418 case 2:
419 dev_priv->core_freq = 150;
420 break;
421 case 3:
422 dev_priv->core_freq = 178;
423 break;
424 case 4:
425 dev_priv->core_freq = 200;
426 break;
427 case 5:
428 case 6:
429 case 7:
430 dev_priv->core_freq = 266;
431 default:
432 dev_priv->core_freq = 0;
433 }
434 }
435
436 static int psb_do_init(struct drm_device *dev)
437 {
438 struct drm_psb_private *dev_priv =
439 (struct drm_psb_private *) dev->dev_private;
440 struct psb_gtt *pg = dev_priv->pg;
441
442 uint32_t stolen_gtt;
443 uint32_t tt_start;
444 uint32_t tt_pages;
445
446 int ret = -ENOMEM;
447
448 if (pg->mmu_gatt_start & 0x0FFFFFFF) {
449 DRM_ERROR("Gatt must be 256M aligned. This is a bug.\n");
450 ret = -EINVAL;
451 goto out_err;
452 }
453
454
455 stolen_gtt = (pg->stolen_size >> PAGE_SHIFT) * 4;
456 stolen_gtt = (stolen_gtt + PAGE_SIZE - 1) >> PAGE_SHIFT;
457 stolen_gtt =
458 (stolen_gtt < pg->gtt_pages) ? stolen_gtt : pg->gtt_pages;
459
460 dev_priv->gatt_free_offset = pg->mmu_gatt_start +
461 (stolen_gtt << PAGE_SHIFT) * 1024;
462
463 if (1 || drm_debug) {
464 uint32_t core_id = PSB_RSGX32(PSB_CR_CORE_ID);
465 uint32_t core_rev = PSB_RSGX32(PSB_CR_CORE_REVISION);
466 DRM_INFO("SGX core id = 0x%08x\n", core_id);
467 DRM_INFO("SGX core rev major = 0x%02x, minor = 0x%02x\n",
468 (core_rev & _PSB_CC_REVISION_MAJOR_MASK) >>
469 _PSB_CC_REVISION_MAJOR_SHIFT,
470 (core_rev & _PSB_CC_REVISION_MINOR_MASK) >>
471 _PSB_CC_REVISION_MINOR_SHIFT);
472 DRM_INFO
473 ("SGX core rev maintenance = 0x%02x, designer = 0x%02x\n",
474 (core_rev & _PSB_CC_REVISION_MAINTENANCE_MASK) >>
475 _PSB_CC_REVISION_MAINTENANCE_SHIFT,
476 (core_rev & _PSB_CC_REVISION_DESIGNER_MASK) >>
477 _PSB_CC_REVISION_DESIGNER_SHIFT);
478 }
479
480
481 spin_lock_init(&dev_priv->irqmask_lock);
482
483 tt_pages = (pg->gatt_pages < PSB_TT_PRIV0_PLIMIT) ?
484 pg->gatt_pages : PSB_TT_PRIV0_PLIMIT;
485 tt_start = dev_priv->gatt_free_offset - pg->mmu_gatt_start;
486 tt_pages -= tt_start >> PAGE_SHIFT;
487 /* FIXME: can we kill ta_mem_size ? */
488 dev_priv->sizes.ta_mem_size = 0;
489
490 PSB_WSGX32(0x00000000, PSB_CR_BIF_BANK0);
491 PSB_WSGX32(0x00000000, PSB_CR_BIF_BANK1);
492 PSB_RSGX32(PSB_CR_BIF_BANK1);
493 PSB_WSGX32(PSB_RSGX32(PSB_CR_BIF_CTRL) | _PSB_MMU_ER_MASK,
494 PSB_CR_BIF_CTRL);
495 psb_spank(dev_priv);
496
497 printk(KERN_INFO "TWOD base %08lX\n", (u32) pg->mmu_gatt_start);
498 PSB_WSGX32(pg->mmu_gatt_start, PSB_CR_BIF_TWOD_REQ_BASE);
499
500 return 0;
501 out_err:
502 psb_do_takedown(dev);
503 return ret;
504 }
505
506 static int psb_driver_unload(struct drm_device *dev)
507 {
508 struct drm_psb_private *dev_priv =
509 (struct drm_psb_private *) dev->dev_private;
510
511 /* Kill vblank etc here */
512
513 psb_backlight_exit(); /*writes minimum value to backlight HW reg */
514
515 if (drm_psb_no_fb == 0)
516 psb_modeset_cleanup(dev);
517
518 if (dev_priv) {
519 psb_lid_timer_takedown(dev_priv);
520
521 psb_do_takedown(dev);
522
523
524 if (dev_priv->pf_pd) {
525 psb_mmu_free_pagedir(dev_priv->pf_pd);
526 dev_priv->pf_pd = NULL;
527 }
528 if (dev_priv->mmu) {
529 struct psb_gtt *pg = dev_priv->pg;
530
531 down_read(&pg->sem);
532 psb_mmu_remove_pfn_sequence(
533 psb_mmu_get_default_pd
534 (dev_priv->mmu),
535 pg->mmu_gatt_start,
536 pg->vram_stolen_size >> PAGE_SHIFT);
537 up_read(&pg->sem);
538 psb_mmu_driver_takedown(dev_priv->mmu);
539 dev_priv->mmu = NULL;
540 }
541 psb_gtt_takedown(dev_priv->pg, 1);
542 if (dev_priv->scratch_page) {
543 __free_page(dev_priv->scratch_page);
544 dev_priv->scratch_page = NULL;
545 }
546 if (dev_priv->vdc_reg) {
547 iounmap(dev_priv->vdc_reg);
548 dev_priv->vdc_reg = NULL;
549 }
550 if (dev_priv->sgx_reg) {
551 iounmap(dev_priv->sgx_reg);
552 dev_priv->sgx_reg = NULL;
553 }
554
555 kfree(dev_priv);
556 dev->dev_private = NULL;
557
558 /*destory VBT data*/
559 psb_intel_destroy_bios(dev);
560 }
561
562 gma_power_uninit(dev);
563
564 return 0;
565 }
566
567
568 static int psb_driver_load(struct drm_device *dev, unsigned long chipset)
569 {
570 struct drm_psb_private *dev_priv;
571 unsigned long resource_start;
572 struct psb_gtt *pg;
573 unsigned long irqflags;
574 int ret = -ENOMEM;
575 uint32_t tt_pages;
576
577 dev_priv = kzalloc(sizeof(*dev_priv), GFP_KERNEL);
578 if (dev_priv == NULL)
579 return -ENOMEM;
580
581 if (IS_MRST(dev))
582 dev_priv->num_pipe = 1;
583 else
584 dev_priv->num_pipe = 2;
585
586 dev_priv->dev = dev;
587
588 dev->dev_private = (void *) dev_priv;
589 dev_priv->chipset = chipset;
590
591 PSB_DEBUG_INIT("Mapping MMIO\n");
592 resource_start = pci_resource_start(dev->pdev, PSB_MMIO_RESOURCE);
593
594 dev_priv->vdc_reg =
595 ioremap(resource_start + PSB_VDC_OFFSET, PSB_VDC_SIZE);
596 if (!dev_priv->vdc_reg)
597 goto out_err;
598
599 dev_priv->sgx_reg = ioremap(resource_start + PSB_SGX_OFFSET,
600 PSB_SGX_SIZE);
601
602 if (!dev_priv->sgx_reg)
603 goto out_err;
604
605 if (IS_MRST(dev)) {
606 mrst_get_fuse_settings(dev);
607 mrst_get_vbt_data(dev_priv);
608 mid_get_pci_revID(dev_priv);
609 } else {
610 psb_get_core_freq(dev);
611 psb_intel_opregion_init(dev);
612 psb_intel_init_bios(dev);
613 }
614
615 /* Init OSPM support */
616 gma_power_init(dev);
617
618 ret = -ENOMEM;
619
620 dev_priv->scratch_page = alloc_page(GFP_DMA32 | __GFP_ZERO);
621 if (!dev_priv->scratch_page)
622 goto out_err;
623
624 set_pages_uc(dev_priv->scratch_page, 1);
625
626 dev_priv->pg = psb_gtt_alloc(dev);
627 if (!dev_priv->pg)
628 goto out_err;
629
630 ret = psb_gtt_init(dev_priv->pg, 0);
631 if (ret)
632 goto out_err;
633
634 ret = psb_gtt_mm_init(dev_priv->pg);
635 if (ret)
636 goto out_err;
637
638 dev_priv->mmu = psb_mmu_driver_init((void *)0,
639 drm_psb_trap_pagefaults, 0,
640 dev_priv);
641 if (!dev_priv->mmu)
642 goto out_err;
643
644 pg = dev_priv->pg;
645
646 tt_pages = (pg->gatt_pages < PSB_TT_PRIV0_PLIMIT) ?
647 (pg->gatt_pages) : PSB_TT_PRIV0_PLIMIT;
648
649
650 dev_priv->pf_pd = psb_mmu_alloc_pd(dev_priv->mmu, 1, 0);
651 if (!dev_priv->pf_pd)
652 goto out_err;
653
654 psb_mmu_set_pd_context(psb_mmu_get_default_pd(dev_priv->mmu), 0);
655 psb_mmu_set_pd_context(dev_priv->pf_pd, 1);
656
657 ret = psb_do_init(dev);
658 if (ret)
659 return ret;
660
661 PSB_WSGX32(0x20000000, PSB_CR_PDS_EXEC_BASE);
662 PSB_WSGX32(0x30000000, PSB_CR_BIF_3D_REQ_BASE);
663
664 /* igd_opregion_init(&dev_priv->opregion_dev); */
665 acpi_video_register();
666 if (dev_priv->lid_state)
667 psb_lid_timer_init(dev_priv);
668
669 ret = drm_vblank_init(dev, dev_priv->num_pipe);
670 if (ret)
671 goto out_err;
672
673 /*
674 * Install interrupt handlers prior to powering off SGX or else we will
675 * crash.
676 */
677 dev_priv->vdc_irq_mask = 0;
678 dev_priv->pipestat[0] = 0;
679 dev_priv->pipestat[1] = 0;
680 dev_priv->pipestat[2] = 0;
681 spin_lock_irqsave(&dev_priv->irqmask_lock, irqflags);
682 PSB_WVDC32(0xFFFFFFFF, PSB_HWSTAM);
683 PSB_WVDC32(0x00000000, PSB_INT_ENABLE_R);
684 PSB_WVDC32(0xFFFFFFFF, PSB_INT_MASK_R);
685 spin_unlock_irqrestore(&dev_priv->irqmask_lock, irqflags);
686 if (drm_core_check_feature(dev, DRIVER_MODESET))
687 drm_irq_install(dev);
688
689 dev->vblank_disable_allowed = 1;
690
691 dev->max_vblank_count = 0xffffff; /* only 24 bits of frame count */
692
693 dev->driver->get_vblank_counter = psb_get_vblank_counter;
694
695 if (drm_psb_no_fb == 0) {
696 psb_modeset_init(dev);
697 psb_fbdev_init(dev);
698 drm_kms_helper_poll_init(dev);
699 }
700
701 ret = psb_backlight_init(dev);
702 if (ret)
703 return ret;
704 #if 0
705 /*enable runtime pm at last*/
706 pm_runtime_enable(&dev->pdev->dev);
707 pm_runtime_set_active(&dev->pdev->dev);
708 #endif
709 /*Intel drm driver load is done, continue doing pvr load*/
710 DRM_DEBUG("Pvr driver load\n");
711 return 0;
712 out_err:
713 psb_driver_unload(dev);
714 return ret;
715 }
716
717 int psb_driver_device_is_agp(struct drm_device *dev)
718 {
719 return 0;
720 }
721
722
723 static int psb_vt_leave_ioctl(struct drm_device *dev, void *data,
724 struct drm_file *file_priv)
725 {
726 return 0;
727 }
728
729 static int psb_vt_enter_ioctl(struct drm_device *dev, void *data,
730 struct drm_file *file_priv)
731 {
732 return 0;
733 }
734
735 static int psb_sizes_ioctl(struct drm_device *dev, void *data,
736 struct drm_file *file_priv)
737 {
738 struct drm_psb_private *dev_priv = psb_priv(dev);
739 struct drm_psb_sizes_arg *arg =
740 (struct drm_psb_sizes_arg *) data;
741
742 *arg = dev_priv->sizes;
743 return 0;
744 }
745
746 static int psb_dc_state_ioctl(struct drm_device *dev, void * data,
747 struct drm_file *file_priv)
748 {
749 uint32_t flags;
750 uint32_t obj_id;
751 struct drm_mode_object *obj;
752 struct drm_connector *connector;
753 struct drm_crtc *crtc;
754 struct drm_psb_dc_state_arg *arg =
755 (struct drm_psb_dc_state_arg *)data;
756
757 flags = arg->flags;
758 obj_id = arg->obj_id;
759
760 if (flags & PSB_DC_CRTC_MASK) {
761 obj = drm_mode_object_find(dev, obj_id,
762 DRM_MODE_OBJECT_CRTC);
763 if (!obj) {
764 DRM_DEBUG("Invalid CRTC object.\n");
765 return -EINVAL;
766 }
767
768 crtc = obj_to_crtc(obj);
769
770 mutex_lock(&dev->mode_config.mutex);
771 if (drm_helper_crtc_in_use(crtc)) {
772 if (flags & PSB_DC_CRTC_SAVE)
773 crtc->funcs->save(crtc);
774 else
775 crtc->funcs->restore(crtc);
776 }
777 mutex_unlock(&dev->mode_config.mutex);
778
779 return 0;
780 } else if (flags & PSB_DC_OUTPUT_MASK) {
781 obj = drm_mode_object_find(dev, obj_id,
782 DRM_MODE_OBJECT_CONNECTOR);
783 if (!obj) {
784 DRM_DEBUG("Invalid connector id.\n");
785 return -EINVAL;
786 }
787
788 connector = obj_to_connector(obj);
789 if (flags & PSB_DC_OUTPUT_SAVE)
790 connector->funcs->save(connector);
791 else
792 connector->funcs->restore(connector);
793
794 return 0;
795 }
796
797 DRM_DEBUG("Bad flags 0x%x\n", flags);
798 return -EINVAL;
799 }
800
801 static int psb_dpst_bl_ioctl(struct drm_device *dev, void *data,
802 struct drm_file *file_priv)
803 {
804 struct drm_psb_private *dev_priv = psb_priv(dev);
805 uint32_t *arg = data;
806 struct backlight_device bd;
807 dev_priv->blc_adj2 = *arg;
808
809 #ifdef CONFIG_BACKLIGHT_CLASS_DEVICE
810 bd.props.brightness = psb_get_brightness(&bd);
811 psb_set_brightness(&bd);
812 #endif
813 return 0;
814 }
815
816 static int psb_adb_ioctl(struct drm_device *dev, void *data,
817 struct drm_file *file_priv)
818 {
819 struct drm_psb_private *dev_priv = psb_priv(dev);
820 uint32_t *arg = data;
821 struct backlight_device bd;
822 dev_priv->blc_adj1 = *arg;
823
824 #ifdef CONFIG_BACKLIGHT_CLASS_DEVICE
825 bd.props.brightness = psb_get_brightness(&bd);
826 psb_set_brightness(&bd);
827 #endif
828 return 0;
829 }
830
831 /* return the current mode to the dpst module */
832 static int psb_dpst_ioctl(struct drm_device *dev, void *data,
833 struct drm_file *file_priv)
834 {
835 struct drm_psb_private *dev_priv = psb_priv(dev);
836 uint32_t *arg = data;
837 uint32_t x;
838 uint32_t y;
839 uint32_t reg;
840
841 if (!gma_power_begin(dev, 0))
842 return 0;
843
844 reg = PSB_RVDC32(PIPEASRC);
845
846 gma_power_end(dev);
847
848 /* horizontal is the left 16 bits */
849 x = reg >> 16;
850 /* vertical is the right 16 bits */
851 y = reg & 0x0000ffff;
852
853 /* the values are the image size minus one */
854 x++;
855 y++;
856
857 *arg = (x << 16) | y;
858
859 return 0;
860 }
861 static int psb_gamma_ioctl(struct drm_device *dev, void *data,
862 struct drm_file *file_priv)
863 {
864 struct drm_psb_dpst_lut_arg *lut_arg = data;
865 struct drm_mode_object *obj;
866 struct drm_crtc *crtc;
867 struct drm_connector *connector;
868 struct psb_intel_crtc *psb_intel_crtc;
869 int i = 0;
870 int32_t obj_id;
871
872 obj_id = lut_arg->output_id;
873 obj = drm_mode_object_find(dev, obj_id, DRM_MODE_OBJECT_CONNECTOR);
874 if (!obj) {
875 DRM_DEBUG("Invalid Connector object.\n");
876 return -EINVAL;
877 }
878
879 connector = obj_to_connector(obj);
880 crtc = connector->encoder->crtc;
881 psb_intel_crtc = to_psb_intel_crtc(crtc);
882
883 for (i = 0; i < 256; i++)
884 psb_intel_crtc->lut_adj[i] = lut_arg->lut[i];
885
886 psb_intel_crtc_load_lut(crtc);
887
888 return 0;
889 }
890
891 static int psb_mode_operation_ioctl(struct drm_device *dev, void *data,
892 struct drm_file *file_priv)
893 {
894 uint32_t obj_id;
895 uint16_t op;
896 struct drm_mode_modeinfo *umode;
897 struct drm_display_mode *mode = NULL;
898 struct drm_psb_mode_operation_arg *arg;
899 struct drm_mode_object *obj;
900 struct drm_connector *connector;
901 struct drm_framebuffer *drm_fb;
902 struct psb_framebuffer *psb_fb;
903 struct drm_connector_helper_funcs *connector_funcs;
904 int ret = 0;
905 int resp = MODE_OK;
906 struct drm_psb_private *dev_priv = psb_priv(dev);
907
908 arg = (struct drm_psb_mode_operation_arg *)data;
909 obj_id = arg->obj_id;
910 op = arg->operation;
911
912 switch (op) {
913 case PSB_MODE_OPERATION_SET_DC_BASE:
914 obj = drm_mode_object_find(dev, obj_id, DRM_MODE_OBJECT_FB);
915 if (!obj) {
916 DRM_ERROR("Invalid FB id %d\n", obj_id);
917 return -EINVAL;
918 }
919
920 drm_fb = obj_to_fb(obj);
921 psb_fb = to_psb_fb(drm_fb);
922
923 if (gma_power_begin(dev, 0)) {
924 REG_WRITE(DSPASURF, psb_fb->offset);
925 REG_READ(DSPASURF);
926 gma_power_end(dev);
927 } else {
928 dev_priv->saveDSPASURF = psb_fb->offset;
929 }
930
931 return 0;
932 case PSB_MODE_OPERATION_MODE_VALID:
933 umode = &arg->mode;
934
935 mutex_lock(&dev->mode_config.mutex);
936
937 obj = drm_mode_object_find(dev, obj_id,
938 DRM_MODE_OBJECT_CONNECTOR);
939 if (!obj) {
940 ret = -EINVAL;
941 goto mode_op_out;
942 }
943
944 connector = obj_to_connector(obj);
945
946 mode = drm_mode_create(dev);
947 if (!mode) {
948 ret = -ENOMEM;
949 goto mode_op_out;
950 }
951
952 /* drm_crtc_convert_umode(mode, umode); */
953 {
954 mode->clock = umode->clock;
955 mode->hdisplay = umode->hdisplay;
956 mode->hsync_start = umode->hsync_start;
957 mode->hsync_end = umode->hsync_end;
958 mode->htotal = umode->htotal;
959 mode->hskew = umode->hskew;
960 mode->vdisplay = umode->vdisplay;
961 mode->vsync_start = umode->vsync_start;
962 mode->vsync_end = umode->vsync_end;
963 mode->vtotal = umode->vtotal;
964 mode->vscan = umode->vscan;
965 mode->vrefresh = umode->vrefresh;
966 mode->flags = umode->flags;
967 mode->type = umode->type;
968 strncpy(mode->name, umode->name, DRM_DISPLAY_MODE_LEN);
969 mode->name[DRM_DISPLAY_MODE_LEN-1] = 0;
970 }
971
972 connector_funcs = (struct drm_connector_helper_funcs *)
973 connector->helper_private;
974
975 if (connector_funcs->mode_valid) {
976 resp = connector_funcs->mode_valid(connector, mode);
977 arg->data = (void *)resp;
978 }
979
980 /*do some clean up work*/
981 if (mode)
982 drm_mode_destroy(dev, mode);
983 mode_op_out:
984 mutex_unlock(&dev->mode_config.mutex);
985 return ret;
986
987 default:
988 DRM_DEBUG("Unsupported psb mode operation");
989 return -EOPNOTSUPP;
990 }
991
992 return 0;
993 }
994
995 static int psb_stolen_memory_ioctl(struct drm_device *dev, void *data,
996 struct drm_file *file_priv)
997 {
998 struct drm_psb_private *dev_priv = psb_priv(dev);
999 struct drm_psb_stolen_memory_arg *arg = data;
1000
1001 arg->base = dev_priv->pg->stolen_base;
1002 arg->size = dev_priv->pg->vram_stolen_size;
1003
1004 return 0;
1005 }
1006
1007 static int psb_register_rw_ioctl(struct drm_device *dev, void *data,
1008 struct drm_file *file_priv)
1009 {
1010 struct drm_psb_private *dev_priv = psb_priv(dev);
1011 struct drm_psb_register_rw_arg *arg = data;
1012 bool usage = arg->b_force_hw_on ? true : false;
1013
1014 if (arg->display_write_mask != 0) {
1015 if (gma_power_begin(dev, usage)) {
1016 if (arg->display_write_mask & REGRWBITS_PFIT_CONTROLS)
1017 PSB_WVDC32(arg->display.pfit_controls,
1018 PFIT_CONTROL);
1019 if (arg->display_write_mask &
1020 REGRWBITS_PFIT_AUTOSCALE_RATIOS)
1021 PSB_WVDC32(arg->display.pfit_autoscale_ratios,
1022 PFIT_AUTO_RATIOS);
1023 if (arg->display_write_mask &
1024 REGRWBITS_PFIT_PROGRAMMED_SCALE_RATIOS)
1025 PSB_WVDC32(
1026 arg->display.pfit_programmed_scale_ratios,
1027 PFIT_PGM_RATIOS);
1028 if (arg->display_write_mask & REGRWBITS_PIPEASRC)
1029 PSB_WVDC32(arg->display.pipeasrc,
1030 PIPEASRC);
1031 if (arg->display_write_mask & REGRWBITS_PIPEBSRC)
1032 PSB_WVDC32(arg->display.pipebsrc,
1033 PIPEBSRC);
1034 if (arg->display_write_mask & REGRWBITS_VTOTAL_A)
1035 PSB_WVDC32(arg->display.vtotal_a,
1036 VTOTAL_A);
1037 if (arg->display_write_mask & REGRWBITS_VTOTAL_B)
1038 PSB_WVDC32(arg->display.vtotal_b,
1039 VTOTAL_B);
1040 gma_power_end(dev);
1041 } else {
1042 if (arg->display_write_mask & REGRWBITS_PFIT_CONTROLS)
1043 dev_priv->savePFIT_CONTROL =
1044 arg->display.pfit_controls;
1045 if (arg->display_write_mask &
1046 REGRWBITS_PFIT_AUTOSCALE_RATIOS)
1047 dev_priv->savePFIT_AUTO_RATIOS =
1048 arg->display.pfit_autoscale_ratios;
1049 if (arg->display_write_mask &
1050 REGRWBITS_PFIT_PROGRAMMED_SCALE_RATIOS)
1051 dev_priv->savePFIT_PGM_RATIOS =
1052 arg->display.pfit_programmed_scale_ratios;
1053 if (arg->display_write_mask & REGRWBITS_PIPEASRC)
1054 dev_priv->savePIPEASRC = arg->display.pipeasrc;
1055 if (arg->display_write_mask & REGRWBITS_PIPEBSRC)
1056 dev_priv->savePIPEBSRC = arg->display.pipebsrc;
1057 if (arg->display_write_mask & REGRWBITS_VTOTAL_A)
1058 dev_priv->saveVTOTAL_A = arg->display.vtotal_a;
1059 if (arg->display_write_mask & REGRWBITS_VTOTAL_B)
1060 dev_priv->saveVTOTAL_B = arg->display.vtotal_b;
1061 }
1062 }
1063
1064 if (arg->display_read_mask != 0) {
1065 if (gma_power_begin(dev, usage)) {
1066 if (arg->display_read_mask &
1067 REGRWBITS_PFIT_CONTROLS)
1068 arg->display.pfit_controls =
1069 PSB_RVDC32(PFIT_CONTROL);
1070 if (arg->display_read_mask &
1071 REGRWBITS_PFIT_AUTOSCALE_RATIOS)
1072 arg->display.pfit_autoscale_ratios =
1073 PSB_RVDC32(PFIT_AUTO_RATIOS);
1074 if (arg->display_read_mask &
1075 REGRWBITS_PFIT_PROGRAMMED_SCALE_RATIOS)
1076 arg->display.pfit_programmed_scale_ratios =
1077 PSB_RVDC32(PFIT_PGM_RATIOS);
1078 if (arg->display_read_mask & REGRWBITS_PIPEASRC)
1079 arg->display.pipeasrc = PSB_RVDC32(PIPEASRC);
1080 if (arg->display_read_mask & REGRWBITS_PIPEBSRC)
1081 arg->display.pipebsrc = PSB_RVDC32(PIPEBSRC);
1082 if (arg->display_read_mask & REGRWBITS_VTOTAL_A)
1083 arg->display.vtotal_a = PSB_RVDC32(VTOTAL_A);
1084 if (arg->display_read_mask & REGRWBITS_VTOTAL_B)
1085 arg->display.vtotal_b = PSB_RVDC32(VTOTAL_B);
1086 gma_power_end(dev);
1087 } else {
1088 if (arg->display_read_mask &
1089 REGRWBITS_PFIT_CONTROLS)
1090 arg->display.pfit_controls =
1091 dev_priv->savePFIT_CONTROL;
1092 if (arg->display_read_mask &
1093 REGRWBITS_PFIT_AUTOSCALE_RATIOS)
1094 arg->display.pfit_autoscale_ratios =
1095 dev_priv->savePFIT_AUTO_RATIOS;
1096 if (arg->display_read_mask &
1097 REGRWBITS_PFIT_PROGRAMMED_SCALE_RATIOS)
1098 arg->display.pfit_programmed_scale_ratios =
1099 dev_priv->savePFIT_PGM_RATIOS;
1100 if (arg->display_read_mask & REGRWBITS_PIPEASRC)
1101 arg->display.pipeasrc = dev_priv->savePIPEASRC;
1102 if (arg->display_read_mask & REGRWBITS_PIPEBSRC)
1103 arg->display.pipebsrc = dev_priv->savePIPEBSRC;
1104 if (arg->display_read_mask & REGRWBITS_VTOTAL_A)
1105 arg->display.vtotal_a = dev_priv->saveVTOTAL_A;
1106 if (arg->display_read_mask & REGRWBITS_VTOTAL_B)
1107 arg->display.vtotal_b = dev_priv->saveVTOTAL_B;
1108 }
1109 }
1110
1111 if (arg->overlay_write_mask != 0) {
1112 if (gma_power_begin(dev, usage)) {
1113 if (arg->overlay_write_mask & OV_REGRWBITS_OGAM_ALL) {
1114 PSB_WVDC32(arg->overlay.OGAMC5, OV_OGAMC5);
1115 PSB_WVDC32(arg->overlay.OGAMC4, OV_OGAMC4);
1116 PSB_WVDC32(arg->overlay.OGAMC3, OV_OGAMC3);
1117 PSB_WVDC32(arg->overlay.OGAMC2, OV_OGAMC2);
1118 PSB_WVDC32(arg->overlay.OGAMC1, OV_OGAMC1);
1119 PSB_WVDC32(arg->overlay.OGAMC0, OV_OGAMC0);
1120 }
1121 if (arg->overlay_write_mask & OVC_REGRWBITS_OGAM_ALL) {
1122 PSB_WVDC32(arg->overlay.OGAMC5, OVC_OGAMC5);
1123 PSB_WVDC32(arg->overlay.OGAMC4, OVC_OGAMC4);
1124 PSB_WVDC32(arg->overlay.OGAMC3, OVC_OGAMC3);
1125 PSB_WVDC32(arg->overlay.OGAMC2, OVC_OGAMC2);
1126 PSB_WVDC32(arg->overlay.OGAMC1, OVC_OGAMC1);
1127 PSB_WVDC32(arg->overlay.OGAMC0, OVC_OGAMC0);
1128 }
1129
1130 if (arg->overlay_write_mask & OV_REGRWBITS_OVADD) {
1131 PSB_WVDC32(arg->overlay.OVADD, OV_OVADD);
1132
1133 if (arg->overlay.b_wait_vblank) {
1134 /* Wait for 20ms.*/
1135 unsigned long vblank_timeout = jiffies
1136 + HZ/50;
1137 uint32_t temp;
1138 while (time_before_eq(jiffies,
1139 vblank_timeout)) {
1140 temp = PSB_RVDC32(OV_DOVASTA);
1141 if ((temp & (0x1 << 31)) != 0)
1142 break;
1143 cpu_relax();
1144 }
1145 }
1146 }
1147 if (arg->overlay_write_mask & OVC_REGRWBITS_OVADD) {
1148 PSB_WVDC32(arg->overlay.OVADD, OVC_OVADD);
1149 if (arg->overlay.b_wait_vblank) {
1150 /* Wait for 20ms.*/
1151 unsigned long vblank_timeout =
1152 jiffies + HZ/50;
1153 uint32_t temp;
1154 while (time_before_eq(jiffies,
1155 vblank_timeout)) {
1156 temp = PSB_RVDC32(OVC_DOVCSTA);
1157 if ((temp & (0x1 << 31)) != 0)
1158 break;
1159 cpu_relax();
1160 }
1161 }
1162 }
1163 gma_power_end(dev);
1164 } else {
1165 if (arg->overlay_write_mask & OV_REGRWBITS_OGAM_ALL) {
1166 dev_priv->saveOV_OGAMC5 = arg->overlay.OGAMC5;
1167 dev_priv->saveOV_OGAMC4 = arg->overlay.OGAMC4;
1168 dev_priv->saveOV_OGAMC3 = arg->overlay.OGAMC3;
1169 dev_priv->saveOV_OGAMC2 = arg->overlay.OGAMC2;
1170 dev_priv->saveOV_OGAMC1 = arg->overlay.OGAMC1;
1171 dev_priv->saveOV_OGAMC0 = arg->overlay.OGAMC0;
1172 }
1173 if (arg->overlay_write_mask & OVC_REGRWBITS_OGAM_ALL) {
1174 dev_priv->saveOVC_OGAMC5 = arg->overlay.OGAMC5;
1175 dev_priv->saveOVC_OGAMC4 = arg->overlay.OGAMC4;
1176 dev_priv->saveOVC_OGAMC3 = arg->overlay.OGAMC3;
1177 dev_priv->saveOVC_OGAMC2 = arg->overlay.OGAMC2;
1178 dev_priv->saveOVC_OGAMC1 = arg->overlay.OGAMC1;
1179 dev_priv->saveOVC_OGAMC0 = arg->overlay.OGAMC0;
1180 }
1181 if (arg->overlay_write_mask & OV_REGRWBITS_OVADD)
1182 dev_priv->saveOV_OVADD = arg->overlay.OVADD;
1183 if (arg->overlay_write_mask & OVC_REGRWBITS_OVADD)
1184 dev_priv->saveOVC_OVADD = arg->overlay.OVADD;
1185 }
1186 }
1187
1188 if (arg->overlay_read_mask != 0) {
1189 if (gma_power_begin(dev, usage)) {
1190 if (arg->overlay_read_mask & OV_REGRWBITS_OGAM_ALL) {
1191 arg->overlay.OGAMC5 = PSB_RVDC32(OV_OGAMC5);
1192 arg->overlay.OGAMC4 = PSB_RVDC32(OV_OGAMC4);
1193 arg->overlay.OGAMC3 = PSB_RVDC32(OV_OGAMC3);
1194 arg->overlay.OGAMC2 = PSB_RVDC32(OV_OGAMC2);
1195 arg->overlay.OGAMC1 = PSB_RVDC32(OV_OGAMC1);
1196 arg->overlay.OGAMC0 = PSB_RVDC32(OV_OGAMC0);
1197 }
1198 if (arg->overlay_read_mask & OVC_REGRWBITS_OGAM_ALL) {
1199 arg->overlay.OGAMC5 = PSB_RVDC32(OVC_OGAMC5);
1200 arg->overlay.OGAMC4 = PSB_RVDC32(OVC_OGAMC4);
1201 arg->overlay.OGAMC3 = PSB_RVDC32(OVC_OGAMC3);
1202 arg->overlay.OGAMC2 = PSB_RVDC32(OVC_OGAMC2);
1203 arg->overlay.OGAMC1 = PSB_RVDC32(OVC_OGAMC1);
1204 arg->overlay.OGAMC0 = PSB_RVDC32(OVC_OGAMC0);
1205 }
1206 if (arg->overlay_read_mask & OV_REGRWBITS_OVADD)
1207 arg->overlay.OVADD = PSB_RVDC32(OV_OVADD);
1208 if (arg->overlay_read_mask & OVC_REGRWBITS_OVADD)
1209 arg->overlay.OVADD = PSB_RVDC32(OVC_OVADD);
1210 gma_power_end(dev);
1211 } else {
1212 if (arg->overlay_read_mask & OV_REGRWBITS_OGAM_ALL) {
1213 arg->overlay.OGAMC5 = dev_priv->saveOV_OGAMC5;
1214 arg->overlay.OGAMC4 = dev_priv->saveOV_OGAMC4;
1215 arg->overlay.OGAMC3 = dev_priv->saveOV_OGAMC3;
1216 arg->overlay.OGAMC2 = dev_priv->saveOV_OGAMC2;
1217 arg->overlay.OGAMC1 = dev_priv->saveOV_OGAMC1;
1218 arg->overlay.OGAMC0 = dev_priv->saveOV_OGAMC0;
1219 }
1220 if (arg->overlay_read_mask & OVC_REGRWBITS_OGAM_ALL) {
1221 arg->overlay.OGAMC5 = dev_priv->saveOVC_OGAMC5;
1222 arg->overlay.OGAMC4 = dev_priv->saveOVC_OGAMC4;
1223 arg->overlay.OGAMC3 = dev_priv->saveOVC_OGAMC3;
1224 arg->overlay.OGAMC2 = dev_priv->saveOVC_OGAMC2;
1225 arg->overlay.OGAMC1 = dev_priv->saveOVC_OGAMC1;
1226 arg->overlay.OGAMC0 = dev_priv->saveOVC_OGAMC0;
1227 }
1228 if (arg->overlay_read_mask & OV_REGRWBITS_OVADD)
1229 arg->overlay.OVADD = dev_priv->saveOV_OVADD;
1230 if (arg->overlay_read_mask & OVC_REGRWBITS_OVADD)
1231 arg->overlay.OVADD = dev_priv->saveOVC_OVADD;
1232 }
1233 }
1234
1235 if (arg->sprite_enable_mask != 0) {
1236 if (gma_power_begin(dev, usage)) {
1237 PSB_WVDC32(0x1F3E, DSPARB);
1238 PSB_WVDC32(arg->sprite.dspa_control
1239 | PSB_RVDC32(DSPACNTR), DSPACNTR);
1240 PSB_WVDC32(arg->sprite.dspa_key_value, DSPAKEYVAL);
1241 PSB_WVDC32(arg->sprite.dspa_key_mask, DSPAKEYMASK);
1242 PSB_WVDC32(PSB_RVDC32(DSPASURF), DSPASURF);
1243 PSB_RVDC32(DSPASURF);
1244 PSB_WVDC32(arg->sprite.dspc_control, DSPCCNTR);
1245 PSB_WVDC32(arg->sprite.dspc_stride, DSPCSTRIDE);
1246 PSB_WVDC32(arg->sprite.dspc_position, DSPCPOS);
1247 PSB_WVDC32(arg->sprite.dspc_linear_offset, DSPCLINOFF);
1248 PSB_WVDC32(arg->sprite.dspc_size, DSPCSIZE);
1249 PSB_WVDC32(arg->sprite.dspc_surface, DSPCSURF);
1250 PSB_RVDC32(DSPCSURF);
1251 gma_power_end(dev);
1252 }
1253 }
1254
1255 if (arg->sprite_disable_mask != 0) {
1256 if (gma_power_begin(dev, usage)) {
1257 PSB_WVDC32(0x3F3E, DSPARB);
1258 PSB_WVDC32(0x0, DSPCCNTR);
1259 PSB_WVDC32(arg->sprite.dspc_surface, DSPCSURF);
1260 PSB_RVDC32(DSPCSURF);
1261 gma_power_end(dev);
1262 }
1263 }
1264
1265 if (arg->subpicture_enable_mask != 0) {
1266 if (gma_power_begin(dev, usage)) {
1267 uint32_t temp;
1268 if (arg->subpicture_enable_mask & REGRWBITS_DSPACNTR) {
1269 temp = PSB_RVDC32(DSPACNTR);
1270 temp &= ~DISPPLANE_PIXFORMAT_MASK;
1271 temp &= ~DISPPLANE_BOTTOM;
1272 temp |= DISPPLANE_32BPP;
1273 PSB_WVDC32(temp, DSPACNTR);
1274
1275 temp = PSB_RVDC32(DSPABASE);
1276 PSB_WVDC32(temp, DSPABASE);
1277 PSB_RVDC32(DSPABASE);
1278 temp = PSB_RVDC32(DSPASURF);
1279 PSB_WVDC32(temp, DSPASURF);
1280 PSB_RVDC32(DSPASURF);
1281 }
1282 if (arg->subpicture_enable_mask & REGRWBITS_DSPBCNTR) {
1283 temp = PSB_RVDC32(DSPBCNTR);
1284 temp &= ~DISPPLANE_PIXFORMAT_MASK;
1285 temp &= ~DISPPLANE_BOTTOM;
1286 temp |= DISPPLANE_32BPP;
1287 PSB_WVDC32(temp, DSPBCNTR);
1288
1289 temp = PSB_RVDC32(DSPBBASE);
1290 PSB_WVDC32(temp, DSPBBASE);
1291 PSB_RVDC32(DSPBBASE);
1292 temp = PSB_RVDC32(DSPBSURF);
1293 PSB_WVDC32(temp, DSPBSURF);
1294 PSB_RVDC32(DSPBSURF);
1295 }
1296 if (arg->subpicture_enable_mask & REGRWBITS_DSPCCNTR) {
1297 temp = PSB_RVDC32(DSPCCNTR);
1298 temp &= ~DISPPLANE_PIXFORMAT_MASK;
1299 temp &= ~DISPPLANE_BOTTOM;
1300 temp |= DISPPLANE_32BPP;
1301 PSB_WVDC32(temp, DSPCCNTR);
1302
1303 temp = PSB_RVDC32(DSPCBASE);
1304 PSB_WVDC32(temp, DSPCBASE);
1305 PSB_RVDC32(DSPCBASE);
1306 temp = PSB_RVDC32(DSPCSURF);
1307 PSB_WVDC32(temp, DSPCSURF);
1308 PSB_RVDC32(DSPCSURF);
1309 }
1310 gma_power_end(dev);
1311 }
1312 }
1313
1314 if (arg->subpicture_disable_mask != 0) {
1315 if (gma_power_begin(dev, usage)) {
1316 uint32_t temp;
1317 if (arg->subpicture_disable_mask & REGRWBITS_DSPACNTR) {
1318 temp = PSB_RVDC32(DSPACNTR);
1319 temp &= ~DISPPLANE_PIXFORMAT_MASK;
1320 temp |= DISPPLANE_32BPP_NO_ALPHA;
1321 PSB_WVDC32(temp, DSPACNTR);
1322
1323 temp = PSB_RVDC32(DSPABASE);
1324 PSB_WVDC32(temp, DSPABASE);
1325 PSB_RVDC32(DSPABASE);
1326 temp = PSB_RVDC32(DSPASURF);
1327 PSB_WVDC32(temp, DSPASURF);
1328 PSB_RVDC32(DSPASURF);
1329 }
1330 if (arg->subpicture_disable_mask & REGRWBITS_DSPBCNTR) {
1331 temp = PSB_RVDC32(DSPBCNTR);
1332 temp &= ~DISPPLANE_PIXFORMAT_MASK;
1333 temp |= DISPPLANE_32BPP_NO_ALPHA;
1334 PSB_WVDC32(temp, DSPBCNTR);
1335
1336 temp = PSB_RVDC32(DSPBBASE);
1337 PSB_WVDC32(temp, DSPBBASE);
1338 PSB_RVDC32(DSPBBASE);
1339 temp = PSB_RVDC32(DSPBSURF);
1340 PSB_WVDC32(temp, DSPBSURF);
1341 PSB_RVDC32(DSPBSURF);
1342 }
1343 if (arg->subpicture_disable_mask & REGRWBITS_DSPCCNTR) {
1344 temp = PSB_RVDC32(DSPCCNTR);
1345 temp &= ~DISPPLANE_PIXFORMAT_MASK;
1346 temp |= DISPPLANE_32BPP_NO_ALPHA;
1347 PSB_WVDC32(temp, DSPCCNTR);
1348
1349 temp = PSB_RVDC32(DSPCBASE);
1350 PSB_WVDC32(temp, DSPCBASE);
1351 PSB_RVDC32(DSPCBASE);
1352 temp = PSB_RVDC32(DSPCSURF);
1353 PSB_WVDC32(temp, DSPCSURF);
1354 PSB_RVDC32(DSPCSURF);
1355 }
1356 gma_power_end(dev);
1357 }
1358 }
1359
1360 return 0;
1361 }
1362
1363 /* always available as we are SIGIO'd */
1364 static unsigned int psb_poll(struct file *filp,
1365 struct poll_table_struct *wait)
1366 {
1367 return POLLIN | POLLRDNORM;
1368 }
1369
1370 /* Not sure what we will need yet - in the PVR driver this disappears into
1371 a tangle of abstracted handlers and per process crap */
1372
1373 struct psb_priv {
1374 int dummy;
1375 };
1376
1377 static int psb_driver_open(struct drm_device *dev, struct drm_file *priv)
1378 {
1379 struct psb_priv *psb = kzalloc(sizeof(struct psb_priv), GFP_KERNEL);
1380 if (psb == NULL)
1381 return -ENOMEM;
1382 priv->driver_priv = psb;
1383 DRM_DEBUG("\n");
1384 /*return PVRSRVOpen(dev, priv);*/
1385 return 0;
1386 }
1387
1388 static void psb_driver_close(struct drm_device *dev, struct drm_file *priv)
1389 {
1390 kfree(priv->driver_priv);
1391 priv->driver_priv = NULL;
1392 }
1393
1394 static long psb_unlocked_ioctl(struct file *filp, unsigned int cmd,
1395 unsigned long arg)
1396 {
1397 struct drm_file *file_priv = filp->private_data;
1398 struct drm_device *dev = file_priv->minor->dev;
1399 struct drm_psb_private *dev_priv = dev->dev_private;
1400 static unsigned int runtime_allowed;
1401 unsigned int nr = DRM_IOCTL_NR(cmd);
1402
1403 DRM_DEBUG("cmd = %x, nr = %x\n", cmd, nr);
1404
1405 if (runtime_allowed == 1 && dev_priv->is_lvds_on) {
1406 runtime_allowed++;
1407 pm_runtime_allow(&dev->pdev->dev);
1408 dev_priv->rpm_enabled = 1;
1409 }
1410 /*
1411 * The driver private ioctls should be thread-safe.
1412 */
1413
1414 if ((nr >= DRM_COMMAND_BASE) && (nr < DRM_COMMAND_END)
1415 && (nr < DRM_COMMAND_BASE + dev->driver->num_ioctls)) {
1416 struct drm_ioctl_desc *ioctl =
1417 &psb_ioctls[nr - DRM_COMMAND_BASE];
1418
1419 if (unlikely(ioctl->cmd != cmd)) {
1420 DRM_ERROR(
1421 "Invalid drm cmnd %d ioctl->cmd %x, cmd %x\n",
1422 nr - DRM_COMMAND_BASE, ioctl->cmd, cmd);
1423 return -EINVAL;
1424 }
1425
1426 return drm_ioctl(filp, cmd, arg);
1427 }
1428 /*
1429 * Not all old drm ioctls are thread-safe.
1430 */
1431
1432 return drm_ioctl(filp, cmd, arg);
1433 }
1434
1435
1436 /* When a client dies:
1437 * - Check for and clean up flipped page state
1438 */
1439 void psb_driver_preclose(struct drm_device *dev, struct drm_file *priv)
1440 {
1441 }
1442
1443 static void psb_remove(struct pci_dev *pdev)
1444 {
1445 struct drm_device *dev = pci_get_drvdata(pdev);
1446 drm_put_dev(dev);
1447 }
1448
1449 static int psb_open(struct inode *inode, struct file *filp)
1450 {
1451 return 0;
1452 }
1453
1454 static int psb_release(struct inode *inode, struct file *filp)
1455 {
1456 return 0;
1457 }
1458
1459
1460 static const struct dev_pm_ops psb_pm_ops = {
1461 .runtime_suspend = psb_runtime_suspend,
1462 .runtime_resume = psb_runtime_resume,
1463 .runtime_idle = psb_runtime_idle,
1464 };
1465
1466 static struct drm_driver driver = {
1467 .driver_features = DRIVER_HAVE_IRQ | DRIVER_IRQ_SHARED | \
1468 DRIVER_IRQ_VBL | DRIVER_MODESET,
1469 .load = psb_driver_load,
1470 .unload = psb_driver_unload,
1471
1472 .ioctls = psb_ioctls,
1473 .num_ioctls = DRM_ARRAY_SIZE(psb_ioctls),
1474 .device_is_agp = psb_driver_device_is_agp,
1475 .irq_preinstall = psb_irq_preinstall,
1476 .irq_postinstall = psb_irq_postinstall,
1477 .irq_uninstall = psb_irq_uninstall,
1478 .irq_handler = psb_irq_handler,
1479 .enable_vblank = psb_enable_vblank,
1480 .disable_vblank = psb_disable_vblank,
1481 .get_vblank_counter = psb_get_vblank_counter,
1482 .firstopen = NULL,
1483 .lastclose = psb_lastclose,
1484 .open = psb_driver_open,
1485 .postclose = psb_driver_close,
1486 #if 0 /* ACFIXME */
1487 .get_map_ofs = drm_core_get_map_ofs,
1488 .get_reg_ofs = drm_core_get_reg_ofs,
1489 .proc_init = psb_proc_init,
1490 .proc_cleanup = psb_proc_cleanup,
1491 #endif
1492 .preclose = psb_driver_preclose,
1493 .fops = {
1494 .owner = THIS_MODULE,
1495 .open = psb_open,
1496 .release = psb_release,
1497 .unlocked_ioctl = psb_unlocked_ioctl,
1498 /* .mmap = psb_mmap, */
1499 .poll = psb_poll,
1500 .fasync = drm_fasync,
1501 .read = drm_read,
1502 },
1503 .name = DRIVER_NAME,
1504 .desc = DRIVER_DESC,
1505 .date = PSB_DRM_DRIVER_DATE,
1506 .major = PSB_DRM_DRIVER_MAJOR,
1507 .minor = PSB_DRM_DRIVER_MINOR,
1508 .patchlevel = PSB_DRM_DRIVER_PATCHLEVEL
1509 };
1510
1511 static struct pci_driver psb_pci_driver = {
1512 .name = DRIVER_NAME,
1513 .id_table = pciidlist,
1514 .resume = gma_power_resume,
1515 .suspend = gma_power_suspend,
1516 .probe = psb_probe,
1517 .remove = psb_remove,
1518 #ifdef CONFIG_PM
1519 .driver.pm = &psb_pm_ops,
1520 #endif
1521 };
1522
1523 static int psb_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
1524 {
1525 /* MLD Added this from Inaky's patch */
1526 if (pci_enable_msi(pdev))
1527 DRM_ERROR("Enable MSI failed!\n");
1528 return drm_get_pci_dev(pdev, ent, &driver);
1529 }
1530
1531 static int __init psb_init(void)
1532 {
1533 return drm_pci_init(&driver, &psb_pci_driver);
1534 }
1535
1536 static void __exit psb_exit(void)
1537 {
1538 drm_pci_exit(&driver, &psb_pci_driver);
1539 }
1540
1541 late_initcall(psb_init);
1542 module_exit(psb_exit);
1543
1544 MODULE_AUTHOR(DRIVER_AUTHOR);
1545 MODULE_DESCRIPTION(DRIVER_DESC);
1546 MODULE_LICENSE("GPL");
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