arch/arm/boot/dts/atlas6.dtsi

   1 /*
   2  * DTS file for CSR SiRFatlas6 SoC
   3  *
   4  * Copyright (c) 2012 Cambridge Silicon Radio Limited, a CSR plc group company.
   5  *
   6  * Licensed under GPLv2 or later.
   7  */
   8
   9 /include/ "skeleton.dtsi"
  10 / {
  11         compatible = "sirf,atlas6";
  12         #address-cells = <1>;
  13         #size-cells = <1>;
  14         interrupt-parent = <&intc>;
  15
  16         cpus {
  17                 #address-cells = <1>;
  18                 #size-cells = <0>;
  19
  20                 cpu@0 {
  21                         reg = <0x0>;
  22                         d-cache-line-size = <32>;
  23                         i-cache-line-size = <32>;
  24                         d-cache-size = <32768>;
  25                         i-cache-size = <32768>;
  26                         /* from bootloader */
  27                         timebase-frequency = <0>;
  28                         bus-frequency = <0>;
  29                         clock-frequency = <0>;
  30                 };
  31         };
  32
  33         axi {
  34                 compatible = "simple-bus";
  35                 #address-cells = <1>;
  36                 #size-cells = <1>;
  37                 ranges = <0x40000000 0x40000000 0x80000000>;
  38
  39                 intc: interrupt-controller@80020000 {
  40                         #interrupt-cells = <1>;
  41                         interrupt-controller;
  42                         compatible = "sirf,prima2-intc";
  43                         reg = <0x80020000 0x1000>;
  44                 };
  45
  46                 sys-iobg {
  47                         compatible = "simple-bus";
  48                         #address-cells = <1>;
  49                         #size-cells = <1>;
  50                         ranges = <0x88000000 0x88000000 0x40000>;
  51
  52                         clks: clock-controller@88000000 {
  53                                 compatible = "sirf,atlas6-clkc";
  54                                 reg = <0x88000000 0x1000>;
  55                                 interrupts = <3>;
  56                                 #clock-cells = <1>;
  57                         };
  58
  59                         reset-controller@88010000 {
  60                                 compatible = "sirf,prima2-rstc";
  61                                 reg = <0x88010000 0x1000>;
  62                         };
  63
  64                         rsc-controller@88020000 {
  65                                 compatible = "sirf,prima2-rsc";
  66                                 reg = <0x88020000 0x1000>;
  67                         };
  68
  69                         cphifbg@88030000 {
  70                                 compatible = "sirf,prima2-cphifbg";
  71                                 reg = <0x88030000 0x1000>;
  72                         };
  73                 };
  74
  75                 mem-iobg {
  76                         compatible = "simple-bus";
  77                         #address-cells = <1>;
  78                         #size-cells = <1>;
  79                         ranges = <0x90000000 0x90000000 0x10000>;
  80
  81                         memory-controller@90000000 {
  82                                 compatible = "sirf,prima2-memc";
  83                                 reg = <0x90000000 0x2000>;
  84                                 interrupts = <27>;
  85                                 clocks = <&clks 5>;
  86                         };
  87
  88                         memc-monitor {
  89                                 compatible = "sirf,prima2-memcmon";
  90                                 reg = <0x90002000 0x200>;
  91                                 interrupts = <4>;
  92                                 clocks = <&clks 32>;
  93                         };
  94                 };
  95
  96                 disp-iobg {
  97                         compatible = "simple-bus";
  98                         #address-cells = <1>;
  99                         #size-cells = <1>;
 100                         ranges = <0x90010000 0x90010000 0x30000>;
 101
 102                         lcd@90010000 {
 103                                 compatible = "sirf,prima2-lcd";
 104                                 reg = <0x90010000 0x20000>;
 105                                 interrupts = <30>;
 106                                 clocks = <&clks 34>;
 107                                 display=<&display>;
 108                                 /* later transfer to pwm */
 109                                 bl-gpio = <&gpio 7 0>;
 110                                 default-panel = <&panel0>;
 111                         };
 112
 113                         vpp@90020000 {
 114                                 compatible = "sirf,prima2-vpp";
 115                                 reg = <0x90020000 0x10000>;
 116                                 interrupts = <31>;
 117                                 clocks = <&clks 35>;
 118                         };
 119                 };
 120
 121                 graphics-iobg {
 122                         compatible = "simple-bus";
 123                         #address-cells = <1>;
 124                         #size-cells = <1>;
 125                         ranges = <0x98000000 0x98000000 0x8000000>;
 126
 127                         graphics@98000000 {
 128                                 compatible = "powervr,sgx510";
 129                                 reg = <0x98000000 0x8000000>;
 130                                 interrupts = <6>;
 131                                 clocks = <&clks 32>;
 132                         };
 133                 };
 134
 135                 graphics2d-iobg {
 136                         compatible = "simple-bus";
 137                         #address-cells = <1>;
 138                         #size-cells = <1>;
 139                         ranges = <0xa0000000 0xa0000000 0x8000000>;
 140
 141                         ble@a0000000 {
 142                                 compatible = "sirf,atlas6-ble";
 143                                 reg = <0xa0000000 0x2000>;
 144                                 interrupts = <5>;
 145                                 clocks = <&clks 33>;
 146                         };
 147                 };
 148
 149                 dsp-iobg {
 150                         compatible = "simple-bus";
 151                         #address-cells = <1>;
 152                         #size-cells = <1>;
 153                         ranges = <0xa8000000 0xa8000000 0x2000000>;
 154
 155                         dspif@a8000000 {
 156                                 compatible = "sirf,prima2-dspif";
 157                                 reg = <0xa8000000 0x10000>;
 158                                 interrupts = <9>;
 159                         };
 160
 161                         gps@a8010000 {
 162                                 compatible = "sirf,prima2-gps";
 163                                 reg = <0xa8010000 0x10000>;
 164                                 interrupts = <7>;
 165                                 clocks = <&clks 9>;
 166                         };
 167
 168                         dsp@a9000000 {
 169                                 compatible = "sirf,prima2-dsp";
 170                                 reg = <0xa9000000 0x1000000>;
 171                                 interrupts = <8>;
 172                                 clocks = <&clks 8>;
 173                         };
 174                 };
 175
 176                 peri-iobg {
 177                         compatible = "simple-bus";
 178                         #address-cells = <1>;
 179                         #size-cells = <1>;
 180                         ranges = <0xb0000000 0xb0000000 0x180000>,
 181                                <0x56000000 0x56000000 0x1b00000>;
 182
 183                         timer@b0020000 {
 184                                 compatible = "sirf,prima2-tick";
 185                                 reg = <0xb0020000 0x1000>;
 186                                 interrupts = <0>;
 187                         };
 188
 189                         nand@b0030000 {
 190                                 compatible = "sirf,prima2-nand";
 191                                 reg = <0xb0030000 0x10000>;
 192                                 interrupts = <41>;
 193                                 clocks = <&clks 26>;
 194                         };
 195
 196                         audio@b0040000 {
 197                                 compatible = "sirf,prima2-audio";
 198                                 reg = <0xb0040000 0x10000>;
 199                                 interrupts = <35>;
 200                                 clocks = <&clks 27>;
 201                         };
 202
 203                         uart0: uart@b0050000 {
 204                                 cell-index = <0>;
 205                                 compatible = "sirf,prima2-uart";
 206                                 reg = <0xb0050000 0x1000>;
 207                                 interrupts = <17>;
 208                                 fifosize = <128>;
 209                                 clocks = <&clks 13>;
 210                                 sirf,uart-dma-rx-channel = <21>;
 211                                 sirf,uart-dma-tx-channel = <2>;
 212                         };
 213
 214                         uart1: uart@b0060000 {
 215                                 cell-index = <1>;
 216                                 compatible = "sirf,prima2-uart";
 217                                 reg = <0xb0060000 0x1000>;
 218                                 interrupts = <18>;
 219                                 fifosize = <32>;
 220                                 clocks = <&clks 14>;
 221                         };
 222
 223                         uart2: uart@b0070000 {
 224                                 cell-index = <2>;
 225                                 compatible = "sirf,prima2-uart";
 226                                 reg = <0xb0070000 0x1000>;
 227                                 interrupts = <19>;
 228                                 fifosize = <128>;
 229                                 clocks = <&clks 15>;
 230                                 sirf,uart-dma-rx-channel = <6>;
 231                                 sirf,uart-dma-tx-channel = <7>;
 232                         };
 233
 234                         usp0: usp@b0080000 {
 235                                 cell-index = <0>;
 236                                 compatible = "sirf,prima2-usp";
 237                                 reg = <0xb0080000 0x10000>;
 238                                 interrupts = <20>;
 239                                 fifosize = <128>;
 240                                 clocks = <&clks 28>;
 241                                 sirf,usp-dma-rx-channel = <17>;
 242                                 sirf,usp-dma-tx-channel = <18>;
 243                         };
 244
 245                         usp1: usp@b0090000 {
 246                                 cell-index = <1>;
 247                                 compatible = "sirf,prima2-usp";
 248                                 reg = <0xb0090000 0x10000>;
 249                                 interrupts = <21>;
 250                                 fifosize = <128>;
 251                                 clocks = <&clks 29>;
 252                                 sirf,usp-dma-rx-channel = <14>;
 253                                 sirf,usp-dma-tx-channel = <15>;
 254                         };
 255
 256                         dmac0: dma-controller@b00b0000 {
 257                                 cell-index = <0>;
 258                                 compatible = "sirf,prima2-dmac";
 259                                 reg = <0xb00b0000 0x10000>;
 260                                 interrupts = <12>;
 261                                 clocks = <&clks 24>;
 262                         };
 263
 264                         dmac1: dma-controller@b0160000 {
 265                                 cell-index = <1>;
 266                                 compatible = "sirf,prima2-dmac";
 267                                 reg = <0xb0160000 0x10000>;
 268                                 interrupts = <13>;
 269                                 clocks = <&clks 25>;
 270                         };
 271
 272                         vip@b00C0000 {
 273                                 compatible = "sirf,prima2-vip";
 274                                 reg = <0xb00C0000 0x10000>;
 275                                 clocks = <&clks 31>;
 276                                 interrupts = <14>;
 277                                 sirf,vip-dma-rx-channel = <16>;
 278                         };
 279
 280                         spi0: spi@b00d0000 {
 281                                 cell-index = <0>;
 282                                 compatible = "sirf,prima2-spi";
 283                                 reg = <0xb00d0000 0x10000>;
 284                                 interrupts = <15>;
 285                                 sirf,spi-num-chipselects = <1>;
 286                                 cs-gpios = <&gpio 0 0>;
 287                                 sirf,spi-dma-rx-channel = <25>;
 288                                 sirf,spi-dma-tx-channel = <20>;
 289                                 #address-cells = <1>;
 290                                 #size-cells = <0>;
 291                                 clocks = <&clks 19>;
 292                                 status = "disabled";
 293                         };
 294
 295                         spi1: spi@b0170000 {
 296                                 cell-index = <1>;
 297                                 compatible = "sirf,prima2-spi";
 298                                 reg = <0xb0170000 0x10000>;
 299                                 interrupts = <16>;
 300                                 clocks = <&clks 20>;
 301                                 status = "disabled";
 302                         };
 303
 304                         i2c0: i2c@b00e0000 {
 305                                 cell-index = <0>;
 306                                 compatible = "sirf,prima2-i2c";
 307                                 reg = <0xb00e0000 0x10000>;
 308                                 interrupts = <24>;
 309                                 #address-cells = <1>;
 310                                 #size-cells = <0>;
 311                                 clocks = <&clks 17>;
 312                         };
 313
 314                         i2c1: i2c@b00f0000 {
 315                                 cell-index = <1>;
 316                                 compatible = "sirf,prima2-i2c";
 317                                 reg = <0xb00f0000 0x10000>;
 318                                 interrupts = <25>;
 319                                 #address-cells = <1>;
 320                                 #size-cells = <0>;
 321                                 clocks = <&clks 18>;
 322                         };
 323
 324                         tsc@b0110000 {
 325                                 compatible = "sirf,prima2-tsc";
 326                                 reg = <0xb0110000 0x10000>;
 327                                 interrupts = <33>;
 328                                 clocks = <&clks 16>;
 329                         };
 330
 331                         gpio: pinctrl@b0120000 {
 332                                 #gpio-cells = <2>;
 333                                 #interrupt-cells = <2>;
 334                                 compatible = "sirf,atlas6-pinctrl";
 335                                 reg = <0xb0120000 0x10000>;
 336                                 interrupts = <43 44 45 46 47>;
 337                                 gpio-controller;
 338                                 interrupt-controller;
 339
 340                                 lcd_16pins_a: lcd0@0 {
 341                                         lcd {
 342                                                 sirf,pins = "lcd_16bitsgrp";
 343                                                 sirf,function = "lcd_16bits";
 344                                         };
 345                                 };
 346                                 lcd_18pins_a: lcd0@1 {
 347                                         lcd {
 348                                                 sirf,pins = "lcd_18bitsgrp";
 349                                                 sirf,function = "lcd_18bits";
 350                                         };
 351                                 };
 352                                 lcd_24pins_a: lcd0@2 {
 353                                         lcd {
 354                                                 sirf,pins = "lcd_24bitsgrp";
 355                                                 sirf,function = "lcd_24bits";
 356                                         };
 357                                 };
 358                                 lcdrom_pins_a: lcdrom0@0 {
 359                                         lcd {
 360                                                 sirf,pins = "lcdromgrp";
 361                                                 sirf,function = "lcdrom";
 362                                         };
 363                                 };
 364                                 uart0_pins_a: uart0@0 {
 365                                         uart {
 366                                                 sirf,pins = "uart0grp";
 367                                                 sirf,function = "uart0";
 368                                         };
 369                                 };
 370                                 uart0_noflow_pins_a: uart0@1 {
 371                                         uart {
 372                                                 sirf,pins = "uart0_nostreamctrlgrp";
 373                                                 sirf,function = "uart0_nostreamctrl";
 374                                         };
 375                                 };
 376                                 uart1_pins_a: uart1@0 {
 377                                         uart {
 378                                                 sirf,pins = "uart1grp";
 379                                                 sirf,function = "uart1";
 380                                         };
 381                                 };
 382                                 uart2_pins_a: uart2@0 {
 383                                         uart {
 384                                                 sirf,pins = "uart2grp";
 385                                                 sirf,function = "uart2";
 386                                         };
 387                                 };
 388                                 uart2_noflow_pins_a: uart2@1 {
 389                                         uart {
 390                                                 sirf,pins = "uart2_nostreamctrlgrp";
 391                                                 sirf,function = "uart2_nostreamctrl";
 392                                         };
 393                                 };
 394                                 spi0_pins_a: spi0@0 {
 395                                         spi {
 396                                                 sirf,pins = "spi0grp";
 397                                                 sirf,function = "spi0";
 398                                         };
 399                                 };
 400                                 spi1_pins_a: spi1@0 {
 401                                         spi {
 402                                                 sirf,pins = "spi1grp";
 403                                                 sirf,function = "spi1";
 404                                         };
 405                                 };
 406                                 i2c0_pins_a: i2c0@0 {
 407                                         i2c {
 408                                                 sirf,pins = "i2c0grp";
 409                                                 sirf,function = "i2c0";
 410                                         };
 411                                 };
 412                                 i2c1_pins_a: i2c1@0 {
 413                                         i2c {
 414                                                 sirf,pins = "i2c1grp";
 415                                                 sirf,function = "i2c1";
 416                                         };
 417                                 };
 418                                 pwm0_pins_a: pwm0@0 {
 419                                         pwm {
 420                                                 sirf,pins = "pwm0grp";
 421                                                 sirf,function = "pwm0";
 422                                         };
 423                                 };
 424                                 pwm1_pins_a: pwm1@0 {
 425                                         pwm {
 426                                                 sirf,pins = "pwm1grp";
 427                                                 sirf,function = "pwm1";
 428                                         };
 429                                 };
 430                                 pwm2_pins_a: pwm2@0 {
 431                                         pwm {
 432                                                 sirf,pins = "pwm2grp";
 433                                                 sirf,function = "pwm2";
 434                                         };
 435                                 };
 436                                 pwm3_pins_a: pwm3@0 {
 437                                         pwm {
 438                                                 sirf,pins = "pwm3grp";
 439                                                 sirf,function = "pwm3";
 440                                         };
 441                                 };
 442                                 pwm4_pins_a: pwm4@0 {
 443                                         pwm {
 444                                                 sirf,pins = "pwm4grp";
 445                                                 sirf,function = "pwm4";
 446                                         };
 447                                 };
 448                                 gps_pins_a: gps@0 {
 449                                         gps {
 450                                                 sirf,pins = "gpsgrp";
 451                                                 sirf,function = "gps";
 452                                         };
 453                                 };
 454                                 vip_pins_a: vip@0 {
 455                                         vip {
 456                                                 sirf,pins = "vipgrp";
 457                                                 sirf,function = "vip";
 458                                         };
 459                                 };
 460                                 sdmmc0_pins_a: sdmmc0@0 {
 461                                         sdmmc0 {
 462                                                 sirf,pins = "sdmmc0grp";
 463                                                 sirf,function = "sdmmc0";
 464                                         };
 465                                 };
 466                                 sdmmc1_pins_a: sdmmc1@0 {
 467                                         sdmmc1 {
 468                                                 sirf,pins = "sdmmc1grp";
 469                                                 sirf,function = "sdmmc1";
 470                                         };
 471                                 };
 472                                 sdmmc2_pins_a: sdmmc2@0 {
 473                                         sdmmc2 {
 474                                                 sirf,pins = "sdmmc2grp";
 475                                                 sirf,function = "sdmmc2";
 476                                         };
 477                                 };
 478                                 sdmmc2_nowp_pins_a: sdmmc2_nowp@0 {
 479                                         sdmmc2_nowp {
 480                                                 sirf,pins = "sdmmc2_nowpgrp";
 481                                                 sirf,function = "sdmmc2_nowp";
 482                                         };
 483                                 };
 484                                 sdmmc3_pins_a: sdmmc3@0 {
 485                                         sdmmc3 {
 486                                                 sirf,pins = "sdmmc3grp";
 487                                                 sirf,function = "sdmmc3";
 488                                         };
 489                                 };
 490                                 sdmmc5_pins_a: sdmmc5@0 {
 491                                         sdmmc5 {
 492                                                 sirf,pins = "sdmmc5grp";
 493                                                 sirf,function = "sdmmc5";
 494                                         };
 495                                 };
 496                                 i2s_pins_a: i2s@0 {
 497                                         i2s {
 498                                                 sirf,pins = "i2sgrp";
 499                                                 sirf,function = "i2s";
 500                                         };
 501                                 };
 502                                 i2s_no_din_pins_a: i2s_no_din@0 {
 503                                         i2s_no_din {
 504                                                 sirf,pins = "i2s_no_dingrp";
 505                                                 sirf,function = "i2s_no_din";
 506                                         };
 507                                 };
 508                                 i2s_6chn_pins_a: i2s_6chn@0 {
 509                                         i2s_6chn {
 510                                                 sirf,pins = "i2s_6chngrp";
 511                                                 sirf,function = "i2s_6chn";
 512                                         };
 513                                 };
 514                                 ac97_pins_a: ac97@0 {
 515                                         ac97 {
 516                                                 sirf,pins = "ac97grp";
 517                                                 sirf,function = "ac97";
 518                                         };
 519                                 };
 520                                 nand_pins_a: nand@0 {
 521                                         nand {
 522                                                 sirf,pins = "nandgrp";
 523                                                 sirf,function = "nand";
 524                                         };
 525                                 };
 526                                 usp0_pins_a: usp0@0 {
 527                                         usp0 {
 528                                                 sirf,pins = "usp0grp";
 529                                                 sirf,function = "usp0";
 530                                         };
 531                                 };
 532                                 usp0_uart_nostreamctrl_pins_a: usp0@1 {
 533                                         usp0 {
 534                                                 sirf,pins = "usp0_uart_nostreamctrl_grp";
 535                                                 sirf,function = "usp0_uart_nostreamctrl";
 536                                         };
 537                                 };
 538                                 usp1_pins_a: usp1@0 {
 539                                         usp1 {
 540                                                 sirf,pins = "usp1grp";
 541                                                 sirf,function = "usp1";
 542                                         };
 543                                 };
 544                                 usb0_upli_drvbus_pins_a: usb0_upli_drvbus@0 {
 545                                         usb0_upli_drvbus {
 546                                                 sirf,pins = "usb0_upli_drvbusgrp";
 547                                                 sirf,function = "usb0_upli_drvbus";
 548                                         };
 549                                 };
 550                                 usb1_utmi_drvbus_pins_a: usb1_utmi_drvbus@0 {
 551                                         usb1_utmi_drvbus {
 552                                                 sirf,pins = "usb1_utmi_drvbusgrp";
 553                                                 sirf,function = "usb1_utmi_drvbus";
 554                                         };
 555                                 };
 556                                 warm_rst_pins_a: warm_rst@0 {
 557                                         warm_rst {
 558                                                 sirf,pins = "warm_rstgrp";
 559                                                 sirf,function = "warm_rst";
 560                                         };
 561                                 };
 562                                 pulse_count_pins_a: pulse_count@0 {
 563                                         pulse_count {
 564                                                 sirf,pins = "pulse_countgrp";
 565                                                 sirf,function = "pulse_count";
 566                                         };
 567                                 };
 568                                 cko0_pins_a: cko0@0 {
 569                                         cko0 {
 570                                                 sirf,pins = "cko0grp";
 571                                                 sirf,function = "cko0";
 572                                         };
 573                                 };
 574                                 cko1_pins_a: cko1@0 {
 575                                         cko1 {
 576                                                 sirf,pins = "cko1grp";
 577                                                 sirf,function = "cko1";
 578                                         };
 579                                 };
 580                         };
 581
 582                         pwm@b0130000 {
 583                                 compatible = "sirf,prima2-pwm";
 584                                 reg = <0xb0130000 0x10000>;
 585                                 clocks = <&clks 21>;
 586                         };
 587
 588                         efusesys@b0140000 {
 589                                 compatible = "sirf,prima2-efuse";
 590                                 reg = <0xb0140000 0x10000>;
 591                                 clocks = <&clks 22>;
 592                         };
 593
 594                         pulsec@b0150000 {
 595                                 compatible = "sirf,prima2-pulsec";
 596                                 reg = <0xb0150000 0x10000>;
 597                                 interrupts = <48>;
 598                                 clocks = <&clks 23>;
 599                         };
 600
 601                         pci-iobg {
 602                                 compatible = "sirf,prima2-pciiobg", "simple-bus";
 603                                 #address-cells = <1>;
 604                                 #size-cells = <1>;
 605                                 ranges = <0x56000000 0x56000000 0x1b00000>;
 606
 607                                 sd0: sdhci@56000000 {
 608                                         cell-index = <0>;
 609                                         compatible = "sirf,prima2-sdhc";
 610                                         reg = <0x56000000 0x100000>;
 611                                         interrupts = <38>;
 612                                         bus-width = <8>;
 613                                         clocks = <&clks 36>;
 614                                 };
 615
 616                                 sd1: sdhci@56100000 {
 617                                         cell-index = <1>;
 618                                         compatible = "sirf,prima2-sdhc";
 619                                         reg = <0x56100000 0x100000>;
 620                                         interrupts = <38>;
 621                                         status = "disabled";
 622                                         clocks = <&clks 36>;
 623                                 };
 624
 625                                 sd2: sdhci@56200000 {
 626                                         cell-index = <2>;
 627                                         compatible = "sirf,prima2-sdhc";
 628                                         reg = <0x56200000 0x100000>;
 629                                         interrupts = <23>;
 630                                         status = "disabled";
 631                                         clocks = <&clks 37>;
 632                                 };
 633
 634                                 sd3: sdhci@56300000 {
 635                                         cell-index = <3>;
 636                                         compatible = "sirf,prima2-sdhc";
 637                                         reg = <0x56300000 0x100000>;
 638                                         interrupts = <23>;
 639                                         status = "disabled";
 640                                         clocks = <&clks 37>;
 641                                 };
 642
 643                                 sd5: sdhci@56500000 {
 644                                         cell-index = <5>;
 645                                         compatible = "sirf,prima2-sdhc";
 646                                         reg = <0x56500000 0x100000>;
 647                                         interrupts = <39>;
 648                                         status = "disabled";
 649                                         clocks = <&clks 38>;
 650                                 };
 651
 652                                 pci-copy@57900000 {
 653                                         compatible = "sirf,prima2-pcicp";
 654                                         reg = <0x57900000 0x100000>;
 655                                         interrupts = <40>;
 656                                 };
 657
 658                                 rom-interface@57a00000 {
 659                                         compatible = "sirf,prima2-romif";
 660                                         reg = <0x57a00000 0x100000>;
 661                                 };
 662                         };
 663                 };
 664
 665                 rtc-iobg {
 666                         compatible = "sirf,prima2-rtciobg", "sirf-prima2-rtciobg-bus", "simple-bus";
 667                         #address-cells = <1>;
 668                         #size-cells = <1>;
 669                         reg = <0x80030000 0x10000>;
 670
 671                         gpsrtc@1000 {
 672                                 compatible = "sirf,prima2-gpsrtc";
 673                                 reg = <0x1000 0x1000>;
 674                                 interrupts = <55 56 57>;
 675                         };
 676
 677                         sysrtc@2000 {
 678                                 compatible = "sirf,prima2-sysrtc";
 679                                 reg = <0x2000 0x1000>;
 680                                 interrupts = <52 53 54>;
 681                         };
 682
 683                         pwrc@3000 {
 684                                 compatible = "sirf,prima2-pwrc";
 685                                 reg = <0x3000 0x1000>;
 686                                 interrupts = <32>;
 687                         };
 688                 };
 689
 690                 uus-iobg {
 691                         compatible = "simple-bus";
 692                         #address-cells = <1>;
 693                         #size-cells = <1>;
 694                         ranges = <0xb8000000 0xb8000000 0x40000>;
 695
 696                         usb0: usb@b00e0000 {
 697                                 compatible = "chipidea,ci13611a-prima2";
 698                                 reg = <0xb8000000 0x10000>;
 699                                 interrupts = <10>;
 700                                 clocks = <&clks 40>;
 701                         };
 702
 703                         usb1: usb@b00f0000 {
 704                                 compatible = "chipidea,ci13611a-prima2";
 705                                 reg = <0xb8010000 0x10000>;
 706                                 interrupts = <11>;
 707                                 clocks = <&clks 41>;
 708                         };
 709
 710                         security@b00f0000 {
 711                                 compatible = "sirf,prima2-security";
 712                                 reg = <0xb8030000 0x10000>;
 713                                 interrupts = <42>;
 714                                 clocks = <&clks 7>;
 715                         };
 716                 };
 717         };
 718 };